1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * U-Boot additions
4 *
5 * Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
6 */
7
8#include "socfpga_soc64_fit-u-boot.dtsi"
9
10/{
11	memory {
12		#address-cells = <2>;
13		#size-cells = <2>;
14		u-boot,dm-pre-reloc;
15	};
16
17	soc {
18		u-boot,dm-pre-reloc;
19
20		ccu: cache-controller@f7000000 {
21			compatible = "arteris,ncore-ccu";
22			reg = <0xf7000000 0x100900>;
23			u-boot,dm-pre-reloc;
24		};
25	};
26};
27
28&clkmgr {
29	u-boot,dm-pre-reloc;
30};
31
32&gmac1 {
33	altr,sysmgr-syscon = <&sysmgr 0x48 0>;
34};
35
36&gmac2 {
37	altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
38};
39
40&i2c0 {
41	reset-names = "i2c";
42};
43
44&i2c1 {
45	reset-names = "i2c";
46};
47
48&i2c2 {
49	reset-names = "i2c";
50};
51
52&i2c3 {
53	reset-names = "i2c";
54};
55
56&mmc {
57	resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
58};
59
60&porta {
61	bank-name = "porta";
62};
63
64&portb {
65	bank-name = "portb";
66};
67
68&qspi {
69	u-boot,dm-pre-reloc;
70};
71
72&rst {
73	compatible = "altr,rst-mgr";
74	altr,modrst-offset = <0x20>;
75	u-boot,dm-pre-reloc;
76};
77
78&sdr {
79	compatible = "intel,sdr-ctl-agilex";
80	reg = <0xf8000400 0x80>,
81	      <0xf8010000 0x190>,
82	      <0xf8011000 0x500>;
83	resets = <&rst DDRSCH_RESET>;
84	u-boot,dm-pre-reloc;
85};
86
87&sysmgr {
88	compatible = "altr,sys-mgr", "syscon";
89	u-boot,dm-pre-reloc;
90};
91
92&uart0 {
93	u-boot,dm-pre-reloc;
94};
95
96&watchdog0 {
97	u-boot,dm-pre-reloc;
98};
99