1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP ZCU111 4 * 5 * (C) Copyright 2017 - 2020, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 */ 9 10/dts-v1/; 11 12#include "zynqmp.dtsi" 13#include "zynqmp-clk-ccf.dtsi" 14#include <dt-bindings/input/input.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 17#include <dt-bindings/phy/phy.h> 18 19/ { 20 model = "ZynqMP ZCU111 RevA"; 21 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; 22 23 aliases { 24 ethernet0 = &gem3; 25 gpio0 = &gpio; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 mmc0 = &sdhci1; 29 rtc0 = &rtc; 30 serial0 = &uart0; 31 serial1 = &dcc; 32 spi0 = &qspi; 33 usb0 = &usb0; 34 }; 35 36 chosen { 37 bootargs = "earlycon"; 38 stdout-path = "serial0:115200n8"; 39 xlnx,eeprom = &eeprom; 40 }; 41 42 memory@0 { 43 device_type = "memory"; 44 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; 45 /* Another 4GB connected to PL */ 46 }; 47 48 gpio-keys { 49 compatible = "gpio-keys"; 50 autorepeat; 51 sw19 { 52 label = "sw19"; 53 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; 54 linux,code = <KEY_DOWN>; 55 wakeup-source; 56 autorepeat; 57 }; 58 }; 59 60 leds { 61 compatible = "gpio-leds"; 62 heartbeat-led { 63 label = "heartbeat"; 64 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; 65 linux,default-trigger = "heartbeat"; 66 }; 67 }; 68 69 ina226-u67 { 70 compatible = "iio-hwmon"; 71 io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; 72 }; 73 ina226-u59 { 74 compatible = "iio-hwmon"; 75 io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; 76 }; 77 ina226-u61 { 78 compatible = "iio-hwmon"; 79 io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; 80 }; 81 ina226-u60 { 82 compatible = "iio-hwmon"; 83 io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; 84 }; 85 ina226-u64 { 86 compatible = "iio-hwmon"; 87 io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; 88 }; 89 ina226-u69 { 90 compatible = "iio-hwmon"; 91 io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; 92 }; 93 ina226-u66 { 94 compatible = "iio-hwmon"; 95 io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; 96 }; 97 ina226-u65 { 98 compatible = "iio-hwmon"; 99 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; 100 }; 101 ina226-u63 { 102 compatible = "iio-hwmon"; 103 io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; 104 }; 105 ina226-u3 { 106 compatible = "iio-hwmon"; 107 io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; 108 }; 109 ina226-u71 { 110 compatible = "iio-hwmon"; 111 io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; 112 }; 113 ina226-u77 { 114 compatible = "iio-hwmon"; 115 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; 116 }; 117 ina226-u73 { 118 compatible = "iio-hwmon"; 119 io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; 120 }; 121 ina226-u79 { 122 compatible = "iio-hwmon"; 123 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; 124 }; 125 126 /* 48MHz reference crystal */ 127 ref48: ref48M { 128 compatible = "fixed-clock"; 129 #clock-cells = <0>; 130 clock-frequency = <48000000>; 131 }; 132}; 133 134&dcc { 135 status = "okay"; 136}; 137 138&fpd_dma_chan1 { 139 status = "okay"; 140}; 141 142&fpd_dma_chan2 { 143 status = "okay"; 144}; 145 146&fpd_dma_chan3 { 147 status = "okay"; 148}; 149 150&fpd_dma_chan4 { 151 status = "okay"; 152}; 153 154&fpd_dma_chan5 { 155 status = "okay"; 156}; 157 158&fpd_dma_chan6 { 159 status = "okay"; 160}; 161 162&fpd_dma_chan7 { 163 status = "okay"; 164}; 165 166&fpd_dma_chan8 { 167 status = "okay"; 168}; 169 170&gem3 { 171 status = "okay"; 172 phy-handle = <&phy0>; 173 phy-mode = "rgmii-id"; 174 pinctrl-names = "default"; 175 pinctrl-0 = <&pinctrl_gem3_default>; 176 phy0: ethernet-phy@c { 177 reg = <0xc>; 178 ti,rx-internal-delay = <0x8>; 179 ti,tx-internal-delay = <0xa>; 180 ti,fifo-depth = <0x1>; 181 ti,dp83867-rxctrl-strap-quirk; 182 }; 183}; 184 185&gpio { 186 status = "okay"; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_gpio_default>; 189}; 190 191&gpu { 192 status = "okay"; 193}; 194 195&i2c0 { 196 status = "okay"; 197 clock-frequency = <400000>; 198 pinctrl-names = "default", "gpio"; 199 pinctrl-0 = <&pinctrl_i2c0_default>; 200 pinctrl-1 = <&pinctrl_i2c0_gpio>; 201 scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; 202 sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; 203 204 tca6416_u22: gpio@20 { 205 compatible = "ti,tca6416"; 206 reg = <0x20>; 207 gpio-controller; /* interrupt not connected */ 208 #gpio-cells = <2>; 209 /* 210 * IRQ not connected 211 * Lines: 212 * 0 - MAX6643_OT_B 213 * 1 - MAX6643_FANFAIL_B 214 * 2 - MIO26_PMU_INPUT_LS 215 * 4 - SFP_SI5382_INT_ALM 216 * 5 - IIC_MUX_RESET_B 217 * 6 - GEM3_EXP_RESET_B 218 * 10 - FMCP_HSPC_PRSNT_M2C_B 219 * 11 - CLK_SPI_MUX_SEL0 220 * 12 - CLK_SPI_MUX_SEL1 221 * 16 - IRPS5401_ALERT_B 222 * 17 - INA226_PMBUS_ALERT 223 * 3, 7, 13-15 - not connected 224 */ 225 }; 226 227 i2c-mux@75 { /* u23 */ 228 compatible = "nxp,pca9544"; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 reg = <0x75>; 232 i2c@0 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 reg = <0>; 236 /* PS_PMBUS */ 237 /* PMBUS_ALERT done via pca9544 */ 238 u67: ina226@40 { /* u67 */ 239 compatible = "ti,ina226"; 240 #io-channel-cells = <1>; 241 label = "ina226-u67"; 242 reg = <0x40>; 243 shunt-resistor = <2000>; 244 }; 245 u59: ina226@41 { /* u59 */ 246 compatible = "ti,ina226"; 247 #io-channel-cells = <1>; 248 label = "ina226-u59"; 249 reg = <0x41>; 250 shunt-resistor = <5000>; 251 }; 252 u61: ina226@42 { /* u61 */ 253 compatible = "ti,ina226"; 254 #io-channel-cells = <1>; 255 label = "ina226-u61"; 256 reg = <0x42>; 257 shunt-resistor = <5000>; 258 }; 259 u60: ina226@43 { /* u60 */ 260 compatible = "ti,ina226"; 261 #io-channel-cells = <1>; 262 label = "ina226-u60"; 263 reg = <0x43>; 264 shunt-resistor = <5000>; 265 }; 266 u64: ina226@45 { /* u64 */ 267 compatible = "ti,ina226"; 268 #io-channel-cells = <1>; 269 label = "ina226-u64"; 270 reg = <0x45>; 271 shunt-resistor = <5000>; 272 }; 273 u69: ina226@46 { /* u69 */ 274 compatible = "ti,ina226"; 275 #io-channel-cells = <1>; 276 label = "ina226-u69"; 277 reg = <0x46>; 278 shunt-resistor = <2000>; 279 }; 280 u66: ina226@47 { /* u66 */ 281 compatible = "ti,ina226"; 282 #io-channel-cells = <1>; 283 label = "ina226-u66"; 284 reg = <0x47>; 285 shunt-resistor = <5000>; 286 }; 287 u65: ina226@48 { /* u65 */ 288 compatible = "ti,ina226"; 289 #io-channel-cells = <1>; 290 label = "ina226-u65"; 291 reg = <0x48>; 292 shunt-resistor = <5000>; 293 }; 294 u63: ina226@49 { /* u63 */ 295 compatible = "ti,ina226"; 296 #io-channel-cells = <1>; 297 label = "ina226-u63"; 298 reg = <0x49>; 299 shunt-resistor = <5000>; 300 }; 301 u3: ina226@4a { /* u3 */ 302 compatible = "ti,ina226"; 303 #io-channel-cells = <1>; 304 label = "ina226-u3"; 305 reg = <0x4a>; 306 shunt-resistor = <5000>; 307 }; 308 u71: ina226@4b { /* u71 */ 309 compatible = "ti,ina226"; 310 #io-channel-cells = <1>; 311 label = "ina226-u71"; 312 reg = <0x4b>; 313 shunt-resistor = <5000>; 314 }; 315 u77: ina226@4c { /* u77 */ 316 compatible = "ti,ina226"; 317 #io-channel-cells = <1>; 318 label = "ina226-u77"; 319 reg = <0x4c>; 320 shunt-resistor = <5000>; 321 }; 322 u73: ina226@4d { /* u73 */ 323 compatible = "ti,ina226"; 324 #io-channel-cells = <1>; 325 label = "ina226-u73"; 326 reg = <0x4d>; 327 shunt-resistor = <5000>; 328 }; 329 u79: ina226@4e { /* u79 */ 330 compatible = "ti,ina226"; 331 #io-channel-cells = <1>; 332 label = "ina226-u79"; 333 reg = <0x4e>; 334 shunt-resistor = <5000>; 335 }; 336 }; 337 i2c@1 { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 reg = <1>; 341 /* NC */ 342 }; 343 i2c@2 { 344 #address-cells = <1>; 345 #size-cells = <0>; 346 reg = <2>; 347 irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ 348 compatible = "infineon,irps5401"; 349 reg = <0x43>; 350 }; 351 irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ 352 compatible = "infineon,irps5401"; 353 reg = <0x44>; 354 }; 355 irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ 356 compatible = "infineon,irps5401"; 357 reg = <0x45>; 358 }; 359 /* u68 IR38064 +0 */ 360 /* u70 IR38060 +1 */ 361 /* u74 IR38060 +2 */ 362 /* u75 IR38060 +6 */ 363 /* J19 header too */ 364 365 }; 366 i2c@3 { 367 #address-cells = <1>; 368 #size-cells = <0>; 369 reg = <3>; 370 /* SYSMON */ 371 }; 372 }; 373}; 374 375&i2c1 { 376 status = "okay"; 377 clock-frequency = <400000>; 378 pinctrl-names = "default", "gpio"; 379 pinctrl-0 = <&pinctrl_i2c1_default>; 380 pinctrl-1 = <&pinctrl_i2c1_gpio>; 381 scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; 382 sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; 383 384 i2c-mux@74 { /* u26 */ 385 compatible = "nxp,pca9548"; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 reg = <0x74>; 389 i2c@0 { 390 #address-cells = <1>; 391 #size-cells = <0>; 392 reg = <0>; 393 /* 394 * IIC_EEPROM 1kB memory which uses 256B blocks 395 * where every block has different address. 396 * 0 - 256B address 0x54 397 * 256B - 512B address 0x55 398 * 512B - 768B address 0x56 399 * 768B - 1024B address 0x57 400 */ 401 eeprom: eeprom@54 { /* u88 */ 402 compatible = "atmel,24c08"; 403 reg = <0x54>; 404 }; 405 }; 406 i2c@1 { 407 #address-cells = <1>; 408 #size-cells = <0>; 409 reg = <1>; 410 si5341: clock-generator@36 { /* SI5341 - u46 */ 411 compatible = "silabs,si5341"; 412 reg = <0x36>; 413 #clock-cells = <2>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 clocks = <&ref48>; 417 clock-names = "xtal"; 418 clock-output-names = "si5341"; 419 420 si5341_0: out@0 { 421 /* refclk0 for PS-GT, used for DP */ 422 reg = <0>; 423 always-on; 424 }; 425 si5341_2: out@2 { 426 /* refclk2 for PS-GT, used for USB3 */ 427 reg = <2>; 428 always-on; 429 }; 430 si5341_3: out@3 { 431 /* refclk3 for PS-GT, used for SATA */ 432 reg = <3>; 433 always-on; 434 }; 435 si5341_5: out@5 { 436 /* refclk5 PL CLK100 */ 437 reg = <5>; 438 always-on; 439 }; 440 si5341_6: out@6 { 441 /* refclk6 PL CLK125 */ 442 reg = <6>; 443 always-on; 444 }; 445 si5341_9: out@9 { 446 /* refclk9 used for PS_REF_CLK 33.3 MHz */ 447 reg = <9>; 448 always-on; 449 }; 450 }; 451 }; 452 i2c@2 { 453 #address-cells = <1>; 454 #size-cells = <0>; 455 reg = <2>; 456 si570_1: clock-generator@5d { /* USER SI570 - u47 */ 457 #clock-cells = <0>; 458 compatible = "silabs,si570"; 459 reg = <0x5d>; 460 temperature-stability = <50>; 461 factory-fout = <300000000>; 462 clock-frequency = <300000000>; 463 clock-output-names = "si570_user"; 464 }; 465 }; 466 i2c@3 { 467 #address-cells = <1>; 468 #size-cells = <0>; 469 reg = <3>; 470 si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ 471 #clock-cells = <0>; 472 compatible = "silabs,si570"; 473 reg = <0x5d>; 474 temperature-stability = <50>; 475 factory-fout = <156250000>; 476 clock-frequency = <156250000>; 477 clock-output-names = "si570_mgt"; 478 }; 479 }; 480 i2c@4 { 481 #address-cells = <1>; 482 #size-cells = <0>; 483 reg = <4>; 484 si5382: clock-generator@69 { /* SI5382 - u48 */ 485 compatible = "silabs,si5382"; 486 reg = <0x69>; 487 }; 488 }; 489 i2c@5 { 490 #address-cells = <1>; 491 #size-cells = <0>; 492 reg = <5>; 493 sc18is603@2f { /* sc18is602 - u93 */ 494 compatible = "nxp,sc18is603"; 495 reg = <0x2f>; 496 /* 4 gpios for CS not handled by driver */ 497 /* 498 * USB2ANY cable or 499 * LMK04208 - u90 or 500 * LMX2594 - u102 or 501 * LMX2594 - u103 or 502 * LMX2594 - u104 503 */ 504 }; 505 }; 506 i2c@6 { 507 #address-cells = <1>; 508 #size-cells = <0>; 509 reg = <6>; 510 /* FMC connector */ 511 }; 512 /* 7 NC */ 513 }; 514 515 i2c-mux@75 { 516 compatible = "nxp,pca9548"; /* u27 */ 517 #address-cells = <1>; 518 #size-cells = <0>; 519 reg = <0x75>; 520 521 i2c@0 { 522 #address-cells = <1>; 523 #size-cells = <0>; 524 reg = <0>; 525 /* FMCP_HSPC_IIC */ 526 }; 527 i2c@1 { 528 #address-cells = <1>; 529 #size-cells = <0>; 530 reg = <1>; 531 /* NC */ 532 }; 533 i2c@2 { 534 #address-cells = <1>; 535 #size-cells = <0>; 536 reg = <2>; 537 /* SYSMON */ 538 }; 539 i2c@3 { 540 #address-cells = <1>; 541 #size-cells = <0>; 542 reg = <3>; 543 /* DDR4 SODIMM */ 544 }; 545 i2c@4 { 546 #address-cells = <1>; 547 #size-cells = <0>; 548 reg = <4>; 549 /* SFP3 */ 550 }; 551 i2c@5 { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 reg = <5>; 555 /* SFP2 */ 556 }; 557 i2c@6 { 558 #address-cells = <1>; 559 #size-cells = <0>; 560 reg = <6>; 561 /* SFP1 */ 562 }; 563 i2c@7 { 564 #address-cells = <1>; 565 #size-cells = <0>; 566 reg = <7>; 567 /* SFP0 */ 568 }; 569 }; 570}; 571 572&pinctrl0 { 573 status = "okay"; 574 pinctrl_i2c0_default: i2c0-default { 575 mux { 576 groups = "i2c0_3_grp"; 577 function = "i2c0"; 578 }; 579 580 conf { 581 groups = "i2c0_3_grp"; 582 bias-pull-up; 583 slew-rate = <SLEW_RATE_SLOW>; 584 power-source = <IO_STANDARD_LVCMOS18>; 585 }; 586 }; 587 588 pinctrl_i2c0_gpio: i2c0-gpio { 589 mux { 590 groups = "gpio0_14_grp", "gpio0_15_grp"; 591 function = "gpio0"; 592 }; 593 594 conf { 595 groups = "gpio0_14_grp", "gpio0_15_grp"; 596 slew-rate = <SLEW_RATE_SLOW>; 597 power-source = <IO_STANDARD_LVCMOS18>; 598 }; 599 }; 600 601 pinctrl_i2c1_default: i2c1-default { 602 mux { 603 groups = "i2c1_4_grp"; 604 function = "i2c1"; 605 }; 606 607 conf { 608 groups = "i2c1_4_grp"; 609 bias-pull-up; 610 slew-rate = <SLEW_RATE_SLOW>; 611 power-source = <IO_STANDARD_LVCMOS18>; 612 }; 613 }; 614 615 pinctrl_i2c1_gpio: i2c1-gpio { 616 mux { 617 groups = "gpio0_16_grp", "gpio0_17_grp"; 618 function = "gpio0"; 619 }; 620 621 conf { 622 groups = "gpio0_16_grp", "gpio0_17_grp"; 623 slew-rate = <SLEW_RATE_SLOW>; 624 power-source = <IO_STANDARD_LVCMOS18>; 625 }; 626 }; 627 628 pinctrl_uart0_default: uart0-default { 629 mux { 630 groups = "uart0_4_grp"; 631 function = "uart0"; 632 }; 633 634 conf { 635 groups = "uart0_4_grp"; 636 slew-rate = <SLEW_RATE_SLOW>; 637 power-source = <IO_STANDARD_LVCMOS18>; 638 }; 639 640 conf-rx { 641 pins = "MIO18"; 642 bias-high-impedance; 643 }; 644 645 conf-tx { 646 pins = "MIO19"; 647 bias-disable; 648 }; 649 }; 650 651 pinctrl_usb0_default: usb0-default { 652 mux { 653 groups = "usb0_0_grp"; 654 function = "usb0"; 655 }; 656 657 conf { 658 groups = "usb0_0_grp"; 659 slew-rate = <SLEW_RATE_SLOW>; 660 power-source = <IO_STANDARD_LVCMOS18>; 661 }; 662 663 conf-rx { 664 pins = "MIO52", "MIO53", "MIO55"; 665 bias-high-impedance; 666 }; 667 668 conf-tx { 669 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", 670 "MIO60", "MIO61", "MIO62", "MIO63"; 671 bias-disable; 672 }; 673 }; 674 675 pinctrl_gem3_default: gem3-default { 676 mux { 677 function = "ethernet3"; 678 groups = "ethernet3_0_grp"; 679 }; 680 681 conf { 682 groups = "ethernet3_0_grp"; 683 slew-rate = <SLEW_RATE_SLOW>; 684 power-source = <IO_STANDARD_LVCMOS18>; 685 }; 686 687 conf-rx { 688 pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", 689 "MIO75"; 690 bias-high-impedance; 691 low-power-disable; 692 }; 693 694 conf-tx { 695 pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", 696 "MIO69"; 697 bias-disable; 698 low-power-enable; 699 }; 700 701 mux-mdio { 702 function = "mdio3"; 703 groups = "mdio3_0_grp"; 704 }; 705 706 conf-mdio { 707 groups = "mdio3_0_grp"; 708 slew-rate = <SLEW_RATE_SLOW>; 709 power-source = <IO_STANDARD_LVCMOS18>; 710 bias-disable; 711 }; 712 }; 713 714 pinctrl_sdhci1_default: sdhci1-default { 715 mux { 716 groups = "sdio1_0_grp"; 717 function = "sdio1"; 718 }; 719 720 conf { 721 groups = "sdio1_0_grp"; 722 slew-rate = <SLEW_RATE_SLOW>; 723 power-source = <IO_STANDARD_LVCMOS18>; 724 bias-disable; 725 }; 726 727 mux-cd { 728 groups = "sdio1_cd_0_grp"; 729 function = "sdio1_cd"; 730 }; 731 732 conf-cd { 733 groups = "sdio1_cd_0_grp"; 734 bias-high-impedance; 735 bias-pull-up; 736 slew-rate = <SLEW_RATE_SLOW>; 737 power-source = <IO_STANDARD_LVCMOS18>; 738 }; 739 }; 740 741 pinctrl_gpio_default: gpio-default { 742 mux { 743 function = "gpio0"; 744 groups = "gpio0_22_grp", "gpio0_23_grp"; 745 }; 746 747 conf { 748 groups = "gpio0_22_grp", "gpio0_23_grp"; 749 slew-rate = <SLEW_RATE_SLOW>; 750 power-source = <IO_STANDARD_LVCMOS18>; 751 }; 752 753 mux-msp { 754 function = "gpio0"; 755 groups = "gpio0_13_grp", "gpio0_38_grp"; 756 }; 757 758 conf-msp { 759 groups = "gpio0_13_grp", "gpio0_38_grp"; 760 slew-rate = <SLEW_RATE_SLOW>; 761 power-source = <IO_STANDARD_LVCMOS18>; 762 }; 763 764 conf-pull-up { 765 pins = "MIO22"; 766 bias-pull-up; 767 }; 768 769 conf-pull-none { 770 pins = "MIO13", "MIO23", "MIO38"; 771 bias-disable; 772 }; 773 }; 774}; 775 776&psgtr { 777 status = "okay"; 778 /* nc, sata, usb3, dp */ 779 clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; 780 clock-names = "ref1", "ref2", "ref3"; 781}; 782 783&qspi { 784 status = "okay"; 785 is-dual = <1>; 786 flash@0 { 787 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ 788 #address-cells = <1>; 789 #size-cells = <1>; 790 reg = <0x0>; 791 spi-tx-bus-width = <1>; 792 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ 793 spi-max-frequency = <108000000>; /* Based on DC1 spec */ 794 partition@0 { /* for testing purpose */ 795 label = "qspi-fsbl-uboot"; 796 reg = <0x0 0x100000>; 797 }; 798 partition@100000 { /* for testing purpose */ 799 label = "qspi-linux"; 800 reg = <0x100000 0x500000>; 801 }; 802 partition@600000 { /* for testing purpose */ 803 label = "qspi-device-tree"; 804 reg = <0x600000 0x20000>; 805 }; 806 partition@620000 { /* for testing purpose */ 807 label = "qspi-rootfs"; 808 reg = <0x620000 0x5E0000>; 809 }; 810 }; 811}; 812 813&rtc { 814 status = "okay"; 815}; 816 817&sata { 818 status = "okay"; 819 /* SATA OOB timing settings */ 820 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 821 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 822 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 823 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 824 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; 825 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; 826 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; 827 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; 828 phy-names = "sata-phy"; 829 phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; 830}; 831 832/* SD1 with level shifter */ 833&sdhci1 { 834 status = "okay"; 835 pinctrl-names = "default"; 836 pinctrl-0 = <&pinctrl_sdhci1_default>; 837 disable-wp; 838 /* 839 * This property should be removed for supporting UHS mode 840 */ 841 no-1-8-v; 842 xlnx,mio-bank = <1>; 843}; 844 845&uart0 { 846 status = "okay"; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&pinctrl_uart0_default>; 849}; 850 851/* ULPI SMSC USB3320 */ 852&usb0 { 853 status = "okay"; 854 pinctrl-names = "default"; 855 pinctrl-0 = <&pinctrl_usb0_default>; 856}; 857 858&dwc3_0 { 859 status = "okay"; 860 dr_mode = "host"; 861 snps,usb3_lpm_capable; 862 phy-names = "usb3-phy"; 863 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; 864}; 865 866&zynqmp_dpdma { 867 status = "okay"; 868}; 869 870&zynqmp_dpsub { 871 status = "okay"; 872 phy-names = "dp-phy0", "dp-phy1"; 873 phys = <&psgtr 1 PHY_TYPE_DP 0 1>, 874 <&psgtr 0 PHY_TYPE_DP 1 1>; 875}; 876