1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2020 Toradex
4  */
5 
6 #include <common.h>
7 #include <command.h>
8 #include <image.h>
9 #include <init.h>
10 #include <log.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/ddr.h>
13 #include <asm/arch/imx8mm_pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <cpu_func.h>
20 #include <dm/device.h>
21 #include <dm/device-internal.h>
22 #include <dm/uclass.h>
23 #include <dm/uclass-internal.h>
24 #include <hang.h>
25 #include <i2c.h>
26 #include <power/bd71837.h>
27 #include <power/pca9450.h>
28 #include <power/pmic.h>
29 #include <spl.h>
30 
31 DECLARE_GLOBAL_DATA_PTR;
32 
33 #define I2C_PMIC_BUS_ID        1
34 
spl_board_boot_device(enum boot_device boot_dev_spl)35 int spl_board_boot_device(enum boot_device boot_dev_spl)
36 {
37 	switch (boot_dev_spl) {
38 	case MMC1_BOOT:
39 		return BOOT_DEVICE_MMC1;
40 	case SD2_BOOT:
41 	case MMC2_BOOT:
42 		return BOOT_DEVICE_MMC2;
43 	case SD3_BOOT:
44 	case MMC3_BOOT:
45 		return BOOT_DEVICE_MMC1;
46 	case USB_BOOT:
47 		return BOOT_DEVICE_BOARD;
48 	default:
49 		return BOOT_DEVICE_NONE;
50 	}
51 }
52 
spl_dram_init(void)53 void spl_dram_init(void)
54 {
55 	ddr_init(&dram_timing);
56 }
57 
spl_board_init(void)58 void spl_board_init(void)
59 {
60 	/* Serial download mode */
61 	if (is_usb_boot()) {
62 		puts("Back to ROM, SDP\n");
63 		restore_boot_params();
64 	}
65 	puts("Normal Boot\n");
66 }
67 
68 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)69 int board_fit_config_name_match(const char *name)
70 {
71 	/* Just empty function now - can't decide what to choose */
72 	debug("%s: %s\n", __func__, name);
73 
74 	return 0;
75 }
76 #endif
77 
78 #define UART_PAD_CTRL	(PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
80 
81 /* Verdin UART_3, Console/Debug UART */
82 static iomux_v3_cfg_t const uart_pads[] = {
83 	IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
84 	IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
85 };
86 
87 static iomux_v3_cfg_t const wdog_pads[] = {
88 	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
89 };
90 
board_early_init_f(void)91 int board_early_init_f(void)
92 {
93 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
94 
95 	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
96 
97 	set_wdog_reset(wdog);
98 
99 	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
100 
101 	return 0;
102 }
103 
power_init_board(void)104 int power_init_board(void)
105 {
106 	struct udevice *dev;
107 	int ret;
108 
109 	if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) {
110 		ret = pmic_get("pmic", &dev);
111 		if (ret == -ENODEV) {
112 			puts("No pmic found\n");
113 			return ret;
114 		}
115 
116 		if (ret != 0)
117 			return ret;
118 
119 		/* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
120 		pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
121 
122 		/* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */
123 		pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
124 
125 		/* set WDOG_B_CFG to cold reset */
126 		pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
127 
128 		pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
129 
130 		return 0;
131 	}
132 
133 	return 0;
134 }
135 
board_init_f(ulong dummy)136 void board_init_f(ulong dummy)
137 {
138 	struct udevice *dev;
139 	int ret;
140 
141 	arch_cpu_init();
142 
143 	init_uart_clk(0);
144 
145 	board_early_init_f();
146 
147 	timer_init();
148 
149 	preloader_console_init();
150 
151 	/* Clear the BSS. */
152 	memset(__bss_start, 0, __bss_end - __bss_start);
153 
154 	ret = spl_early_init();
155 	if (ret) {
156 		debug("spl_early_init() failed: %d\n", ret);
157 		hang();
158 	}
159 
160 	ret = uclass_get_device_by_name(UCLASS_CLK,
161 					"clock-controller@30380000",
162 					&dev);
163 	if (ret < 0) {
164 		printf("Failed to find clock node. Check device tree\n");
165 		hang();
166 	}
167 
168 	enable_tzc380();
169 
170 	power_init_board();
171 
172 	/* DDR initialization */
173 	spl_dram_init();
174 
175 	board_init_r(NULL, 0);
176 }
177