1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 * (C) Copyright 2002,2003 Motorola,Inc. 5 * Xianghua Xiao <X.Xiao@motorola.com> 6 */ 7 8 /* 9 * mpc8540ads board configuration file 10 * 11 * Please refer to doc/README.mpc85xx for more info. 12 * 13 * Make sure you change the MAC address and other network params first, 14 * search for CONFIG_SERVERIP, etc in this file. 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * default CCARBAR is at 0xff700000 22 * assume U-Boot is less than 0.5MB 23 */ 24 25 #ifndef CONFIG_HAS_FEC 26 #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ 27 #endif 28 29 #define CONFIG_PCI_INDIRECT_BRIDGE 30 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 31 32 /* 33 * sysclk for MPC85xx 34 * 35 * Two valid values are: 36 * 33000000 37 * 66000000 38 * 39 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 40 * is likely the desired value here, so that is now the default. 41 * The board, however, can run at 66MHz. In any event, this value 42 * must match the settings of some switches. Details can be found 43 * in the README.mpc85xxads. 44 * 45 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to 46 * 33MHz to accommodate, based on a PCI pin. 47 * Note that PCI-X won't work at 33MHz. 48 */ 49 50 #ifndef CONFIG_SYS_CLK_FREQ 51 #define CONFIG_SYS_CLK_FREQ 33000000 52 #endif 53 54 /* 55 * These can be toggled for performance analysis, otherwise use default. 56 */ 57 #define CONFIG_L2_CACHE /* toggle L2 cache */ 58 #define CONFIG_BTB /* toggle branch predition */ 59 60 #define CONFIG_SYS_CCSRBAR 0xe0000000 61 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 62 63 /* DDR Setup */ 64 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 65 #define CONFIG_DDR_SPD 66 67 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 68 69 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 70 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 71 72 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 73 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 74 75 /* I2C addresses of SPD EEPROMs */ 76 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 77 78 /* These are used when DDR doesn't use SPD. */ 79 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 80 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 81 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 82 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 83 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 84 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 85 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 86 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 87 88 /* 89 * SDRAM on the Local Bus 90 */ 91 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 92 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 93 94 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 95 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 96 97 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 98 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 99 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 100 #undef CONFIG_SYS_FLASH_CHECKSUM 101 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 102 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 103 104 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 105 106 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 107 #define CONFIG_SYS_RAMBOOT 108 #else 109 #undef CONFIG_SYS_RAMBOOT 110 #endif 111 112 #define CONFIG_SYS_FLASH_EMPTY_INFO 113 114 /* 115 * Local Bus Definitions 116 */ 117 118 /* 119 * Base Register 2 and Option Register 2 configure SDRAM. 120 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 121 * 122 * For BR2, need: 123 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 124 * port-size = 32-bits = BR2[19:20] = 11 125 * no parity checking = BR2[21:22] = 00 126 * SDRAM for MSEL = BR2[24:26] = 011 127 * Valid = BR[31] = 1 128 * 129 * 0 4 8 12 16 20 24 28 130 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 131 * 132 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 133 * FIXME: the top 17 bits of BR2. 134 */ 135 136 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 137 138 /* 139 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 140 * 141 * For OR2, need: 142 * 64MB mask for AM, OR2[0:7] = 1111 1100 143 * XAM, OR2[17:18] = 11 144 * 9 columns OR2[19-21] = 010 145 * 13 rows OR2[23-25] = 100 146 * EAD set for extra time OR[31] = 1 147 * 148 * 0 4 8 12 16 20 24 28 149 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 150 */ 151 152 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 153 154 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 155 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 156 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 157 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 158 159 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 160 | LSDMR_RFCR5 \ 161 | LSDMR_PRETOACT3 \ 162 | LSDMR_ACTTORW3 \ 163 | LSDMR_BL8 \ 164 | LSDMR_WRC2 \ 165 | LSDMR_CL3 \ 166 | LSDMR_RFEN \ 167 ) 168 169 /* 170 * SDRAM Controller configuration sequence. 171 */ 172 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 173 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 174 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 175 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 176 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 177 178 /* 179 * 32KB, 8-bit wide for ADS config reg 180 */ 181 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 182 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 183 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 184 185 #define CONFIG_SYS_INIT_RAM_LOCK 1 186 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 187 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 188 189 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 190 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 191 192 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 193 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 194 195 /* Serial Port */ 196 #define CONFIG_SYS_NS16550_SERIAL 197 #define CONFIG_SYS_NS16550_REG_SIZE 1 198 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 199 200 #define CONFIG_SYS_BAUDRATE_TABLE \ 201 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 202 203 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 204 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 205 206 /* 207 * I2C 208 */ 209 #define CONFIG_SYS_I2C 210 #define CONFIG_SYS_I2C_FSL 211 #define CONFIG_SYS_FSL_I2C_SPEED 400000 212 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 213 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 214 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 215 216 /* RapidIO MMU */ 217 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 218 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 219 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 220 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 221 222 /* 223 * General PCI 224 * Memory space is mapped 1-1, but I/O space must start from 0. 225 */ 226 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 227 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 228 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 229 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 230 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 231 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 232 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 233 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 234 235 #if defined(CONFIG_PCI) 236 237 #if !defined(CONFIG_PCI_PNP) 238 #define PCI_ENET0_IOADDR 0xe0000000 239 #define PCI_ENET0_MEMADDR 0xe0000000 240 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 241 #endif 242 243 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 244 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 245 246 #endif /* CONFIG_PCI */ 247 248 #if defined(CONFIG_TSEC_ENET) 249 250 #define CONFIG_TSEC1 1 251 #define CONFIG_TSEC1_NAME "TSEC0" 252 #define CONFIG_TSEC2 1 253 #define CONFIG_TSEC2_NAME "TSEC1" 254 #define TSEC1_PHY_ADDR 0 255 #define TSEC2_PHY_ADDR 1 256 #define TSEC1_PHYIDX 0 257 #define TSEC2_PHYIDX 0 258 #define TSEC1_FLAGS TSEC_GIGABIT 259 #define TSEC2_FLAGS TSEC_GIGABIT 260 261 #if CONFIG_HAS_FEC 262 #define CONFIG_MPC85XX_FEC 1 263 #define CONFIG_MPC85XX_FEC_NAME "FEC" 264 #define FEC_PHY_ADDR 3 265 #define FEC_PHYIDX 0 266 #define FEC_FLAGS 0 267 #endif 268 269 /* Options are: TSEC[0-1], FEC */ 270 #define CONFIG_ETHPRIME "TSEC0" 271 272 #endif /* CONFIG_TSEC_ENET */ 273 274 /* 275 * Environment 276 */ 277 278 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 279 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 280 281 /* 282 * BOOTP options 283 */ 284 #define CONFIG_BOOTP_BOOTFILESIZE 285 286 #undef CONFIG_WATCHDOG /* watchdog disabled */ 287 288 /* 289 * Miscellaneous configurable options 290 */ 291 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 292 293 /* 294 * For booting Linux, the board info and command line data 295 * have to be in the first 64 MB of memory, since this is 296 * the maximum mapped by the Linux kernel during initialization. 297 */ 298 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 299 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 300 301 #if defined(CONFIG_CMD_KGDB) 302 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 303 #endif 304 305 /* 306 * Environment Configuration 307 */ 308 309 /* The mac addresses for all ethernet interface */ 310 #if defined(CONFIG_TSEC_ENET) 311 #define CONFIG_HAS_ETH0 312 #define CONFIG_HAS_ETH1 313 #define CONFIG_HAS_ETH2 314 #endif 315 316 #define CONFIG_IPADDR 192.168.1.253 317 318 #define CONFIG_HOSTNAME "unknown" 319 #define CONFIG_ROOTPATH "/nfsroot" 320 #define CONFIG_BOOTFILE "your.uImage" 321 322 #define CONFIG_SERVERIP 192.168.1.1 323 #define CONFIG_GATEWAYIP 192.168.1.1 324 #define CONFIG_NETMASK 255.255.255.0 325 326 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 327 328 #define CONFIG_EXTRA_ENV_SETTINGS \ 329 "netdev=eth0\0" \ 330 "consoledev=ttyS0\0" \ 331 "ramdiskaddr=1000000\0" \ 332 "ramdiskfile=your.ramdisk.u-boot\0" \ 333 "fdtaddr=400000\0" \ 334 "fdtfile=your.fdt.dtb\0" 335 336 #define CONFIG_NFSBOOTCOMMAND \ 337 "setenv bootargs root=/dev/nfs rw " \ 338 "nfsroot=$serverip:$rootpath " \ 339 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 340 "console=$consoledev,$baudrate $othbootargs;" \ 341 "tftp $loadaddr $bootfile;" \ 342 "tftp $fdtaddr $fdtfile;" \ 343 "bootm $loadaddr - $fdtaddr" 344 345 #define CONFIG_RAMBOOTCOMMAND \ 346 "setenv bootargs root=/dev/ram rw " \ 347 "console=$consoledev,$baudrate $othbootargs;" \ 348 "tftp $ramdiskaddr $ramdiskfile;" \ 349 "tftp $loadaddr $bootfile;" \ 350 "tftp $fdtaddr $fdtfile;" \ 351 "bootm $loadaddr $ramdiskaddr $fdtaddr" 352 353 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 354 355 #endif /* __CONFIG_H */ 356