1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <common.h>
10 #include <init.h>
11 #include <linux/delay.h>
12 #include <linux/errno.h>
13 #include <asm/io.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/bootm.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <asm/mach-imx/dma.h>
20 #include <asm/mach-imx/hab.h>
21 #include <stdbool.h>
22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/arch/crm_regs.h>
24 #include <dm.h>
25 #include <imx_thermal.h>
26 #include <mmc.h>
27
28 struct scu_regs {
29 u32 ctrl;
30 u32 config;
31 u32 status;
32 u32 invalidate;
33 u32 fpga_rev;
34 };
35
36 #if defined(CONFIG_IMX_THERMAL)
37 static const struct imx_thermal_plat imx6_thermal_plat = {
38 .regs = (void *)ANATOP_BASE_ADDR,
39 .fuse_bank = 1,
40 .fuse_word = 6,
41 };
42
43 U_BOOT_DEVICE(imx6_thermal) = {
44 .name = "imx_thermal",
45 .platdata = &imx6_thermal_plat,
46 };
47 #endif
48
49 #if defined(CONFIG_IMX_HAB)
50 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
51 .bank = 0,
52 .word = 6,
53 };
54 #endif
55
get_nr_cpus(void)56 u32 get_nr_cpus(void)
57 {
58 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
59 return readl(&scu->config) & 3;
60 }
61
get_cpu_rev(void)62 u32 get_cpu_rev(void)
63 {
64 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
65 u32 reg = readl(&anatop->digprog_sololite);
66 u32 type = ((reg >> 16) & 0xff);
67 u32 major, cfg = 0;
68
69 if (type != MXC_CPU_MX6SL) {
70 reg = readl(&anatop->digprog);
71 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
72 cfg = readl(&scu->config) & 3;
73 type = ((reg >> 16) & 0xff);
74 if (type == MXC_CPU_MX6DL) {
75 if (!cfg)
76 type = MXC_CPU_MX6SOLO;
77 }
78
79 if (type == MXC_CPU_MX6Q) {
80 if (cfg == 1)
81 type = MXC_CPU_MX6D;
82 }
83
84 if (type == MXC_CPU_MX6ULL) {
85 if (readl(SRC_BASE_ADDR + 0x1c) & (1 << 6))
86 type = MXC_CPU_MX6ULZ;
87 }
88 }
89 major = ((reg >> 8) & 0xff);
90 if ((major >= 1) &&
91 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
92 major--;
93 type = MXC_CPU_MX6QP;
94 if (cfg == 1)
95 type = MXC_CPU_MX6DP;
96 }
97 reg &= 0xff; /* mx6 silicon revision */
98
99 /* For 6DQ, the value 0x00630005 is Silicon revision 1.3*/
100 if (((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D)) && (reg == 0x5))
101 reg = 0x3;
102
103 return (type << 12) | (reg + (0x10 * (major + 1)));
104 }
105
106 /*
107 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
108 * defines a 2-bit SPEED_GRADING
109 */
110 #define OCOTP_CFG3_SPEED_SHIFT 16
111 #define OCOTP_CFG3_SPEED_800MHZ 0
112 #define OCOTP_CFG3_SPEED_850MHZ 1
113 #define OCOTP_CFG3_SPEED_1GHZ 2
114 #define OCOTP_CFG3_SPEED_1P2GHZ 3
115
116 /*
117 * For i.MX6UL
118 */
119 #define OCOTP_CFG3_SPEED_528MHZ 1
120 #define OCOTP_CFG3_SPEED_696MHZ 2
121
122 /*
123 * For i.MX6ULL
124 */
125 #define OCOTP_CFG3_SPEED_792MHZ 2
126 #define OCOTP_CFG3_SPEED_900MHZ 3
127
get_cpu_speed_grade_hz(void)128 u32 get_cpu_speed_grade_hz(void)
129 {
130 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
131 struct fuse_bank *bank = &ocotp->bank[0];
132 struct fuse_bank0_regs *fuse =
133 (struct fuse_bank0_regs *)bank->fuse_regs;
134 uint32_t val;
135
136 val = readl(&fuse->cfg3);
137 val >>= OCOTP_CFG3_SPEED_SHIFT;
138 val &= 0x3;
139
140 if (is_mx6ul()) {
141 if (val == OCOTP_CFG3_SPEED_528MHZ)
142 return 528000000;
143 else if (val == OCOTP_CFG3_SPEED_696MHZ)
144 return 696000000;
145 else
146 return 0;
147 }
148
149 if (is_mx6ull()) {
150 if (val == OCOTP_CFG3_SPEED_528MHZ)
151 return 528000000;
152 else if (val == OCOTP_CFG3_SPEED_792MHZ)
153 return 792000000;
154 else if (val == OCOTP_CFG3_SPEED_900MHZ)
155 return 900000000;
156 else
157 return 0;
158 }
159
160 switch (val) {
161 /* Valid for IMX6DQ */
162 case OCOTP_CFG3_SPEED_1P2GHZ:
163 if (is_mx6dq() || is_mx6dqp())
164 return 1200000000;
165 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
166 case OCOTP_CFG3_SPEED_1GHZ:
167 return 996000000;
168 /* Valid for IMX6DQ */
169 case OCOTP_CFG3_SPEED_850MHZ:
170 if (is_mx6dq() || is_mx6dqp())
171 return 852000000;
172 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
173 case OCOTP_CFG3_SPEED_800MHZ:
174 return 792000000;
175 }
176 return 0;
177 }
178
179 /*
180 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
181 * defines a 2-bit Temperature Grade
182 *
183 * return temperature grade and min/max temperature in Celsius
184 */
185 #define OCOTP_MEM0_TEMP_SHIFT 6
186
get_cpu_temp_grade(int * minc,int * maxc)187 u32 get_cpu_temp_grade(int *minc, int *maxc)
188 {
189 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
190 struct fuse_bank *bank = &ocotp->bank[1];
191 struct fuse_bank1_regs *fuse =
192 (struct fuse_bank1_regs *)bank->fuse_regs;
193 uint32_t val;
194
195 val = readl(&fuse->mem0);
196 val >>= OCOTP_MEM0_TEMP_SHIFT;
197 val &= 0x3;
198
199 if (minc && maxc) {
200 if (val == TEMP_AUTOMOTIVE) {
201 *minc = -40;
202 *maxc = 125;
203 } else if (val == TEMP_INDUSTRIAL) {
204 *minc = -40;
205 *maxc = 105;
206 } else if (val == TEMP_EXTCOMMERCIAL) {
207 *minc = -20;
208 *maxc = 105;
209 } else {
210 *minc = 0;
211 *maxc = 95;
212 }
213 }
214 return val;
215 }
216
217 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)218 u32 __weak get_board_rev(void)
219 {
220 u32 cpurev = get_cpu_rev();
221 u32 type = ((cpurev >> 12) & 0xff);
222 if (type == MXC_CPU_MX6SOLO)
223 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
224
225 if (type == MXC_CPU_MX6D)
226 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
227
228 return cpurev;
229 }
230 #endif
231
clear_ldo_ramp(void)232 static void clear_ldo_ramp(void)
233 {
234 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
235 int reg;
236
237 /* ROM may modify LDO ramp up time according to fuse setting, so in
238 * order to be in the safe side we neeed to reset these settings to
239 * match the reset value: 0'b00
240 */
241 reg = readl(&anatop->ana_misc2);
242 reg &= ~(0x3f << 24);
243 writel(reg, &anatop->ana_misc2);
244 }
245
246 /*
247 * Set the PMU_REG_CORE register
248 *
249 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
250 * Possible values are from 0.725V to 1.450V in steps of
251 * 0.025V (25mV).
252 */
set_ldo_voltage(enum ldo_reg ldo,u32 mv)253 int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
254 {
255 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
256 u32 val, step, old, reg = readl(&anatop->reg_core);
257 u8 shift;
258
259 /* No LDO_SOC/PU/ARM */
260 if (is_mx6sll())
261 return 0;
262
263 if (mv < 725)
264 val = 0x00; /* Power gated off */
265 else if (mv > 1450)
266 val = 0x1F; /* Power FET switched full on. No regulation */
267 else
268 val = (mv - 700) / 25;
269
270 clear_ldo_ramp();
271
272 switch (ldo) {
273 case LDO_SOC:
274 shift = 18;
275 break;
276 case LDO_PU:
277 shift = 9;
278 break;
279 case LDO_ARM:
280 shift = 0;
281 break;
282 default:
283 return -EINVAL;
284 }
285
286 old = (reg & (0x1F << shift)) >> shift;
287 step = abs(val - old);
288 if (step == 0)
289 return 0;
290
291 reg = (reg & ~(0x1F << shift)) | (val << shift);
292 writel(reg, &anatop->reg_core);
293
294 /*
295 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
296 * step
297 */
298 udelay(3 * step);
299
300 return 0;
301 }
302
set_ahb_rate(u32 val)303 static void set_ahb_rate(u32 val)
304 {
305 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
306 u32 reg, div;
307
308 div = get_periph_clk() / val - 1;
309 reg = readl(&mxc_ccm->cbcdr);
310
311 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
312 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
313 }
314
clear_mmdc_ch_mask(void)315 static void clear_mmdc_ch_mask(void)
316 {
317 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
318 u32 reg;
319 reg = readl(&mxc_ccm->ccdr);
320
321 /* Clear MMDC channel mask */
322 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
323 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
324 else
325 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
326 writel(reg, &mxc_ccm->ccdr);
327 }
328
329 #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
330
init_bandgap(void)331 static void init_bandgap(void)
332 {
333 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
334 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
335 struct fuse_bank *bank = &ocotp->bank[1];
336 struct fuse_bank1_regs *fuse =
337 (struct fuse_bank1_regs *)bank->fuse_regs;
338 uint32_t val;
339
340 /*
341 * Ensure the bandgap has stabilized.
342 */
343 while (!(readl(&anatop->ana_misc0) & 0x80))
344 ;
345 /*
346 * For best noise performance of the analog blocks using the
347 * outputs of the bandgap, the reftop_selfbiasoff bit should
348 * be set.
349 */
350 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
351 /*
352 * On i.MX6ULL,we need to set VBGADJ bits according to the
353 * REFTOP_TRIM[3:0] in fuse table
354 * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
355 * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
356 * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
357 * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
358 * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
359 * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
360 * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
361 * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
362 */
363 if (is_mx6ull()) {
364 val = readl(&fuse->mem0);
365 val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
366 val &= 0x7;
367
368 writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
369 &anatop->ana_misc0_set);
370 }
371 }
372
373 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
noc_setup(void)374 static void noc_setup(void)
375 {
376 enable_ipu_clock();
377
378 writel(0x80000201, 0xbb0608);
379 /* Bypass IPU1 QoS generator */
380 writel(0x00000002, 0x00bb048c);
381 /* Bypass IPU2 QoS generator */
382 writel(0x00000002, 0x00bb050c);
383 /* Bandwidth THR for of PRE0 */
384 writel(0x00000200, 0x00bb0690);
385 /* Bandwidth THR for of PRE1 */
386 writel(0x00000200, 0x00bb0710);
387 /* Bandwidth THR for of PRE2 */
388 writel(0x00000200, 0x00bb0790);
389 /* Bandwidth THR for of PRE3 */
390 writel(0x00000200, 0x00bb0810);
391 /* Saturation THR for of PRE0 */
392 writel(0x00000010, 0x00bb0694);
393 /* Saturation THR for of PRE1 */
394 writel(0x00000010, 0x00bb0714);
395 /* Saturation THR for of PRE2 */
396 writel(0x00000010, 0x00bb0794);
397 /* Saturation THR for of PRE */
398 writel(0x00000010, 0x00bb0814);
399
400 disable_ipu_clock();
401 }
402 #endif
403
arch_cpu_init(void)404 int arch_cpu_init(void)
405 {
406 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
407
408 init_aips();
409
410 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
411 clear_mmdc_ch_mask();
412
413 /*
414 * Disable self-bias circuit in the analog bandap.
415 * The self-bias circuit is used by the bandgap during startup.
416 * This bit should be set after the bandgap has initialized.
417 */
418 init_bandgap();
419
420 if (!is_mx6ul() && !is_mx6ull()) {
421 /*
422 * When low freq boot is enabled, ROM will not set AHB
423 * freq, so we need to ensure AHB freq is 132MHz in such
424 * scenario.
425 *
426 * To i.MX6UL, when power up, default ARM core and
427 * AHB rate is 396M and 132M.
428 */
429 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
430 set_ahb_rate(132000000);
431 }
432
433 if (is_mx6ul()) {
434 if (is_soc_rev(CHIP_REV_1_0) == 0) {
435 /*
436 * According to the design team's requirement on
437 * i.MX6UL,the PMIC_STBY_REQ PAD should be configured
438 * as open drain 100K (0x0000b8a0).
439 * Only exists on TO1.0
440 */
441 writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c);
442 } else {
443 /*
444 * From TO1.1, SNVS adds internal pull up control
445 * for POR_B, the register filed is GPBIT[1:0],
446 * after system boot up, it can be set to 2b'01
447 * to disable internal pull up.It can save about
448 * 30uA power in SNVS mode.
449 */
450 writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) &
451 (~0x1400)) | 0x400,
452 MX6UL_SNVS_LP_BASE_ADDR + 0x10);
453 }
454 }
455
456 if (is_mx6ull()) {
457 /*
458 * GPBIT[1:0] is suggested to set to 2'b11:
459 * 2'b00 : always PUP100K
460 * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
461 * 2'b10 : always disable PUP100K
462 * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
463 * register offset is different from i.MX6UL, since
464 * i.MX6UL is fixed by ECO.
465 */
466 writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
467 0x3, MX6UL_SNVS_LP_BASE_ADDR);
468 }
469
470 /* Set perclk to source from OSC 24MHz */
471 if (is_mx6sl())
472 setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
473
474 imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */
475
476 if (is_mx6sx())
477 setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
478
479 init_src();
480
481 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
482 if (is_mx6dqp())
483 noc_setup();
484 #endif
485 return 0;
486 }
487
488 #ifdef CONFIG_ENV_IS_IN_MMC
board_mmc_get_env_dev(int devno)489 __weak int board_mmc_get_env_dev(int devno)
490 {
491 return CONFIG_SYS_MMC_ENV_DEV;
492 }
493
mmc_get_boot_dev(void)494 static int mmc_get_boot_dev(void)
495 {
496 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
497 u32 soc_sbmr = readl(&src_regs->sbmr1);
498 u32 bootsel;
499 int devno;
500
501 /*
502 * Refer to
503 * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
504 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
505 * i.MX6SL/SX/UL has same layout.
506 */
507 bootsel = (soc_sbmr & 0x000000FF) >> 6;
508
509 /* No boot from sd/mmc */
510 if (bootsel != 1)
511 return -1;
512
513 /* BOOT_CFG2[3] and BOOT_CFG2[4] */
514 devno = (soc_sbmr & 0x00001800) >> 11;
515
516 return devno;
517 }
518
mmc_get_env_dev(void)519 int mmc_get_env_dev(void)
520 {
521 int devno = mmc_get_boot_dev();
522
523 /* If not boot from sd/mmc, use default value */
524 if (devno < 0)
525 return CONFIG_SYS_MMC_ENV_DEV;
526
527 return board_mmc_get_env_dev(devno);
528 }
529
530 #ifdef CONFIG_SYS_MMC_ENV_PART
board_mmc_get_env_part(int devno)531 __weak int board_mmc_get_env_part(int devno)
532 {
533 return CONFIG_SYS_MMC_ENV_PART;
534 }
535
mmc_get_env_part(struct mmc * mmc)536 uint mmc_get_env_part(struct mmc *mmc)
537 {
538 int devno = mmc_get_boot_dev();
539
540 /* If not boot from sd/mmc, use default value */
541 if (devno < 0)
542 return CONFIG_SYS_MMC_ENV_PART;
543
544 return board_mmc_get_env_part(devno);
545 }
546 #endif
547 #endif
548
board_postclk_init(void)549 int board_postclk_init(void)
550 {
551 /* NO LDO SOC on i.MX6SLL */
552 if (is_mx6sll())
553 return 0;
554
555 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
556
557 return 0;
558 }
559
560 #ifndef CONFIG_SPL_BUILD
561 /*
562 * cfg_val will be used for
563 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
564 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
565 * instead of SBMR1 to determine the boot device.
566 */
567 const struct boot_mode soc_boot_modes[] = {
568 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
569 /* reserved value should start rom usb */
570 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
571 {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
572 #else
573 {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
574 #endif
575 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
576 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
577 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
578 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
579 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
580 /* 4 bit bus width */
581 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
582 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
583 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
584 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
585 {NULL, 0},
586 };
587 #endif
588
reset_misc(void)589 void reset_misc(void)
590 {
591 #ifndef CONFIG_SPL_BUILD
592 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
593 lcdif_power_down();
594 #endif
595 #endif
596 }
597
s_init(void)598 void s_init(void)
599 {
600 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
601 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
602 u32 mask480;
603 u32 mask528;
604 u32 reg, periph1, periph2;
605
606 if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
607 return;
608
609 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
610 * to make sure PFD is working right, otherwise, PFDs may
611 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
612 * workaround in ROM code, as bus clock need it
613 */
614
615 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
616 ANATOP_PFD_CLKGATE_MASK(1) |
617 ANATOP_PFD_CLKGATE_MASK(2) |
618 ANATOP_PFD_CLKGATE_MASK(3);
619 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
620 ANATOP_PFD_CLKGATE_MASK(3);
621
622 reg = readl(&ccm->cbcmr);
623 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
624 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
625 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
626 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
627
628 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
629 if ((periph2 != 0x2) && (periph1 != 0x2))
630 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
631
632 if ((periph2 != 0x1) && (periph1 != 0x1) &&
633 (periph2 != 0x3) && (periph1 != 0x3))
634 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
635
636 writel(mask480, &anatop->pfd_480_set);
637 writel(mask528, &anatop->pfd_528_set);
638 writel(mask480, &anatop->pfd_480_clr);
639 writel(mask528, &anatop->pfd_528_clr);
640 }
641
642 #ifdef CONFIG_IMX_HDMI
imx_enable_hdmi_phy(void)643 void imx_enable_hdmi_phy(void)
644 {
645 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
646 u8 reg;
647 reg = readb(&hdmi->phy_conf0);
648 reg |= HDMI_PHY_CONF0_PDZ_MASK;
649 writeb(reg, &hdmi->phy_conf0);
650 udelay(3000);
651 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
652 writeb(reg, &hdmi->phy_conf0);
653 udelay(3000);
654 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
655 writeb(reg, &hdmi->phy_conf0);
656 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
657 }
658
imx_setup_hdmi(void)659 void imx_setup_hdmi(void)
660 {
661 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
662 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
663 int reg, count;
664 u8 val;
665
666 /* Turn on HDMI PHY clock */
667 reg = readl(&mxc_ccm->CCGR2);
668 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
669 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
670 writel(reg, &mxc_ccm->CCGR2);
671 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
672 reg = readl(&mxc_ccm->chsccdr);
673 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
674 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
675 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
676 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
677 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
678 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
679 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
680 writel(reg, &mxc_ccm->chsccdr);
681
682 /* Clear the overflow condition */
683 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
684 /* TMDS software reset */
685 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
686 val = readb(&hdmi->fc_invidconf);
687 /* Need minimum 3 times to write to clear the register */
688 for (count = 0 ; count < 5 ; count++)
689 writeb(val, &hdmi->fc_invidconf);
690 }
691 }
692 #endif
693
694
695 /*
696 * gpr_init() function is common for boards using MX6S, MX6DL, MX6D,
697 * MX6Q and MX6QP processors
698 */
gpr_init(void)699 void gpr_init(void)
700 {
701 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
702
703 /*
704 * If this function is used in a common MX6 spl implementation
705 * we have to ensure that it is only called for suitable cpu types,
706 * otherwise it breaks hardware parts like enet1, can1, can2, etc.
707 */
708 if (!is_mx6dqp() && !is_mx6dq() && !is_mx6sdl())
709 return;
710
711 /* enable AXI cache for VDOA/VPU/IPU */
712 writel(0xF00000CF, &iomux->gpr[4]);
713 if (is_mx6dqp()) {
714 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
715 writel(0x77177717, &iomux->gpr[6]);
716 writel(0x77177717, &iomux->gpr[7]);
717 } else {
718 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
719 writel(0x007F007F, &iomux->gpr[6]);
720 writel(0x007F007F, &iomux->gpr[7]);
721 }
722 }
723