1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <fdt_support.h>
8 #include <init.h>
9 #include <log.h>
10 #include <spl.h>
11 #include <spl_gpio.h>
12 #include <syscon.h>
13 #include <asm/armv8/mmu.h>
14 #include <asm/io.h>
15 #include <asm/arch-rockchip/bootrom.h>
16 #include <asm/arch-rockchip/clock.h>
17 #include <asm/arch-rockchip/gpio.h>
18 #include <asm/arch-rockchip/grf_rk3399.h>
19 #include <asm/arch-rockchip/hardware.h>
20 #include <linux/bitops.h>
21 #include <power/regulator.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 #define GRF_EMMCCORE_CON11 0xff77f02c
26 #define GRF_BASE 0xff770000
27
28 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
29 [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
30 [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
31 [BROM_BOOTSOURCE_SD] = "/mmc@fe320000",
32 };
33
34 static struct mm_region rk3399_mem_map[] = {
35 {
36 .virt = 0x0UL,
37 .phys = 0x0UL,
38 .size = 0xf8000000UL,
39 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
40 PTE_BLOCK_INNER_SHARE
41 }, {
42 .virt = 0xf8000000UL,
43 .phys = 0xf8000000UL,
44 .size = 0x08000000UL,
45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46 PTE_BLOCK_NON_SHARE |
47 PTE_BLOCK_PXN | PTE_BLOCK_UXN
48 }, {
49 /* List terminator */
50 0,
51 }
52 };
53
54 struct mm_region *mem_map = rk3399_mem_map;
55
56 #ifdef CONFIG_SPL_BUILD
57
58 #define TIMER_END_COUNT_L 0x00
59 #define TIMER_END_COUNT_H 0x04
60 #define TIMER_INIT_COUNT_L 0x10
61 #define TIMER_INIT_COUNT_H 0x14
62 #define TIMER_CONTROL_REG 0x1c
63
64 #define TIMER_EN 0x1
65 #define TIMER_FMODE BIT(0)
66 #define TIMER_RMODE BIT(1)
67
rockchip_stimer_init(void)68 void rockchip_stimer_init(void)
69 {
70 /* If Timer already enabled, don't re-init it */
71 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
72
73 if (reg & TIMER_EN)
74 return;
75
76 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
77 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
78 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
79 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
80 writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
81 TIMER_CONTROL_REG);
82 }
83 #endif
84
arch_cpu_init(void)85 int arch_cpu_init(void)
86 {
87
88 #ifdef CONFIG_SPL_BUILD
89 struct rk3399_pmusgrf_regs *sgrf;
90 struct rk3399_grf_regs *grf;
91
92 /*
93 * Disable DDR and SRAM security regions.
94 *
95 * As we are entered from the BootROM, the region from
96 * 0x0 through 0xfffff (i.e. the first MB of memory) will
97 * be protected. This will cause issues with the DW_MMC
98 * driver, which tries to DMA from/to the stack (likely)
99 * located in this range.
100 */
101 sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
102 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
103 rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
104
105 /* eMMC clock generator: disable the clock multipilier */
106 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
107 rk_clrreg(&grf->emmccore_con[11], 0x0ff);
108 #endif
109
110 return 0;
111 }
112
113 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)114 void board_debug_uart_init(void)
115 {
116 #define GRF_BASE 0xff770000
117 #define GPIO0_BASE 0xff720000
118 #define PMUGRF_BASE 0xff320000
119 struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
120 #ifdef CONFIG_TARGET_CHROMEBOOK_BOB
121 struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
122 struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
123 #endif
124
125 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
126 /* Enable early UART0 on the RK3399 */
127 rk_clrsetreg(&grf->gpio2c_iomux,
128 GRF_GPIO2C0_SEL_MASK,
129 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
130 rk_clrsetreg(&grf->gpio2c_iomux,
131 GRF_GPIO2C1_SEL_MASK,
132 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
133 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
134 /* Enable early UART3 on the RK3399 */
135 rk_clrsetreg(&grf->gpio3b_iomux,
136 GRF_GPIO3B6_SEL_MASK,
137 GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
138 rk_clrsetreg(&grf->gpio3b_iomux,
139 GRF_GPIO3B7_SEL_MASK,
140 GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
141 #else
142 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB
143 rk_setreg(&grf->io_vsel, 1 << 0);
144
145 /*
146 * Let's enable these power rails here, we are already running the SPI
147 * Flash based code.
148 */
149 spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
150 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
151
152 spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
153 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
154 #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
155
156 /* Enable early UART2 channel C on the RK3399 */
157 rk_clrsetreg(&grf->gpio4c_iomux,
158 GRF_GPIO4C3_SEL_MASK,
159 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
160 rk_clrsetreg(&grf->gpio4c_iomux,
161 GRF_GPIO4C4_SEL_MASK,
162 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
163 /* Set channel C as UART2 input */
164 rk_clrsetreg(&grf->soc_con7,
165 GRF_UART_DBG_SEL_MASK,
166 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
167 #endif
168 }
169 #endif
170
171 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
spl_decode_boot_device(u32 boot_device)172 const char *spl_decode_boot_device(u32 boot_device)
173 {
174 int i;
175 static const struct {
176 u32 boot_device;
177 const char *ofpath;
178 } spl_boot_devices_tbl[] = {
179 { BOOT_DEVICE_MMC1, "/mmc@fe320000" },
180 { BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
181 { BOOT_DEVICE_SPI, "/spi@ff1d0000" },
182 };
183
184 for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
185 if (spl_boot_devices_tbl[i].boot_device == boot_device)
186 return spl_boot_devices_tbl[i].ofpath;
187
188 return NULL;
189 }
190
spl_perform_fixups(struct spl_image_info * spl_image)191 void spl_perform_fixups(struct spl_image_info *spl_image)
192 {
193 void *blob = spl_image->fdt_addr;
194 const char *boot_ofpath;
195 int chosen;
196
197 /*
198 * Inject the ofpath of the device the full U-Boot (or Linux in
199 * Falcon-mode) was booted from into the FDT, if a FDT has been
200 * loaded at the same time.
201 */
202 if (!blob)
203 return;
204
205 boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
206 if (!boot_ofpath) {
207 pr_err("%s: could not map boot_device to ofpath\n", __func__);
208 return;
209 }
210
211 chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
212 if (chosen < 0) {
213 pr_err("%s: could not find/create '/chosen'\n", __func__);
214 return;
215 }
216 fdt_setprop_string(blob, chosen,
217 "u-boot,spl-boot-device", boot_ofpath);
218 }
219
220 #if defined(SPL_GPIO_SUPPORT)
rk3399_force_power_on_reset(void)221 static void rk3399_force_power_on_reset(void)
222 {
223 ofnode node;
224 struct gpio_desc sysreset_gpio;
225
226 debug("%s: trying to force a power-on reset\n", __func__);
227
228 node = ofnode_path("/config");
229 if (!ofnode_valid(node)) {
230 debug("%s: no /config node?\n", __func__);
231 return;
232 }
233
234 if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
235 &sysreset_gpio, GPIOD_IS_OUT)) {
236 debug("%s: could not find a /config/sysreset-gpio\n", __func__);
237 return;
238 }
239
240 dm_gpio_set_value(&sysreset_gpio, 1);
241 }
242 #endif
243
spl_board_init(void)244 void spl_board_init(void)
245 {
246 #if defined(SPL_GPIO_SUPPORT)
247 struct rockchip_cru *cru = rockchip_get_cru();
248
249 /*
250 * The RK3399 resets only 'almost all logic' (see also in the TRM
251 * "3.9.4 Global software reset"), when issuing a software reset.
252 * This may cause issues during boot-up for some configurations of
253 * the application software stack.
254 *
255 * To work around this, we test whether the last reset reason was
256 * a power-on reset and (if not) issue an overtemp-reset to reset
257 * the entire module.
258 *
259 * While this was previously fixed by modifying the various places
260 * that could generate a software reset (e.g. U-Boot's sysreset
261 * driver, the ATF or Linux), we now have it here to ensure that
262 * we no longer have to track this through the various components.
263 */
264 if (cru->glb_rst_st != 0)
265 rk3399_force_power_on_reset();
266 #endif
267
268 #if defined(SPL_DM_REGULATOR)
269 /*
270 * Turning the eMMC and SPI back on (if disabled via the Qseven
271 * BIOS_ENABLE) signal is done through a always-on regulator).
272 */
273 if (regulators_enable_boot_on(false))
274 debug("%s: Cannot enable boot on regulator\n", __func__);
275 #endif
276 }
277 #endif
278