1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * UniPhier SG (SoC Glue) block registers
4  *
5  * Copyright (C) 2011-2015 Copyright (C) 2011-2015 Panasonic Corporation
6  * Copyright (C) 2016-2017 Socionext Inc.
7  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8  */
9 
10 #ifndef UNIPHIER_SG_REGS_H
11 #define UNIPHIER_SG_REGS_H
12 
13 #ifndef __ASSEMBLY__
14 #include <linux/compiler.h>
15 #ifdef CONFIG_ARCH_UNIPHIER_V8_MULTI
16 extern void __iomem *sg_base;
17 #else
18 #define sg_base			((void __iomem *)SG_BASE)
19 #endif
20 #endif /* __ASSEMBLY__ */
21 
22 /* Base Address */
23 #define SG_BASE			0x5f800000
24 
25 /* Revision */
26 #define SG_REVISION		0x0000
27 
28 /* Memory Configuration */
29 #define SG_MEMCONF		0x0400
30 
31 #define SG_MEMCONF_CH0_SZ_MASK		((0x1 << 10) | (0x03 << 0))
32 #define SG_MEMCONF_CH0_SZ_64M		((0x0 << 10) | (0x01 << 0))
33 #define SG_MEMCONF_CH0_SZ_128M		((0x0 << 10) | (0x02 << 0))
34 #define SG_MEMCONF_CH0_SZ_256M		((0x0 << 10) | (0x03 << 0))
35 #define SG_MEMCONF_CH0_SZ_512M		((0x1 << 10) | (0x00 << 0))
36 #define SG_MEMCONF_CH0_SZ_1G		((0x1 << 10) | (0x01 << 0))
37 #define SG_MEMCONF_CH0_NUM_MASK		(0x1 << 8)
38 #define SG_MEMCONF_CH0_NUM_1		(0x1 << 8)
39 #define SG_MEMCONF_CH0_NUM_2		(0x0 << 8)
40 
41 #define SG_MEMCONF_CH1_SZ_MASK		((0x1 << 11) | (0x03 << 2))
42 #define SG_MEMCONF_CH1_SZ_64M		((0x0 << 11) | (0x01 << 2))
43 #define SG_MEMCONF_CH1_SZ_128M		((0x0 << 11) | (0x02 << 2))
44 #define SG_MEMCONF_CH1_SZ_256M		((0x0 << 11) | (0x03 << 2))
45 #define SG_MEMCONF_CH1_SZ_512M		((0x1 << 11) | (0x00 << 2))
46 #define SG_MEMCONF_CH1_SZ_1G		((0x1 << 11) | (0x01 << 2))
47 #define SG_MEMCONF_CH1_NUM_MASK		(0x1 << 9)
48 #define SG_MEMCONF_CH1_NUM_1		(0x1 << 9)
49 #define SG_MEMCONF_CH1_NUM_2		(0x0 << 9)
50 
51 #define SG_MEMCONF_CH2_SZ_MASK		((0x1 << 26) | (0x03 << 16))
52 #define SG_MEMCONF_CH2_SZ_64M		((0x0 << 26) | (0x01 << 16))
53 #define SG_MEMCONF_CH2_SZ_128M		((0x0 << 26) | (0x02 << 16))
54 #define SG_MEMCONF_CH2_SZ_256M		((0x0 << 26) | (0x03 << 16))
55 #define SG_MEMCONF_CH2_SZ_512M		((0x1 << 26) | (0x00 << 16))
56 #define SG_MEMCONF_CH2_SZ_1G		((0x1 << 26) | (0x01 << 16))
57 #define SG_MEMCONF_CH2_NUM_MASK		(0x1 << 24)
58 #define SG_MEMCONF_CH2_NUM_1		(0x1 << 24)
59 #define SG_MEMCONF_CH2_NUM_2		(0x0 << 24)
60 /* PH1-LD6b, ProXstream2, PH1-LD20 only */
61 #define SG_MEMCONF_CH2_DISABLE		(0x1 << 21)
62 
63 #define SG_MEMCONF_SPARSEMEM		(0x1 << 4)
64 
65 #define SG_USBPHYCTRL		0x0500
66 #define SG_ETPHYPSHUT		0x0554
67 #define SG_ETPHYCNT		0x0550
68 
69 /* Pin Control */
70 #define SG_PINCTRL_BASE		0x1000
71 
72 /* PH1-Pro4, PH1-Pro5 */
73 #define SG_LOADPINCTRL		0x1700
74 
75 /* Input Enable */
76 #define SG_IECTRL		0x1d00
77 
78 /* Pin Monitor */
79 #define SG_PINMON0		0x00100100
80 #define SG_PINMON2		0x00100108
81 
82 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK	(0x3 << 19)
83 #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT	(0x0 << 19)
84 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A	(0x2 << 19)
85 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B	(0x3 << 19)
86 
87 #define SG_PINMON0_CLK_MODE_AXOSEL_MASK		(0x3 << 16)
88 #define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ	(0x0 << 16)
89 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ	(0x1 << 16)
90 #define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ	(0x2 << 16)
91 #define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ	(0x3 << 16)
92 
93 #define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT	(0x0 << 16)
94 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U	(0x1 << 16)
95 #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ	(0x2 << 16)
96 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A	(0x3 << 16)
97 
98 #endif /* UNIPHIER_SG_REGS_H */
99