1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * fec.h -- Fast Ethernet Controller definitions
4  *
5  * Some definitions copied from commproc.h for MPC8xx:
6  * MPC8xx Communication Processor Module.
7  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
8  *
9  * Add FEC Structure and definitions
10  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
11  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
12  */
13 
14 #ifndef	fec_h
15 #define	fec_h
16 
17 #include <phy.h>
18 
19 /* Buffer descriptors used FEC.
20 */
21 typedef struct cpm_buf_desc {
22 	ushort cbd_sc;		/* Status and Control */
23 	ushort cbd_datlen;	/* Data length in buffer */
24 	uint cbd_bufaddr;	/* Buffer address in host memory */
25 } cbd_t;
26 
27 #define BD_SC_EMPTY		((ushort)0x8000)	/* Receive is empty */
28 #define BD_SC_READY		((ushort)0x8000)	/* Transmit is ready */
29 #define BD_SC_WRAP		((ushort)0x2000)	/* Last buffer descriptor */
30 #define BD_SC_INTRPT		((ushort)0x1000)	/* Interrupt on change */
31 #define BD_SC_LAST		((ushort)0x0800)	/* Last buffer in frame */
32 #define BD_SC_TC		((ushort)0x0400)	/* Transmit CRC */
33 #define BD_SC_CM		((ushort)0x0200)	/* Continous mode */
34 #define BD_SC_ID		((ushort)0x0100)	/* Rec'd too many idles */
35 #define BD_SC_P			((ushort)0x0100)	/* xmt preamble */
36 #define BD_SC_BR		((ushort)0x0020)	/* Break received */
37 #define BD_SC_FR		((ushort)0x0010)	/* Framing error */
38 #define BD_SC_PR		((ushort)0x0008)	/* Parity error */
39 #define BD_SC_OV		((ushort)0x0002)	/* Overrun */
40 #define BD_SC_CD		((ushort)0x0001)	/* Carrier Detect lost */
41 
42 /* Buffer descriptor control/status used by Ethernet receive.
43 */
44 #define BD_ENET_RX_EMPTY	((ushort)0x8000)
45 #define BD_ENET_RX_RO1		((ushort)0x4000)
46 #define BD_ENET_RX_WRAP		((ushort)0x2000)
47 #define BD_ENET_RX_INTR		((ushort)0x1000)
48 #define BD_ENET_RX_RO2		BD_ENET_RX_INTR
49 #define BD_ENET_RX_LAST		((ushort)0x0800)
50 #define BD_ENET_RX_FIRST	((ushort)0x0400)
51 #define BD_ENET_RX_MISS		((ushort)0x0100)
52 #define BD_ENET_RX_BC		((ushort)0x0080)
53 #define BD_ENET_RX_MC		((ushort)0x0040)
54 #define BD_ENET_RX_LG		((ushort)0x0020)
55 #define BD_ENET_RX_NO		((ushort)0x0010)
56 #define BD_ENET_RX_SH		((ushort)0x0008)
57 #define BD_ENET_RX_CR		((ushort)0x0004)
58 #define BD_ENET_RX_OV		((ushort)0x0002)
59 #define BD_ENET_RX_CL		((ushort)0x0001)
60 #define BD_ENET_RX_TR		BD_ENET_RX_CL
61 #define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
62 
63 /* Buffer descriptor control/status used by Ethernet transmit.
64 */
65 #define BD_ENET_TX_READY	((ushort)0x8000)
66 #define BD_ENET_TX_PAD		((ushort)0x4000)
67 #define BD_ENET_TX_TO1		BD_ENET_TX_PAD
68 #define BD_ENET_TX_WRAP		((ushort)0x2000)
69 #define BD_ENET_TX_INTR		((ushort)0x1000)
70 #define BD_ENET_TX_TO2		BD_ENET_TX_INTR_
71 #define BD_ENET_TX_LAST		((ushort)0x0800)
72 #define BD_ENET_TX_TC		((ushort)0x0400)
73 #define BD_ENET_TX_DEF		((ushort)0x0200)
74 #define BD_ENET_TX_ABC		BD_ENET_TX_DEF
75 #define BD_ENET_TX_HB		((ushort)0x0100)
76 #define BD_ENET_TX_LC		((ushort)0x0080)
77 #define BD_ENET_TX_RL		((ushort)0x0040)
78 #define BD_ENET_TX_RCMASK	((ushort)0x003c)
79 #define BD_ENET_TX_UN		((ushort)0x0002)
80 #define BD_ENET_TX_CSL		((ushort)0x0001)
81 #define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
82 
83 /*********************************************************************
84 * Fast Ethernet Controller (FEC)
85 *********************************************************************/
86 /* FEC private information */
87 struct fec_info_s {
88 	int index;
89 	u32 iobase;
90 	u32 pinmux;
91 	u32 miibase;
92 	int phy_addr;
93 	int dup_spd;
94 	char *phy_name;
95 	int phyname_init;
96 	cbd_t *rxbd;		/* Rx BD */
97 	cbd_t *txbd;		/* Tx BD */
98 	uint rx_idx;
99 	uint tx_idx;
100 	char *txbuf;
101 	int initialized;
102 	int to_loop;
103 	struct mii_dev *bus;
104 };
105 
106 #ifdef CONFIG_MCFFEC
107 /* Register read/write struct */
108 typedef struct fec {
109 #ifdef CONFIG_M5272
110 	u32 ecr;		/* 0x00 */
111 	u32 eir;		/* 0x04 */
112 	u32 eimr;		/* 0x08 */
113 	u32 ivsr;		/* 0x0C */
114 	u32 rdar;		/* 0x10 */
115 	u32 tdar;		/* 0x14 */
116 	u8 resv1[0x28];		/* 0x18 */
117 	u32 mmfr;		/* 0x40 */
118 	u32 mscr;		/* 0x44 */
119 	u8 resv2[0x44];		/* 0x48 */
120 	u32 frbr;		/* 0x8C */
121 	u32 frsr;		/* 0x90 */
122 	u8 resv3[0x10];		/* 0x94 */
123 	u32 tfwr;		/* 0xA4 */
124 	u32 res4;		/* 0xA8 */
125 	u32 tfsr;		/* 0xAC */
126 	u8 resv4[0x50];		/* 0xB0 */
127 	u32 opd;		/* 0x100 - dummy  */
128 	u32 rcr;		/* 0x104 */
129 	u32 mibc;		/* 0x108 */
130 	u8 resv5[0x38];		/* 0x10C */
131 	u32 tcr;		/* 0x144 */
132 	u8 resv6[0x270];	/* 0x148 */
133 	u32 iaur;		/* 0x3B8 - dummy */
134 	u32 ialr;		/* 0x3BC - dummy  */
135 	u32 palr;		/* 0x3C0 */
136 	u32 paur;		/* 0x3C4 */
137 	u32 gaur;		/* 0x3C8 */
138 	u32 galr;		/* 0x3CC */
139 	u32 erdsr;		/* 0x3D0 */
140 	u32 etdsr;		/* 0x3D4 */
141 	u32 emrbr;		/* 0x3D8 */
142 	u8 resv12[0x74];	/* 0x18C */
143 #else
144 	u8 resv0[0x4];
145 	u32 eir;
146 	u32 eimr;
147 	u8 resv1[0x4];
148 	u32 rdar;
149 	u32 tdar;
150 	u8 resv2[0xC];
151 	u32 ecr;
152 	u8 resv3[0x18];
153 	u32 mmfr;
154 	u32 mscr;
155 	u8 resv4[0x1C];
156 	u32 mibc;
157 	u8 resv5[0x1C];
158 	u32 rcr;
159 	u8 resv6[0x3C];
160 	u32 tcr;
161 	u8 resv7[0x1C];
162 	u32 palr;
163 	u32 paur;
164 	u32 opd;
165 	u8 resv8[0x28];
166 	u32 iaur;
167 	u32 ialr;
168 	u32 gaur;
169 	u32 galr;
170 	u8 resv9[0x1C];
171 	u32 tfwr;
172 	u8 resv10[0x4];
173 	u32 frbr;
174 	u32 frsr;
175 	u8 resv11[0x2C];
176 	u32 erdsr;
177 	u32 etdsr;
178 	u32 emrbr;
179 	u8 resv12[0x74];
180 #endif
181 
182 	u32 rmon_t_drop;
183 	u32 rmon_t_packets;
184 	u32 rmon_t_bc_pkt;
185 	u32 rmon_t_mc_pkt;
186 	u32 rmon_t_crc_align;
187 	u32 rmon_t_undersize;
188 	u32 rmon_t_oversize;
189 	u32 rmon_t_frag;
190 	u32 rmon_t_jab;
191 	u32 rmon_t_col;
192 	u32 rmon_t_p64;
193 	u32 rmon_t_p65to127;
194 	u32 rmon_t_p128to255;
195 	u32 rmon_t_p256to511;
196 	u32 rmon_t_p512to1023;
197 	u32 rmon_t_p1024to2047;
198 	u32 rmon_t_p_gte2048;
199 	u32 rmon_t_octets;
200 
201 	u32 ieee_t_drop;
202 	u32 ieee_t_frame_ok;
203 	u32 ieee_t_1col;
204 	u32 ieee_t_mcol;
205 	u32 ieee_t_def;
206 	u32 ieee_t_lcol;
207 	u32 ieee_t_excol;
208 	u32 ieee_t_macerr;
209 	u32 ieee_t_cserr;
210 	u32 ieee_t_sqe;
211 	u32 ieee_t_fdxfc;
212 	u32 ieee_t_octets_ok;
213 	u8 resv13[0x8];
214 
215 	u32 rmon_r_drop;
216 	u32 rmon_r_packets;
217 	u32 rmon_r_bc_pkt;
218 	u32 rmon_r_mc_pkt;
219 	u32 rmon_r_crc_align;
220 	u32 rmon_r_undersize;
221 	u32 rmon_r_oversize;
222 	u32 rmon_r_frag;
223 	u32 rmon_r_jab;
224 	u32 rmon_r_resvd_0;
225 	u32 rmon_r_p64;
226 	u32 rmon_r_p65to127;
227 	u32 rmon_r_p128to255;
228 	u32 rmon_r_p256to511;
229 	u32 rmon_r_p512to1023;
230 	u32 rmon_r_p1024to2047;
231 	u32 rmon_r_p_gte2048;
232 	u32 rmon_r_octets;
233 
234 	u32 ieee_r_drop;
235 	u32 ieee_r_frame_ok;
236 	u32 ieee_r_crc;
237 	u32 ieee_r_align;
238 	u32 ieee_r_macerr;
239 	u32 ieee_r_fdxfc;
240 	u32 ieee_r_octets_ok;
241 } fec_t;
242 #endif				/* CONFIG_MCFFEC */
243 
244 /*********************************************************************
245 * Fast Ethernet Controller (FEC)
246 *********************************************************************/
247 /* Bit definitions and macros for FEC_EIR */
248 #define FEC_EIR_CLEAR_ALL		(0xFFF80000)
249 #define FEC_EIR_HBERR			(0x80000000)
250 #define FEC_EIR_BABR			(0x40000000)
251 #define FEC_EIR_BABT			(0x20000000)
252 #define FEC_EIR_GRA			(0x10000000)
253 #define FEC_EIR_TXF			(0x08000000)
254 #define FEC_EIR_TXB			(0x04000000)
255 #define FEC_EIR_RXF			(0x02000000)
256 #define FEC_EIR_RXB			(0x01000000)
257 #define FEC_EIR_MII			(0x00800000)
258 #define FEC_EIR_EBERR			(0x00400000)
259 #define FEC_EIR_LC			(0x00200000)
260 #define FEC_EIR_RL			(0x00100000)
261 #define FEC_EIR_UN			(0x00080000)
262 
263 /* Bit definitions and macros for FEC_RDAR */
264 #define FEC_RDAR_R_DES_ACTIVE		(0x01000000)
265 
266 /* Bit definitions and macros for FEC_TDAR */
267 #define FEC_TDAR_X_DES_ACTIVE		(0x01000000)
268 
269 /* Bit definitions and macros for FEC_ECR */
270 #define FEC_ECR_ETHER_EN		(0x00000002)
271 #define FEC_ECR_RESET			(0x00000001)
272 
273 /* Bit definitions and macros for FEC_MMFR */
274 #define FEC_MMFR_DATA(x)		(((x)&0xFFFF))
275 #define FEC_MMFR_ST(x)			(((x)&0x03)<<30)
276 #define FEC_MMFR_ST_01			(0x40000000)
277 #define FEC_MMFR_OP_RD			(0x20000000)
278 #define FEC_MMFR_OP_WR			(0x10000000)
279 #define FEC_MMFR_PA(x)			(((x)&0x1F)<<23)
280 #define FEC_MMFR_RA(x)			(((x)&0x1F)<<18)
281 #define FEC_MMFR_TA(x)			(((x)&0x03)<<16)
282 #define FEC_MMFR_TA_10			(0x00020000)
283 
284 /* Bit definitions and macros for FEC_MSCR */
285 #define FEC_MSCR_DIS_PREAMBLE		(0x00000080)
286 #define FEC_MSCR_MII_SPEED(x)		(((x)&0x3F)<<1)
287 
288 /* Bit definitions and macros for FEC_MIBC */
289 #define FEC_MIBC_MIB_DISABLE		(0x80000000)
290 #define FEC_MIBC_MIB_IDLE		(0x40000000)
291 
292 /* Bit definitions and macros for FEC_RCR */
293 #define FEC_RCR_MAX_FL(x)		(((x)&0x7FF)<<16)
294 #define FEC_RCR_FCE			(0x00000020)
295 #define FEC_RCR_BC_REJ			(0x00000010)
296 #define FEC_RCR_PROM			(0x00000008)
297 #define FEC_RCR_MII_MODE		(0x00000004)
298 #define FEC_RCR_DRT			(0x00000002)
299 #define FEC_RCR_LOOP			(0x00000001)
300 
301 /* Bit definitions and macros for FEC_TCR */
302 #define FEC_TCR_RFC_PAUSE		(0x00000010)
303 #define FEC_TCR_TFC_PAUSE		(0x00000008)
304 #define FEC_TCR_FDEN			(0x00000004)
305 #define FEC_TCR_HBC			(0x00000002)
306 #define FEC_TCR_GTS			(0x00000001)
307 
308 /* Bit definitions and macros for FEC_PAUR */
309 #define FEC_PAUR_PADDR2(x)		(((x)&0xFFFF)<<16)
310 #define FEC_PAUR_TYPE(x)		((x)&0xFFFF)
311 
312 /* Bit definitions and macros for FEC_OPD */
313 #define FEC_OPD_PAUSE_DUR(x)		(((x)&0x0000FFFF)<<0)
314 #define FEC_OPD_OPCODE(x)		(((x)&0x0000FFFF)<<16)
315 
316 /* Bit definitions and macros for FEC_TFWR */
317 #define FEC_TFWR_X_WMRK(x)		((x)&0x03)
318 #define FEC_TFWR_X_WMRK_64		(0x01)
319 #define FEC_TFWR_X_WMRK_128		(0x02)
320 #define FEC_TFWR_X_WMRK_192		(0x03)
321 
322 /* Bit definitions and macros for FEC_FRBR */
323 #define FEC_FRBR_R_BOUND(x)		(((x)&0xFF)<<2)
324 
325 /* Bit definitions and macros for FEC_FRSR */
326 #define FEC_FRSR_R_FSTART(x)		(((x)&0xFF)<<2)
327 
328 /* Bit definitions and macros for FEC_ERDSR */
329 #define FEC_ERDSR_R_DES_START(x)	(((x)&0x3FFFFFFF)<<2)
330 
331 /* Bit definitions and macros for FEC_ETDSR */
332 #define FEC_ETDSR_X_DES_START(x)	(((x)&0x3FFFFFFF)<<2)
333 
334 /* Bit definitions and macros for FEC_EMRBR */
335 #define FEC_EMRBR_R_BUF_SIZE(x)		(((x)&0x7F)<<4)
336 
337 #define	FEC_RESET_DELAY			100
338 #define FEC_RX_TOUT			100
339 
340 #ifdef CONFIG_MCF547x_8x
341 typedef struct fec_info_dma fec_info_t;
342 #define FEC_T fecdma_t
343 #else
344 typedef struct fec_info_s fec_info_t;
345 #define FEC_T fec_t
346 #endif
347 
348 int fecpin_setclear(fec_info_t *info, int setclear);
349 int mii_discover_phy(fec_info_t *info);
350 int fec_get_base_addr(int fec_idx, u32 *fec_iobase);
351 int fec_get_mii_base(int fec_idx, u32 *mii_base);
352 
353 #ifdef CONFIG_SYS_DISCOVER_PHY
354 void __mii_init(void);
355 uint mii_send(uint mii_cmd);
356 int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
357 int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
358 			u16 value);
359 #endif
360 
361 #endif				/* fec_h */
362