1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Renesas Solutions Corp.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <env.h>
9 #include <flash.h>
10 #include <init.h>
11 #include <malloc.h>
12 #include <net.h>
13 #include <asm/processor.h>
14 #include <asm/io.h>
15 #include <asm/mmc.h>
16 #include <spi.h>
17 #include <spi_flash.h>
18 #include <linux/delay.h>
19
checkboard(void)20 int checkboard(void)
21 {
22 puts("BOARD: SH7753 EVB\n");
23
24 return 0;
25 }
26
init_gpio(void)27 static void init_gpio(void)
28 {
29 struct gpio_regs *gpio = GPIO_BASE;
30 struct sermux_regs *sermux = SERMUX_BASE;
31
32 /* GPIO */
33 writew(0x0000, &gpio->pacr); /* GETHER */
34 writew(0x0001, &gpio->pbcr); /* INTC */
35 writew(0x0000, &gpio->pccr); /* PWMU, INTC */
36 writew(0x0000, &gpio->pdcr); /* SPI0 */
37 writew(0xeaff, &gpio->pecr); /* GPIO */
38 writew(0x0000, &gpio->pfcr); /* WDT */
39 writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */
40 writew(0x0000, &gpio->phcr); /* SPI1 */
41 writew(0x0000, &gpio->picr); /* SDHI */
42 writew(0x0000, &gpio->pjcr); /* SCIF4 */
43 writew(0x0003, &gpio->pkcr); /* SerMux */
44 writew(0x0000, &gpio->plcr); /* SerMux */
45 writew(0x0000, &gpio->pmcr); /* RIIC */
46 writew(0x0000, &gpio->pncr); /* USB, SGPIO */
47 writew(0x0000, &gpio->pocr); /* SGPIO */
48 writew(0xd555, &gpio->pqcr); /* GPIO */
49 writew(0x0000, &gpio->prcr); /* RIIC */
50 writew(0x0000, &gpio->pscr); /* RIIC */
51 writew(0x0000, &gpio->ptcr); /* STATUS */
52 writeb(0x00, &gpio->pudr);
53 writew(0x5555, &gpio->pucr); /* Debug LED */
54 writew(0x0000, &gpio->pvcr); /* RSPI */
55 writew(0x0000, &gpio->pwcr); /* EVC */
56 writew(0x0000, &gpio->pxcr); /* LBSC */
57 writew(0x0000, &gpio->pycr); /* LBSC */
58 writew(0x0000, &gpio->pzcr); /* eMMC */
59 writew(0xfe00, &gpio->psel0);
60 writew(0x0000, &gpio->psel1);
61 writew(0x3000, &gpio->psel2);
62 writew(0xff00, &gpio->psel3);
63 writew(0x771f, &gpio->psel4);
64 writew(0x0ffc, &gpio->psel5);
65 writew(0x00ff, &gpio->psel6);
66 writew(0xfc00, &gpio->psel7);
67
68 writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
69 }
70
init_usb_phy(void)71 static void init_usb_phy(void)
72 {
73 struct usb_common_regs *common0 = USB0_COMMON_BASE;
74 struct usb_common_regs *common1 = USB1_COMMON_BASE;
75 struct usb0_phy_regs *phy = USB0_PHY_BASE;
76 struct usb1_port_regs *port = USB1_PORT_BASE;
77 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
78
79 writew(0x0100, &phy->reset); /* set reset */
80 /* port0 = USB0, port1 = USB1 */
81 writew(0x0002, &phy->portsel);
82 writel(0x0001, &port->port1sel); /* port1 = Host */
83 writew(0x0111, &phy->reset); /* clear reset */
84
85 writew(0x4000, &common0->suspmode);
86 writew(0x4000, &common1->suspmode);
87
88 #if defined(__LITTLE_ENDIAN)
89 writel(0x00000000, &align->ehcidatac);
90 writel(0x00000000, &align->ohcidatac);
91 #endif
92 }
93
init_gether_mdio(void)94 static void init_gether_mdio(void)
95 {
96 struct gpio_regs *gpio = GPIO_BASE;
97
98 writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
99 writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
100 }
101
set_mac_to_sh_giga_eth_register(int channel,char * mac_string)102 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
103 {
104 struct ether_mac_regs *ether;
105 unsigned char mac[6];
106 unsigned long val;
107
108 string_to_enetaddr(mac_string, mac);
109
110 if (!channel)
111 ether = GETHER0_MAC_BASE;
112 else
113 ether = GETHER1_MAC_BASE;
114
115 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
116 writel(val, ðer->mahr);
117 val = (mac[4] << 8) | mac[5];
118 writel(val, ðer->malr);
119 }
120
121 #if defined(CONFIG_SH_32BIT)
122 /*****************************************************************
123 * This PMB must be set on this timing. The lowlevel_init is run on
124 * Area 0(phys 0x00000000), so we have to map it.
125 *
126 * The new PMB table is following:
127 * ent virt phys v sz c wt
128 * 0 0xa0000000 0x40000000 1 128M 0 1
129 * 1 0xa8000000 0x48000000 1 128M 0 1
130 * 2 0xb0000000 0x50000000 1 128M 0 1
131 * 3 0xb8000000 0x58000000 1 128M 0 1
132 * 4 0x80000000 0x40000000 1 128M 1 1
133 * 5 0x88000000 0x48000000 1 128M 1 1
134 * 6 0x90000000 0x50000000 1 128M 1 1
135 * 7 0x98000000 0x58000000 1 128M 1 1
136 */
set_pmb_on_board_init(void)137 static void set_pmb_on_board_init(void)
138 {
139 struct mmu_regs *mmu = MMU_BASE;
140
141 /* clear ITLB */
142 writel(0x00000004, &mmu->mmucr);
143
144 /* delete PMB for SPIBOOT */
145 writel(0, PMB_ADDR_BASE(0));
146 writel(0, PMB_DATA_BASE(0));
147
148 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
149 /* ppn ub v s1 s0 c wt */
150 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
151 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
152 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
153 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
154 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
155 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
156 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
157 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
158 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
159 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
160 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
161 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
162 }
163 #endif
164
board_init(void)165 int board_init(void)
166 {
167 struct gether_control_regs *gether = GETHER_CONTROL_BASE;
168
169 init_gpio();
170 #if defined(CONFIG_SH_32BIT)
171 set_pmb_on_board_init();
172 #endif
173
174 /* Sets TXnDLY to B'010 */
175 writel(0x00000202, &gether->gbecont);
176
177 init_usb_phy();
178 init_gether_mdio();
179
180 return 0;
181 }
182
board_mmc_init(bd_t * bis)183 int board_mmc_init(bd_t *bis)
184 {
185 struct gpio_regs *gpio = GPIO_BASE;
186
187 writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
188 writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
189 udelay(1);
190 writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
191 udelay(200);
192
193 return mmcif_mmc_init();
194 }
195
get_sh_eth_mac_raw(unsigned char * buf,int size)196 static int get_sh_eth_mac_raw(unsigned char *buf, int size)
197 {
198 #ifdef CONFIG_DEPRECATED
199 struct spi_flash *spi;
200 int ret;
201
202 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
203 if (spi == NULL) {
204 printf("%s: spi_flash probe failed.\n", __func__);
205 return 1;
206 }
207
208 ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
209 if (ret) {
210 printf("%s: spi_flash read failed.\n", __func__);
211 spi_flash_free(spi);
212 return 1;
213 }
214 spi_flash_free(spi);
215 #endif
216
217 return 0;
218 }
219
get_sh_eth_mac(int channel,char * mac_string,unsigned char * buf)220 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
221 {
222 memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
223 SH7753EVB_ETHERNET_MAC_SIZE);
224 mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
225
226 return 0;
227 }
228
init_ethernet_mac(void)229 static void init_ethernet_mac(void)
230 {
231 char mac_string[64];
232 char env_string[64];
233 int i;
234 unsigned char *buf;
235
236 buf = malloc(256);
237 if (!buf) {
238 printf("%s: malloc failed.\n", __func__);
239 return;
240 }
241 get_sh_eth_mac_raw(buf, 256);
242
243 /* Gigabit Ethernet */
244 for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
245 get_sh_eth_mac(i, mac_string, buf);
246 if (i == 0)
247 env_set("ethaddr", mac_string);
248 else {
249 sprintf(env_string, "eth%daddr", i);
250 env_set(env_string, mac_string);
251 }
252 set_mac_to_sh_giga_eth_register(i, mac_string);
253 }
254
255 free(buf);
256 }
257
board_late_init(void)258 int board_late_init(void)
259 {
260 init_ethernet_mac();
261
262 return 0;
263 }
264
265 #ifdef CONFIG_DEPRECATED
do_write_mac(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])266 int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
267 {
268 int i, ret;
269 char mac_string[256];
270 struct spi_flash *spi;
271 unsigned char *buf;
272
273 if (argc != 3) {
274 buf = malloc(256);
275 if (!buf) {
276 printf("%s: malloc failed.\n", __func__);
277 return 1;
278 }
279
280 get_sh_eth_mac_raw(buf, 256);
281
282 /* print current MAC address */
283 for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
284 get_sh_eth_mac(i, mac_string, buf);
285 printf("GETHERC ch%d = %s\n", i, mac_string);
286 }
287 free(buf);
288 return 0;
289 }
290
291 /* new setting */
292 memset(mac_string, 0xff, sizeof(mac_string));
293 sprintf(mac_string, "%s\t%s",
294 argv[1], argv[2]);
295
296 /* write MAC data to SPI rom */
297 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
298 if (!spi) {
299 printf("%s: spi_flash probe failed.\n", __func__);
300 return 1;
301 }
302
303 ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
304 SH7753EVB_SPI_SECTOR_SIZE);
305 if (ret) {
306 printf("%s: spi_flash erase failed.\n", __func__);
307 return 1;
308 }
309
310 ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
311 sizeof(mac_string), mac_string);
312 if (ret) {
313 printf("%s: spi_flash write failed.\n", __func__);
314 spi_flash_free(spi);
315 return 1;
316 }
317 spi_flash_free(spi);
318
319 puts("The writing of the MAC address to SPI ROM was completed.\n");
320
321 return 0;
322 }
323
324 U_BOOT_CMD(
325 write_mac, 3, 1, do_write_mac,
326 "write MAC address for GETHERC",
327 "[GETHERC ch0] [GETHERC ch1]\n"
328 );
329 #endif
330