1 /*
2 * (C) Copyright 2007-2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <watchdog.h>
10 #include <command.h>
11 #include <asm/cache.h>
12 #include <asm/ppc4xx.h>
13
14 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
15 #include <libfdt.h>
16 #include <fdt_support.h>
17 #include <asm/4xx_pcie.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
__ft_board_setup(void * blob,bd_t * bd)21 int __ft_board_setup(void *blob, bd_t *bd)
22 {
23 int rc;
24 int i;
25 u32 bxcr;
26 u32 ranges[EBC_NUM_BANKS * 4];
27 u32 *p = ranges;
28 char ebc_path[] = "/plb/opb/ebc";
29
30 ft_cpu_setup(blob, bd);
31
32 /*
33 * Read 4xx EBC bus bridge registers to get mappings of the
34 * peripheral banks into the OPB/PLB address space
35 */
36 for (i = 0; i < EBC_NUM_BANKS; i++) {
37 mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
38 bxcr = mfdcr(EBC0_CFGDATA);
39
40 if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
41 *p++ = i;
42 *p++ = 0;
43 *p++ = bxcr & EBC_BXCR_BAS_MASK;
44 *p++ = EBC_BXCR_BANK_SIZE(bxcr);
45 }
46 }
47
48
49 #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
50 /* Update reg property in all nor flash nodes too */
51 fdt_fixup_nor_flash_size(blob);
52 #endif
53
54 /* Some 405 PPC's have EBC as direct PLB child in the dts */
55 if (fdt_path_offset(blob, ebc_path) < 0)
56 strcpy(ebc_path, "/plb/ebc");
57 rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
58 (p - ranges) * sizeof(u32), 1);
59 if (rc) {
60 printf("Unable to update property EBC mappings, err=%s\n",
61 fdt_strerror(rc));
62 }
63
64 return 0;
65 }
66 int ft_board_setup(void *blob, bd_t *bd)
67 __attribute__((weak, alias("__ft_board_setup")));
68
69 /*
70 * Fixup all PCIe nodes by setting the device_type property
71 * to "pci-endpoint" instead is "pci" for endpoint ports.
72 * This property will get checked later by the Linux driver
73 * to properly configure the PCIe port in Linux (again).
74 */
fdt_pcie_setup(void * blob)75 void fdt_pcie_setup(void *blob)
76 {
77 const char *compat = "ibm,plb-pciex";
78 const char *prop = "device_type";
79 const char *prop_val = "pci-endpoint";
80 const u32 *port;
81 int no;
82 int rc;
83
84 /* Search first PCIe node */
85 no = fdt_node_offset_by_compatible(blob, -1, compat);
86 while (no != -FDT_ERR_NOTFOUND) {
87 port = fdt_getprop(blob, no, "port", NULL);
88 if (port == NULL) {
89 printf("WARNING: could not find port property\n");
90 } else {
91 if (is_end_point(*port)) {
92 rc = fdt_setprop(blob, no, prop, prop_val,
93 strlen(prop_val) + 1);
94 if (rc < 0)
95 printf("WARNING: could not set %s for %s: %s.\n",
96 prop, compat, fdt_strerror(rc));
97 }
98 }
99
100 /* Jump to next PCIe node */
101 no = fdt_node_offset_by_compatible(blob, no, compat);
102 }
103 }
104
ft_cpu_setup(void * blob,bd_t * bd)105 void ft_cpu_setup(void *blob, bd_t *bd)
106 {
107 sys_info_t sys_info;
108 int off, ndepth = 0;
109
110 get_sys_info(&sys_info);
111
112 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency",
113 bd->bi_intfreq, 1);
114 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency",
115 bd->bi_intfreq, 1);
116 do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
117 do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);
118
119 if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0)
120 do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
121 sys_info.freqEBC, 1);
122 else
123 do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency",
124 sys_info.freqEBC, 1);
125
126 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
127
128 /*
129 * Fixup all UART clocks for CPU internal UARTs
130 * (only these UARTs are definitely clocked by gd->arch.uart_clk)
131 *
132 * These UARTs are direct childs of /plb/opb. This code
133 * does not touch any UARTs that are connected to the ebc.
134 */
135 off = fdt_path_offset(blob, "/plb/opb");
136 while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
137 /*
138 * process all sub nodes and stop when we are back
139 * at the starting depth
140 */
141 if (ndepth <= 0)
142 break;
143
144 /* only update direct childs */
145 if ((ndepth == 1) &&
146 (fdt_node_check_compatible(blob, off, "ns16550") == 0))
147 fdt_setprop(blob, off,
148 "clock-frequency",
149 (void *)&gd->arch.uart_clk, 4);
150 }
151
152 /*
153 * Fixup all ethernet nodes
154 * Note: aliases in the dts are required for this
155 */
156 fdt_fixup_ethernet(blob);
157
158 /*
159 * Fixup all available PCIe nodes by setting the device_type property
160 */
161 fdt_pcie_setup(blob);
162 }
163 #endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
164