1 /*
2  * (C) Copyright 2003
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * (C) Copyright 2004
6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7  *
8  * (C) Copyright 2010
9  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
10  *
11  * SPDX-License-Identifier:	GPL-2.0+
12  */
13 
14 #include <common.h>
15 #include <mpc5xxx.h>
16 #include <pci.h>
17 #include <asm/processor.h>
18 #include <asm/io.h>
19 #include <libfdt.h>
20 #include <netdev.h>
21 #include <led-display.h>
22 #include <linux/err.h>
23 
24 #include "mt46v32m16.h"
25 
26 #ifndef CONFIG_SYS_RAMBOOT
sdram_start(int hi_addr)27 static void sdram_start (int hi_addr)
28 {
29 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
30 	long control = SDRAM_CONTROL | hi_addr_bit;
31 
32 	/* unlock mode register */
33 	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
34 	__asm__ volatile ("sync");
35 
36 	/* precharge all banks */
37 	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
38 	__asm__ volatile ("sync");
39 
40 #if SDRAM_DDR
41 	/* set mode register: extended mode */
42 	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
43 	__asm__ volatile ("sync");
44 
45 	/* set mode register: reset DLL */
46 	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
47 	__asm__ volatile ("sync");
48 #endif
49 
50 	/* precharge all banks */
51 	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
52 	__asm__ volatile ("sync");
53 
54 	/* auto refresh */
55 	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
56 	__asm__ volatile ("sync");
57 
58 	/* set mode register */
59 	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
60 	__asm__ volatile ("sync");
61 
62 	/* normal operation */
63 	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
64 	__asm__ volatile ("sync");
65 }
66 #endif
67 
68 /*
69  * ATTENTION: Although partially referenced initdram does NOT make real use
70  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
71  *            is something else than 0x00000000.
72  */
73 
initdram(int board_type)74 phys_size_t initdram (int board_type)
75 {
76 	ulong dramsize = 0;
77 	uint svr, pvr;
78 
79 #ifndef CONFIG_SYS_RAMBOOT
80 	ulong test1, test2;
81 
82 	/* setup SDRAM chip selects */
83 	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
84 	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
85 	__asm__ volatile ("sync");
86 
87 	/* setup config registers */
88 	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
89 	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
90 	__asm__ volatile ("sync");
91 
92 #if SDRAM_DDR
93 	/* set tap delay */
94 	out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
95 	__asm__ volatile ("sync");
96 #endif
97 
98 	/* find RAM size using SDRAM CS0 only */
99 	sdram_start(0);
100 	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
101 	sdram_start(1);
102 	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
103 	if (test1 > test2) {
104 		sdram_start(0);
105 		dramsize = test1;
106 	} else {
107 		dramsize = test2;
108 	}
109 
110 	/* memory smaller than 1MB is impossible */
111 	if (dramsize < (1 << 20)) {
112 		dramsize = 0;
113 	}
114 
115 	/* set SDRAM CS0 size according to the amount of RAM found */
116 	if (dramsize > 0) {
117 		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
118 				 0x13 + __builtin_ffs(dramsize >> 20) - 1);
119 	} else {
120 		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
121 	}
122 
123 #else /* CONFIG_SYS_RAMBOOT */
124 
125 	/* retrieve size of memory connected to SDRAM CS0 */
126 	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
127 	if (dramsize >= 0x13) {
128 		dramsize = (1 << (dramsize - 0x13)) << 20;
129 	} else {
130 		dramsize = 0;
131 	}
132 
133 #endif /* CONFIG_SYS_RAMBOOT */
134 
135 	/*
136 	 * On MPC5200B we need to set the special configuration delay in the
137 	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
138 	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
139 	 *
140 	 * "The SDelay should be written to a value of 0x00000004. It is
141 	 * required to account for changes caused by normal wafer processing
142 	 * parameters."
143 	 */
144 	svr = get_svr();
145 	pvr = get_pvr();
146 	if ((SVR_MJREV(svr) >= 2) &&
147 	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
148 
149 		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
150 		__asm__ volatile ("sync");
151 	}
152 
153 	return dramsize;
154 }
155 
checkboard(void)156 int checkboard (void)
157 {
158 	puts ("Board: A4M072\n");
159 	return 0;
160 }
161 
162 #ifdef	CONFIG_PCI
163 static struct pci_controller hose;
164 
165 extern void pci_mpc5xxx_init(struct pci_controller *);
166 
pci_init_board(void)167 void pci_init_board(void)
168 {
169 	pci_mpc5xxx_init(&hose);
170 }
171 #endif
172 
173 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)174 int ft_board_setup(void *blob, bd_t *bd)
175 {
176 	ft_cpu_setup(blob, bd);
177 
178 	return 0;
179 }
180 #endif
181 
board_eth_init(bd_t * bis)182 int board_eth_init(bd_t *bis)
183 {
184 	int rv, num_if = 0;
185 
186 	/* Initialize TSECs first */
187 	if ((rv = cpu_eth_init(bis)) >= 0)
188 		num_if += rv;
189 	else
190 		printf("ERROR: failed to initialize FEC.\n");
191 
192 	if ((rv = pci_eth_init(bis)) >= 0)
193 		num_if += rv;
194 	else
195 		printf("ERROR: failed to initialize PCI Ethernet.\n");
196 
197 	return num_if;
198 }
199 /*
200  * Miscellaneous late-boot configurations
201  *
202  * Initialize EEPROM write-protect GPIO pin.
203  */
misc_init_r(void)204 int misc_init_r(void)
205 {
206 #if defined(CONFIG_SYS_EEPROM_WREN)
207 	/* Enable GPIO pin */
208 	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
209 	/* Set direction, output */
210 	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
211 	/* De-assert write enable */
212 	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
213 #endif
214 	return 0;
215 }
216 #if defined(CONFIG_SYS_EEPROM_WREN)
217 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
218  *         <state>     -1: deliver current state
219  *	               0: disable write
220  *		       1: enable write
221  *  Returns:           -1: wrong device address
222  *                      0: dis-/en- able done
223  *		     0/1: current state if <state> was -1.
224  */
eeprom_write_enable(unsigned dev_addr,int state)225 int eeprom_write_enable (unsigned dev_addr, int state)
226 {
227 	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
228 		return -1;
229 	} else {
230 		switch (state) {
231 		case 1:
232 			/* Enable write access */
233 			clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
234 			state = 0;
235 			break;
236 		case 0:
237 			/* Disable write access */
238 			setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
239 			state = 0;
240 			break;
241 		default:
242 			/* Read current status back. */
243 			state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
244 						   CONFIG_SYS_EEPROM_WP));
245 			break;
246 		}
247 	}
248 	return state;
249 }
250 #endif
251 
252 #ifdef CONFIG_CMD_DISPLAY
253 #define DISPLAY_BUF_SIZE	2
254 static u8 display_buf[DISPLAY_BUF_SIZE];
255 static u8 display_putc_pos;
256 static u8 display_out_pos;
257 
display_set(int cmd)258 void display_set(int cmd) {
259 
260 	if (cmd & DISPLAY_CLEAR) {
261 		display_buf[0] = display_buf[1] = 0;
262 	}
263 
264 	if (cmd & DISPLAY_HOME) {
265 		display_putc_pos = 0;
266 	}
267 }
268 
269 #define SEG_A    (1<<0)
270 #define SEG_B    (1<<1)
271 #define SEG_C    (1<<2)
272 #define SEG_D    (1<<3)
273 #define SEG_E    (1<<4)
274 #define SEG_F    (1<<5)
275 #define SEG_G    (1<<6)
276 #define SEG_P    (1<<7)
277 #define SEG__    0
278 
279 /*
280  * +- A -+
281  * |     |
282  * F     B
283  * |     |
284  * +- G -+
285  * |     |
286  * E     C
287  * |     |
288  * +- D -+  P
289  *
290  * 0..9		index 0..9
291  * A..Z		index 10..35
292  * -		index 36
293  * _		index 37
294  * .		index 38
295  */
296 
297 #define SYMBOL_DASH		(36)
298 #define SYMBOL_UNDERLINE	(37)
299 #define SYMBOL_DOT		(38)
300 
301 static u8 display_char2seg7_tbl[]=
302 {
303 	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* 0 */
304 	SEG_B | SEG_C,						/* 1 */
305 	SEG_A | SEG_B | SEG_D | SEG_E | SEG_G,			/* 2 */
306 	SEG_A | SEG_B | SEG_C | SEG_D | SEG_G,			/* 3 */
307 	SEG_B | SEG_C | SEG_F | SEG_G,				/* 4 */
308 	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* 5 */
309 	SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,		/* 6 */
310 	SEG_A | SEG_B | SEG_C,					/* 7 */
311 	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,	/* 8 */
312 	SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,		/* 9 */
313 	SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,		/* A */
314 	SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,			/* b */
315 	SEG_A | SEG_D | SEG_E | SEG_F,				/* C */
316 	SEG_B | SEG_C | SEG_D | SEG_E | SEG_G,			/* d */
317 	SEG_A | SEG_D | SEG_E | SEG_F | SEG_G,			/* E */
318 	SEG_A | SEG_E | SEG_F | SEG_G,				/* F */
319 	0,					/* g - not displayed */
320 	SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,			/* H */
321 	SEG_B | SEG_C,						/* I */
322 	0,					/* J - not displayed */
323 	0,					/* K - not displayed */
324 	SEG_D | SEG_E | SEG_F,					/* L */
325 	0,					/* m - not displayed */
326 	0,					/* n - not displayed */
327 	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* O */
328 	SEG_A | SEG_B | SEG_E | SEG_F | SEG_G,			/* P */
329 	0,					/* q - not displayed */
330 	0,					/* r - not displayed */
331 	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* S */
332 	SEG_D | SEG_E | SEG_F | SEG_G,				/* t */
333 	SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,			/* U */
334 	0,					/* V - not displayed */
335 	0,					/* w - not displayed */
336 	0,					/* X - not displayed */
337 	SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,			/* Y */
338 	0,					/* Z - not displayed */
339 	SEG_G,							/* - */
340 	SEG_D,							/* _ */
341 	SEG_P							/* . */
342 };
343 
344 /* Convert char to the LED segments representation */
display_char2seg7(char c)345 static u8 display_char2seg7(char c)
346 {
347 	u8 val = 0;
348 
349 	if (c >= '0' && c <= '9')
350 		c -= '0';
351 	else if (c >= 'a' && c <= 'z')
352 		c -= 'a' - 10;
353 	else if (c >= 'A' && c <= 'Z')
354 		c -= 'A' - 10;
355 	else if (c == '-')
356 		c = SYMBOL_DASH;
357 	else if (c == '_')
358 		c = SYMBOL_UNDERLINE;
359 	else if (c == '.')
360 		c = SYMBOL_DOT;
361 	else
362 		c = ' ';	/* display unsupported symbols as space */
363 
364 	if (c != ' ')
365 		val = display_char2seg7_tbl[(int)c];
366 
367 	return val;
368 }
369 
display_putc(char c)370 int display_putc(char c)
371 {
372 	if (display_putc_pos >= DISPLAY_BUF_SIZE)
373 		return -1;
374 
375 	display_buf[display_putc_pos++] = display_char2seg7(c);
376 	/* one-symbol message should be steady */
377 	if (display_putc_pos == 1)
378 		display_buf[display_putc_pos] = display_char2seg7(c);
379 
380 	return c;
381 }
382 
383 /*
384  * Flush current symbol to the LED display hardware
385  */
display_flush(void)386 static inline void display_flush(void)
387 {
388 	u32 val = display_buf[display_out_pos];
389 
390 	val |= (val << 8) | (val << 16) | (val << 24);
391 	out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
392 }
393 
394 /*
395  * Output contents of the software display buffer to the LED display every 0.5s
396  */
board_show_activity(ulong timestamp)397 void board_show_activity(ulong timestamp)
398 {
399 	static ulong last;
400 	static u8 once;
401 
402 	if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
403 		display_flush();
404 		display_out_pos ^= 1;
405 		last = timestamp;
406 		once = 1;
407 	}
408 }
409 
410 /*
411  * Empty fake function
412  */
show_activity(int arg)413 void show_activity(int arg)
414 {
415 }
416 #endif
417 #if defined (CONFIG_SHOW_BOOT_PROGRESS)
a4m072_status2code(int status,char * buf)418 static int a4m072_status2code(int status, char *buf)
419 {
420 	char c = 0;
421 
422 	if (((status > 0) && (status <= 8)) ||
423 				((status >= 100) && (status <= 108)) ||
424 				((status < 0) && (status >= -9)) ||
425 				(status == -100) || (status == -101) ||
426 				((status <= -103) && (status >= -113))) {
427 		c = '5';
428 	} else if (((status >= 9) && (status <= 14)) ||
429 			((status >= 120) && (status <= 123)) ||
430 			((status >= 125) && (status <= 129)) ||
431 			((status >= -13) && (status <= -10)) ||
432 			(status == -120) || (status == -122) ||
433 			((status <= -124) && (status >= -127)) ||
434 			(status == -129)) {
435 		c = '8';
436 	} else if (status == 15) {
437 		c = '9';
438 	} else if ((status <= -30) && (status >= -32)) {
439 		c = 'A';
440 	} else if (((status <= -35) && (status >= -40)) ||
441 			((status <= -42) && (status >= -51)) ||
442 			((status <= -53) && (status >= -58)) ||
443 			(status == -64) ||
444 			((status <= -80) && (status >= -83)) ||
445 			(status == -130) || (status == -140) ||
446 			(status == -150)) {
447 		c = 'B';
448 	}
449 
450 	if (c == 0)
451 		return -EINVAL;
452 
453 	buf[0] = (status < 0) ? '-' : c;
454 	buf[1] = c;
455 
456 	return 0;
457 }
458 
show_boot_progress(int status)459 void show_boot_progress(int status)
460 {
461 	char buf[2];
462 
463 	if (a4m072_status2code(status, buf) < 0)
464 		return;
465 
466 	display_putc(buf[0]);
467 	display_putc(buf[1]);
468 	display_set(DISPLAY_HOME);
469 	display_out_pos = 0;	/* reset output position */
470 
471 	/* we want to flush status 15 now */
472 	if (status == BOOTSTAGE_ID_RUN_OS)
473 		display_flush();
474 }
475 #endif
476