1 /*
2 * Copyright (C) 2014 Samsung Electronics
3 * Przemyslaw Marczak <p.marczak@samsung.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <asm/arch/pinmux.h>
10 #include <asm/arch/power.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/gpio.h>
13 #include <asm/gpio.h>
14 #include <asm/arch/cpu.h>
15 #include <dm.h>
16 #include <power/pmic.h>
17 #include <power/regulator.h>
18 #include <power/max77686_pmic.h>
19 #include <errno.h>
20 #include <mmc.h>
21 #include <usb.h>
22 #include <usb/s3c_udc.h>
23 #include <samsung/misc.h>
24 #include "setup.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #ifdef CONFIG_BOARD_TYPES
29 /* Odroid board types */
30 enum {
31 ODROID_TYPE_U3,
32 ODROID_TYPE_X2,
33 ODROID_TYPES,
34 };
35
36 static const char *mmc_regulators[] = {
37 "VDDQ_EMMC_1.8V",
38 "VDDQ_EMMC_2.8V",
39 "TFLASH_2.8V",
40 NULL,
41 };
42
set_board_type(void)43 void set_board_type(void)
44 {
45 /* Set GPA1 pin 1 to HI - enable XCL205 output */
46 writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON);
47 writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4);
48 writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8);
49 writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc);
50
51 /* Set GPC1 pin 2 to IN - check XCL205 output state */
52 writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON);
53 writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8);
54
55 /* XCL205 - needs some latch time */
56 sdelay(200000);
57
58 /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
59 if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN))
60 gd->board_type = ODROID_TYPE_X2;
61 else
62 gd->board_type = ODROID_TYPE_U3;
63 }
64
get_board_type(void)65 const char *get_board_type(void)
66 {
67 const char *board_type[] = {"u3", "x2"};
68
69 return board_type[gd->board_type];
70 }
71 #endif
72
73 #ifdef CONFIG_SET_DFU_ALT_INFO
get_dfu_alt_system(char * interface,char * devstr)74 char *get_dfu_alt_system(char *interface, char *devstr)
75 {
76 return getenv("dfu_alt_system");
77 }
78
get_dfu_alt_boot(char * interface,char * devstr)79 char *get_dfu_alt_boot(char *interface, char *devstr)
80 {
81 struct mmc *mmc;
82 char *alt_boot;
83 int dev_num;
84
85 dev_num = simple_strtoul(devstr, NULL, 10);
86
87 mmc = find_mmc_device(dev_num);
88 if (!mmc)
89 return NULL;
90
91 if (mmc_init(mmc))
92 return NULL;
93
94 alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD :
95 CONFIG_DFU_ALT_BOOT_EMMC;
96
97 return alt_boot;
98 }
99 #endif
100
board_clock_init(void)101 static void board_clock_init(void)
102 {
103 unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
104 struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
105 samsung_get_base_clock();
106
107 /*
108 * CMU_CPU clocks src to MPLL
109 * Bit values: 0 ; 1
110 * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
111 * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
112 * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
113 * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
114 */
115 clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
116 MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
117 set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
118 MUX_MPLL_USER_SEL_C(1);
119
120 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
121
122 /* Wait for mux change */
123 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
124 continue;
125
126 /* Set APLL to 1000MHz */
127 clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
128 set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
129
130 clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
131
132 /* Wait for PLL to be locked */
133 while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
134 continue;
135
136 /* Set CMU_CPU clocks src to APLL */
137 set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
138 MUX_MPLL_USER_SEL_C(1);
139 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
140
141 /* Wait for mux change */
142 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
143 continue;
144
145 set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
146 PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
147 APLL_RATIO(0) | CORE2_RATIO(0);
148 /*
149 * Set dividers for MOUTcore = 1000 MHz
150 * coreout = MOUT / (ratio + 1) = 1000 MHz (0)
151 * corem0 = armclk / (ratio + 1) = 333 MHz (2)
152 * corem1 = armclk / (ratio + 1) = 166 MHz (5)
153 * periph = armclk / (ratio + 1) = 1000 MHz (0)
154 * atbout = MOUT / (ratio + 1) = 200 MHz (4)
155 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
156 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
157 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
158 */
159 clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
160 PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
161 APLL_RATIO(7) | CORE2_RATIO(7);
162
163 clrsetbits_le32(&clk->div_cpu0, clr, set);
164
165 /* Wait for divider ready status */
166 while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
167 continue;
168
169 /*
170 * For MOUThpm = 1000 MHz (MOUTapll)
171 * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
172 * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
173 * cores_out = armclk / (ratio + 1) = 200 (4)
174 */
175 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
176 set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
177
178 clrsetbits_le32(&clk->div_cpu1, clr, set);
179
180 /* Wait for divider ready status */
181 while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
182 continue;
183
184 /*
185 * Set CMU_DMC clocks src to APLL
186 * Bit values: 0 ; 1
187 * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
188 * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
189 * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
190 * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
191 * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
192 * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
193 * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
194 * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
195 */
196 clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
197 MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
198 MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
199 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
200 set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
201 MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
202 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
203
204 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
205
206 /* Wait for mux change */
207 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
208 continue;
209
210 /* Set MPLL to 800MHz */
211 set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
212
213 clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
214
215 /* Wait for PLL to be locked */
216 while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
217 continue;
218
219 /* Switch back CMU_DMC mux */
220 set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
221 MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
222 MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
223
224 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
225
226 /* Wait for mux change */
227 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
228 continue;
229
230 /* CLK_DIV_DMC0 */
231 clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
232 DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
233 /*
234 * For:
235 * MOUTdmc = 800 MHz
236 * MOUTdphy = 800 MHz
237 *
238 * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
239 * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
240 * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
241 * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
242 * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
243 * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
244 */
245 set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
246 DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
247
248 clrsetbits_le32(&clk->div_dmc0, clr, set);
249
250 /* Wait for divider ready status */
251 while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
252 continue;
253
254 /* CLK_DIV_DMC1 */
255 clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
256 C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
257 /*
258 * For:
259 * MOUTg2d = 800 MHz
260 * MOUTc2c = 800 Mhz
261 * MOUTpwi = 108 MHz
262 *
263 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
264 * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
265 * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
266 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
267 */
268 set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) |
269 C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
270
271 clrsetbits_le32(&clk->div_dmc1, clr, set);
272
273 /* Wait for divider ready status */
274 while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
275 continue;
276
277 /* CLK_SRC_PERIL0 */
278 clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
279 UART3_SEL(15) | UART4_SEL(15);
280 /*
281 * Set CLK_SRC_PERIL0 clocks src to MPLL
282 * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
283 * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
284 * 8(SCLK_VPLL)
285 *
286 * Set all to SCLK_MPLL_USER_T
287 */
288 set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
289 UART4_SEL(6);
290
291 clrsetbits_le32(&clk->src_peril0, clr, set);
292
293 /* CLK_DIV_PERIL0 */
294 clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
295 UART3_RATIO(15) | UART4_RATIO(15);
296 /*
297 * For MOUTuart0-4: 800MHz
298 *
299 * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
300 */
301 set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
302 UART3_RATIO(7) | UART4_RATIO(7);
303
304 clrsetbits_le32(&clk->div_peril0, clr, set);
305
306 while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
307 continue;
308
309 /* CLK_DIV_FSYS1 */
310 clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
311 MMC1_PRE_RATIO(255);
312 /*
313 * For MOUTmmc0-3 = 800 MHz (MPLL)
314 *
315 * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
316 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
317 * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
318 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
319 */
320 set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
321 MMC1_PRE_RATIO(1);
322
323 clrsetbits_le32(&clk->div_fsys1, clr, set);
324
325 /* Wait for divider ready status */
326 while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
327 continue;
328
329 /* CLK_DIV_FSYS2 */
330 clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
331 MMC3_PRE_RATIO(255);
332 /*
333 * For MOUTmmc0-3 = 800 MHz (MPLL)
334 *
335 * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
336 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
337 * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
338 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
339 */
340 set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
341 MMC3_PRE_RATIO(1);
342
343 clrsetbits_le32(&clk->div_fsys2, clr, set);
344
345 /* Wait for divider ready status */
346 while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
347 continue;
348
349 /* CLK_DIV_FSYS3 */
350 clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
351 /*
352 * For MOUTmmc4 = 800 MHz (MPLL)
353 *
354 * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
355 * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
356 */
357 set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
358
359 clrsetbits_le32(&clk->div_fsys3, clr, set);
360
361 /* Wait for divider ready status */
362 while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
363 continue;
364
365 return;
366 }
367
board_gpio_init(void)368 static void board_gpio_init(void)
369 {
370 /* eMMC Reset Pin */
371 gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
372
373 gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
374 gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
375 gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
376
377 /* Enable FAN (Odroid U3) */
378 gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
379
380 gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
381 gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
382 gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
383
384 /* OTG Vbus output (Odroid U3+) */
385 gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
386
387 gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
388 gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
389 gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
390
391 /* OTG INT (Odroid U3+) */
392 gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
393
394 gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
395 gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
396 gpio_direction_input(EXYNOS4X12_GPIO_X31);
397
398 /* Blue LED (Odroid X2/U2/U3) */
399 gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
400
401 gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
402
403 #ifdef CONFIG_CMD_USB
404 /* USB3503A Reference frequency */
405 gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
406
407 /* USB3503A Connect */
408 gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
409
410 /* USB3503A Reset */
411 gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
412 #endif
413 }
414
exynos_early_init_f(void)415 int exynos_early_init_f(void)
416 {
417 board_clock_init();
418
419 return 0;
420 }
421
exynos_init(void)422 int exynos_init(void)
423 {
424 board_gpio_init();
425
426 return 0;
427 }
428
exynos_power_init(void)429 int exynos_power_init(void)
430 {
431 if (regulator_list_autoset(mmc_regulators, NULL, true))
432 error("Unable to init all mmc regulators");
433
434 return 0;
435 }
436
437 #ifdef CONFIG_USB_GADGET
s5pc210_phy_control(int on)438 static int s5pc210_phy_control(int on)
439 {
440 struct udevice *dev;
441 int ret;
442
443 ret = regulator_get_by_platname("VDD_UOTG_3.0V", &dev);
444 if (ret) {
445 error("Regulator get error: %d", ret);
446 return ret;
447 }
448
449 if (on)
450 return regulator_set_mode(dev, OPMODE_ON);
451 else
452 return regulator_set_mode(dev, OPMODE_LPM);
453
454 }
455
456 struct s3c_plat_otg_data s5pc210_otg_data = {
457 .phy_control = s5pc210_phy_control,
458 .regs_phy = EXYNOS4X12_USBPHY_BASE,
459 .regs_otg = EXYNOS4X12_USBOTG_BASE,
460 .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
461 .usb_flags = PHY0_SLEEP,
462 };
463 #endif
464
465 #if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
466
board_usb_init(int index,enum usb_init_type init)467 int board_usb_init(int index, enum usb_init_type init)
468 {
469 #ifdef CONFIG_CMD_USB
470 struct udevice *dev;
471 int ret;
472
473 /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
474 /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
475 if (gd->board_type == ODROID_TYPE_U3)
476 gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
477 else
478 gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
479
480 /* Disconnect, Reset, Connect */
481 gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
482 gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
483 gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
484 gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
485
486 /* Power off and on BUCK8 for LAN9730 */
487 debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
488
489 ret = regulator_get_by_platname("VCC_P3V3_2.85V", &dev);
490 if (ret) {
491 error("Regulator get error: %d", ret);
492 return ret;
493 }
494
495 ret = regulator_set_enable(dev, true);
496 if (ret) {
497 error("Regulator %s enable setting error: %d", dev->name, ret);
498 return ret;
499 }
500
501 ret = regulator_set_value(dev, 750000);
502 if (ret) {
503 error("Regulator %s value setting error: %d", dev->name, ret);
504 return ret;
505 }
506
507 ret = regulator_set_value(dev, 3300000);
508 if (ret) {
509 error("Regulator %s value setting error: %d", dev->name, ret);
510 return ret;
511 }
512 #endif
513 debug("USB_udc_probe\n");
514 return s3c_udc_probe(&s5pc210_otg_data);
515 }
516 #endif
517