1 /*
2 * Altera 10/100/1000 triple speed ethernet mac driver
3 *
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <config.h>
12 #include <common.h>
13 #include <malloc.h>
14 #include <net.h>
15 #include <command.h>
16 #include <asm/cache.h>
17 #include <asm/dma-mapping.h>
18 #include <miiphy.h>
19 #include "altera_tse.h"
20
21 /* sgdma debug - print descriptor */
alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor * desc)22 static void alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor *desc)
23 {
24 debug("SGDMA DEBUG :\n");
25 debug("desc->source : 0x%x \n", (unsigned int)desc->source);
26 debug("desc->destination : 0x%x \n", (unsigned int)desc->destination);
27 debug("desc->next : 0x%x \n", (unsigned int)desc->next);
28 debug("desc->source_pad : 0x%x \n", (unsigned int)desc->source_pad);
29 debug("desc->destination_pad : 0x%x \n",
30 (unsigned int)desc->destination_pad);
31 debug("desc->next_pad : 0x%x \n", (unsigned int)desc->next_pad);
32 debug("desc->bytes_to_transfer : 0x%x \n",
33 (unsigned int)desc->bytes_to_transfer);
34 debug("desc->actual_bytes_transferred : 0x%x \n",
35 (unsigned int)desc->actual_bytes_transferred);
36 debug("desc->descriptor_status : 0x%x \n",
37 (unsigned int)desc->descriptor_status);
38 debug("desc->descriptor_control : 0x%x \n",
39 (unsigned int)desc->descriptor_control);
40 }
41
42 /* This is a generic routine that the SGDMA mode-specific routines
43 * call to populate a descriptor.
44 * arg1 :pointer to first SGDMA descriptor.
45 * arg2 :pointer to next SGDMA descriptor.
46 * arg3 :Address to where data to be written.
47 * arg4 :Address from where data to be read.
48 * arg5 :no of byte to transaction.
49 * arg6 :variable indicating to generate start of packet or not
50 * arg7 :read fixed
51 * arg8 :write fixed
52 * arg9 :read burst
53 * arg10 :write burst
54 * arg11 :atlantic_channel number
55 */
alt_sgdma_construct_descriptor_burst(volatile struct alt_sgdma_descriptor * desc,volatile struct alt_sgdma_descriptor * next,unsigned int * read_addr,unsigned int * write_addr,unsigned short length_or_eop,int generate_eop,int read_fixed,int write_fixed_or_sop,int read_burst,int write_burst,unsigned char atlantic_channel)56 static void alt_sgdma_construct_descriptor_burst(
57 volatile struct alt_sgdma_descriptor *desc,
58 volatile struct alt_sgdma_descriptor *next,
59 unsigned int *read_addr,
60 unsigned int *write_addr,
61 unsigned short length_or_eop,
62 int generate_eop,
63 int read_fixed,
64 int write_fixed_or_sop,
65 int read_burst,
66 int write_burst,
67 unsigned char atlantic_channel)
68 {
69 /*
70 * Mark the "next" descriptor as "not" owned by hardware. This prevents
71 * The SGDMA controller from continuing to process the chain. This is
72 * done as a single IO write to bypass cache, without flushing
73 * the entire descriptor, since only the 8-bit descriptor status must
74 * be flushed.
75 */
76 if (!next)
77 debug("Next descriptor not defined!!\n");
78
79 next->descriptor_control = (next->descriptor_control &
80 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK);
81
82 desc->source = (unsigned int *)((unsigned int)read_addr & 0x1FFFFFFF);
83 desc->destination =
84 (unsigned int *)((unsigned int)write_addr & 0x1FFFFFFF);
85 desc->next = (unsigned int *)((unsigned int)next & 0x1FFFFFFF);
86 desc->source_pad = 0x0;
87 desc->destination_pad = 0x0;
88 desc->next_pad = 0x0;
89 desc->bytes_to_transfer = length_or_eop;
90 desc->actual_bytes_transferred = 0;
91 desc->descriptor_status = 0x0;
92
93 /* SGDMA burst not currently supported */
94 desc->read_burst = 0;
95 desc->write_burst = 0;
96
97 /*
98 * Set the descriptor control block as follows:
99 * - Set "owned by hardware" bit
100 * - Optionally set "generate EOP" bit
101 * - Optionally set the "read from fixed address" bit
102 * - Optionally set the "write to fixed address bit (which serves
103 * serves as a "generate SOP" control bit in memory-to-stream mode).
104 * - Set the 4-bit atlantic channel, if specified
105 *
106 * Note this step is performed after all other descriptor information
107 * has been filled out so that, if the controller already happens to be
108 * pointing at this descriptor, it will not run (via the "owned by
109 * hardware" bit) until all other descriptor has been set up.
110 */
111
112 desc->descriptor_control =
113 ((ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK) |
114 (generate_eop ?
115 ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK : 0x0) |
116 (read_fixed ?
117 ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK : 0x0) |
118 (write_fixed_or_sop ?
119 ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK : 0x0) |
120 (atlantic_channel ? ((atlantic_channel & 0x0F) << 3) : 0)
121 );
122 }
123
alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers * dev,volatile struct alt_sgdma_descriptor * desc)124 static int alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers *dev,
125 volatile struct alt_sgdma_descriptor *desc)
126 {
127 unsigned int status;
128 int counter = 0;
129
130 /* Wait for any pending transfers to complete */
131 alt_sgdma_print_desc(desc);
132 status = dev->status;
133
134 counter = 0;
135 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) {
136 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
137 break;
138 }
139
140 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
141 debug("Timeout waiting sgdma in do sync!\n");
142
143 /*
144 * Clear any (previous) status register information
145 * that might occlude our error checking later.
146 */
147 dev->status = 0xFF;
148
149 /* Point the controller at the descriptor */
150 dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF;
151 debug("next desc in sgdma 0x%x\n",
152 (unsigned int)dev->next_descriptor_pointer);
153
154 /*
155 * Set up SGDMA controller to:
156 * - Disable interrupt generation
157 * - Run once a valid descriptor is written to controller
158 * - Stop on an error with any particular descriptor
159 */
160 dev->control = (ALT_SGDMA_CONTROL_RUN_MSK |
161 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK);
162
163 /* Wait for the descriptor (chain) to complete */
164 status = dev->status;
165 debug("wait for sgdma....");
166 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK)
167 ;
168 debug("done\n");
169
170 /* Clear Run */
171 dev->control = (dev->control & (~ALT_SGDMA_CONTROL_RUN_MSK));
172
173 /* Get & clear status register contents */
174 status = dev->status;
175 dev->status = 0xFF;
176
177 /* we really should check if the transfer completes properly */
178 debug("tx sgdma status = 0x%x", status);
179 return 0;
180 }
181
alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers * dev,volatile struct alt_sgdma_descriptor * desc)182 static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers *dev,
183 volatile struct alt_sgdma_descriptor *desc)
184 {
185 unsigned int status;
186 int counter = 0;
187
188 /* Wait for any pending transfers to complete */
189 alt_sgdma_print_desc(desc);
190 status = dev->status;
191
192 counter = 0;
193 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) {
194 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
195 break;
196 }
197
198 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
199 debug("Timeout waiting sgdma in do async!\n");
200
201 /*
202 * Clear the RUN bit in the control register. This is needed
203 * to restart the SGDMA engine later on.
204 */
205 dev->control = 0;
206
207 /*
208 * Clear any (previous) status register information
209 * that might occlude our error checking later.
210 */
211 dev->status = 0xFF;
212
213 /* Point the controller at the descriptor */
214 dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF;
215
216 /*
217 * Set up SGDMA controller to:
218 * - Disable interrupt generation
219 * - Run once a valid descriptor is written to controller
220 * - Stop on an error with any particular descriptor
221 */
222 dev->control = (ALT_SGDMA_CONTROL_RUN_MSK |
223 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK);
224
225 /* we really should check if the transfer completes properly */
226 return 0;
227 }
228
229 /* u-boot interface */
tse_adjust_link(struct altera_tse_priv * priv)230 static int tse_adjust_link(struct altera_tse_priv *priv)
231 {
232 unsigned int refvar;
233
234 refvar = priv->mac_dev->command_config.image;
235
236 if (!(priv->duplexity))
237 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
238 else
239 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
240
241 switch (priv->speed) {
242 case 1000:
243 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
244 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
245 break;
246 case 100:
247 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
248 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
249 break;
250 case 10:
251 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
252 refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
253 break;
254 }
255 priv->mac_dev->command_config.image = refvar;
256
257 return 0;
258 }
259
tse_eth_send(struct eth_device * dev,void * packet,int length)260 static int tse_eth_send(struct eth_device *dev, void *packet, int length)
261 {
262 struct altera_tse_priv *priv = dev->priv;
263 volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
264 volatile struct alt_sgdma_descriptor *tx_desc =
265 (volatile struct alt_sgdma_descriptor *)priv->tx_desc;
266
267 volatile struct alt_sgdma_descriptor *tx_desc_cur =
268 (volatile struct alt_sgdma_descriptor *)&tx_desc[0];
269
270 flush_dcache_range((unsigned long)packet,
271 (unsigned long)packet + length);
272 alt_sgdma_construct_descriptor_burst(
273 (volatile struct alt_sgdma_descriptor *)&tx_desc[0],
274 (volatile struct alt_sgdma_descriptor *)&tx_desc[1],
275 (unsigned int *)packet, /* read addr */
276 (unsigned int *)0,
277 length, /* length or EOP ,will change for each tx */
278 0x1, /* gen eop */
279 0x0, /* read fixed */
280 0x1, /* write fixed or sop */
281 0x0, /* read burst */
282 0x0, /* write burst */
283 0x0 /* channel */
284 );
285 debug("TX Packet @ 0x%x,0x%x bytes", (unsigned int)packet, length);
286
287 /* send the packet */
288 debug("sending packet\n");
289 alt_sgdma_do_sync_transfer(tx_sgdma, tx_desc_cur);
290 debug("sent %d bytes\n", tx_desc_cur->actual_bytes_transferred);
291 return tx_desc_cur->actual_bytes_transferred;
292 }
293
tse_eth_rx(struct eth_device * dev)294 static int tse_eth_rx(struct eth_device *dev)
295 {
296 int packet_length = 0;
297 struct altera_tse_priv *priv = dev->priv;
298 volatile struct alt_sgdma_descriptor *rx_desc =
299 (volatile struct alt_sgdma_descriptor *)priv->rx_desc;
300 volatile struct alt_sgdma_descriptor *rx_desc_cur = &rx_desc[0];
301
302 if (rx_desc_cur->descriptor_status &
303 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
304 debug("got packet\n");
305 packet_length = rx_desc->actual_bytes_transferred;
306 net_process_received_packet(net_rx_packets[0], packet_length);
307
308 /* start descriptor again */
309 flush_dcache_range((unsigned long)(net_rx_packets[0]),
310 (unsigned long)(net_rx_packets[0] +
311 PKTSIZE_ALIGN));
312 alt_sgdma_construct_descriptor_burst(
313 (volatile struct alt_sgdma_descriptor *)&rx_desc[0],
314 (volatile struct alt_sgdma_descriptor *)&rx_desc[1],
315 (unsigned int)0x0, /* read addr */
316 (unsigned int *)net_rx_packets[0],
317 0x0, /* length or EOP */
318 0x0, /* gen eop */
319 0x0, /* read fixed */
320 0x0, /* write fixed or sop */
321 0x0, /* read burst */
322 0x0, /* write burst */
323 0x0 /* channel */
324 );
325
326 /* setup the sgdma */
327 alt_sgdma_do_async_transfer(priv->sgdma_rx, &rx_desc[0]);
328
329 return packet_length;
330 }
331
332 return -1;
333 }
334
tse_eth_halt(struct eth_device * dev)335 static void tse_eth_halt(struct eth_device *dev)
336 {
337 /* don't do anything! */
338 /* this gets called after each uboot */
339 /* network command. don't need to reset the thing all of the time */
340 }
341
tse_eth_reset(struct eth_device * dev)342 static void tse_eth_reset(struct eth_device *dev)
343 {
344 /* stop sgdmas, disable tse receive */
345 struct altera_tse_priv *priv = dev->priv;
346 volatile struct alt_tse_mac *mac_dev = priv->mac_dev;
347 volatile struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
348 volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
349 int counter;
350 volatile struct alt_sgdma_descriptor *rx_desc =
351 (volatile struct alt_sgdma_descriptor *)&priv->rx_desc[0];
352
353 /* clear rx desc & wait for sgdma to complete */
354 rx_desc->descriptor_control = 0;
355 rx_sgdma->control = 0;
356 counter = 0;
357 while (rx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) {
358 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
359 break;
360 }
361
362 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) {
363 debug("Timeout waiting for rx sgdma!\n");
364 rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
365 rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
366 }
367
368 counter = 0;
369 tx_sgdma->control = 0;
370 while (tx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) {
371 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
372 break;
373 }
374
375 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) {
376 debug("Timeout waiting for tx sgdma!\n");
377 tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
378 tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
379 }
380 /* reset the mac */
381 mac_dev->command_config.bits.transmit_enable = 1;
382 mac_dev->command_config.bits.receive_enable = 1;
383 mac_dev->command_config.bits.software_reset = 1;
384
385 counter = 0;
386 while (mac_dev->command_config.bits.software_reset) {
387 if (counter++ > ALT_TSE_SW_RESET_WATCHDOG_CNTR)
388 break;
389 }
390
391 if (counter >= ALT_TSE_SW_RESET_WATCHDOG_CNTR)
392 debug("TSEMAC SW reset bit never cleared!\n");
393 }
394
tse_mdio_read(struct altera_tse_priv * priv,unsigned int regnum)395 static int tse_mdio_read(struct altera_tse_priv *priv, unsigned int regnum)
396 {
397 volatile struct alt_tse_mac *mac_dev;
398 unsigned int *mdio_regs;
399 unsigned int data;
400 u16 value;
401
402 mac_dev = priv->mac_dev;
403
404 /* set mdio address */
405 mac_dev->mdio_phy1_addr = priv->phyaddr;
406 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1;
407
408 /* get the data */
409 data = mdio_regs[regnum];
410
411 value = data & 0xffff;
412
413 return value;
414 }
415
tse_mdio_write(struct altera_tse_priv * priv,unsigned int regnum,unsigned int value)416 static int tse_mdio_write(struct altera_tse_priv *priv, unsigned int regnum,
417 unsigned int value)
418 {
419 volatile struct alt_tse_mac *mac_dev;
420 unsigned int *mdio_regs;
421 unsigned int data;
422
423 mac_dev = priv->mac_dev;
424
425 /* set mdio address */
426 mac_dev->mdio_phy1_addr = priv->phyaddr;
427 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1;
428
429 /* get the data */
430 data = (unsigned int)value;
431
432 mdio_regs[regnum] = data;
433
434 return 0;
435 }
436
437 /* MDIO access to phy */
438 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
altera_tse_miiphy_write(const char * devname,unsigned char addr,unsigned char reg,unsigned short value)439 static int altera_tse_miiphy_write(const char *devname, unsigned char addr,
440 unsigned char reg, unsigned short value)
441 {
442 struct eth_device *dev;
443 struct altera_tse_priv *priv;
444 dev = eth_get_dev_by_name(devname);
445 priv = dev->priv;
446
447 tse_mdio_write(priv, (uint) reg, (uint) value);
448
449 return 0;
450 }
451
altera_tse_miiphy_read(const char * devname,unsigned char addr,unsigned char reg,unsigned short * value)452 static int altera_tse_miiphy_read(const char *devname, unsigned char addr,
453 unsigned char reg, unsigned short *value)
454 {
455 struct eth_device *dev;
456 struct altera_tse_priv *priv;
457 volatile struct alt_tse_mac *mac_dev;
458 unsigned int *mdio_regs;
459
460 dev = eth_get_dev_by_name(devname);
461 priv = dev->priv;
462
463 mac_dev = priv->mac_dev;
464 mac_dev->mdio_phy1_addr = (int)addr;
465 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1;
466
467 *value = 0xffff & mdio_regs[reg];
468
469 return 0;
470
471 }
472 #endif
473
474 /*
475 * Also copied from tsec.c
476 */
477 /* Parse the status register for link, and then do
478 * auto-negotiation
479 */
mii_parse_sr(uint mii_reg,struct altera_tse_priv * priv)480 static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv)
481 {
482 /*
483 * Wait if the link is up, and autonegotiation is in progress
484 * (ie - we're capable and it's not done)
485 */
486 mii_reg = tse_mdio_read(priv, MIIM_STATUS);
487
488 if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & BMSR_ANEGCAPABLE)
489 && !(mii_reg & BMSR_ANEGCOMPLETE)) {
490 int i = 0;
491
492 puts("Waiting for PHY auto negotiation to complete");
493 while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
494 /*
495 * Timeout reached ?
496 */
497 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
498 puts(" TIMEOUT !\n");
499 priv->link = 0;
500 return 0;
501 }
502
503 if ((i++ % 1000) == 0)
504 putc('.');
505 udelay(1000); /* 1 ms */
506 mii_reg = tse_mdio_read(priv, MIIM_STATUS);
507 }
508 puts(" done\n");
509 priv->link = 1;
510 udelay(500000); /* another 500 ms (results in faster booting) */
511 } else {
512 if (mii_reg & MIIM_STATUS_LINK) {
513 debug("Link is up\n");
514 priv->link = 1;
515 } else {
516 debug("Link is down\n");
517 priv->link = 0;
518 }
519 }
520
521 return 0;
522 }
523
524 /* Parse the 88E1011's status register for speed and duplex
525 * information
526 */
mii_parse_88E1011_psr(uint mii_reg,struct altera_tse_priv * priv)527 static uint mii_parse_88E1011_psr(uint mii_reg, struct altera_tse_priv *priv)
528 {
529 uint speed;
530
531 mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS);
532
533 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
534 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
535 int i = 0;
536
537 puts("Waiting for PHY realtime link");
538 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
539 /* Timeout reached ? */
540 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
541 puts(" TIMEOUT !\n");
542 priv->link = 0;
543 break;
544 }
545
546 if ((i++ == 1000) == 0) {
547 i = 0;
548 puts(".");
549 }
550 udelay(1000); /* 1 ms */
551 mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS);
552 }
553 puts(" done\n");
554 udelay(500000); /* another 500 ms (results in faster booting) */
555 } else {
556 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
557 priv->link = 1;
558 else
559 priv->link = 0;
560 }
561
562 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
563 priv->duplexity = 1;
564 else
565 priv->duplexity = 0;
566
567 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
568
569 switch (speed) {
570 case MIIM_88E1011_PHYSTAT_GBIT:
571 priv->speed = 1000;
572 debug("PHY Speed is 1000Mbit\n");
573 break;
574 case MIIM_88E1011_PHYSTAT_100:
575 debug("PHY Speed is 100Mbit\n");
576 priv->speed = 100;
577 break;
578 default:
579 debug("PHY Speed is 10Mbit\n");
580 priv->speed = 10;
581 }
582
583 return 0;
584 }
585
mii_m88e1111s_setmode_sr(uint mii_reg,struct altera_tse_priv * priv)586 static uint mii_m88e1111s_setmode_sr(uint mii_reg, struct altera_tse_priv *priv)
587 {
588 uint mii_data = tse_mdio_read(priv, mii_reg);
589 mii_data &= 0xfff0;
590 if ((priv->flags >= 1) && (priv->flags <= 4))
591 mii_data |= 0xb;
592 else if (priv->flags == 5)
593 mii_data |= 0x4;
594
595 return mii_data;
596 }
597
mii_m88e1111s_setmode_cr(uint mii_reg,struct altera_tse_priv * priv)598 static uint mii_m88e1111s_setmode_cr(uint mii_reg, struct altera_tse_priv *priv)
599 {
600 uint mii_data = tse_mdio_read(priv, mii_reg);
601 mii_data &= ~0x82;
602 if ((priv->flags >= 1) && (priv->flags <= 4))
603 mii_data |= 0x82;
604
605 return mii_data;
606 }
607
608 /*
609 * Returns which value to write to the control register.
610 * For 10/100, the value is slightly different
611 */
mii_cr_init(uint mii_reg,struct altera_tse_priv * priv)612 static uint mii_cr_init(uint mii_reg, struct altera_tse_priv *priv)
613 {
614 return MIIM_CONTROL_INIT;
615 }
616
617 /*
618 * PHY & MDIO code
619 * Need to add SGMII stuff
620 *
621 */
622
623 static struct phy_info phy_info_M88E1111S = {
624 0x01410cc,
625 "Marvell 88E1111S",
626 4,
627 (struct phy_cmd[]){ /* config */
628 /* Reset and configure the PHY */
629 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
630 {MIIM_88E1111_PHY_EXT_SR, 0x848f,
631 &mii_m88e1111s_setmode_sr},
632 /* Delay RGMII TX and RX */
633 {MIIM_88E1111_PHY_EXT_CR, 0x0cd2,
634 &mii_m88e1111s_setmode_cr},
635 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
636 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
637 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
638 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
639 {miim_end,}
640 },
641 (struct phy_cmd[]){ /* startup */
642 /* Status is read once to clear old link state */
643 {MIIM_STATUS, miim_read, NULL},
644 /* Auto-negotiate */
645 {MIIM_STATUS, miim_read, &mii_parse_sr},
646 /* Read the status */
647 {MIIM_88E1011_PHY_STATUS, miim_read,
648 &mii_parse_88E1011_psr},
649 {miim_end,}
650 },
651 (struct phy_cmd[]){ /* shutdown */
652 {miim_end,}
653 },
654 };
655
656 /* a generic flavor. */
657 static struct phy_info phy_info_generic = {
658 0,
659 "Unknown/Generic PHY",
660 32,
661 (struct phy_cmd[]){ /* config */
662 {MII_BMCR, BMCR_RESET, NULL},
663 {MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART, NULL},
664 {miim_end,}
665 },
666 (struct phy_cmd[]){ /* startup */
667 {MII_BMSR, miim_read, NULL},
668 {MII_BMSR, miim_read, &mii_parse_sr},
669 {miim_end,}
670 },
671 (struct phy_cmd[]){ /* shutdown */
672 {miim_end,}
673 }
674 };
675
676 static struct phy_info *phy_info[] = {
677 &phy_info_M88E1111S,
678 NULL
679 };
680
681 /* Grab the identifier of the device's PHY, and search through
682 * all of the known PHYs to see if one matches. If so, return
683 * it, if not, return NULL
684 */
get_phy_info(struct eth_device * dev)685 static struct phy_info *get_phy_info(struct eth_device *dev)
686 {
687 struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv;
688 uint phy_reg, phy_ID;
689 int i;
690 struct phy_info *theInfo = NULL;
691
692 /* Grab the bits from PHYIR1, and put them in the upper half */
693 phy_reg = tse_mdio_read(priv, MIIM_PHYIR1);
694 phy_ID = (phy_reg & 0xffff) << 16;
695
696 /* Grab the bits from PHYIR2, and put them in the lower half */
697 phy_reg = tse_mdio_read(priv, MIIM_PHYIR2);
698 phy_ID |= (phy_reg & 0xffff);
699
700 /* loop through all the known PHY types, and find one that */
701 /* matches the ID we read from the PHY. */
702 for (i = 0; phy_info[i]; i++) {
703 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
704 theInfo = phy_info[i];
705 break;
706 }
707 }
708
709 if (theInfo == NULL) {
710 theInfo = &phy_info_generic;
711 debug("%s: No support for PHY id %x; assuming generic\n",
712 dev->name, phy_ID);
713 } else
714 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
715
716 return theInfo;
717 }
718
719 /* Execute the given series of commands on the given device's
720 * PHY, running functions as necessary
721 */
phy_run_commands(struct altera_tse_priv * priv,struct phy_cmd * cmd)722 static void phy_run_commands(struct altera_tse_priv *priv, struct phy_cmd *cmd)
723 {
724 int i;
725 uint result;
726
727 for (i = 0; cmd->mii_reg != miim_end; i++) {
728 if (cmd->mii_data == miim_read) {
729 result = tse_mdio_read(priv, cmd->mii_reg);
730
731 if (cmd->funct != NULL)
732 (*(cmd->funct)) (result, priv);
733
734 } else {
735 if (cmd->funct != NULL)
736 result = (*(cmd->funct)) (cmd->mii_reg, priv);
737 else
738 result = cmd->mii_data;
739
740 tse_mdio_write(priv, cmd->mii_reg, result);
741
742 }
743 cmd++;
744 }
745 }
746
747 /* Phy init code */
init_phy(struct eth_device * dev)748 static int init_phy(struct eth_device *dev)
749 {
750 struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv;
751 struct phy_info *curphy;
752
753 /* Get the cmd structure corresponding to the attached
754 * PHY */
755 curphy = get_phy_info(dev);
756
757 if (curphy == NULL) {
758 priv->phyinfo = NULL;
759 debug("%s: No PHY found\n", dev->name);
760
761 return 0;
762 } else
763 debug("%s found\n", curphy->name);
764 priv->phyinfo = curphy;
765
766 phy_run_commands(priv, priv->phyinfo->config);
767
768 return 1;
769 }
770
tse_set_mac_address(struct eth_device * dev)771 static int tse_set_mac_address(struct eth_device *dev)
772 {
773 struct altera_tse_priv *priv = dev->priv;
774 volatile struct alt_tse_mac *mac_dev = priv->mac_dev;
775
776 debug("Setting MAC address to 0x%02x%02x%02x%02x%02x%02x\n",
777 dev->enetaddr[5], dev->enetaddr[4],
778 dev->enetaddr[3], dev->enetaddr[2],
779 dev->enetaddr[1], dev->enetaddr[0]);
780 mac_dev->mac_addr_0 = ((dev->enetaddr[3]) << 24 |
781 (dev->enetaddr[2]) << 16 |
782 (dev->enetaddr[1]) << 8 | (dev->enetaddr[0]));
783
784 mac_dev->mac_addr_1 = ((dev->enetaddr[5] << 8 |
785 (dev->enetaddr[4])) & 0xFFFF);
786
787 /* Set the MAC address */
788 mac_dev->supp_mac_addr_0_0 = mac_dev->mac_addr_0;
789 mac_dev->supp_mac_addr_0_1 = mac_dev->mac_addr_1;
790
791 /* Set the MAC address */
792 mac_dev->supp_mac_addr_1_0 = mac_dev->mac_addr_0;
793 mac_dev->supp_mac_addr_1_1 = mac_dev->mac_addr_1;
794
795 /* Set the MAC address */
796 mac_dev->supp_mac_addr_2_0 = mac_dev->mac_addr_0;
797 mac_dev->supp_mac_addr_2_1 = mac_dev->mac_addr_1;
798
799 /* Set the MAC address */
800 mac_dev->supp_mac_addr_3_0 = mac_dev->mac_addr_0;
801 mac_dev->supp_mac_addr_3_1 = mac_dev->mac_addr_1;
802 return 0;
803 }
804
tse_eth_init(struct eth_device * dev,bd_t * bd)805 static int tse_eth_init(struct eth_device *dev, bd_t * bd)
806 {
807 int dat;
808 struct altera_tse_priv *priv = dev->priv;
809 volatile struct alt_tse_mac *mac_dev = priv->mac_dev;
810 volatile struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
811 volatile struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
812 volatile struct alt_sgdma_descriptor *rx_desc_cur =
813 (volatile struct alt_sgdma_descriptor *)&rx_desc[0];
814
815 /* stop controller */
816 debug("Reseting TSE & SGDMAs\n");
817 tse_eth_reset(dev);
818
819 /* start the phy */
820 debug("Configuring PHY\n");
821 phy_run_commands(priv, priv->phyinfo->startup);
822
823 /* need to create sgdma */
824 debug("Configuring tx desc\n");
825 alt_sgdma_construct_descriptor_burst(
826 (volatile struct alt_sgdma_descriptor *)&tx_desc[0],
827 (volatile struct alt_sgdma_descriptor *)&tx_desc[1],
828 (unsigned int *)NULL, /* read addr */
829 (unsigned int *)0,
830 0, /* length or EOP ,will change for each tx */
831 0x1, /* gen eop */
832 0x0, /* read fixed */
833 0x1, /* write fixed or sop */
834 0x0, /* read burst */
835 0x0, /* write burst */
836 0x0 /* channel */
837 );
838 debug("Configuring rx desc\n");
839 flush_dcache_range((unsigned long)(net_rx_packets[0]),
840 (unsigned long)(net_rx_packets[0]) + PKTSIZE_ALIGN);
841 alt_sgdma_construct_descriptor_burst(
842 (volatile struct alt_sgdma_descriptor *)&rx_desc[0],
843 (volatile struct alt_sgdma_descriptor *)&rx_desc[1],
844 (unsigned int)0x0, /* read addr */
845 (unsigned int *)net_rx_packets[0],
846 0x0, /* length or EOP */
847 0x0, /* gen eop */
848 0x0, /* read fixed */
849 0x0, /* write fixed or sop */
850 0x0, /* read burst */
851 0x0, /* write burst */
852 0x0 /* channel */
853 );
854 /* start rx async transfer */
855 debug("Starting rx sgdma\n");
856 alt_sgdma_do_async_transfer(priv->sgdma_rx, rx_desc_cur);
857
858 /* start TSE */
859 debug("Configuring TSE Mac\n");
860 /* Initialize MAC registers */
861 mac_dev->max_frame_length = PKTSIZE_ALIGN;
862 mac_dev->rx_almost_empty_threshold = 8;
863 mac_dev->rx_almost_full_threshold = 8;
864 mac_dev->tx_almost_empty_threshold = 8;
865 mac_dev->tx_almost_full_threshold = 3;
866 mac_dev->tx_sel_empty_threshold =
867 CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16;
868 mac_dev->tx_sel_full_threshold = 0;
869 mac_dev->rx_sel_empty_threshold =
870 CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16;
871 mac_dev->rx_sel_full_threshold = 0;
872
873 /* NO Shift */
874 mac_dev->rx_cmd_stat.bits.rx_shift16 = 0;
875 mac_dev->tx_cmd_stat.bits.tx_shift16 = 0;
876
877 /* enable MAC */
878 dat = 0;
879 dat = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
880
881 mac_dev->command_config.image = dat;
882
883 /* configure the TSE core */
884 /* -- output clocks, */
885 /* -- and later config stuff for SGMII */
886 if (priv->link) {
887 debug("Adjusting TSE to link speed\n");
888 tse_adjust_link(priv);
889 }
890
891 return priv->link ? 0 : -1;
892 }
893
894 /* TSE init code */
altera_tse_initialize(u8 dev_num,int mac_base,int sgdma_rx_base,int sgdma_tx_base,u32 sgdma_desc_base,u32 sgdma_desc_size)895 int altera_tse_initialize(u8 dev_num, int mac_base,
896 int sgdma_rx_base, int sgdma_tx_base,
897 u32 sgdma_desc_base, u32 sgdma_desc_size)
898 {
899 struct altera_tse_priv *priv;
900 struct eth_device *dev;
901 struct alt_sgdma_descriptor *rx_desc;
902 struct alt_sgdma_descriptor *tx_desc;
903 unsigned long dma_handle;
904
905 dev = (struct eth_device *)malloc(sizeof *dev);
906
907 if (NULL == dev)
908 return 0;
909
910 memset(dev, 0, sizeof *dev);
911
912 priv = malloc(sizeof(*priv));
913
914 if (!priv) {
915 free(dev);
916 return 0;
917 }
918 if (sgdma_desc_size) {
919 if (sgdma_desc_size < (sizeof(*tx_desc) * (3 + PKTBUFSRX))) {
920 printf("ALTERA_TSE-%hu: "
921 "descriptor memory is too small\n", dev_num);
922 free(priv);
923 free(dev);
924 return 0;
925 }
926 tx_desc = (struct alt_sgdma_descriptor *)sgdma_desc_base;
927 } else {
928 tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX),
929 &dma_handle);
930 }
931
932 rx_desc = tx_desc + 2;
933 debug("tx desc: address = 0x%x\n", (unsigned int)tx_desc);
934 debug("rx desc: address = 0x%x\n", (unsigned int)rx_desc);
935
936 if (!tx_desc) {
937 free(priv);
938 free(dev);
939 return 0;
940 }
941 memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1));
942 memset(tx_desc, 0, (sizeof *tx_desc) * 2);
943
944 /* initialize tse priv */
945 priv->mac_dev = (volatile struct alt_tse_mac *)mac_base;
946 priv->sgdma_rx = (volatile struct alt_sgdma_registers *)sgdma_rx_base;
947 priv->sgdma_tx = (volatile struct alt_sgdma_registers *)sgdma_tx_base;
948 priv->phyaddr = CONFIG_SYS_ALTERA_TSE_PHY_ADDR;
949 priv->flags = CONFIG_SYS_ALTERA_TSE_FLAGS;
950 priv->rx_desc = rx_desc;
951 priv->tx_desc = tx_desc;
952
953 /* init eth structure */
954 dev->priv = priv;
955 dev->init = tse_eth_init;
956 dev->halt = tse_eth_halt;
957 dev->send = tse_eth_send;
958 dev->recv = tse_eth_rx;
959 dev->write_hwaddr = tse_set_mac_address;
960 sprintf(dev->name, "%s-%hu", "ALTERA_TSE", dev_num);
961
962 eth_register(dev);
963
964 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
965 miiphy_register(dev->name, altera_tse_miiphy_read,
966 altera_tse_miiphy_write);
967 #endif
968
969 init_phy(dev);
970
971 return 1;
972 }
973