1 /* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * board/config.h - configuration options, board specific 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20 #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ 21 #define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ 22 #define CONFIG_SYS_GENERIC_BOARD 23 #define CONFIG_DISPLAY_BOARDINFO 24 25 #define CONFIG_SYS_TEXT_BASE 0x40000000 26 27 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 28 #define CONFIG_SYS_SMC_RXBUFLEN 128 29 #define CONFIG_SYS_MAXIDLE 10 30 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 31 32 #define CONFIG_BOOTCOUNT_LIMIT 33 34 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 35 36 #define CONFIG_BOARD_TYPES 1 /* support board types */ 37 38 #define CONFIG_PREBOOT "echo;" \ 39 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 40 "echo" 41 42 #undef CONFIG_BOOTARGS 43 44 #define CONFIG_EXTRA_ENV_SETTINGS \ 45 "netdev=eth0\0" \ 46 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 47 "nfsroot=${serverip}:${rootpath}\0" \ 48 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 49 "addip=setenv bootargs ${bootargs} " \ 50 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 51 ":${hostname}:${netdev}:off panic=1\0" \ 52 "flash_nfs=run nfsargs addip;" \ 53 "bootm ${kernel_addr}\0" \ 54 "flash_self=run ramargs addip;" \ 55 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 56 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 57 "rootpath=/opt/eldk/ppc_8xx\0" \ 58 "hostname=TQM860M\0" \ 59 "bootfile=TQM860M/uImage\0" \ 60 "fdt_addr=400C0000\0" \ 61 "kernel_addr=40100000\0" \ 62 "ramdisk_addr=40280000\0" \ 63 "u-boot=TQM860M/u-image.bin\0" \ 64 "load=tftp 200000 ${u-boot}\0" \ 65 "update=prot off 40000000 +${filesize};" \ 66 "era 40000000 +${filesize};" \ 67 "cp.b 200000 40000000 ${filesize};" \ 68 "sete filesize;save\0" \ 69 "" 70 #define CONFIG_BOOTCOMMAND "run flash_self" 71 72 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 73 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 74 75 #undef CONFIG_WATCHDOG /* watchdog disabled */ 76 77 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 78 79 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 80 81 /* 82 * BOOTP options 83 */ 84 #define CONFIG_BOOTP_SUBNETMASK 85 #define CONFIG_BOOTP_GATEWAY 86 #define CONFIG_BOOTP_HOSTNAME 87 #define CONFIG_BOOTP_BOOTPATH 88 #define CONFIG_BOOTP_BOOTFILESIZE 89 90 91 #define CONFIG_MAC_PARTITION 92 #define CONFIG_DOS_PARTITION 93 94 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 95 96 97 /* 98 * Command line configuration. 99 */ 100 #define CONFIG_CMD_ASKENV 101 #define CONFIG_CMD_DATE 102 #define CONFIG_CMD_DHCP 103 #define CONFIG_CMD_ELF 104 #define CONFIG_CMD_EXT2 105 #define CONFIG_CMD_IDE 106 #define CONFIG_CMD_JFFS2 107 #define CONFIG_CMD_SNTP 108 109 110 #define CONFIG_NETCONSOLE 111 112 113 /* 114 * Miscellaneous configurable options 115 */ 116 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 117 118 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 119 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 120 121 #if defined(CONFIG_CMD_KGDB) 122 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 123 #else 124 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 125 #endif 126 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 127 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 128 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 129 130 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 131 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 132 133 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 134 135 /* 136 * Low Level Configuration Settings 137 * (address mappings, register initial values, etc.) 138 * You should know what you are doing if you make changes here. 139 */ 140 /*----------------------------------------------------------------------- 141 * Internal Memory Mapped Register 142 */ 143 #define CONFIG_SYS_IMMR 0xFFF00000 144 145 /*----------------------------------------------------------------------- 146 * Definitions for initial stack pointer and data area (in DPRAM) 147 */ 148 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 149 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 150 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 151 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 152 153 /*----------------------------------------------------------------------- 154 * Start addresses for the final memory configuration 155 * (Set up by the startup code) 156 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 157 */ 158 #define CONFIG_SYS_SDRAM_BASE 0x00000000 159 #define CONFIG_SYS_FLASH_BASE 0x40000000 160 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 162 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ 163 164 /* 165 * For booting Linux, the board info and command line data 166 * have to be in the first 8 MB of memory, since this is 167 * the maximum mapped by the Linux kernel during initialization. 168 */ 169 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 170 171 /*----------------------------------------------------------------------- 172 * FLASH organization 173 */ 174 /* use CFI flash driver */ 175 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 176 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 177 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 178 #define CONFIG_SYS_FLASH_EMPTY_INFO 179 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 180 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 181 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 182 183 #define CONFIG_ENV_IS_IN_FLASH 1 184 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 185 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ 186 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ 187 188 /* Address and size of Redundant Environment Sector */ 189 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 190 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 191 192 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 193 194 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 195 196 /*----------------------------------------------------------------------- 197 * Dynamic MTD partition support 198 */ 199 #define CONFIG_CMD_MTDPARTS 200 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 201 #define CONFIG_FLASH_CFI_MTD 202 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" 203 204 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ 205 "128k(dtb)," \ 206 "1920k(kernel)," \ 207 "5632(rootfs)," \ 208 "4m(data)" 209 210 /*----------------------------------------------------------------------- 211 * Hardware Information Block 212 */ 213 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 214 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 215 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 216 217 /*----------------------------------------------------------------------- 218 * Cache Configuration 219 */ 220 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 221 #if defined(CONFIG_CMD_KGDB) 222 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 223 #endif 224 225 /*----------------------------------------------------------------------- 226 * SYPCR - System Protection Control 11-9 227 * SYPCR can only be written once after reset! 228 *----------------------------------------------------------------------- 229 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 230 */ 231 #if defined(CONFIG_WATCHDOG) 232 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 233 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 234 #else 235 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 236 #endif 237 238 /*----------------------------------------------------------------------- 239 * SIUMCR - SIU Module Configuration 11-6 240 *----------------------------------------------------------------------- 241 * PCMCIA config., multi-function pin tri-state 242 */ 243 #ifndef CONFIG_CAN_DRIVER 244 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 245 #else /* we must activate GPL5 in the SIUMCR for CAN */ 246 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 247 #endif /* CONFIG_CAN_DRIVER */ 248 249 /*----------------------------------------------------------------------- 250 * TBSCR - Time Base Status and Control 11-26 251 *----------------------------------------------------------------------- 252 * Clear Reference Interrupt Status, Timebase freezing enabled 253 */ 254 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 255 256 /*----------------------------------------------------------------------- 257 * RTCSC - Real-Time Clock Status and Control Register 11-27 258 *----------------------------------------------------------------------- 259 */ 260 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 261 262 /*----------------------------------------------------------------------- 263 * PISCR - Periodic Interrupt Status and Control 11-31 264 *----------------------------------------------------------------------- 265 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 266 */ 267 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 268 269 /*----------------------------------------------------------------------- 270 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 271 *----------------------------------------------------------------------- 272 * Reset PLL lock status sticky bit, timer expired status bit and timer 273 * interrupt status bit 274 */ 275 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 276 277 /*----------------------------------------------------------------------- 278 * SCCR - System Clock and reset Control Register 15-27 279 *----------------------------------------------------------------------- 280 * Set clock output, timebase and RTC source and divider, 281 * power management and some other internal clocks 282 */ 283 #define SCCR_MASK SCCR_EBDF11 284 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 285 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 286 SCCR_DFALCD00) 287 288 /*----------------------------------------------------------------------- 289 * PCMCIA stuff 290 *----------------------------------------------------------------------- 291 * 292 */ 293 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 294 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 295 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 296 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 297 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 298 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 299 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 300 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 301 302 /*----------------------------------------------------------------------- 303 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 304 *----------------------------------------------------------------------- 305 */ 306 307 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 308 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 309 310 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 311 #undef CONFIG_IDE_LED /* LED for ide not supported */ 312 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 313 314 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 315 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 316 317 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 318 319 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 320 321 /* Offset for data I/O */ 322 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 323 324 /* Offset for normal register accesses */ 325 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 326 327 /* Offset for alternate registers */ 328 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 329 330 /*----------------------------------------------------------------------- 331 * 332 *----------------------------------------------------------------------- 333 * 334 */ 335 #define CONFIG_SYS_DER 0 336 337 /* 338 * Init Memory Controller: 339 * 340 * BR0/1 and OR0/1 (FLASH) 341 */ 342 343 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 344 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 345 346 /* used to re-map FLASH both when starting from SRAM or FLASH: 347 * restrict access enough to keep SRAM working (if any) 348 * but not too much to meddle with FLASH accesses 349 */ 350 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 351 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 352 353 /* 354 * FLASH timing: 355 */ 356 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 357 OR_SCY_3_CLK | OR_EHTR | OR_BI) 358 359 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 360 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 361 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 362 363 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 364 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 365 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 366 367 /* 368 * BR2/3 and OR2/3 (SDRAM) 369 * 370 */ 371 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 372 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 373 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */ 374 375 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 376 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 377 378 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 379 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 380 381 #ifndef CONFIG_CAN_DRIVER 382 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 383 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 384 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 385 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 386 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 387 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 388 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 389 BR_PS_8 | BR_MS_UPMB | BR_V ) 390 #endif /* CONFIG_CAN_DRIVER */ 391 392 /* 393 * Memory Periodic Timer Prescaler 394 * 395 * The Divider for PTA (refresh timer) configuration is based on an 396 * example SDRAM configuration (64 MBit, one bank). The adjustment to 397 * the number of chip selects (NCS) and the actually needed refresh 398 * rate is done by setting MPTPR. 399 * 400 * PTA is calculated from 401 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 402 * 403 * gclk CPU clock (not bus clock!) 404 * Trefresh Refresh cycle * 4 (four word bursts used) 405 * 406 * 4096 Rows from SDRAM example configuration 407 * 1000 factor s -> ms 408 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 409 * 4 Number of refresh cycles per period 410 * 64 Refresh cycle in ms per number of rows 411 * -------------------------------------------- 412 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 413 * 414 * 50 MHz => 50.000.000 / Divider = 98 415 * 66 Mhz => 66.000.000 / Divider = 129 416 * 80 Mhz => 80.000.000 / Divider = 156 417 */ 418 419 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 420 #define CONFIG_SYS_MAMR_PTA 98 421 422 /* 423 * For 16 MBit, refresh rates could be 31.3 us 424 * (= 64 ms / 2K = 125 / quad bursts). 425 * For a simpler initialization, 15.6 us is used instead. 426 * 427 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 428 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 429 */ 430 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 431 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 432 433 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 434 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 435 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 436 437 /* 438 * MAMR settings for SDRAM 439 */ 440 441 /* 8 column SDRAM */ 442 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 443 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 444 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 445 /* 9 column SDRAM */ 446 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 447 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 448 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 449 /* 10 column SDRAM */ 450 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 451 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ 452 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 453 454 #define CONFIG_SCC1_ENET 455 #define CONFIG_FEC_ENET 456 #define CONFIG_ETHPRIME "SCC" 457 458 /* pass open firmware flat tree */ 459 #define CONFIG_OF_LIBFDT 1 460 #define CONFIG_OF_BOARD_SETUP 1 461 #define CONFIG_HWCONFIG 1 462 463 #endif /* __CONFIG_H */ 464