1 /* 2 * (C) Copyright 2006 3 * MicroSys GmbH 4 * 5 * (C) Copyright 2009 6 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 18 #define CONFIG_MPC5200 19 #define CONFIG_MPX5200 1 /* MPX5200 board */ 20 #define CONFIG_MPC5200_DDR 1 /* use DDR RAM */ 21 #define CONFIG_IPEK01 /* Motherboard is ipek01 */ 22 23 #define CONFIG_SYS_TEXT_BASE 0xfc000000 24 25 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ 26 27 #define CONFIG_MISC_INIT_R 28 29 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 30 #ifdef CONFIG_CMD_KGDB 31 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 32 #endif 33 34 /* 35 * Serial console configuration 36 */ 37 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 38 #define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */ 39 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 40 41 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 42 43 /* 44 * Video configuration for LIME GDC 45 */ 46 #define CONFIG_VIDEO 47 #ifdef CONFIG_VIDEO 48 #define CONFIG_VIDEO_MB862xx 49 #define CONFIG_VIDEO_MB862xx_ACCEL 50 #define VIDEO_FB_16BPP_WORD_SWAP 51 #define CONFIG_CFB_CONSOLE 52 #define CONFIG_VIDEO_LOGO 53 #define CONFIG_VIDEO_BMP_LOGO 54 #define CONFIG_CONSOLE_EXTRA_INFO 55 #define CONFIG_VGA_AS_SINGLE_DEVICE 56 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 57 #define CONFIG_VIDEO_SW_CURSOR 58 #define CONFIG_SPLASH_SCREEN 59 #define CONFIG_VIDEO_BMP_GZIP 60 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ 61 /* Lime clock frequency */ 62 #define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */ 63 /* SDRAM parameter */ 64 #define CONFIG_SYS_MB862xx_MMR 0x41c767e3 65 #endif 66 67 /* 68 * PCI Mapping: 69 * 0x40000000 - 0x4fffffff - PCI Memory 70 * 0x50000000 - 0x50ffffff - PCI IO Space 71 */ 72 #define CONFIG_PCI 1 73 #define CONFIG_PCI_PNP 1 74 #define CONFIG_PCI_SCAN_SHOW 1 75 76 #define CONFIG_PCI_MEM_BUS 0x40000000 77 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 78 #define CONFIG_PCI_MEM_SIZE 0x10000000 79 80 #define CONFIG_PCI_IO_BUS 0x50000000 81 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 82 #define CONFIG_PCI_IO_SIZE 0x01000000 83 84 #define CONFIG_MII 1 85 #define CONFIG_EEPRO100 1 86 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 87 88 /* Partitions */ 89 #define CONFIG_DOS_PARTITION 90 91 /* USB */ 92 #define CONFIG_USB_OHCI_NEW 93 #define CONFIG_SYS_OHCI_BE_CONTROLLER 94 #define CONFIG_USB_STORAGE 95 96 #define CONFIG_SYS_USB_OHCI_CPU_INIT 97 #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB 98 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" 99 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 100 101 /* 102 * Command line configuration. 103 */ 104 #ifdef CONFIG_VIDEO 105 #define CONFIG_CMD_BMP /* BMP support */ 106 #endif 107 #define CONFIG_CMD_DATE /* support for RTC, date/time...*/ 108 #define CONFIG_CMD_DHCP /* DHCP Support */ 109 #define CONFIG_CMD_FAT /* FAT support */ 110 #define CONFIG_CMD_I2C /* I2C serial bus support */ 111 #define CONFIG_CMD_IDE /* IDE harddisk support */ 112 #define CONFIG_CMD_IRQ /* irqinfo */ 113 #define CONFIG_CMD_MII /* MII support */ 114 #define CONFIG_CMD_PCI /* pciinfo */ 115 #define CONFIG_CMD_USB /* USB Support */ 116 117 #define CONFIG_SYS_LOWBOOT 1 118 119 /* 120 * Autobooting 121 */ 122 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 123 124 #define CONFIG_PREBOOT "echo;" \ 125 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 126 "echo" 127 128 #undef CONFIG_BOOTARGS 129 130 #define CONFIG_EXTRA_ENV_SETTINGS \ 131 "netdev=eth0\0" \ 132 "consoledev=ttyPSC0\0" \ 133 "hostname=ipek01\0" \ 134 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 135 "nfsroot=${serverip}:${rootpath}\0" \ 136 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 137 "addip=setenv bootargs ${bootargs} " \ 138 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 139 ":${hostname}:${netdev}:off panic=1\0" \ 140 "addtty=setenv bootargs ${bootargs} " \ 141 "console=${consoledev},${baudrate}\0" \ 142 "flash_nfs=run nfsargs addip addtty;" \ 143 "bootm ${kernel_addr} - ${fdtaddr}\0" \ 144 "flash_self=run ramargs addip addtty;" \ 145 "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \ 146 "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \ 147 "run nfsargs addip addtty;" \ 148 "bootm ${loadaddr} - ${fdtaddr}\0" \ 149 "rootpath=/opt/eldk/ppc_6xx\0" \ 150 "bootfile=ipek01/uImage\0" \ 151 "load=tftp 100000 ipek01/u-boot.bin\0" \ 152 "update=protect off FC000000 +60000; era FC000000 +60000; " \ 153 "cp.b 100000 FC000000 ${filesize}\0" \ 154 "upd=run load;run update\0" \ 155 "fdtaddr=800000\0" \ 156 "loadaddr=400000\0" \ 157 "fdtfile=ipek01/ipek01.dtb\0" \ 158 "" 159 160 #define CONFIG_BOOTCOMMAND "run flash_self" 161 162 /* 163 * IPB Bus clocking configuration. 164 */ 165 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */ 166 /* PCI clock must be 33, because board will not boot */ 167 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */ 168 169 /* 170 * Open firmware flat tree support 171 */ 172 #define CONFIG_OF_LIBFDT 1 173 #define CONFIG_OF_BOARD_SETUP 1 174 175 #define OF_CPU "PowerPC,5200@0" 176 #define OF_SOC "soc5200@f0000000" 177 #define OF_TBCLK (bd->bi_busfreq / 4) 178 179 /* 180 * I2C configuration 181 */ 182 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 183 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ 184 185 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 186 #define CONFIG_SYS_I2C_SLAVE 0x7F 187 188 /* 189 * EEPROM configuration 190 */ 191 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 192 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 193 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 194 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 195 196 /* 197 * RTC configuration 198 */ 199 #define CONFIG_RTC_PCF8563 200 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 201 202 #define CONFIG_SYS_FLASH_BASE 0xFC000000 203 #define CONFIG_SYS_FLASH_SIZE 0x01000000 204 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 205 CONFIG_SYS_MONITOR_LEN) 206 207 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 208 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ 209 #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 210 211 /* use CFI flash driver */ 212 #define CONFIG_FLASH_CFI_DRIVER 213 #define CONFIG_SYS_FLASH_CFI 214 #define CONFIG_SYS_FLASH_EMPTY_INFO 215 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 216 217 /* 218 * Environment settings 219 */ 220 #define CONFIG_ENV_IS_IN_FLASH 1 221 #define CONFIG_ENV_SIZE 0x10000 222 #define CONFIG_ENV_SECT_SIZE 0x20000 223 #define CONFIG_ENV_OVERWRITE 1 224 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 225 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 226 227 /* 228 * Memory map 229 */ 230 #define CONFIG_SYS_MBAR 0xf0000000 231 #define CONFIG_SYS_SDRAM_BASE 0x00000000 232 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 233 #define CONFIG_SYS_SRAM_BASE 0xF1000000 234 #define CONFIG_SYS_SRAM_SIZE 0x00200000 235 #define CONFIG_SYS_LIME_BASE 0xE4000000 236 #define CONFIG_SYS_LIME_SIZE 0x04000000 237 #define CONFIG_SYS_FPGA_BASE 0xC0000000 238 #define CONFIG_SYS_FPGA_SIZE 0x10000000 239 #define CONFIG_SYS_MPEG_BASE 0xe2000000 240 #define CONFIG_SYS_MPEG_SIZE 0x01000000 241 #define CONFIG_SYS_CF_BASE 0xe1000000 242 #define CONFIG_SYS_CF_SIZE 0x01000000 243 244 /* Use SRAM until RAM will be available */ 245 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 246 /* End of used area in DPRAM */ 247 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE 248 249 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 250 GENERATED_GBL_DATA_SIZE) 251 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 252 253 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 254 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 255 # define CONFIG_SYS_RAMBOOT 1 256 #endif 257 258 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ 259 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */ 260 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 261 262 /* 263 * Ethernet configuration 264 */ 265 #define CONFIG_MPC5xxx_FEC 1 266 #define CONFIG_MPC5xxx_FEC_MII100 267 #define CONFIG_PHY_ADDR 0x00 268 269 /* 270 * GPIO configuration 271 */ 272 #define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624 273 274 /* 275 * Miscellaneous configurable options 276 */ 277 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 278 #ifdef CONFIG_CMD_KGDB 279 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 280 #else 281 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 282 #endif 283 /* Print Buffer Size */ 284 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 285 sizeof(CONFIG_SYS_PROMPT) + 16) 286 /* max number of command args */ 287 #define CONFIG_SYS_MAXARGS 16 288 /* Boot Argument Buffer Size */ 289 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 290 291 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 292 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */ 293 294 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 295 296 #define CONFIG_LOOPW 297 298 /* 299 * Various low-level settings 300 */ 301 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 302 #define CONFIG_SYS_HID0_FINAL HID0_ICE 303 304 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 305 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 306 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 307 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 308 #define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE 309 #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE 310 #define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE 311 #define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE 312 #define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE 313 #define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE 314 #define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE 315 #define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE 316 #define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE 317 #define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE 318 319 #ifdef CONFIG_SYS_PCISPEED_66 320 #define CONFIG_SYS_BOOTCS_CFG 0x0006F900 321 #define CONFIG_SYS_CS1_CFG 0x0004FB00 322 #define CONFIG_SYS_CS2_CFG 0x0006F900 323 #else 324 #define CONFIG_SYS_BOOTCS_CFG 0x0002F900 325 #define CONFIG_SYS_CS1_CFG 0x0001FB00 326 #define CONFIG_SYS_CS2_CFG 0x0002F90C 327 #endif 328 329 /* 330 * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0 331 * waitstates, writeswap and readswap enabled 332 */ 333 #define CONFIG_SYS_CS3_CFG 0x00FFFB0C 334 #define CONFIG_SYS_CS6_CFG 0x00FFFB0C 335 #define CONFIG_SYS_CS7_CFG 0x4040751C 336 337 #define CONFIG_SYS_CS_BURST 0x00000000 338 #define CONFIG_SYS_CS_DEADCYCLE 0x33330000 339 340 #define CONFIG_SYS_RESET_ADDRESS 0xff000000 341 342 /*----------------------------------------------------------------------- 343 * USB stuff 344 *----------------------------------------------------------------------- 345 */ 346 #define CONFIG_USB_CLOCK 0x0001BBBB 347 #define CONFIG_USB_CONFIG 0x00005000 348 349 /*----------------------------------------------------------------------- 350 * IDE/ATA stuff Supports IDE harddisk 351 *----------------------------------------------------------------------- 352 */ 353 #define CONFIG_IDE_PREINIT 354 355 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 356 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ 357 358 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 359 360 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 361 362 /* Offset for data I/O */ 363 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 364 365 /* Offset for normal register accesses */ 366 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 367 368 /* Offset for alternate registers */ 369 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) 370 371 /* Interval between registers */ 372 #define CONFIG_SYS_ATA_STRIDE 4 373 374 #endif /* __CONFIG_H */ 375