1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2013 Keymile AG
4  * Valentin Longchamp <valentin.longchamp@keymile.com>
5  *
6  * Copyright 2009-2011 Freescale Semiconductor, Inc.
7  */
8 
9 #include <common.h>
10 #include <i2c.h>
11 #include <hwconfig.h>
12 #include <init.h>
13 #include <log.h>
14 #include <asm/global_data.h>
15 #include <asm/mmu.h>
16 #include <fsl_ddr_sdram.h>
17 #include <fsl_ddr_dimm_params.h>
18 
19 DECLARE_GLOBAL_DATA_PTR;
20 
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)21 void fsl_ddr_board_options(memctl_options_t *popts,
22 				dimm_params_t *pdimm,
23 				unsigned int ctrl_num)
24 {
25 	if (ctrl_num) {
26 		printf("Wrong parameter for controller number %d", ctrl_num);
27 		return;
28 	}
29 
30 	/* automatic calibration for nb of cycles between read and DQS pre */
31 	popts->cpo_override = 0xFF;
32 
33 	/* 1/2 clk delay between wr command and data strobe */
34 	popts->write_data_delay = 4;
35 	/* clk lauched 1/2 applied cylcle after address command */
36 	popts->clk_adjust = 4;
37 	/* 1T timing: command/address held for only 1 cycle */
38 	popts->twot_en = 0;
39 
40 	/* we have only one module, half str should be OK */
41 	popts->half_strength_driver_enable = 1;
42 
43 	/* wrlvl values overridden as recommended by ddr init func */
44 	popts->wrlvl_override = 1;
45 	popts->wrlvl_sample = 0xf;
46 	popts->wrlvl_start = 0x6;
47 
48 	/* Enable ZQ calibration */
49 	popts->zq_en = 1;
50 
51 	/* DHC_EN =1, ODT = 75 Ohm */
52 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
53 }
54 
dram_init(void)55 int dram_init(void)
56 {
57 	phys_size_t dram_size = 0;
58 
59 	puts("Initializing with SPD\n");
60 
61 	dram_size = fsl_ddr_sdram();
62 
63 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
64 	dram_size *= 0x100000;
65 
66 	debug("    DDR: ");
67 	gd->ram_size = dram_size;
68 
69 	return 0;
70 }
71