1 /** @file 2 * 3 * Copyright (c) 2012-2014, ARM Limited. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-2-Clause-Patent 6 * 7 **/ 8 9 #ifndef __LAN9118_DXE_HW_H__ 10 #define __LAN9118_DXE_HW_H__ 11 12 /*------------------------------------------------------------------------------ 13 LAN9118 SMCS Registers 14 ------------------------------------------------------------------------------*/ 15 16 // Base address as on the VE board 17 #define LAN9118_BA ((UINT32) PcdGet32(PcdLan9118DxeBaseAddress)) 18 19 /* ------------- Tx and Rx Data and Status Memory Locations ------------------*/ 20 #define LAN9118_RX_DATA (0x00000000 + LAN9118_BA) 21 #define LAN9118_RX_STATUS (0x00000040 + LAN9118_BA) 22 #define LAN9118_RX_STATUS_PEEK (0x00000044 + LAN9118_BA) 23 #define LAN9118_TX_DATA (0x00000020 + LAN9118_BA) 24 #define LAN9118_TX_STATUS (0x00000048 + LAN9118_BA) 25 #define LAN9118_TX_STATUS_PEEK (0x0000004C + LAN9118_BA) 26 27 /* ------------- System Control and Status Registers -------------------------*/ 28 #define LAN9118_ID_REV (0x00000050 + LAN9118_BA) // Chip ID and Revision 29 #define LAN9118_IRQ_CFG (0x00000054 + LAN9118_BA) // Interrupt Configuration 30 #define LAN9118_INT_STS (0x00000058 + LAN9118_BA) // Interrupt Status 31 #define LAN9118_INT_EN (0x0000005C + LAN9118_BA) // Interrupt Enable 32 //#define LAN9118_RESERVED (0x00000060) 33 #define LAN9118_BYTE_TEST (0x00000064 + LAN9118_BA) // Byte Order Test 34 #define LAN9118_FIFO_INT (0x00000068 + LAN9118_BA) // FIFO Level Interrupts 35 #define LAN9118_RX_CFG (0x0000006C + LAN9118_BA) // Receive Configuration 36 #define LAN9118_TX_CFG (0x00000070 + LAN9118_BA) // Transmit Configuration 37 #define LAN9118_HW_CFG (0x00000074 + LAN9118_BA) // Hardware Configuration 38 #define LAN9118_RX_DP_CTL (0x00000078 + LAN9118_BA) // Receive Data-Path Configuration 39 #define LAN9118_RX_FIFO_INF (0x0000007C + LAN9118_BA) // Receive FIFO Information 40 #define LAN9118_TX_FIFO_INF (0x00000080 + LAN9118_BA) // Transmit FIFO Information 41 #define LAN9118_PMT_CTRL (0x00000084 + LAN9118_BA) // Power Management Control 42 #define LAN9118_GPIO_CFG (0x00000088 + LAN9118_BA) // General Purpose IO Configuration 43 #define LAN9118_GPT_CFG (0x0000008C + LAN9118_BA) // General Purpose Timer Configuration 44 #define LAN9118_GPT_CNT (0x00000090 + LAN9118_BA) // General Purpose Timer Current Count 45 #define LAN9118_WORD_SWAP (0x00000098 + LAN9118_BA) // Word Swap Control 46 #define LAN9118_FREE_RUN (0x0000009C + LAN9118_BA) // Free-Run 25MHz Counter 47 #define LAN9118_RX_DROP (0x000000A0 + LAN9118_BA) // Receiver Dropped Frames Counter 48 #define LAN9118_MAC_CSR_CMD (0x000000A4 + LAN9118_BA) // MAC CSR Synchronizer Command 49 #define LAN9118_MAC_CSR_DATA (0x000000A8 + LAN9118_BA) // MAC CSR Synchronizer Data 50 #define LAN9118_AFC_CFG (0x000000AC + LAN9118_BA) // Automatic Flow Control Configuration 51 #define LAN9118_E2P_CMD (0x000000B0 + LAN9118_BA) // EEPROM Command 52 #define LAN9118_E2P_DATA (0x000000B4 + LAN9118_BA) // EEPROM Data 53 54 /* 55 * Required delays following write cycles (number of BYTE_TEST reads) 56 * Taken from Table 6.1 in Revision 1.5 (07-11-08) of the LAN9118 datasheet. 57 * Where no delay listed, 0 has been assumed. 58 */ 59 #define LAN9118_RX_DATA_WR_DELAY 0 60 #define LAN9118_RX_STATUS_WR_DELAY 0 61 #define LAN9118_RX_STATUS_PEEK_WR_DELAY 0 62 #define LAN9118_TX_DATA_WR_DELAY 0 63 #define LAN9118_TX_STATUS_WR_DELAY 0 64 #define LAN9118_TX_STATUS_PEEK_WR_DELAY 0 65 #define LAN9118_ID_REV_WR_DELAY 0 66 #define LAN9118_IRQ_CFG_WR_DELAY 3 67 #define LAN9118_INT_STS_WR_DELAY 2 68 #define LAN9118_INT_EN_WR_DELAY 1 69 #define LAN9118_BYTE_TEST_WR_DELAY 0 70 #define LAN9118_FIFO_INT_WR_DELAY 1 71 #define LAN9118_RX_CFG_WR_DELAY 1 72 #define LAN9118_TX_CFG_WR_DELAY 1 73 #define LAN9118_HW_CFG_WR_DELAY 1 74 #define LAN9118_RX_DP_CTL_WR_DELAY 1 75 #define LAN9118_RX_FIFO_INF_WR_DELAY 0 76 #define LAN9118_TX_FIFO_INF_WR_DELAY 3 77 #define LAN9118_PMT_CTRL_WR_DELAY 7 78 #define LAN9118_GPIO_CFG_WR_DELAY 1 79 #define LAN9118_GPT_CFG_WR_DELAY 1 80 #define LAN9118_GPT_CNT_WR_DELAY 3 81 #define LAN9118_WORD_SWAP_WR_DELAY 1 82 #define LAN9118_FREE_RUN_WR_DELAY 4 83 #define LAN9118_RX_DROP_WR_DELAY 0 84 #define LAN9118_MAC_CSR_CMD_WR_DELAY 1 85 #define LAN9118_MAC_CSR_DATA_WR_DELAY 1 86 #define LAN9118_AFC_CFG_WR_DELAY 1 87 #define LAN9118_E2P_CMD_WR_DELAY 1 88 #define LAN9118_E2P_DATA_WR_DELAY 1 89 90 /* 91 * Required delays following read cycles (number of BYTE_TEST reads) 92 * Taken from Table 6.2 in Revision 1.5 (07-11-08) of the LAN9118 datasheet. 93 * Where no delay listed, 0 has been assumed. 94 */ 95 #define LAN9118_RX_DATA_RD_DELAY 3 96 #define LAN9118_RX_STATUS_RD_DELAY 3 97 #define LAN9118_RX_STATUS_PEEK_RD_DELAY 0 98 #define LAN9118_TX_DATA_RD_DELAY 0 99 #define LAN9118_TX_STATUS_RD_DELAY 3 100 #define LAN9118_TX_STATUS_PEEK_RD_DELAY 0 101 #define LAN9118_ID_REV_RD_DELAY 0 102 #define LAN9118_IRQ_CFG_RD_DELAY 0 103 #define LAN9118_INT_STS_RD_DELAY 0 104 #define LAN9118_INT_EN_RD_DELAY 0 105 #define LAN9118_BYTE_TEST_RD_DELAY 0 106 #define LAN9118_FIFO_INT_RD_DELAY 0 107 #define LAN9118_RX_CFG_RD_DELAY 0 108 #define LAN9118_TX_CFG_RD_DELAY 0 109 #define LAN9118_HW_CFG_RD_DELAY 0 110 #define LAN9118_RX_DP_CTL_RD_DELAY 0 111 #define LAN9118_RX_FIFO_INF_RD_DELAY 0 112 #define LAN9118_TX_FIFO_INF_RD_DELAY 0 113 #define LAN9118_PMT_CTRL_RD_DELAY 0 114 #define LAN9118_GPIO_CFG_RD_DELAY 0 115 #define LAN9118_GPT_CFG_RD_DELAY 0 116 #define LAN9118_GPT_CNT_RD_DELAY 0 117 #define LAN9118_WORD_SWAP_RD_DELAY 0 118 #define LAN9118_FREE_RUN_RD_DELAY 0 119 #define LAN9118_RX_DROP_RD_DELAY 4 120 #define LAN9118_MAC_CSR_CMD_RD_DELAY 0 121 #define LAN9118_MAC_CSR_DATA_RD_DELAY 0 122 #define LAN9118_AFC_CFG_RD_DELAY 0 123 #define LAN9118_E2P_CMD_RD_DELAY 0 124 #define LAN9118_E2P_DATA_RD_DELAY 0 125 126 // Receiver Status bits 127 #define RXSTATUS_CRC_ERROR BIT1 // Cyclic Redundancy Check Error 128 #define RXSTATUS_DB BIT2 // Dribbling bit: Frame had non-integer multiple of 8bits 129 #define RXSTATUS_MII_ERROR BIT3 // Receive error during interception 130 #define RXSTATUS_RXW_TO BIT4 // Incoming frame larger than 2kb 131 #define RXSTATUS_FT BIT5 // 1: Ether type / 0: 802.3 type frame 132 #define RXSTATUS_LCOLL BIT6 // Late collision detected 133 #define RXSTATUS_FTL BIT7 // Frame longer than Ether type 134 #define RXSTATUS_MCF BIT10 // Frame has Multicast Address 135 #define RXSTATUS_RUNT BIT11 // Bad frame 136 #define RXSTATUS_LE BIT12 // Actual length of frame different than it claims 137 #define RXSTATUS_BCF BIT13 // Frame has Broadcast Address 138 #define RXSTATUS_ES BIT15 // Reports any error from bits 1,6,7 and 11 139 #define RXSTATUS_PL_MASK (0x3FFF0000) // Packet length bit mask 140 #define GET_RXSTATUS_PACKET_LENGTH(RxStatus) (((RxStatus) >> 16) & 0x3FFF) // Packet length bit mask 141 #define RXSTATUS_FILT_FAIL BIT30 // The frame failed filtering test 142 143 // Transmitter Status bits 144 #define TXSTATUS_DEF BIT0 // Packet tx was deferred 145 #define TXSTATUS_EDEF BIT2 // Tx ended because of excessive deferral (> 24288 bit times) 146 #define TXSTATUS_CC_MASK (0x00000078) // Collision Count (before Tx) bit mask 147 #define TXSTATUS_ECOLL BIT8 // Tx ended because of Excessive Collisions (makes CC_MASK invalid after 16 collisions) 148 #define TXSTATUS_LCOLL BIT9 // Packet Tx aborted after coll window of 64 bytes 149 #define TXSTATUS_NO_CA BIT10 // Carrier signal not present during Tx (bad?) 150 #define TXSTATUS_LOST_CA BIT11 // Lost carrier during Tx 151 #define TXSTATUS_ES BIT15 // Reports any errors from bits 1,2,8,9,10 and 11 152 #define TXSTATUS_PTAG_MASK (0xFFFF0000) // Mask for Unique ID of packets (So we know who the packets are for) 153 154 // ID_REV register bits 155 #define IDREV_ID ((Lan9118MmioRead32(LAN9118_ID_REV) & 0xFFFF0000) >> 16) 156 #define IDREV_REV (Lan9118MmioRead32(LAN9118_ID_REV) & 0x0000FFFF) 157 158 // Interrupt Config Register bits 159 #define IRQCFG_IRQ_TYPE BIT0 // IRQ Buffer type 160 #define IRQCFG_IRQ_POL BIT4 // IRQ Polarity 161 #define IRQCFG_IRQ_EN BIT8 // Enable external interrupt 162 #define IRQCFG_IRQ_INT BIT12 // State of internal interrupts line 163 #define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion interval 164 #define IRQCFG_INT_DEAS_CLR BIT14 // Clear the deassertion counter 165 #define IRQCFG_INT_DEAS_MASK (0xFF000000) // Interrupt deassertion interval value mask 166 167 // Interrupt Status Register bits 168 #define INSTS_GPIO_MASK (0x7) // GPIO interrupts mask 169 #define INSTS_RSFL (0x8) // Rx Status FIFO Level reached 170 #define INSTS_RSFF BIT4 // Rx Status FIFO full 171 #define INSTS_RXDF_INT BIT6 // Rx Frame dropped 172 #define INSTS_TSFL BIT7 // Tx Status FIFO Level reached 173 #define INSTS_TSFF BIT8 // Tx Status FIFO full 174 #define INSTS_TDFA BIT9 // Tx Data FIFO Level exceeded 175 #define INSTS_TDFO BIT10 // Tx Data FIFO full 176 #define INSTS_TXE BIT13 // Transmitter Error 177 #define INSTS_RXE BIT14 // Receiver Error 178 #define INSTS_RWT BIT15 // Packet > 2048 bytes received 179 #define INSTS_TXSO BIT16 // Tx Status FIFO Overflow 180 #define INSTS_PME_INT BIT17 // PME Signal detected 181 #define INSTS_PHY_INT BIT18 // Indicates PHY Interrupt 182 #define INSTS_GPT_INT BIT19 // GP Timer wrapped past 0xFFFF 183 #define INSTS_RXD_INT BIT20 // Indicates that amount of data written to RX_CFG was cleared 184 #define INSTS_TX_IOC BIT21 // Finished loading IOC flagged buffer to Tx FIFO 185 #define INSTS_RXDFH_INT BIT23 // Rx Dropped frames went past 0x7FFFFFFF 186 #define INSTS_RXSTOP_INT BIT24 // Rx was stopped 187 #define INSTS_TXSTOP_INT BIT25 // Tx was stopped 188 #define INSTS_SW_INT BIT31 // Software Interrupt occurred 189 190 // Interrupt Enable Register bits 191 192 193 // Hardware Config Register bits 194 #define HWCFG_SRST BIT0 // Software Reset bit (SC) 195 #define HWCFG_SRST_TO BIT1 // Software Reset Timeout bit (RO) 196 #define HWCFG_BMODE BIT2 // 32/16 bit Mode bit (RO) 197 #define HWCFG_TX_FIFO_SIZE_MASK (~ (UINT32)0xF0000) // Mask to Clear FIFO Size 198 #define HWCFG_MBO BIT20 // Must Be One bit 199 200 // Power Management Control Register 201 #define MPTCTRL_READY BIT0 // Device ready indicator 202 #define MPTCTRL_PME_EN BIT1 // Enable external PME signals 203 #define MPTCTRL_PME_POL BIT2 // Set polarity of PME signals 204 #define MPTCTRL_PME_IND BIT3 // Signal type of PME (refer to Spec) 205 #define MPTCTRL_WUPS_MASK (0x18) // Wake up status indicator mask 206 #define MPTCTRL_PME_TYPE BIT6 // PME Buffer type (Open Drain or Push-Pull) 207 #define MPTCTRL_ED_EN BIT8 // Energy-detect enable 208 #define MPTCTRL_WOL_EN BIT9 // Enable wake-on-lan 209 #define MPTCTRL_PHY_RST BIT10 // Reset the PHY 210 #define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode 211 212 // PHY control register bits 213 #define PHYCR_COLL_TEST BIT7 // Collision test enable 214 #define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode 215 #define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities 216 #define PHYCR_PD BIT11 // Power-Down switch 217 #define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable 218 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection 219 #define PHYCR_LOOPBK BIT14 // Set loopback mode 220 #define PHYCR_RESET BIT15 // Do a PHY reset 221 222 // PHY status register bits 223 #define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability 224 #define PHYSTS_JABBER BIT1 // Jabber condition detected 225 #define PHYSTS_LINK_STS BIT2 // Link Status 226 #define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability 227 #define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected 228 #define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed 229 #define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability 230 #define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability 231 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability 232 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability 233 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability 234 235 // PHY Auto-Negotiation advertisement 236 #define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector 237 #define PHYANA_10BASET BIT5 // Advertise 10BASET capability 238 #define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability 239 #define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability 240 #define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability 241 #define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability 242 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected 243 244 245 // PHY Auto-Negotiation Link Partner Ability 246 247 // PHY Auto-Negotiation Expansion 248 249 // PHY Mode control/status 250 251 // PHY Special Modes 252 253 // PHY Special control/status 254 255 // PHY Interrupt Source Flags 256 257 // PHY Interrupt Mask 258 259 // PHY Super Special control/status 260 #define PHYSSCS_HCDSPEED_MASK (7 << 2) // Speed indication 261 #define PHYSSCS_AUTODONE BIT12 // Auto-Negotiation Done 262 263 264 // MAC control register bits 265 #define MACCR_RX_EN BIT2 // Enable Receiver bit 266 #define MACCR_TX_EN BIT3 // Enable Transmitter bit 267 #define MACCR_DFCHK BIT5 // Deferral Check bit 268 #define MACCR_PADSTR BIT8 // Automatic Pad Stripping bit 269 #define MACCR_BOLMT_MASK (0xC0) // Back-Off limit mask 270 #define MACCR_DISRTY BIT10 // Disable Transmit Retry bit 271 #define MACCR_BCAST BIT11 // Disable Broadcast Frames bit 272 #define MACCR_LCOLL BIT12 // Late Collision Control bit 273 #define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode bit 274 #define MACCR_HO BIT15 // Hash Only Filtering Mode 275 #define MACCR_PASSBAD BIT16 // Receive all frames that passed filter bit 276 #define MACCR_INVFILT BIT17 // Enable Inverse Filtering bit 277 #define MACCR_PRMS BIT18 // Promiscuous Mode bit 278 #define MACCR_MCPAS BIT19 // Pass all Multicast packets bit 279 #define MACCR_FDPX BIT20 // Full Duplex Mode bit 280 #define MACCR_LOOPBK BIT21 // Loopback operation mode bit 281 #define MACCR_RCVOWN BIT23 // Disable Receive Own frames bit 282 #define MACCR_RX_ALL BIT31 // Receive all Packets and route to Filter 283 284 // Wake-Up Control and Status Register 285 #define WUCSR_MPEN BIT1 // Magic Packet enable (allow wake from Magic P) 286 #define WUCSR_WUEN BIT2 // Allow remote wake up using Wake-Up Frames 287 #define WUCSR_MPR_MASK (0x10) // Received Magic Packet 288 #define WUCSR_WUFR_MASK (0x20) // Received Wake-Up Frame 289 #define WUCSR_GUE BIT9 // Enable wake on global unicast frames 290 291 // RX Configuration Register bits 292 #define RXCFG_RXDOFF_MASK (0x1F00) // Rx Data Offset in Bytes 293 #define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs 294 #define RXCFG_RX_DMA_CNT_MASK (0x0FFF0000) // Amount of data to be read from Rx FIFO 295 #define RXCFG_RX_DMA_CNT(cnt) (((cnt) & 0xFFF) << 16) // Amount of data to be read from Rx FIFO 296 #define RXCFG_RX_END_ALIGN_MASK (0xC0000000) // Alignment to preserve 297 298 // TX Configuration Register bits 299 #define TXCFG_STOP_TX BIT0 // Stop the transmitter 300 #define TXCFG_TX_ON BIT1 // Start the transmitter 301 #define TXCFG_TXSAO BIT2 // Tx Status FIFO full 302 #define TXCFG_TXD_DUMP BIT14 // Clear Tx Data FIFO 303 #define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO 304 305 // Rx FIFO Information Register bits 306 #define RXFIFOINF_RXDUSED_MASK (0xFFFF) // Rx Data FIFO Used Space 307 #define RXFIFOINF_RXSUSED_MASK (0xFF0000) // Rx Status FIFO Used Space 308 309 // Tx FIFO Information Register bits 310 #define TXFIFOINF_TDFREE_MASK (0xFFFF) // Tx Data FIFO Free Space 311 #define TXFIFOINF_TXSUSED_MASK (0xFF0000) // Tx Status FIFO Used Space 312 313 // E2P Register 314 #define E2P_EPC_BUSY BIT31 315 #define E2P_EPC_CMD_READ (0) 316 #define E2P_EPC_TIMEOUT BIT9 317 #define E2P_EPC_MAC_ADDRESS_LOADED BIT8 318 #define E2P_EPC_ADDRESS(address) ((address) & 0xFFFF) 319 320 // GPIO Configuration register 321 #define GPIO_GPIO0_PUSH_PULL BIT16 322 #define GPIO_GPIO1_PUSH_PULL BIT17 323 #define GPIO_GPIO2_PUSH_PULL BIT18 324 #define GPIO_LED1_ENABLE BIT28 325 #define GPIO_LED2_ENABLE BIT29 326 #define GPIO_LED3_ENABLE BIT30 327 328 // MII_ACC bits 329 #define MII_ACC_MII_BUSY BIT0 330 #define MII_ACC_MII_WRITE BIT1 331 #define MII_ACC_MII_READ 0 332 333 #define MII_ACC_PHY_VALUE BIT11 334 #define MII_ACC_MII_REG_INDEX(index) (((index) & 0x1F) << 6) 335 336 // 337 // PHY Control Indexes 338 // 339 #define PHY_INDEX_BASIC_CTRL 0 340 #define PHY_INDEX_BASIC_STATUS 1 341 #define PHY_INDEX_ID1 2 342 #define PHY_INDEX_ID2 3 343 #define PHY_INDEX_AUTO_NEG_ADVERT 4 344 #define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5 345 #define PHY_INDEX_AUTO_NEG_EXP 6 346 #define PHY_INDEX_MODE 17 347 #define PHY_INDEX_SPECIAL_MODES 18 348 #define PHY_INDEX_SPECIAL_CTLR 27 349 #define PHY_INDEX_INT_SRC 29 350 #define PHY_INDEX_INT_MASK 30 351 #define PHY_INDEX_SPECIAL_PHY_CTLR 31 352 353 // Indirect MAC Indexes 354 #define INDIRECT_MAC_INDEX_CR 1 355 #define INDIRECT_MAC_INDEX_ADDRH 2 356 #define INDIRECT_MAC_INDEX_ADDRL 3 357 #define INDIRECT_MAC_INDEX_HASHH 4 358 #define INDIRECT_MAC_INDEX_HASHL 5 359 #define INDIRECT_MAC_INDEX_MII_ACC 6 360 #define INDIRECT_MAC_INDEX_MII_DATA 7 361 362 // 363 // MAC CSR Synchronizer Command register 364 // 365 #define MAC_CSR_BUSY BIT31 366 #define MAC_CSR_READ BIT30 367 #define MAC_CSR_WRITE 0 368 #define MAC_CSR_ADDR(Addr) ((Addr) & 0xFF) 369 370 // 371 // TX Packet Format 372 // 373 #define TX_CMD_A_COMPLETION_INT BIT31 374 #define TX_CMD_A_FIRST_SEGMENT BIT13 375 #define TX_CMD_A_LAST_SEGMENT BIT12 376 #define TX_CMD_A_BUFF_SIZE(size) ((size) & 0x000003FF) 377 #define TX_CMD_A_DATA_START_OFFSET(offset) (((offset) & 0x1F) << 16) 378 #define TX_CMD_B_PACKET_LENGTH(size) ((size) & 0x000003FF) 379 #define TX_CMD_B_PACKET_TAG(tag) (((tag) & 0x3FF) << 16) 380 381 // Hardware Configuration Register 382 #define HW_CFG_TX_FIFO_SIZE_MASK (0xF << 16) 383 #define HW_CFG_TX_FIFO_SIZE(size) (((size) & 0xF) << 16) 384 385 // EEPROM Definition 386 #define EEPROM_EXTERNAL_SERIAL_EEPROM 0xA5 387 388 // 389 // Conditional compilation flags 390 // 391 //#define EVAL_PERFORMANCE 392 393 394 #endif /* __LAN9118_DXE_HDR_H__ */ 395