1 /* 2 * Copyright 2013 The Native Client Authors. All rights reserved. 3 * Use of this source code is governed by a BSD-style license that can 4 * be found in the LICENSE file. 5 */ 6 7 // DO NOT EDIT: GENERATED CODE 8 9 #ifndef NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_BASELINES_1_H_ 10 #define NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_BASELINES_1_H_ 11 12 #include "native_client/src/trusted/validator_arm/arm_helpers.h" 13 #include "native_client/src/trusted/validator_arm/inst_classes.h" 14 15 namespace nacl_arm_dec { 16 17 // ADC_immediate_cccc0010101snnnnddddiiiiiiiiiiii_case_0: 18 // 19 // {NZCV: 16, 20 // None: 32, 21 // Rd: Rd(15:12), 22 // Rn: Rn(19:16), 23 // S: S(20), 24 // cond: cond(31:28), 25 // defs: {Rd, NZCV 26 // if setflags 27 // else None}, 28 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)], 29 // imm12: imm12(11:0), 30 // imm32: ARMExpandImm(imm12), 31 // pattern: cccc0010101snnnnddddiiiiiiiiiiii, 32 // rule: ADC_immediate, 33 // safety: [(Rd(15:12)=1111 && 34 // S(20)=1) => DECODER_ERROR, 35 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 36 // setflags: S(20)=1, 37 // uses: {Rn}} 38 class ADC_immediate_cccc0010101snnnnddddiiiiiiiiiiii_case_0 39 : public ClassDecoder { 40 public: ADC_immediate_cccc0010101snnnnddddiiiiiiiiiiii_case_0()41 ADC_immediate_cccc0010101snnnnddddiiiiiiiiiiii_case_0() 42 : ClassDecoder() {} 43 virtual RegisterList defs(Instruction inst) const; 44 virtual SafetyLevel safety(Instruction i) const; 45 virtual RegisterList uses(Instruction i) const; 46 private: 47 NACL_DISALLOW_COPY_AND_ASSIGN( 48 ADC_immediate_cccc0010101snnnnddddiiiiiiiiiiii_case_0); 49 }; 50 51 // ADC_register_cccc0000101snnnnddddiiiiitt0mmmm_case_0: 52 // 53 // {NZCV: 16, 54 // None: 32, 55 // Rd: Rd(15:12), 56 // Rm: Rm(3:0), 57 // Rn: Rn(19:16), 58 // S: S(20), 59 // cond: cond(31:28), 60 // defs: {Rd, NZCV 61 // if S 62 // else None}, 63 // fields: [cond(31:28), 64 // S(20), 65 // Rn(19:16), 66 // Rd(15:12), 67 // imm5(11:7), 68 // type(6:5), 69 // Rm(3:0)], 70 // imm5: imm5(11:7), 71 // pattern: cccc0000101snnnnddddiiiiitt0mmmm, 72 // rule: ADC_register, 73 // safety: [(Rd(15:12)=1111 && 74 // S(20)=1) => DECODER_ERROR, 75 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 76 // shift: DecodeImmShift(type, imm5), 77 // type: type(6:5), 78 // uses: {Rn, Rm}} 79 class ADC_register_cccc0000101snnnnddddiiiiitt0mmmm_case_0 80 : public ClassDecoder { 81 public: ADC_register_cccc0000101snnnnddddiiiiitt0mmmm_case_0()82 ADC_register_cccc0000101snnnnddddiiiiitt0mmmm_case_0() 83 : ClassDecoder() {} 84 virtual RegisterList defs(Instruction inst) const; 85 virtual SafetyLevel safety(Instruction i) const; 86 virtual RegisterList uses(Instruction i) const; 87 private: 88 NACL_DISALLOW_COPY_AND_ASSIGN( 89 ADC_register_cccc0000101snnnnddddiiiiitt0mmmm_case_0); 90 }; 91 92 // ADC_register_shifted_register_cccc0000101snnnnddddssss0tt1mmmm_case_0: 93 // 94 // {NZCV: 16, 95 // None: 32, 96 // Pc: 15, 97 // Rd: Rd(15:12), 98 // Rm: Rm(3:0), 99 // Rn: Rn(19:16), 100 // Rs: Rs(11:8), 101 // S: S(20), 102 // cond: cond(31:28), 103 // defs: {Rd, NZCV 104 // if setflags 105 // else None}, 106 // fields: [cond(31:28), 107 // S(20), 108 // Rn(19:16), 109 // Rd(15:12), 110 // Rs(11:8), 111 // type(6:5), 112 // Rm(3:0)], 113 // pattern: cccc0000101snnnnddddssss0tt1mmmm, 114 // rule: ADC_register_shifted_register, 115 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE], 116 // setflags: S(20)=1, 117 // shift_t: DecodeRegShift(type), 118 // type: type(6:5), 119 // uses: {Rn, Rm, Rs}} 120 class ADC_register_shifted_register_cccc0000101snnnnddddssss0tt1mmmm_case_0 121 : public ClassDecoder { 122 public: ADC_register_shifted_register_cccc0000101snnnnddddssss0tt1mmmm_case_0()123 ADC_register_shifted_register_cccc0000101snnnnddddssss0tt1mmmm_case_0() 124 : ClassDecoder() {} 125 virtual RegisterList defs(Instruction inst) const; 126 virtual SafetyLevel safety(Instruction i) const; 127 virtual RegisterList uses(Instruction i) const; 128 private: 129 NACL_DISALLOW_COPY_AND_ASSIGN( 130 ADC_register_shifted_register_cccc0000101snnnnddddssss0tt1mmmm_case_0); 131 }; 132 133 // ADD_immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_0: 134 // 135 // {NZCV: 16, 136 // None: 32, 137 // Rd: Rd(15:12), 138 // Rn: Rn(19:16), 139 // S: S(20), 140 // cond: cond(31:28), 141 // defs: {Rd, NZCV 142 // if setflags 143 // else None}, 144 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)], 145 // imm12: imm12(11:0), 146 // imm32: ARMExpandImm(imm12), 147 // pattern: cccc0010100snnnnddddiiiiiiiiiiii, 148 // rule: ADD_immediate, 149 // safety: [(Rd(15:12)=1111 && 150 // S(20)=1) => DECODER_ERROR, 151 // (Rn(19:16)=1111 && 152 // S(20)=0) => DECODER_ERROR, 153 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 154 // setflags: S(20)=1, 155 // uses: {Rn}} 156 class ADD_immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_0 157 : public ClassDecoder { 158 public: ADD_immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_0()159 ADD_immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_0() 160 : ClassDecoder() {} 161 virtual RegisterList defs(Instruction inst) const; 162 virtual SafetyLevel safety(Instruction i) const; 163 virtual RegisterList uses(Instruction i) const; 164 private: 165 NACL_DISALLOW_COPY_AND_ASSIGN( 166 ADD_immediate_cccc0010100snnnnddddiiiiiiiiiiii_case_0); 167 }; 168 169 // ADD_register_cccc0000100snnnnddddiiiiitt0mmmm_case_0: 170 // 171 // {NZCV: 16, 172 // None: 32, 173 // Rd: Rd(15:12), 174 // Rm: Rm(3:0), 175 // Rn: Rn(19:16), 176 // S: S(20), 177 // cond: cond(31:28), 178 // defs: {Rd, NZCV 179 // if S 180 // else None}, 181 // fields: [cond(31:28), 182 // S(20), 183 // Rn(19:16), 184 // Rd(15:12), 185 // imm5(11:7), 186 // type(6:5), 187 // Rm(3:0)], 188 // imm5: imm5(11:7), 189 // pattern: cccc0000100snnnnddddiiiiitt0mmmm, 190 // rule: ADD_register, 191 // safety: [(Rd(15:12)=1111 && 192 // S(20)=1) => DECODER_ERROR, 193 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 194 // shift: DecodeImmShift(type, imm5), 195 // type: type(6:5), 196 // uses: {Rn, Rm}} 197 class ADD_register_cccc0000100snnnnddddiiiiitt0mmmm_case_0 198 : public ClassDecoder { 199 public: ADD_register_cccc0000100snnnnddddiiiiitt0mmmm_case_0()200 ADD_register_cccc0000100snnnnddddiiiiitt0mmmm_case_0() 201 : ClassDecoder() {} 202 virtual RegisterList defs(Instruction inst) const; 203 virtual SafetyLevel safety(Instruction i) const; 204 virtual RegisterList uses(Instruction i) const; 205 private: 206 NACL_DISALLOW_COPY_AND_ASSIGN( 207 ADD_register_cccc0000100snnnnddddiiiiitt0mmmm_case_0); 208 }; 209 210 // ADD_register_shifted_register_cccc0000100snnnnddddssss0tt1mmmm_case_0: 211 // 212 // {NZCV: 16, 213 // None: 32, 214 // Pc: 15, 215 // Rd: Rd(15:12), 216 // Rm: Rm(3:0), 217 // Rn: Rn(19:16), 218 // Rs: Rs(11:8), 219 // S: S(20), 220 // cond: cond(31:28), 221 // defs: {Rd, NZCV 222 // if setflags 223 // else None}, 224 // fields: [cond(31:28), 225 // S(20), 226 // Rn(19:16), 227 // Rd(15:12), 228 // Rs(11:8), 229 // type(6:5), 230 // Rm(3:0)], 231 // pattern: cccc0000100snnnnddddssss0tt1mmmm, 232 // rule: ADD_register_shifted_register, 233 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE], 234 // setflags: S(20)=1, 235 // shift_t: DecodeRegShift(type), 236 // type: type(6:5), 237 // uses: {Rn, Rm, Rs}} 238 class ADD_register_shifted_register_cccc0000100snnnnddddssss0tt1mmmm_case_0 239 : public ClassDecoder { 240 public: ADD_register_shifted_register_cccc0000100snnnnddddssss0tt1mmmm_case_0()241 ADD_register_shifted_register_cccc0000100snnnnddddssss0tt1mmmm_case_0() 242 : ClassDecoder() {} 243 virtual RegisterList defs(Instruction inst) const; 244 virtual SafetyLevel safety(Instruction i) const; 245 virtual RegisterList uses(Instruction i) const; 246 private: 247 NACL_DISALLOW_COPY_AND_ASSIGN( 248 ADD_register_shifted_register_cccc0000100snnnnddddssss0tt1mmmm_case_0); 249 }; 250 251 // ADR_A1_cccc001010001111ddddiiiiiiiiiiii_case_0: 252 // 253 // {Pc: 15, 254 // Rd: Rd(15:12), 255 // cond: cond(31:28), 256 // defs: {Rd}, 257 // fields: [cond(31:28), Rd(15:12), imm12(11:0)], 258 // imm12: imm12(11:0), 259 // imm32: ARMExpandImm(imm12), 260 // pattern: cccc001010001111ddddiiiiiiiiiiii, 261 // rule: ADR_A1, 262 // safety: [Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 263 // uses: {Pc}} 264 class ADR_A1_cccc001010001111ddddiiiiiiiiiiii_case_0 265 : public ClassDecoder { 266 public: ADR_A1_cccc001010001111ddddiiiiiiiiiiii_case_0()267 ADR_A1_cccc001010001111ddddiiiiiiiiiiii_case_0() 268 : ClassDecoder() {} 269 virtual RegisterList defs(Instruction inst) const; 270 virtual SafetyLevel safety(Instruction i) const; 271 virtual RegisterList uses(Instruction i) const; 272 private: 273 NACL_DISALLOW_COPY_AND_ASSIGN( 274 ADR_A1_cccc001010001111ddddiiiiiiiiiiii_case_0); 275 }; 276 277 // ADR_A2_cccc001001001111ddddiiiiiiiiiiii_case_0: 278 // 279 // {Pc: 15, 280 // Rd: Rd(15:12), 281 // cond: cond(31:28), 282 // defs: {Rd}, 283 // fields: [cond(31:28), Rd(15:12), imm12(11:0)], 284 // imm12: imm12(11:0), 285 // imm32: ARMExpandImm(imm12), 286 // pattern: cccc001001001111ddddiiiiiiiiiiii, 287 // rule: ADR_A2, 288 // safety: [Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 289 // uses: {Pc}} 290 class ADR_A2_cccc001001001111ddddiiiiiiiiiiii_case_0 291 : public ClassDecoder { 292 public: ADR_A2_cccc001001001111ddddiiiiiiiiiiii_case_0()293 ADR_A2_cccc001001001111ddddiiiiiiiiiiii_case_0() 294 : ClassDecoder() {} 295 virtual RegisterList defs(Instruction inst) const; 296 virtual SafetyLevel safety(Instruction i) const; 297 virtual RegisterList uses(Instruction i) const; 298 private: 299 NACL_DISALLOW_COPY_AND_ASSIGN( 300 ADR_A2_cccc001001001111ddddiiiiiiiiiiii_case_0); 301 }; 302 303 // AND_immediate_cccc0010000snnnnddddiiiiiiiiiiii_case_0: 304 // 305 // {NZCV: 16, 306 // None: 32, 307 // Rd: Rd(15:12), 308 // Rn: Rn(19:16), 309 // S: S(20), 310 // cond: cond(31:28), 311 // defs: {Rd, NZCV 312 // if setflags 313 // else None}, 314 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)], 315 // imm12: imm12(11:0), 316 // imm32: ARMExpandImm(imm12), 317 // pattern: cccc0010000snnnnddddiiiiiiiiiiii, 318 // rule: AND_immediate, 319 // safety: [(Rd(15:12)=1111 && 320 // S(20)=1) => DECODER_ERROR, 321 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 322 // setflags: S(20)=1, 323 // uses: {Rn}} 324 class AND_immediate_cccc0010000snnnnddddiiiiiiiiiiii_case_0 325 : public ClassDecoder { 326 public: AND_immediate_cccc0010000snnnnddddiiiiiiiiiiii_case_0()327 AND_immediate_cccc0010000snnnnddddiiiiiiiiiiii_case_0() 328 : ClassDecoder() {} 329 virtual RegisterList defs(Instruction inst) const; 330 virtual SafetyLevel safety(Instruction i) const; 331 virtual RegisterList uses(Instruction i) const; 332 private: 333 NACL_DISALLOW_COPY_AND_ASSIGN( 334 AND_immediate_cccc0010000snnnnddddiiiiiiiiiiii_case_0); 335 }; 336 337 // AND_register_cccc0000000snnnnddddiiiiitt0mmmm_case_0: 338 // 339 // {NZCV: 16, 340 // None: 32, 341 // Rd: Rd(15:12), 342 // Rm: Rm(3:0), 343 // Rn: Rn(19:16), 344 // S: S(20), 345 // cond: cond(31:28), 346 // defs: {Rd, NZCV 347 // if S 348 // else None}, 349 // fields: [cond(31:28), 350 // S(20), 351 // Rn(19:16), 352 // Rd(15:12), 353 // imm5(11:7), 354 // type(6:5), 355 // Rm(3:0)], 356 // imm5: imm5(11:7), 357 // pattern: cccc0000000snnnnddddiiiiitt0mmmm, 358 // rule: AND_register, 359 // safety: [(Rd(15:12)=1111 && 360 // S(20)=1) => DECODER_ERROR, 361 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 362 // shift: DecodeImmShift(type, imm5), 363 // type: type(6:5), 364 // uses: {Rn, Rm}} 365 class AND_register_cccc0000000snnnnddddiiiiitt0mmmm_case_0 366 : public ClassDecoder { 367 public: AND_register_cccc0000000snnnnddddiiiiitt0mmmm_case_0()368 AND_register_cccc0000000snnnnddddiiiiitt0mmmm_case_0() 369 : ClassDecoder() {} 370 virtual RegisterList defs(Instruction inst) const; 371 virtual SafetyLevel safety(Instruction i) const; 372 virtual RegisterList uses(Instruction i) const; 373 private: 374 NACL_DISALLOW_COPY_AND_ASSIGN( 375 AND_register_cccc0000000snnnnddddiiiiitt0mmmm_case_0); 376 }; 377 378 // AND_register_shifted_register_cccc0000000snnnnddddssss0tt1mmmm_case_0: 379 // 380 // {NZCV: 16, 381 // None: 32, 382 // Pc: 15, 383 // Rd: Rd(15:12), 384 // Rm: Rm(3:0), 385 // Rn: Rn(19:16), 386 // Rs: Rs(11:8), 387 // S: S(20), 388 // cond: cond(31:28), 389 // defs: {Rd, NZCV 390 // if setflags 391 // else None}, 392 // fields: [cond(31:28), 393 // S(20), 394 // Rn(19:16), 395 // Rd(15:12), 396 // Rs(11:8), 397 // type(6:5), 398 // Rm(3:0)], 399 // pattern: cccc0000000snnnnddddssss0tt1mmmm, 400 // rule: AND_register_shifted_register, 401 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE], 402 // setflags: S(20)=1, 403 // shift_t: DecodeRegShift(type), 404 // type: type(6:5), 405 // uses: {Rn, Rm, Rs}} 406 class AND_register_shifted_register_cccc0000000snnnnddddssss0tt1mmmm_case_0 407 : public ClassDecoder { 408 public: AND_register_shifted_register_cccc0000000snnnnddddssss0tt1mmmm_case_0()409 AND_register_shifted_register_cccc0000000snnnnddddssss0tt1mmmm_case_0() 410 : ClassDecoder() {} 411 virtual RegisterList defs(Instruction inst) const; 412 virtual SafetyLevel safety(Instruction i) const; 413 virtual RegisterList uses(Instruction i) const; 414 private: 415 NACL_DISALLOW_COPY_AND_ASSIGN( 416 AND_register_shifted_register_cccc0000000snnnnddddssss0tt1mmmm_case_0); 417 }; 418 419 // ASR_immediate_cccc0001101s0000ddddiiiii100mmmm_case_0: 420 // 421 // {NZCV: 16, 422 // None: 32, 423 // Rd: Rd(15:12), 424 // Rm: Rm(3:0), 425 // S: S(20), 426 // cond: cond(31:28), 427 // defs: {Rd, NZCV 428 // if S 429 // else None}, 430 // fields: [cond(31:28), 431 // S(20), 432 // Rd(15:12), 433 // imm5(11:7), 434 // type(6:5), 435 // Rm(3:0)], 436 // imm5: imm5(11:7), 437 // pattern: cccc0001101s0000ddddiiiii100mmmm, 438 // rule: ASR_immediate, 439 // safety: [(Rd(15:12)=1111 && 440 // S(20)=1) => DECODER_ERROR, 441 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 442 // shift: DecodeImmShift(type, imm5), 443 // type: type(6:5), 444 // uses: {Rm}} 445 class ASR_immediate_cccc0001101s0000ddddiiiii100mmmm_case_0 446 : public ClassDecoder { 447 public: ASR_immediate_cccc0001101s0000ddddiiiii100mmmm_case_0()448 ASR_immediate_cccc0001101s0000ddddiiiii100mmmm_case_0() 449 : ClassDecoder() {} 450 virtual RegisterList defs(Instruction inst) const; 451 virtual SafetyLevel safety(Instruction i) const; 452 virtual RegisterList uses(Instruction i) const; 453 private: 454 NACL_DISALLOW_COPY_AND_ASSIGN( 455 ASR_immediate_cccc0001101s0000ddddiiiii100mmmm_case_0); 456 }; 457 458 // ASR_register_cccc0001101s0000ddddmmmm0101nnnn_case_0: 459 // 460 // {NZCV: 16, 461 // None: 32, 462 // Pc: 15, 463 // Rd: Rd(15:12), 464 // Rm: Rm(11:8), 465 // Rn: Rn(3:0), 466 // S: S(20), 467 // cond: cond(31:28), 468 // defs: {Rd, NZCV 469 // if setflags 470 // else None}, 471 // fields: [cond(31:28), S(20), Rd(15:12), Rm(11:8), Rn(3:0)], 472 // pattern: cccc0001101s0000ddddmmmm0101nnnn, 473 // rule: ASR_register, 474 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 475 // setflags: S(20)=1, 476 // uses: {Rn, Rm}} 477 class ASR_register_cccc0001101s0000ddddmmmm0101nnnn_case_0 478 : public ClassDecoder { 479 public: ASR_register_cccc0001101s0000ddddmmmm0101nnnn_case_0()480 ASR_register_cccc0001101s0000ddddmmmm0101nnnn_case_0() 481 : ClassDecoder() {} 482 virtual RegisterList defs(Instruction inst) const; 483 virtual SafetyLevel safety(Instruction i) const; 484 virtual RegisterList uses(Instruction i) const; 485 private: 486 NACL_DISALLOW_COPY_AND_ASSIGN( 487 ASR_register_cccc0001101s0000ddddmmmm0101nnnn_case_0); 488 }; 489 490 // BFC_cccc0111110mmmmmddddlllll0011111_case_0: 491 // 492 // {Pc: 15, 493 // Rd: Rd(15:12), 494 // arch: v6T2, 495 // cond: cond(31:28), 496 // defs: {Rd}, 497 // fields: [cond(31:28), msb(20:16), Rd(15:12), lsb(11:7)], 498 // lsb: lsb(11:7), 499 // msb: msb(20:16), 500 // pattern: cccc0111110mmmmmddddlllll0011111, 501 // rule: BFC, 502 // safety: [Rd == 503 // Pc => UNPREDICTABLE, 504 // msb < 505 // lsb => UNPREDICTABLE], 506 // uses: {Rd}} 507 class BFC_cccc0111110mmmmmddddlllll0011111_case_0 508 : public ClassDecoder { 509 public: BFC_cccc0111110mmmmmddddlllll0011111_case_0()510 BFC_cccc0111110mmmmmddddlllll0011111_case_0() 511 : ClassDecoder() {} 512 virtual RegisterList defs(Instruction inst) const; 513 virtual SafetyLevel safety(Instruction i) const; 514 virtual RegisterList uses(Instruction i) const; 515 private: 516 NACL_DISALLOW_COPY_AND_ASSIGN( 517 BFC_cccc0111110mmmmmddddlllll0011111_case_0); 518 }; 519 520 // BFI_cccc0111110mmmmmddddlllll001nnnn_case_0: 521 // 522 // {Pc: 15, 523 // Rd: Rd(15:12), 524 // Rn: Rn(3:0), 525 // arch: v6T2, 526 // cond: cond(31:28), 527 // defs: {Rd}, 528 // fields: [cond(31:28), msb(20:16), Rd(15:12), lsb(11:7), Rn(3:0)], 529 // lsb: lsb(11:7), 530 // msb: msb(20:16), 531 // pattern: cccc0111110mmmmmddddlllll001nnnn, 532 // rule: BFI, 533 // safety: [Rn == 534 // Pc => DECODER_ERROR, 535 // Rd == 536 // Pc => UNPREDICTABLE, 537 // msb < 538 // lsb => UNPREDICTABLE], 539 // uses: {Rn, Rd}} 540 class BFI_cccc0111110mmmmmddddlllll001nnnn_case_0 541 : public ClassDecoder { 542 public: BFI_cccc0111110mmmmmddddlllll001nnnn_case_0()543 BFI_cccc0111110mmmmmddddlllll001nnnn_case_0() 544 : ClassDecoder() {} 545 virtual RegisterList defs(Instruction inst) const; 546 virtual SafetyLevel safety(Instruction i) const; 547 virtual RegisterList uses(Instruction i) const; 548 private: 549 NACL_DISALLOW_COPY_AND_ASSIGN( 550 BFI_cccc0111110mmmmmddddlllll001nnnn_case_0); 551 }; 552 553 // BIC_immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_0: 554 // 555 // {NZCV: 16, 556 // None: 32, 557 // Rd: Rd(15:12), 558 // Rn: Rn(19:16), 559 // S: S(20), 560 // clears_bits: (imm32 && 561 // clears_mask()) == 562 // clears_mask(), 563 // cond: cond(31:28), 564 // defs: {Rd, NZCV 565 // if setflags 566 // else None}, 567 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)], 568 // imm12: imm12(11:0), 569 // imm32: ARMExpandImm(imm12), 570 // pattern: cccc0011110snnnnddddiiiiiiiiiiii, 571 // rule: BIC_immediate, 572 // safety: [(Rd(15:12)=1111 && 573 // S(20)=1) => DECODER_ERROR, 574 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 575 // setflags: S(20)=1, 576 // uses: {Rn}} 577 class BIC_immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_0 578 : public ClassDecoder { 579 public: BIC_immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_0()580 BIC_immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_0() 581 : ClassDecoder() {} 582 virtual bool clears_bits(Instruction i, uint32_t clears_mask) const; 583 virtual RegisterList defs(Instruction inst) const; 584 virtual SafetyLevel safety(Instruction i) const; 585 virtual RegisterList uses(Instruction i) const; 586 private: 587 NACL_DISALLOW_COPY_AND_ASSIGN( 588 BIC_immediate_cccc0011110snnnnddddiiiiiiiiiiii_case_0); 589 }; 590 591 // BIC_register_cccc0001110snnnnddddiiiiitt0mmmm_case_0: 592 // 593 // {NZCV: 16, 594 // None: 32, 595 // Rd: Rd(15:12), 596 // Rm: Rm(3:0), 597 // Rn: Rn(19:16), 598 // S: S(20), 599 // cond: cond(31:28), 600 // defs: {Rd, NZCV 601 // if S 602 // else None}, 603 // fields: [cond(31:28), 604 // S(20), 605 // Rn(19:16), 606 // Rd(15:12), 607 // imm5(11:7), 608 // type(6:5), 609 // Rm(3:0)], 610 // imm5: imm5(11:7), 611 // pattern: cccc0001110snnnnddddiiiiitt0mmmm, 612 // rule: BIC_register, 613 // safety: [(Rd(15:12)=1111 && 614 // S(20)=1) => DECODER_ERROR, 615 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 616 // shift: DecodeImmShift(type, imm5), 617 // type: type(6:5), 618 // uses: {Rn, Rm}} 619 class BIC_register_cccc0001110snnnnddddiiiiitt0mmmm_case_0 620 : public ClassDecoder { 621 public: BIC_register_cccc0001110snnnnddddiiiiitt0mmmm_case_0()622 BIC_register_cccc0001110snnnnddddiiiiitt0mmmm_case_0() 623 : ClassDecoder() {} 624 virtual RegisterList defs(Instruction inst) const; 625 virtual SafetyLevel safety(Instruction i) const; 626 virtual RegisterList uses(Instruction i) const; 627 private: 628 NACL_DISALLOW_COPY_AND_ASSIGN( 629 BIC_register_cccc0001110snnnnddddiiiiitt0mmmm_case_0); 630 }; 631 632 // BIC_register_shifted_register_cccc0001110snnnnddddssss0tt1mmmm_case_0: 633 // 634 // {NZCV: 16, 635 // None: 32, 636 // Pc: 15, 637 // Rd: Rd(15:12), 638 // Rm: Rm(3:0), 639 // Rn: Rn(19:16), 640 // Rs: Rs(11:8), 641 // S: S(20), 642 // cond: cond(31:28), 643 // defs: {Rd, NZCV 644 // if setflags 645 // else None}, 646 // fields: [cond(31:28), 647 // S(20), 648 // Rn(19:16), 649 // Rd(15:12), 650 // Rs(11:8), 651 // type(6:5), 652 // Rm(3:0)], 653 // pattern: cccc0001110snnnnddddssss0tt1mmmm, 654 // rule: BIC_register_shifted_register, 655 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE], 656 // setflags: S(20)=1, 657 // shift_t: DecodeRegShift(type), 658 // type: type(6:5), 659 // uses: {Rn, Rm, Rs}} 660 class BIC_register_shifted_register_cccc0001110snnnnddddssss0tt1mmmm_case_0 661 : public ClassDecoder { 662 public: BIC_register_shifted_register_cccc0001110snnnnddddssss0tt1mmmm_case_0()663 BIC_register_shifted_register_cccc0001110snnnnddddssss0tt1mmmm_case_0() 664 : ClassDecoder() {} 665 virtual RegisterList defs(Instruction inst) const; 666 virtual SafetyLevel safety(Instruction i) const; 667 virtual RegisterList uses(Instruction i) const; 668 private: 669 NACL_DISALLOW_COPY_AND_ASSIGN( 670 BIC_register_shifted_register_cccc0001110snnnnddddssss0tt1mmmm_case_0); 671 }; 672 673 // BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_0: 674 // 675 // {arch: v5T, 676 // cond: cond(31:28), 677 // defs: {}, 678 // fields: [cond(31:28), imm12(19:8), imm4(3:0)], 679 // imm12: imm12(19:8), 680 // imm32: ZeroExtend(imm12:imm4, 32), 681 // imm4: imm4(3:0), 682 // inst: inst, 683 // is_literal_pool_head: inst == 684 // LiteralPoolHeadConstant(), 685 // pattern: cccc00010010iiiiiiiiiiii0111iiii, 686 // rule: BKPT, 687 // safety: [cond(31:28)=~1110 => UNPREDICTABLE, 688 // not IsBreakPointAndConstantPoolHead(inst) => FORBIDDEN_OPERANDS], 689 // uses: {}, 690 // violations: [implied by 'is_literal_pool_head']} 691 class BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_0 692 : public ClassDecoder { 693 public: BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_0()694 BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_0() 695 : ClassDecoder() {} 696 virtual RegisterList defs(Instruction inst) const; 697 virtual bool is_literal_pool_head(Instruction i) const; 698 virtual SafetyLevel safety(Instruction i) const; 699 virtual RegisterList uses(Instruction i) const; 700 virtual ViolationSet get_violations( 701 const nacl_arm_val::DecodedInstruction& first, 702 const nacl_arm_val::DecodedInstruction& second, 703 const nacl_arm_val::SfiValidator& sfi, 704 nacl_arm_val::AddressSet* branches, 705 nacl_arm_val::AddressSet* critical, 706 uint32_t* next_inst_addr) const; 707 private: 708 NACL_DISALLOW_COPY_AND_ASSIGN( 709 BKPT_cccc00010010iiiiiiiiiiii0111iiii_case_0); 710 }; 711 712 // BLX_immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_0: 713 // 714 // {arch: v5, 715 // defs: {}, 716 // pattern: 1111101hiiiiiiiiiiiiiiiiiiiiiiii, 717 // rule: BLX_immediate, 718 // safety: [true => FORBIDDEN], 719 // true: true, 720 // uses: {}} 721 class BLX_immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_0 722 : public ClassDecoder { 723 public: BLX_immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_0()724 BLX_immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_0() 725 : ClassDecoder() {} 726 virtual RegisterList defs(Instruction inst) const; 727 virtual SafetyLevel safety(Instruction i) const; 728 virtual RegisterList uses(Instruction i) const; 729 private: 730 NACL_DISALLOW_COPY_AND_ASSIGN( 731 BLX_immediate_1111101hiiiiiiiiiiiiiiiiiiiiiiii_case_0); 732 }; 733 734 // BLX_register_cccc000100101111111111110011mmmm_case_0: 735 // 736 // {Lr: 14, 737 // Pc: 15, 738 // Rm: Rm(3:0), 739 // arch: v5T, 740 // cond: cond(31:28), 741 // defs: {Pc, Lr}, 742 // fields: [cond(31:28), Rm(3:0)], 743 // pattern: cccc000100101111111111110011mmmm, 744 // rule: BLX_register, 745 // safety: [Rm(3:0)=1111 => FORBIDDEN_OPERANDS], 746 // target: Rm, 747 // uses: {Rm}, 748 // violations: [implied by 'target']} 749 class BLX_register_cccc000100101111111111110011mmmm_case_0 750 : public ClassDecoder { 751 public: BLX_register_cccc000100101111111111110011mmmm_case_0()752 BLX_register_cccc000100101111111111110011mmmm_case_0() 753 : ClassDecoder() {} 754 virtual RegisterList defs(Instruction inst) const; 755 virtual SafetyLevel safety(Instruction i) const; 756 virtual Register branch_target_register(Instruction i) const; 757 virtual RegisterList uses(Instruction i) const; 758 virtual ViolationSet get_violations( 759 const nacl_arm_val::DecodedInstruction& first, 760 const nacl_arm_val::DecodedInstruction& second, 761 const nacl_arm_val::SfiValidator& sfi, 762 nacl_arm_val::AddressSet* branches, 763 nacl_arm_val::AddressSet* critical, 764 uint32_t* next_inst_addr) const; 765 private: 766 NACL_DISALLOW_COPY_AND_ASSIGN( 767 BLX_register_cccc000100101111111111110011mmmm_case_0); 768 }; 769 770 // BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0: 771 // 772 // {Cond: Cond(31:28), 773 // Lr: 14, 774 // Pc: 15, 775 // defs: {Pc, Lr}, 776 // fields: [Cond(31:28), imm24(23:0)], 777 // imm24: imm24(23:0), 778 // imm32: SignExtend(imm24:'00'(1:0), 32), 779 // pattern: cccc1011iiiiiiiiiiiiiiiiiiiiiiii, 780 // relative: true, 781 // relative_offset: imm32 + 8, 782 // rule: BL_BLX_immediate, 783 // safety: [true => MAY_BE_SAFE], 784 // true: true, 785 // uses: {Pc}, 786 // violations: [implied by 'relative']} 787 class BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0 788 : public ClassDecoder { 789 public: BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0()790 BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0() 791 : ClassDecoder() {} 792 virtual RegisterList defs(Instruction inst) const; 793 virtual bool is_relative_branch(Instruction i) const; 794 virtual int32_t branch_target_offset(Instruction i) const; 795 virtual SafetyLevel safety(Instruction i) const; 796 virtual RegisterList uses(Instruction i) const; 797 virtual ViolationSet get_violations( 798 const nacl_arm_val::DecodedInstruction& first, 799 const nacl_arm_val::DecodedInstruction& second, 800 const nacl_arm_val::SfiValidator& sfi, 801 nacl_arm_val::AddressSet* branches, 802 nacl_arm_val::AddressSet* critical, 803 uint32_t* next_inst_addr) const; 804 private: 805 NACL_DISALLOW_COPY_AND_ASSIGN( 806 BL_BLX_immediate_cccc1011iiiiiiiiiiiiiiiiiiiiiiii_case_0); 807 }; 808 809 // BXJ_cccc000100101111111111110010mmmm_case_0: 810 // 811 // {arch: v5TEJ, 812 // defs: {}, 813 // pattern: cccc000100101111111111110010mmmm, 814 // rule: BXJ, 815 // safety: [true => FORBIDDEN], 816 // true: true, 817 // uses: {}} 818 class BXJ_cccc000100101111111111110010mmmm_case_0 819 : public ClassDecoder { 820 public: BXJ_cccc000100101111111111110010mmmm_case_0()821 BXJ_cccc000100101111111111110010mmmm_case_0() 822 : ClassDecoder() {} 823 virtual RegisterList defs(Instruction inst) const; 824 virtual SafetyLevel safety(Instruction i) const; 825 virtual RegisterList uses(Instruction i) const; 826 private: 827 NACL_DISALLOW_COPY_AND_ASSIGN( 828 BXJ_cccc000100101111111111110010mmmm_case_0); 829 }; 830 831 // B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0: 832 // 833 // {Cond: Cond(31:28), 834 // Pc: 15, 835 // defs: {Pc}, 836 // fields: [Cond(31:28), imm24(23:0)], 837 // imm24: imm24(23:0), 838 // imm32: SignExtend(imm24:'00'(1:0), 32), 839 // pattern: cccc1010iiiiiiiiiiiiiiiiiiiiiiii, 840 // relative: true, 841 // relative_offset: imm32 + 8, 842 // rule: B, 843 // safety: [true => MAY_BE_SAFE], 844 // true: true, 845 // uses: {Pc}, 846 // violations: [implied by 'relative']} 847 class B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0 848 : public ClassDecoder { 849 public: B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0()850 B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0() 851 : ClassDecoder() {} 852 virtual RegisterList defs(Instruction inst) const; 853 virtual bool is_relative_branch(Instruction i) const; 854 virtual int32_t branch_target_offset(Instruction i) const; 855 virtual SafetyLevel safety(Instruction i) const; 856 virtual RegisterList uses(Instruction i) const; 857 virtual ViolationSet get_violations( 858 const nacl_arm_val::DecodedInstruction& first, 859 const nacl_arm_val::DecodedInstruction& second, 860 const nacl_arm_val::SfiValidator& sfi, 861 nacl_arm_val::AddressSet* branches, 862 nacl_arm_val::AddressSet* critical, 863 uint32_t* next_inst_addr) const; 864 private: 865 NACL_DISALLOW_COPY_AND_ASSIGN( 866 B_cccc1010iiiiiiiiiiiiiiiiiiiiiiii_case_0); 867 }; 868 869 // Bx_cccc000100101111111111110001mmmm_case_0: 870 // 871 // {Pc: 15, 872 // Rm: Rm(3:0), 873 // arch: v4T, 874 // cond: cond(31:28), 875 // defs: {Pc}, 876 // fields: [cond(31:28), Rm(3:0)], 877 // pattern: cccc000100101111111111110001mmmm, 878 // rule: Bx, 879 // safety: [Rm(3:0)=1111 => FORBIDDEN_OPERANDS], 880 // target: Rm, 881 // uses: {Rm}, 882 // violations: [implied by 'target']} 883 class Bx_cccc000100101111111111110001mmmm_case_0 884 : public ClassDecoder { 885 public: Bx_cccc000100101111111111110001mmmm_case_0()886 Bx_cccc000100101111111111110001mmmm_case_0() 887 : ClassDecoder() {} 888 virtual RegisterList defs(Instruction inst) const; 889 virtual SafetyLevel safety(Instruction i) const; 890 virtual Register branch_target_register(Instruction i) const; 891 virtual RegisterList uses(Instruction i) const; 892 virtual ViolationSet get_violations( 893 const nacl_arm_val::DecodedInstruction& first, 894 const nacl_arm_val::DecodedInstruction& second, 895 const nacl_arm_val::SfiValidator& sfi, 896 nacl_arm_val::AddressSet* branches, 897 nacl_arm_val::AddressSet* critical, 898 uint32_t* next_inst_addr) const; 899 private: 900 NACL_DISALLOW_COPY_AND_ASSIGN( 901 Bx_cccc000100101111111111110001mmmm_case_0); 902 }; 903 904 // CDP2_11111110iiiiiiiiiiiiiiiiiii0iiii_case_0: 905 // 906 // {arch: v5, 907 // defs: {}, 908 // pattern: 11111110iiiiiiiiiiiiiiiiiii0iiii, 909 // rule: CDP2, 910 // safety: [true => FORBIDDEN], 911 // true: true, 912 // uses: {}} 913 class CDP2_11111110iiiiiiiiiiiiiiiiiii0iiii_case_0 914 : public ClassDecoder { 915 public: CDP2_11111110iiiiiiiiiiiiiiiiiii0iiii_case_0()916 CDP2_11111110iiiiiiiiiiiiiiiiiii0iiii_case_0() 917 : ClassDecoder() {} 918 virtual RegisterList defs(Instruction inst) const; 919 virtual SafetyLevel safety(Instruction i) const; 920 virtual RegisterList uses(Instruction i) const; 921 private: 922 NACL_DISALLOW_COPY_AND_ASSIGN( 923 CDP2_11111110iiiiiiiiiiiiiiiiiii0iiii_case_0); 924 }; 925 926 // CDP_cccc1110oooonnnnddddccccooo0mmmm_case_0: 927 // 928 // {defs: {}, 929 // pattern: cccc1110oooonnnnddddccccooo0mmmm, 930 // rule: CDP, 931 // safety: [true => FORBIDDEN], 932 // true: true, 933 // uses: {}} 934 class CDP_cccc1110oooonnnnddddccccooo0mmmm_case_0 935 : public ClassDecoder { 936 public: CDP_cccc1110oooonnnnddddccccooo0mmmm_case_0()937 CDP_cccc1110oooonnnnddddccccooo0mmmm_case_0() 938 : ClassDecoder() {} 939 virtual RegisterList defs(Instruction inst) const; 940 virtual SafetyLevel safety(Instruction i) const; 941 virtual RegisterList uses(Instruction i) const; 942 private: 943 NACL_DISALLOW_COPY_AND_ASSIGN( 944 CDP_cccc1110oooonnnnddddccccooo0mmmm_case_0); 945 }; 946 947 // CLREX_11110101011111111111000000011111_case_0: 948 // 949 // {arch: V6K, 950 // defs: {}, 951 // pattern: 11110101011111111111000000011111, 952 // rule: CLREX, 953 // safety: [true => FORBIDDEN], 954 // true: true, 955 // uses: {}} 956 class CLREX_11110101011111111111000000011111_case_0 957 : public ClassDecoder { 958 public: CLREX_11110101011111111111000000011111_case_0()959 CLREX_11110101011111111111000000011111_case_0() 960 : ClassDecoder() {} 961 virtual RegisterList defs(Instruction inst) const; 962 virtual SafetyLevel safety(Instruction i) const; 963 virtual RegisterList uses(Instruction i) const; 964 private: 965 NACL_DISALLOW_COPY_AND_ASSIGN( 966 CLREX_11110101011111111111000000011111_case_0); 967 }; 968 969 // CLZ_cccc000101101111dddd11110001mmmm_case_0: 970 // 971 // {Pc: 15, 972 // Rd: Rd(15:12), 973 // Rm: Rm(3:0), 974 // arch: v5T, 975 // cond: cond(31:28), 976 // defs: {Rd}, 977 // fields: [cond(31:28), Rd(15:12), Rm(3:0)], 978 // pattern: cccc000101101111dddd11110001mmmm, 979 // rule: CLZ, 980 // safety: [Pc in {Rd, Rm} => UNPREDICTABLE], 981 // uses: {Rm}} 982 class CLZ_cccc000101101111dddd11110001mmmm_case_0 983 : public ClassDecoder { 984 public: CLZ_cccc000101101111dddd11110001mmmm_case_0()985 CLZ_cccc000101101111dddd11110001mmmm_case_0() 986 : ClassDecoder() {} 987 virtual RegisterList defs(Instruction inst) const; 988 virtual SafetyLevel safety(Instruction i) const; 989 virtual RegisterList uses(Instruction i) const; 990 private: 991 NACL_DISALLOW_COPY_AND_ASSIGN( 992 CLZ_cccc000101101111dddd11110001mmmm_case_0); 993 }; 994 995 // CMN_immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_0: 996 // 997 // {NZCV: 16, 998 // Rn: Rn(19:16), 999 // cond: cond(31:28), 1000 // defs: {NZCV}, 1001 // fields: [cond(31:28), Rn(19:16), imm12(11:0)], 1002 // imm12: imm12(11:0), 1003 // imm32: ARMExpandImm_C(imm12), 1004 // pattern: cccc00110111nnnn0000iiiiiiiiiiii, 1005 // rule: CMN_immediate, 1006 // uses: {Rn}} 1007 class CMN_immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_0 1008 : public ClassDecoder { 1009 public: CMN_immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_0()1010 CMN_immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_0() 1011 : ClassDecoder() {} 1012 virtual RegisterList defs(Instruction inst) const; 1013 virtual SafetyLevel safety(Instruction i) const; 1014 virtual RegisterList uses(Instruction i) const; 1015 private: 1016 NACL_DISALLOW_COPY_AND_ASSIGN( 1017 CMN_immediate_cccc00110111nnnn0000iiiiiiiiiiii_case_0); 1018 }; 1019 1020 // CMN_register_cccc00010111nnnn0000iiiiitt0mmmm_case_0: 1021 // 1022 // {NZCV: 16, 1023 // None: 32, 1024 // Rm: Rm(3:0), 1025 // Rn: Rn(19:16), 1026 // S: S(20), 1027 // cond: cond(31:28), 1028 // defs: {NZCV 1029 // if S 1030 // else None}, 1031 // fields: [cond(31:28), 1032 // S(20), 1033 // Rn(19:16), 1034 // imm5(11:7), 1035 // type(6:5), 1036 // Rm(3:0)], 1037 // imm5: imm5(11:7), 1038 // pattern: cccc00010111nnnn0000iiiiitt0mmmm, 1039 // rule: CMN_register, 1040 // shift: DecodeImmShift(type, imm5), 1041 // type: type(6:5), 1042 // uses: {Rn, Rm}} 1043 class CMN_register_cccc00010111nnnn0000iiiiitt0mmmm_case_0 1044 : public ClassDecoder { 1045 public: CMN_register_cccc00010111nnnn0000iiiiitt0mmmm_case_0()1046 CMN_register_cccc00010111nnnn0000iiiiitt0mmmm_case_0() 1047 : ClassDecoder() {} 1048 virtual RegisterList defs(Instruction inst) const; 1049 virtual SafetyLevel safety(Instruction i) const; 1050 virtual RegisterList uses(Instruction i) const; 1051 private: 1052 NACL_DISALLOW_COPY_AND_ASSIGN( 1053 CMN_register_cccc00010111nnnn0000iiiiitt0mmmm_case_0); 1054 }; 1055 1056 // CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_case_0: 1057 // 1058 // {NZCV: 16, 1059 // Pc: 15, 1060 // Rm: Rm(3:0), 1061 // Rn: Rn(19:16), 1062 // Rs: Rs(11:8), 1063 // cond: cond(31:28), 1064 // defs: {NZCV}, 1065 // fields: [cond(31:28), Rn(19:16), Rs(11:8), type(6:5), Rm(3:0)], 1066 // pattern: cccc00010111nnnn0000ssss0tt1mmmm, 1067 // rule: CMN_register_shifted_register, 1068 // safety: [Pc in {Rn, Rm, Rs} => UNPREDICTABLE], 1069 // shift_t: DecodeRegShift(type), 1070 // type: type(6:5), 1071 // uses: {Rn, Rm, Rs}} 1072 class CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_case_0 1073 : public ClassDecoder { 1074 public: CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_case_0()1075 CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_case_0() 1076 : ClassDecoder() {} 1077 virtual RegisterList defs(Instruction inst) const; 1078 virtual SafetyLevel safety(Instruction i) const; 1079 virtual RegisterList uses(Instruction i) const; 1080 private: 1081 NACL_DISALLOW_COPY_AND_ASSIGN( 1082 CMN_register_shifted_register_cccc00010111nnnn0000ssss0tt1mmmm_case_0); 1083 }; 1084 1085 // CMP_immediate_cccc00110101nnnn0000iiiiiiiiiiii_case_0: 1086 // 1087 // {NZCV: 16, 1088 // Rn: Rn(19:16), 1089 // cond: cond(31:28), 1090 // defs: {NZCV}, 1091 // fields: [cond(31:28), Rn(19:16), imm12(11:0)], 1092 // imm12: imm12(11:0), 1093 // imm32: ARMExpandImm_C(imm12), 1094 // pattern: cccc00110101nnnn0000iiiiiiiiiiii, 1095 // rule: CMP_immediate, 1096 // uses: {Rn}} 1097 class CMP_immediate_cccc00110101nnnn0000iiiiiiiiiiii_case_0 1098 : public ClassDecoder { 1099 public: CMP_immediate_cccc00110101nnnn0000iiiiiiiiiiii_case_0()1100 CMP_immediate_cccc00110101nnnn0000iiiiiiiiiiii_case_0() 1101 : ClassDecoder() {} 1102 virtual RegisterList defs(Instruction inst) const; 1103 virtual SafetyLevel safety(Instruction i) const; 1104 virtual RegisterList uses(Instruction i) const; 1105 private: 1106 NACL_DISALLOW_COPY_AND_ASSIGN( 1107 CMP_immediate_cccc00110101nnnn0000iiiiiiiiiiii_case_0); 1108 }; 1109 1110 // CMP_register_cccc00010101nnnn0000iiiiitt0mmmm_case_0: 1111 // 1112 // {NZCV: 16, 1113 // None: 32, 1114 // Rm: Rm(3:0), 1115 // Rn: Rn(19:16), 1116 // S: S(20), 1117 // cond: cond(31:28), 1118 // defs: {NZCV 1119 // if S 1120 // else None}, 1121 // fields: [cond(31:28), 1122 // S(20), 1123 // Rn(19:16), 1124 // imm5(11:7), 1125 // type(6:5), 1126 // Rm(3:0)], 1127 // imm5: imm5(11:7), 1128 // pattern: cccc00010101nnnn0000iiiiitt0mmmm, 1129 // rule: CMP_register, 1130 // shift: DecodeImmShift(type, imm5), 1131 // type: type(6:5), 1132 // uses: {Rn, Rm}} 1133 class CMP_register_cccc00010101nnnn0000iiiiitt0mmmm_case_0 1134 : public ClassDecoder { 1135 public: CMP_register_cccc00010101nnnn0000iiiiitt0mmmm_case_0()1136 CMP_register_cccc00010101nnnn0000iiiiitt0mmmm_case_0() 1137 : ClassDecoder() {} 1138 virtual RegisterList defs(Instruction inst) const; 1139 virtual SafetyLevel safety(Instruction i) const; 1140 virtual RegisterList uses(Instruction i) const; 1141 private: 1142 NACL_DISALLOW_COPY_AND_ASSIGN( 1143 CMP_register_cccc00010101nnnn0000iiiiitt0mmmm_case_0); 1144 }; 1145 1146 // CMP_register_shifted_register_cccc00010101nnnn0000ssss0tt1mmmm_case_0: 1147 // 1148 // {NZCV: 16, 1149 // Pc: 15, 1150 // Rm: Rm(3:0), 1151 // Rn: Rn(19:16), 1152 // Rs: Rs(11:8), 1153 // cond: cond(31:28), 1154 // defs: {NZCV}, 1155 // fields: [cond(31:28), Rn(19:16), Rs(11:8), type(6:5), Rm(3:0)], 1156 // pattern: cccc00010101nnnn0000ssss0tt1mmmm, 1157 // rule: CMP_register_shifted_register, 1158 // safety: [Pc in {Rn, Rm, Rs} => UNPREDICTABLE], 1159 // shift_t: DecodeRegShift(type), 1160 // type: type(6:5), 1161 // uses: {Rn, Rm, Rs}} 1162 class CMP_register_shifted_register_cccc00010101nnnn0000ssss0tt1mmmm_case_0 1163 : public ClassDecoder { 1164 public: CMP_register_shifted_register_cccc00010101nnnn0000ssss0tt1mmmm_case_0()1165 CMP_register_shifted_register_cccc00010101nnnn0000ssss0tt1mmmm_case_0() 1166 : ClassDecoder() {} 1167 virtual RegisterList defs(Instruction inst) const; 1168 virtual SafetyLevel safety(Instruction i) const; 1169 virtual RegisterList uses(Instruction i) const; 1170 private: 1171 NACL_DISALLOW_COPY_AND_ASSIGN( 1172 CMP_register_shifted_register_cccc00010101nnnn0000ssss0tt1mmmm_case_0); 1173 }; 1174 1175 // CPS_111100010000iii00000000iii0iiiii_case_0: 1176 // 1177 // {arch: v6, 1178 // defs: {}, 1179 // pattern: 111100010000iii00000000iii0iiiii, 1180 // rule: CPS, 1181 // safety: [true => FORBIDDEN], 1182 // true: true, 1183 // uses: {}} 1184 class CPS_111100010000iii00000000iii0iiiii_case_0 1185 : public ClassDecoder { 1186 public: CPS_111100010000iii00000000iii0iiiii_case_0()1187 CPS_111100010000iii00000000iii0iiiii_case_0() 1188 : ClassDecoder() {} 1189 virtual RegisterList defs(Instruction inst) const; 1190 virtual SafetyLevel safety(Instruction i) const; 1191 virtual RegisterList uses(Instruction i) const; 1192 private: 1193 NACL_DISALLOW_COPY_AND_ASSIGN( 1194 CPS_111100010000iii00000000iii0iiiii_case_0); 1195 }; 1196 1197 // CVT_between_half_precision_and_single_precision_111100111d11ss10dddd011p00m0mmmm_case_0: 1198 // 1199 // {D: D(22), 1200 // M: M(5), 1201 // Vd: Vd(15:12), 1202 // Vm: Vm(3:0), 1203 // arch: ASIMDhp, 1204 // d: D:Vd, 1205 // defs: {}, 1206 // elements: 4, 1207 // esize: 16, 1208 // fields: [D(22), size(19:18), Vd(15:12), op(8), M(5), Vm(3:0)], 1209 // half_to_single: op(8)=1, 1210 // m: M:Vm, 1211 // op: op(8), 1212 // pattern: 111100111d11ss10dddd011p00m0mmmm, 1213 // rule: CVT_between_half_precision_and_single_precision, 1214 // safety: [size(19:18)=~01 => UNDEFINED, 1215 // half_to_single && 1216 // Vd(0)=1 => UNDEFINED, 1217 // not half_to_single && 1218 // Vm(0)=1 => UNDEFINED], 1219 // size: size(19:18), 1220 // uses: {}} 1221 class CVT_between_half_precision_and_single_precision_111100111d11ss10dddd011p00m0mmmm_case_0 1222 : public ClassDecoder { 1223 public: CVT_between_half_precision_and_single_precision_111100111d11ss10dddd011p00m0mmmm_case_0()1224 CVT_between_half_precision_and_single_precision_111100111d11ss10dddd011p00m0mmmm_case_0() 1225 : ClassDecoder() {} 1226 virtual RegisterList defs(Instruction inst) const; 1227 virtual SafetyLevel safety(Instruction i) const; 1228 virtual RegisterList uses(Instruction i) const; 1229 private: 1230 NACL_DISALLOW_COPY_AND_ASSIGN( 1231 CVT_between_half_precision_and_single_precision_111100111d11ss10dddd011p00m0mmmm_case_0); 1232 }; 1233 1234 // DBG_cccc001100100000111100001111iiii_case_0: 1235 // 1236 // {arch: v7, 1237 // defs: {}, 1238 // pattern: cccc001100100000111100001111iiii, 1239 // rule: DBG, 1240 // safety: [true => FORBIDDEN], 1241 // true: true, 1242 // uses: {}} 1243 class DBG_cccc001100100000111100001111iiii_case_0 1244 : public ClassDecoder { 1245 public: DBG_cccc001100100000111100001111iiii_case_0()1246 DBG_cccc001100100000111100001111iiii_case_0() 1247 : ClassDecoder() {} 1248 virtual RegisterList defs(Instruction inst) const; 1249 virtual SafetyLevel safety(Instruction i) const; 1250 virtual RegisterList uses(Instruction i) const; 1251 private: 1252 NACL_DISALLOW_COPY_AND_ASSIGN( 1253 DBG_cccc001100100000111100001111iiii_case_0); 1254 }; 1255 1256 // DMB_1111010101111111111100000101xxxx_case_0: 1257 // 1258 // {arch: v7, 1259 // defs: {}, 1260 // fields: [option(3:0)], 1261 // option: option(3:0), 1262 // pattern: 1111010101111111111100000101xxxx, 1263 // rule: DMB, 1264 // safety: [not option in {'1111'(3:0), '1110'(3:0), '1011'(3:0), '1010'(3:0), '0111'(3:0), '0110'(3:0), '0011'(3:0), '0010'(3:0)} => FORBIDDEN_OPERANDS], 1265 // uses: {}} 1266 class DMB_1111010101111111111100000101xxxx_case_0 1267 : public ClassDecoder { 1268 public: DMB_1111010101111111111100000101xxxx_case_0()1269 DMB_1111010101111111111100000101xxxx_case_0() 1270 : ClassDecoder() {} 1271 virtual RegisterList defs(Instruction inst) const; 1272 virtual SafetyLevel safety(Instruction i) const; 1273 virtual RegisterList uses(Instruction i) const; 1274 private: 1275 NACL_DISALLOW_COPY_AND_ASSIGN( 1276 DMB_1111010101111111111100000101xxxx_case_0); 1277 }; 1278 1279 // DSB_1111010101111111111100000100xxxx_case_0: 1280 // 1281 // {arch: v6T2, 1282 // defs: {}, 1283 // fields: [option(3:0)], 1284 // option: option(3:0), 1285 // pattern: 1111010101111111111100000100xxxx, 1286 // rule: DSB, 1287 // safety: [not option in {'1111'(3:0), '1110'(3:0), '1011'(3:0), '1010'(3:0), '0111'(3:0), '0110'(3:0), '0011'(3:0), '0010'(3:0)} => FORBIDDEN_OPERANDS], 1288 // uses: {}} 1289 class DSB_1111010101111111111100000100xxxx_case_0 1290 : public ClassDecoder { 1291 public: DSB_1111010101111111111100000100xxxx_case_0()1292 DSB_1111010101111111111100000100xxxx_case_0() 1293 : ClassDecoder() {} 1294 virtual RegisterList defs(Instruction inst) const; 1295 virtual SafetyLevel safety(Instruction i) const; 1296 virtual RegisterList uses(Instruction i) const; 1297 private: 1298 NACL_DISALLOW_COPY_AND_ASSIGN( 1299 DSB_1111010101111111111100000100xxxx_case_0); 1300 }; 1301 1302 // EOR_immediate_cccc0010001snnnnddddiiiiiiiiiiii_case_0: 1303 // 1304 // {NZCV: 16, 1305 // None: 32, 1306 // Rd: Rd(15:12), 1307 // Rn: Rn(19:16), 1308 // S: S(20), 1309 // cond: cond(31:28), 1310 // defs: {Rd, NZCV 1311 // if setflags 1312 // else None}, 1313 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)], 1314 // imm12: imm12(11:0), 1315 // imm32: ARMExpandImm(imm12), 1316 // pattern: cccc0010001snnnnddddiiiiiiiiiiii, 1317 // rule: EOR_immediate, 1318 // safety: [(Rd(15:12)=1111 && 1319 // S(20)=1) => DECODER_ERROR, 1320 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 1321 // setflags: S(20)=1, 1322 // uses: {Rn}} 1323 class EOR_immediate_cccc0010001snnnnddddiiiiiiiiiiii_case_0 1324 : public ClassDecoder { 1325 public: EOR_immediate_cccc0010001snnnnddddiiiiiiiiiiii_case_0()1326 EOR_immediate_cccc0010001snnnnddddiiiiiiiiiiii_case_0() 1327 : ClassDecoder() {} 1328 virtual RegisterList defs(Instruction inst) const; 1329 virtual SafetyLevel safety(Instruction i) const; 1330 virtual RegisterList uses(Instruction i) const; 1331 private: 1332 NACL_DISALLOW_COPY_AND_ASSIGN( 1333 EOR_immediate_cccc0010001snnnnddddiiiiiiiiiiii_case_0); 1334 }; 1335 1336 // EOR_register_cccc0000001snnnnddddiiiiitt0mmmm_case_0: 1337 // 1338 // {NZCV: 16, 1339 // None: 32, 1340 // Rd: Rd(15:12), 1341 // Rm: Rm(3:0), 1342 // Rn: Rn(19:16), 1343 // S: S(20), 1344 // cond: cond(31:28), 1345 // defs: {Rd, NZCV 1346 // if S 1347 // else None}, 1348 // fields: [cond(31:28), 1349 // S(20), 1350 // Rn(19:16), 1351 // Rd(15:12), 1352 // imm5(11:7), 1353 // type(6:5), 1354 // Rm(3:0)], 1355 // imm5: imm5(11:7), 1356 // pattern: cccc0000001snnnnddddiiiiitt0mmmm, 1357 // rule: EOR_register, 1358 // safety: [(Rd(15:12)=1111 && 1359 // S(20)=1) => DECODER_ERROR, 1360 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 1361 // shift: DecodeImmShift(type, imm5), 1362 // type: type(6:5), 1363 // uses: {Rn, Rm}} 1364 class EOR_register_cccc0000001snnnnddddiiiiitt0mmmm_case_0 1365 : public ClassDecoder { 1366 public: EOR_register_cccc0000001snnnnddddiiiiitt0mmmm_case_0()1367 EOR_register_cccc0000001snnnnddddiiiiitt0mmmm_case_0() 1368 : ClassDecoder() {} 1369 virtual RegisterList defs(Instruction inst) const; 1370 virtual SafetyLevel safety(Instruction i) const; 1371 virtual RegisterList uses(Instruction i) const; 1372 private: 1373 NACL_DISALLOW_COPY_AND_ASSIGN( 1374 EOR_register_cccc0000001snnnnddddiiiiitt0mmmm_case_0); 1375 }; 1376 1377 // EOR_register_shifted_register_cccc0000001snnnnddddssss0tt1mmmm_case_0: 1378 // 1379 // {NZCV: 16, 1380 // None: 32, 1381 // Pc: 15, 1382 // Rd: Rd(15:12), 1383 // Rm: Rm(3:0), 1384 // Rn: Rn(19:16), 1385 // Rs: Rs(11:8), 1386 // S: S(20), 1387 // cond: cond(31:28), 1388 // defs: {Rd, NZCV 1389 // if setflags 1390 // else None}, 1391 // fields: [cond(31:28), 1392 // S(20), 1393 // Rn(19:16), 1394 // Rd(15:12), 1395 // Rs(11:8), 1396 // type(6:5), 1397 // Rm(3:0)], 1398 // pattern: cccc0000001snnnnddddssss0tt1mmmm, 1399 // rule: EOR_register_shifted_register, 1400 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE], 1401 // setflags: S(20)=1, 1402 // shift_t: DecodeRegShift(type), 1403 // type: type(6:5), 1404 // uses: {Rn, Rm, Rs}} 1405 class EOR_register_shifted_register_cccc0000001snnnnddddssss0tt1mmmm_case_0 1406 : public ClassDecoder { 1407 public: EOR_register_shifted_register_cccc0000001snnnnddddssss0tt1mmmm_case_0()1408 EOR_register_shifted_register_cccc0000001snnnnddddssss0tt1mmmm_case_0() 1409 : ClassDecoder() {} 1410 virtual RegisterList defs(Instruction inst) const; 1411 virtual SafetyLevel safety(Instruction i) const; 1412 virtual RegisterList uses(Instruction i) const; 1413 private: 1414 NACL_DISALLOW_COPY_AND_ASSIGN( 1415 EOR_register_shifted_register_cccc0000001snnnnddddssss0tt1mmmm_case_0); 1416 }; 1417 1418 // ERET_cccc0001011000000000000001101110_case_0: 1419 // 1420 // {arch: v7VE, 1421 // defs: {}, 1422 // pattern: cccc0001011000000000000001101110, 1423 // rule: ERET, 1424 // safety: [true => FORBIDDEN], 1425 // true: true, 1426 // uses: {}} 1427 class ERET_cccc0001011000000000000001101110_case_0 1428 : public ClassDecoder { 1429 public: ERET_cccc0001011000000000000001101110_case_0()1430 ERET_cccc0001011000000000000001101110_case_0() 1431 : ClassDecoder() {} 1432 virtual RegisterList defs(Instruction inst) const; 1433 virtual SafetyLevel safety(Instruction i) const; 1434 virtual RegisterList uses(Instruction i) const; 1435 private: 1436 NACL_DISALLOW_COPY_AND_ASSIGN( 1437 ERET_cccc0001011000000000000001101110_case_0); 1438 }; 1439 1440 // FICTITIOUS_FIRST_case_0: 1441 // 1442 // {defs: {}, 1443 // rule: FICTITIOUS_FIRST, 1444 // safety: [true => FORBIDDEN], 1445 // true: true, 1446 // uses: {}} 1447 class FICTITIOUS_FIRST_case_0 1448 : public ClassDecoder { 1449 public: FICTITIOUS_FIRST_case_0()1450 FICTITIOUS_FIRST_case_0() 1451 : ClassDecoder() {} 1452 virtual RegisterList defs(Instruction inst) const; 1453 virtual SafetyLevel safety(Instruction i) const; 1454 virtual RegisterList uses(Instruction i) const; 1455 private: 1456 NACL_DISALLOW_COPY_AND_ASSIGN( 1457 FICTITIOUS_FIRST_case_0); 1458 }; 1459 1460 // HVC_cccc00010100iiiiiiiiiiii0111iiii_case_0: 1461 // 1462 // {arch: v7VE, 1463 // defs: {}, 1464 // pattern: cccc00010100iiiiiiiiiiii0111iiii, 1465 // rule: HVC, 1466 // safety: [true => FORBIDDEN], 1467 // true: true, 1468 // uses: {}} 1469 class HVC_cccc00010100iiiiiiiiiiii0111iiii_case_0 1470 : public ClassDecoder { 1471 public: HVC_cccc00010100iiiiiiiiiiii0111iiii_case_0()1472 HVC_cccc00010100iiiiiiiiiiii0111iiii_case_0() 1473 : ClassDecoder() {} 1474 virtual RegisterList defs(Instruction inst) const; 1475 virtual SafetyLevel safety(Instruction i) const; 1476 virtual RegisterList uses(Instruction i) const; 1477 private: 1478 NACL_DISALLOW_COPY_AND_ASSIGN( 1479 HVC_cccc00010100iiiiiiiiiiii0111iiii_case_0); 1480 }; 1481 1482 // ISB_1111010101111111111100000110xxxx_case_0: 1483 // 1484 // {arch: v6T2, 1485 // defs: {}, 1486 // fields: [option(3:0)], 1487 // option: option(3:0), 1488 // pattern: 1111010101111111111100000110xxxx, 1489 // rule: ISB, 1490 // safety: [option(3:0)=~1111 => FORBIDDEN_OPERANDS], 1491 // uses: {}} 1492 class ISB_1111010101111111111100000110xxxx_case_0 1493 : public ClassDecoder { 1494 public: ISB_1111010101111111111100000110xxxx_case_0()1495 ISB_1111010101111111111100000110xxxx_case_0() 1496 : ClassDecoder() {} 1497 virtual RegisterList defs(Instruction inst) const; 1498 virtual SafetyLevel safety(Instruction i) const; 1499 virtual RegisterList uses(Instruction i) const; 1500 private: 1501 NACL_DISALLOW_COPY_AND_ASSIGN( 1502 ISB_1111010101111111111100000110xxxx_case_0); 1503 }; 1504 1505 // LDC2_immediate_1111110pudw1nnnniiiiiiiiiiiiiiii_case_0: 1506 // 1507 // {arch: v5, 1508 // defs: {}, 1509 // pattern: 1111110pudw1nnnniiiiiiiiiiiiiiii, 1510 // rule: LDC2_immediate, 1511 // safety: [true => FORBIDDEN], 1512 // true: true, 1513 // uses: {}} 1514 class LDC2_immediate_1111110pudw1nnnniiiiiiiiiiiiiiii_case_0 1515 : public ClassDecoder { 1516 public: LDC2_immediate_1111110pudw1nnnniiiiiiiiiiiiiiii_case_0()1517 LDC2_immediate_1111110pudw1nnnniiiiiiiiiiiiiiii_case_0() 1518 : ClassDecoder() {} 1519 virtual RegisterList defs(Instruction inst) const; 1520 virtual SafetyLevel safety(Instruction i) const; 1521 virtual RegisterList uses(Instruction i) const; 1522 private: 1523 NACL_DISALLOW_COPY_AND_ASSIGN( 1524 LDC2_immediate_1111110pudw1nnnniiiiiiiiiiiiiiii_case_0); 1525 }; 1526 1527 // LDC2_literal_1111110pudw11111iiiiiiiiiiiiiiii_case_0: 1528 // 1529 // {arch: v5, 1530 // defs: {}, 1531 // pattern: 1111110pudw11111iiiiiiiiiiiiiiii, 1532 // rule: LDC2_literal, 1533 // safety: [true => FORBIDDEN], 1534 // true: true, 1535 // uses: {}} 1536 class LDC2_literal_1111110pudw11111iiiiiiiiiiiiiiii_case_0 1537 : public ClassDecoder { 1538 public: LDC2_literal_1111110pudw11111iiiiiiiiiiiiiiii_case_0()1539 LDC2_literal_1111110pudw11111iiiiiiiiiiiiiiii_case_0() 1540 : ClassDecoder() {} 1541 virtual RegisterList defs(Instruction inst) const; 1542 virtual SafetyLevel safety(Instruction i) const; 1543 virtual RegisterList uses(Instruction i) const; 1544 private: 1545 NACL_DISALLOW_COPY_AND_ASSIGN( 1546 LDC2_literal_1111110pudw11111iiiiiiiiiiiiiiii_case_0); 1547 }; 1548 1549 // LDC_immediate_cccc110pudw1nnnnddddcccciiiiiiii_case_0: 1550 // 1551 // {defs: {}, 1552 // pattern: cccc110pudw1nnnnddddcccciiiiiiii, 1553 // rule: LDC_immediate, 1554 // safety: [true => FORBIDDEN], 1555 // true: true, 1556 // uses: {}} 1557 class LDC_immediate_cccc110pudw1nnnnddddcccciiiiiiii_case_0 1558 : public ClassDecoder { 1559 public: LDC_immediate_cccc110pudw1nnnnddddcccciiiiiiii_case_0()1560 LDC_immediate_cccc110pudw1nnnnddddcccciiiiiiii_case_0() 1561 : ClassDecoder() {} 1562 virtual RegisterList defs(Instruction inst) const; 1563 virtual SafetyLevel safety(Instruction i) const; 1564 virtual RegisterList uses(Instruction i) const; 1565 private: 1566 NACL_DISALLOW_COPY_AND_ASSIGN( 1567 LDC_immediate_cccc110pudw1nnnnddddcccciiiiiiii_case_0); 1568 }; 1569 1570 // LDC_literal_cccc110pudw11111ddddcccciiiiiiii_case_0: 1571 // 1572 // {defs: {}, 1573 // pattern: cccc110pudw11111ddddcccciiiiiiii, 1574 // rule: LDC_literal, 1575 // safety: [true => FORBIDDEN], 1576 // true: true, 1577 // uses: {}} 1578 class LDC_literal_cccc110pudw11111ddddcccciiiiiiii_case_0 1579 : public ClassDecoder { 1580 public: LDC_literal_cccc110pudw11111ddddcccciiiiiiii_case_0()1581 LDC_literal_cccc110pudw11111ddddcccciiiiiiii_case_0() 1582 : ClassDecoder() {} 1583 virtual RegisterList defs(Instruction inst) const; 1584 virtual SafetyLevel safety(Instruction i) const; 1585 virtual RegisterList uses(Instruction i) const; 1586 private: 1587 NACL_DISALLOW_COPY_AND_ASSIGN( 1588 LDC_literal_cccc110pudw11111ddddcccciiiiiiii_case_0); 1589 }; 1590 1591 // LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0: 1592 // 1593 // {None: 32, 1594 // Pc: 15, 1595 // Rn: Rn(19:16), 1596 // W: W(21), 1597 // base: Rn, 1598 // cond: cond(31:28), 1599 // defs: Union({Rn 1600 // if wback 1601 // else None}, registers), 1602 // fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)], 1603 // pattern: cccc100000w1nnnnrrrrrrrrrrrrrrrr, 1604 // register_list: register_list(15:0), 1605 // registers: RegisterList(register_list), 1606 // rule: LDMDA_LDMFA, 1607 // safety: [Rn == 1608 // Pc || 1609 // NumGPRs(registers) < 1610 // 1 => UNPREDICTABLE, 1611 // wback && 1612 // Contains(registers, Rn) => UNKNOWN, 1613 // Contains(registers, Pc) => FORBIDDEN_OPERANDS], 1614 // small_imm_base_wb: wback, 1615 // uses: {Rn}, 1616 // violations: [implied by 'base'], 1617 // wback: W(21)=1} 1618 class LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0 1619 : public ClassDecoder { 1620 public: LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0()1621 LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0() 1622 : ClassDecoder() {} 1623 virtual Register base_address_register(Instruction i) const; 1624 virtual RegisterList defs(Instruction inst) const; 1625 virtual SafetyLevel safety(Instruction i) const; 1626 virtual bool base_address_register_writeback_small_immediate( 1627 Instruction i) const; 1628 virtual RegisterList uses(Instruction i) const; 1629 virtual ViolationSet get_violations( 1630 const nacl_arm_val::DecodedInstruction& first, 1631 const nacl_arm_val::DecodedInstruction& second, 1632 const nacl_arm_val::SfiValidator& sfi, 1633 nacl_arm_val::AddressSet* branches, 1634 nacl_arm_val::AddressSet* critical, 1635 uint32_t* next_inst_addr) const; 1636 private: 1637 NACL_DISALLOW_COPY_AND_ASSIGN( 1638 LDMDA_LDMFA_cccc100000w1nnnnrrrrrrrrrrrrrrrr_case_0); 1639 }; 1640 1641 // LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0: 1642 // 1643 // {None: 32, 1644 // Pc: 15, 1645 // Rn: Rn(19:16), 1646 // W: W(21), 1647 // base: Rn, 1648 // cond: cond(31:28), 1649 // defs: Union({Rn 1650 // if wback 1651 // else None}, registers), 1652 // fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)], 1653 // pattern: cccc100100w1nnnnrrrrrrrrrrrrrrrr, 1654 // register_list: register_list(15:0), 1655 // registers: RegisterList(register_list), 1656 // rule: LDMDB_LDMEA, 1657 // safety: [Rn == 1658 // Pc || 1659 // NumGPRs(registers) < 1660 // 1 => UNPREDICTABLE, 1661 // wback && 1662 // Contains(registers, Rn) => UNKNOWN, 1663 // Contains(registers, Pc) => FORBIDDEN_OPERANDS], 1664 // small_imm_base_wb: wback, 1665 // uses: {Rn}, 1666 // violations: [implied by 'base'], 1667 // wback: W(21)=1} 1668 class LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0 1669 : public ClassDecoder { 1670 public: LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0()1671 LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0() 1672 : ClassDecoder() {} 1673 virtual Register base_address_register(Instruction i) const; 1674 virtual RegisterList defs(Instruction inst) const; 1675 virtual SafetyLevel safety(Instruction i) const; 1676 virtual bool base_address_register_writeback_small_immediate( 1677 Instruction i) const; 1678 virtual RegisterList uses(Instruction i) const; 1679 virtual ViolationSet get_violations( 1680 const nacl_arm_val::DecodedInstruction& first, 1681 const nacl_arm_val::DecodedInstruction& second, 1682 const nacl_arm_val::SfiValidator& sfi, 1683 nacl_arm_val::AddressSet* branches, 1684 nacl_arm_val::AddressSet* critical, 1685 uint32_t* next_inst_addr) const; 1686 private: 1687 NACL_DISALLOW_COPY_AND_ASSIGN( 1688 LDMDB_LDMEA_cccc100100w1nnnnrrrrrrrrrrrrrrrr_case_0); 1689 }; 1690 1691 // LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0: 1692 // 1693 // {None: 32, 1694 // Pc: 15, 1695 // Rn: Rn(19:16), 1696 // W: W(21), 1697 // base: Rn, 1698 // cond: cond(31:28), 1699 // defs: Union({Rn 1700 // if wback 1701 // else None}, registers), 1702 // fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)], 1703 // pattern: cccc100110w1nnnnrrrrrrrrrrrrrrrr, 1704 // register_list: register_list(15:0), 1705 // registers: RegisterList(register_list), 1706 // rule: LDMIB_LDMED, 1707 // safety: [Rn == 1708 // Pc || 1709 // NumGPRs(registers) < 1710 // 1 => UNPREDICTABLE, 1711 // wback && 1712 // Contains(registers, Rn) => UNKNOWN, 1713 // Contains(registers, Pc) => FORBIDDEN_OPERANDS], 1714 // small_imm_base_wb: wback, 1715 // uses: {Rn}, 1716 // violations: [implied by 'base'], 1717 // wback: W(21)=1} 1718 class LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0 1719 : public ClassDecoder { 1720 public: LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0()1721 LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0() 1722 : ClassDecoder() {} 1723 virtual Register base_address_register(Instruction i) const; 1724 virtual RegisterList defs(Instruction inst) const; 1725 virtual SafetyLevel safety(Instruction i) const; 1726 virtual bool base_address_register_writeback_small_immediate( 1727 Instruction i) const; 1728 virtual RegisterList uses(Instruction i) const; 1729 virtual ViolationSet get_violations( 1730 const nacl_arm_val::DecodedInstruction& first, 1731 const nacl_arm_val::DecodedInstruction& second, 1732 const nacl_arm_val::SfiValidator& sfi, 1733 nacl_arm_val::AddressSet* branches, 1734 nacl_arm_val::AddressSet* critical, 1735 uint32_t* next_inst_addr) const; 1736 private: 1737 NACL_DISALLOW_COPY_AND_ASSIGN( 1738 LDMIB_LDMED_cccc100110w1nnnnrrrrrrrrrrrrrrrr_case_0); 1739 }; 1740 1741 // LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0: 1742 // 1743 // {None: 32, 1744 // Pc: 15, 1745 // Rn: Rn(19:16), 1746 // W: W(21), 1747 // base: Rn, 1748 // cond: cond(31:28), 1749 // defs: Union({Rn 1750 // if wback 1751 // else None}, registers), 1752 // fields: [cond(31:28), W(21), Rn(19:16), register_list(15:0)], 1753 // pattern: cccc100010w1nnnnrrrrrrrrrrrrrrrr, 1754 // register_list: register_list(15:0), 1755 // registers: RegisterList(register_list), 1756 // rule: LDM_LDMIA_LDMFD, 1757 // safety: [Rn == 1758 // Pc || 1759 // NumGPRs(registers) < 1760 // 1 => UNPREDICTABLE, 1761 // wback && 1762 // Contains(registers, Rn) => UNKNOWN, 1763 // Contains(registers, Pc) => FORBIDDEN_OPERANDS], 1764 // small_imm_base_wb: wback, 1765 // uses: {Rn}, 1766 // violations: [implied by 'base'], 1767 // wback: W(21)=1} 1768 class LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0 1769 : public ClassDecoder { 1770 public: LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0()1771 LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0() 1772 : ClassDecoder() {} 1773 virtual Register base_address_register(Instruction i) const; 1774 virtual RegisterList defs(Instruction inst) const; 1775 virtual SafetyLevel safety(Instruction i) const; 1776 virtual bool base_address_register_writeback_small_immediate( 1777 Instruction i) const; 1778 virtual RegisterList uses(Instruction i) const; 1779 virtual ViolationSet get_violations( 1780 const nacl_arm_val::DecodedInstruction& first, 1781 const nacl_arm_val::DecodedInstruction& second, 1782 const nacl_arm_val::SfiValidator& sfi, 1783 nacl_arm_val::AddressSet* branches, 1784 nacl_arm_val::AddressSet* critical, 1785 uint32_t* next_inst_addr) const; 1786 private: 1787 NACL_DISALLOW_COPY_AND_ASSIGN( 1788 LDM_LDMIA_LDMFD_cccc100010w1nnnnrrrrrrrrrrrrrrrr_case_0); 1789 }; 1790 1791 // LDM_User_registers_cccc100pu101nnnn0rrrrrrrrrrrrrrr_case_0: 1792 // 1793 // {defs: {}, 1794 // pattern: cccc100pu101nnnn0rrrrrrrrrrrrrrr, 1795 // rule: LDM_User_registers, 1796 // safety: [true => FORBIDDEN], 1797 // true: true, 1798 // uses: {}} 1799 class LDM_User_registers_cccc100pu101nnnn0rrrrrrrrrrrrrrr_case_0 1800 : public ClassDecoder { 1801 public: LDM_User_registers_cccc100pu101nnnn0rrrrrrrrrrrrrrr_case_0()1802 LDM_User_registers_cccc100pu101nnnn0rrrrrrrrrrrrrrr_case_0() 1803 : ClassDecoder() {} 1804 virtual RegisterList defs(Instruction inst) const; 1805 virtual SafetyLevel safety(Instruction i) const; 1806 virtual RegisterList uses(Instruction i) const; 1807 private: 1808 NACL_DISALLOW_COPY_AND_ASSIGN( 1809 LDM_User_registers_cccc100pu101nnnn0rrrrrrrrrrrrrrr_case_0); 1810 }; 1811 1812 // LDM_exception_return_cccc100pu1w1nnnn1rrrrrrrrrrrrrrr_case_0: 1813 // 1814 // {defs: {}, 1815 // pattern: cccc100pu1w1nnnn1rrrrrrrrrrrrrrr, 1816 // rule: LDM_exception_return, 1817 // safety: [true => FORBIDDEN], 1818 // true: true, 1819 // uses: {}} 1820 class LDM_exception_return_cccc100pu1w1nnnn1rrrrrrrrrrrrrrr_case_0 1821 : public ClassDecoder { 1822 public: LDM_exception_return_cccc100pu1w1nnnn1rrrrrrrrrrrrrrr_case_0()1823 LDM_exception_return_cccc100pu1w1nnnn1rrrrrrrrrrrrrrr_case_0() 1824 : ClassDecoder() {} 1825 virtual RegisterList defs(Instruction inst) const; 1826 virtual SafetyLevel safety(Instruction i) const; 1827 virtual RegisterList uses(Instruction i) const; 1828 private: 1829 NACL_DISALLOW_COPY_AND_ASSIGN( 1830 LDM_exception_return_cccc100pu1w1nnnn1rrrrrrrrrrrrrrr_case_0); 1831 }; 1832 1833 // LDRBT_A1_cccc0100u111nnnnttttiiiiiiiiiiii_case_0: 1834 // 1835 // {defs: {}, 1836 // pattern: cccc0100u111nnnnttttiiiiiiiiiiii, 1837 // rule: LDRBT_A1, 1838 // safety: [true => FORBIDDEN], 1839 // true: true, 1840 // uses: {}} 1841 class LDRBT_A1_cccc0100u111nnnnttttiiiiiiiiiiii_case_0 1842 : public ClassDecoder { 1843 public: LDRBT_A1_cccc0100u111nnnnttttiiiiiiiiiiii_case_0()1844 LDRBT_A1_cccc0100u111nnnnttttiiiiiiiiiiii_case_0() 1845 : ClassDecoder() {} 1846 virtual RegisterList defs(Instruction inst) const; 1847 virtual SafetyLevel safety(Instruction i) const; 1848 virtual RegisterList uses(Instruction i) const; 1849 private: 1850 NACL_DISALLOW_COPY_AND_ASSIGN( 1851 LDRBT_A1_cccc0100u111nnnnttttiiiiiiiiiiii_case_0); 1852 }; 1853 1854 // LDRBT_A2_cccc0110u111nnnnttttiiiiitt0mmmm_case_0: 1855 // 1856 // {defs: {}, 1857 // pattern: cccc0110u111nnnnttttiiiiitt0mmmm, 1858 // rule: LDRBT_A2, 1859 // safety: [true => FORBIDDEN], 1860 // true: true, 1861 // uses: {}} 1862 class LDRBT_A2_cccc0110u111nnnnttttiiiiitt0mmmm_case_0 1863 : public ClassDecoder { 1864 public: LDRBT_A2_cccc0110u111nnnnttttiiiiitt0mmmm_case_0()1865 LDRBT_A2_cccc0110u111nnnnttttiiiiitt0mmmm_case_0() 1866 : ClassDecoder() {} 1867 virtual RegisterList defs(Instruction inst) const; 1868 virtual SafetyLevel safety(Instruction i) const; 1869 virtual RegisterList uses(Instruction i) const; 1870 private: 1871 NACL_DISALLOW_COPY_AND_ASSIGN( 1872 LDRBT_A2_cccc0110u111nnnnttttiiiiitt0mmmm_case_0); 1873 }; 1874 1875 // LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_0: 1876 // 1877 // {None: 32, 1878 // P: P(24), 1879 // Pc: 15, 1880 // Rn: Rn(19:16), 1881 // Rt: Rt(15:12), 1882 // U: U(23), 1883 // W: W(21), 1884 // add: U(23)=1, 1885 // base: Rn, 1886 // cond: cond(31:28), 1887 // defs: {Rt, base 1888 // if wback 1889 // else None}, 1890 // fields: [cond(31:28), 1891 // P(24), 1892 // U(23), 1893 // W(21), 1894 // Rn(19:16), 1895 // Rt(15:12), 1896 // imm12(11:0)], 1897 // imm12: imm12(11:0), 1898 // imm32: ZeroExtend(imm12, 32), 1899 // index: P(24)=1, 1900 // pattern: cccc010pu1w1nnnnttttiiiiiiiiiiii, 1901 // rule: LDRB_immediate, 1902 // safety: [Rn == 1903 // Pc => DECODER_ERROR, 1904 // P(24)=0 && 1905 // W(21)=1 => DECODER_ERROR, 1906 // Rt == 1907 // Pc => UNPREDICTABLE, 1908 // wback && 1909 // Rn == 1910 // Rt => UNPREDICTABLE], 1911 // small_imm_base_wb: wback, 1912 // uses: {Rn}, 1913 // violations: [implied by 'base'], 1914 // wback: P(24)=0 || 1915 // W(21)=1} 1916 class LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_0 1917 : public ClassDecoder { 1918 public: LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_0()1919 LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_0() 1920 : ClassDecoder() {} 1921 virtual Register base_address_register(Instruction i) const; 1922 virtual RegisterList defs(Instruction inst) const; 1923 virtual SafetyLevel safety(Instruction i) const; 1924 virtual bool base_address_register_writeback_small_immediate( 1925 Instruction i) const; 1926 virtual RegisterList uses(Instruction i) const; 1927 virtual ViolationSet get_violations( 1928 const nacl_arm_val::DecodedInstruction& first, 1929 const nacl_arm_val::DecodedInstruction& second, 1930 const nacl_arm_val::SfiValidator& sfi, 1931 nacl_arm_val::AddressSet* branches, 1932 nacl_arm_val::AddressSet* critical, 1933 uint32_t* next_inst_addr) const; 1934 private: 1935 NACL_DISALLOW_COPY_AND_ASSIGN( 1936 LDRB_immediate_cccc010pu1w1nnnnttttiiiiiiiiiiii_case_0); 1937 }; 1938 1939 // LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_0: 1940 // 1941 // {Pc: 15, 1942 // Rt: Rt(15:12), 1943 // U: U(23), 1944 // add: U(23)=1, 1945 // base: Pc, 1946 // cond: cond(31:28), 1947 // defs: {Rt}, 1948 // fields: [cond(31:28), U(23), Rt(15:12), imm12(11:0)], 1949 // imm12: imm12(11:0), 1950 // imm32: ZeroExtend(imm12, 32), 1951 // is_literal_load: true, 1952 // pattern: cccc0101u1011111ttttiiiiiiiiiiii, 1953 // rule: LDRB_literal, 1954 // safety: [Rt == 1955 // Pc => UNPREDICTABLE], 1956 // true: true, 1957 // uses: {Pc}, 1958 // violations: [implied by 'base']} 1959 class LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_0 1960 : public ClassDecoder { 1961 public: LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_0()1962 LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_0() 1963 : ClassDecoder() {} 1964 virtual Register base_address_register(Instruction i) const; 1965 virtual RegisterList defs(Instruction inst) const; 1966 virtual bool is_literal_load(Instruction i) const; 1967 virtual SafetyLevel safety(Instruction i) const; 1968 virtual RegisterList uses(Instruction i) const; 1969 virtual ViolationSet get_violations( 1970 const nacl_arm_val::DecodedInstruction& first, 1971 const nacl_arm_val::DecodedInstruction& second, 1972 const nacl_arm_val::SfiValidator& sfi, 1973 nacl_arm_val::AddressSet* branches, 1974 nacl_arm_val::AddressSet* critical, 1975 uint32_t* next_inst_addr) const; 1976 private: 1977 NACL_DISALLOW_COPY_AND_ASSIGN( 1978 LDRB_literal_cccc0101u1011111ttttiiiiiiiiiiii_case_0); 1979 }; 1980 1981 // LDRB_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_0: 1982 // 1983 // {None: 32, 1984 // P: P(24), 1985 // Pc: 15, 1986 // Rm: Rm(3:0), 1987 // Rn: Rn(19:16), 1988 // Rt: Rt(15:12), 1989 // U: U(23), 1990 // W: W(21), 1991 // add: U(23)=1, 1992 // base: Rn, 1993 // cond: cond(31:28), 1994 // defs: {Rt, base 1995 // if wback 1996 // else None}, 1997 // fields: [cond(31:28), 1998 // P(24), 1999 // U(23), 2000 // W(21), 2001 // Rn(19:16), 2002 // Rt(15:12), 2003 // imm5(11:7), 2004 // type(6:5), 2005 // Rm(3:0)], 2006 // imm5: imm5(11:7), 2007 // index: P(24)=1, 2008 // pattern: cccc011pu1w1nnnnttttiiiiitt0mmmm, 2009 // rule: LDRB_register, 2010 // safety: [P(24)=0 && 2011 // W(21)=1 => DECODER_ERROR, 2012 // Pc in {Rt, Rm} => UNPREDICTABLE, 2013 // wback && 2014 // (Rn == 2015 // Pc || 2016 // Rn == 2017 // Rt) => UNPREDICTABLE, 2018 // ArchVersion() < 2019 // 6 && 2020 // wback && 2021 // Rn == 2022 // Rm => UNPREDICTABLE, 2023 // index => FORBIDDEN], 2024 // shift: DecodeImmShift(type, imm5), 2025 // type: type(6:5), 2026 // uses: {Rm, Rn}, 2027 // violations: [implied by 'base'], 2028 // wback: P(24)=0 || 2029 // W(21)=1} 2030 class LDRB_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_0 2031 : public ClassDecoder { 2032 public: LDRB_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_0()2033 LDRB_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_0() 2034 : ClassDecoder() {} 2035 virtual Register base_address_register(Instruction i) const; 2036 virtual RegisterList defs(Instruction inst) const; 2037 virtual SafetyLevel safety(Instruction i) const; 2038 virtual RegisterList uses(Instruction i) const; 2039 virtual ViolationSet get_violations( 2040 const nacl_arm_val::DecodedInstruction& first, 2041 const nacl_arm_val::DecodedInstruction& second, 2042 const nacl_arm_val::SfiValidator& sfi, 2043 nacl_arm_val::AddressSet* branches, 2044 nacl_arm_val::AddressSet* critical, 2045 uint32_t* next_inst_addr) const; 2046 private: 2047 NACL_DISALLOW_COPY_AND_ASSIGN( 2048 LDRB_register_cccc011pu1w1nnnnttttiiiiitt0mmmm_case_0); 2049 }; 2050 2051 // LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_0: 2052 // 2053 // {None: 32, 2054 // P: P(24), 2055 // Pc: 15, 2056 // Rn: Rn(19:16), 2057 // Rt: Rt(15:12), 2058 // Rt2: Rt + 1, 2059 // U: U(23), 2060 // W: W(21), 2061 // add: U(23)=1, 2062 // address: offset_addr 2063 // if index 2064 // else Rn, 2065 // arch: v5TE, 2066 // base: Rn, 2067 // cond: cond(31:28), 2068 // defs: {Rt, Rt2, base 2069 // if wback 2070 // else None}, 2071 // fields: [cond(31:28), 2072 // P(24), 2073 // U(23), 2074 // W(21), 2075 // Rn(19:16), 2076 // Rt(15:12), 2077 // imm4H(11:8), 2078 // imm4L(3:0)], 2079 // imm32: ZeroExtend(imm4H:imm4L, 32), 2080 // imm4H: imm4H(11:8), 2081 // imm4L: imm4L(3:0), 2082 // index: P(24)=1, 2083 // offset_addr: Rn + imm32 2084 // if add 2085 // else Rn - imm32, 2086 // pattern: cccc000pu1w0nnnnttttiiii1101iiii, 2087 // rule: LDRD_immediate, 2088 // safety: [Rn(19:16)=1111 => DECODER_ERROR, 2089 // Rt(0)=1 => UNPREDICTABLE, 2090 // P(24)=0 && 2091 // W(21)=1 => UNPREDICTABLE, 2092 // wback && 2093 // (Rn == 2094 // Rt || 2095 // Rn == 2096 // Rt2) => UNPREDICTABLE, 2097 // Rt2 == 2098 // Pc => UNPREDICTABLE], 2099 // small_imm_base_wb: wback, 2100 // uses: {Rn}, 2101 // violations: [implied by 'base'], 2102 // wback: (P(24)=0) || 2103 // (W(21)=1)} 2104 class LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_0 2105 : public ClassDecoder { 2106 public: LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_0()2107 LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_0() 2108 : ClassDecoder() {} 2109 virtual Register base_address_register(Instruction i) const; 2110 virtual RegisterList defs(Instruction inst) const; 2111 virtual SafetyLevel safety(Instruction i) const; 2112 virtual bool base_address_register_writeback_small_immediate( 2113 Instruction i) const; 2114 virtual RegisterList uses(Instruction i) const; 2115 virtual ViolationSet get_violations( 2116 const nacl_arm_val::DecodedInstruction& first, 2117 const nacl_arm_val::DecodedInstruction& second, 2118 const nacl_arm_val::SfiValidator& sfi, 2119 nacl_arm_val::AddressSet* branches, 2120 nacl_arm_val::AddressSet* critical, 2121 uint32_t* next_inst_addr) const; 2122 private: 2123 NACL_DISALLOW_COPY_AND_ASSIGN( 2124 LDRD_immediate_cccc000pu1w0nnnnttttiiii1101iiii_case_0); 2125 }; 2126 2127 // LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_0: 2128 // 2129 // {P: P(24), 2130 // Pc: 15, 2131 // Rt: Rt(15:12), 2132 // Rt2: Rt + 1, 2133 // U: U(23), 2134 // W: W(21), 2135 // add: U(23)=1, 2136 // arch: v5TE, 2137 // base: Pc, 2138 // cond: cond(31:28), 2139 // defs: {Rt, Rt2}, 2140 // fields: [cond(31:28), 2141 // P(24), 2142 // U(23), 2143 // W(21), 2144 // Rt(15:12), 2145 // imm4H(11:8), 2146 // imm4L(3:0)], 2147 // imm32: ZeroExtend(imm4H:imm4L, 32), 2148 // imm4H: imm4H(11:8), 2149 // imm4L: imm4L(3:0), 2150 // is_literal_load: true, 2151 // pattern: cccc0001u1001111ttttiiii1101iiii, 2152 // rule: LDRD_literal, 2153 // safety: [Rt(0)=1 => UNPREDICTABLE, 2154 // Rt2 == 2155 // Pc => UNPREDICTABLE], 2156 // true: true, 2157 // uses: {Pc}, 2158 // violations: [implied by 'base']} 2159 class LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_0 2160 : public ClassDecoder { 2161 public: LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_0()2162 LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_0() 2163 : ClassDecoder() {} 2164 virtual Register base_address_register(Instruction i) const; 2165 virtual RegisterList defs(Instruction inst) const; 2166 virtual bool is_literal_load(Instruction i) const; 2167 virtual SafetyLevel safety(Instruction i) const; 2168 virtual RegisterList uses(Instruction i) const; 2169 virtual ViolationSet get_violations( 2170 const nacl_arm_val::DecodedInstruction& first, 2171 const nacl_arm_val::DecodedInstruction& second, 2172 const nacl_arm_val::SfiValidator& sfi, 2173 nacl_arm_val::AddressSet* branches, 2174 nacl_arm_val::AddressSet* critical, 2175 uint32_t* next_inst_addr) const; 2176 private: 2177 NACL_DISALLOW_COPY_AND_ASSIGN( 2178 LDRD_literal_cccc0001u1001111ttttiiii1101iiii_case_0); 2179 }; 2180 2181 // LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_0: 2182 // 2183 // {None: 32, 2184 // P: P(24), 2185 // Pc: 15, 2186 // Rm: Rm(3:0), 2187 // Rn: Rn(19:16), 2188 // Rt: Rt(15:12), 2189 // Rt2: Rt + 1, 2190 // U: U(23), 2191 // W: W(21), 2192 // add: U(23)=1, 2193 // arch: v5TE, 2194 // base: Rn, 2195 // cond: cond(31:28), 2196 // defs: {Rt, Rt2, base 2197 // if wback 2198 // else None}, 2199 // fields: [cond(31:28), 2200 // P(24), 2201 // U(23), 2202 // W(21), 2203 // Rn(19:16), 2204 // Rt(15:12), 2205 // Rm(3:0)], 2206 // index: P(24)=1, 2207 // pattern: cccc000pu0w0nnnntttt00001101mmmm, 2208 // rule: LDRD_register, 2209 // safety: [Rt(0)=1 => UNPREDICTABLE, 2210 // P(24)=0 && 2211 // W(21)=1 => UNPREDICTABLE, 2212 // Rt2 == 2213 // Pc || 2214 // Rm == 2215 // Pc || 2216 // Rm == 2217 // Rt || 2218 // Rm == 2219 // Rt2 => UNPREDICTABLE, 2220 // wback && 2221 // (Rn == 2222 // Pc || 2223 // Rn == 2224 // Rt || 2225 // Rn == 2226 // Rt2) => UNPREDICTABLE, 2227 // ArchVersion() < 2228 // 6 && 2229 // wback && 2230 // Rm == 2231 // Rn => UNPREDICTABLE, 2232 // index => FORBIDDEN], 2233 // uses: {Rn, Rm}, 2234 // violations: [implied by 'base'], 2235 // wback: (P(24)=0) || 2236 // (W(21)=1)} 2237 class LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_0 2238 : public ClassDecoder { 2239 public: LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_0()2240 LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_0() 2241 : ClassDecoder() {} 2242 virtual Register base_address_register(Instruction i) const; 2243 virtual RegisterList defs(Instruction inst) const; 2244 virtual SafetyLevel safety(Instruction i) const; 2245 virtual RegisterList uses(Instruction i) const; 2246 virtual ViolationSet get_violations( 2247 const nacl_arm_val::DecodedInstruction& first, 2248 const nacl_arm_val::DecodedInstruction& second, 2249 const nacl_arm_val::SfiValidator& sfi, 2250 nacl_arm_val::AddressSet* branches, 2251 nacl_arm_val::AddressSet* critical, 2252 uint32_t* next_inst_addr) const; 2253 private: 2254 NACL_DISALLOW_COPY_AND_ASSIGN( 2255 LDRD_register_cccc000pu0w0nnnntttt00001101mmmm_case_0); 2256 }; 2257 2258 // LDREXB_cccc00011101nnnntttt111110011111_case_0: 2259 // 2260 // {Pc: 15, 2261 // Rn: Rn(19:16), 2262 // Rt: Rt(15:12), 2263 // arch: v6K, 2264 // base: Rn, 2265 // cond: cond(31:28), 2266 // defs: {Rt}, 2267 // fields: [cond(31:28), Rn(19:16), Rt(15:12)], 2268 // imm32: Zeros((32)), 2269 // pattern: cccc00011101nnnntttt111110011111, 2270 // rule: LDREXB, 2271 // safety: [Pc in {Rt, Rn} => UNPREDICTABLE], 2272 // uses: {Rn}, 2273 // violations: [implied by 'base']} 2274 class LDREXB_cccc00011101nnnntttt111110011111_case_0 2275 : public ClassDecoder { 2276 public: LDREXB_cccc00011101nnnntttt111110011111_case_0()2277 LDREXB_cccc00011101nnnntttt111110011111_case_0() 2278 : ClassDecoder() {} 2279 virtual Register base_address_register(Instruction i) const; 2280 virtual RegisterList defs(Instruction inst) const; 2281 virtual SafetyLevel safety(Instruction i) const; 2282 virtual RegisterList uses(Instruction i) const; 2283 virtual ViolationSet get_violations( 2284 const nacl_arm_val::DecodedInstruction& first, 2285 const nacl_arm_val::DecodedInstruction& second, 2286 const nacl_arm_val::SfiValidator& sfi, 2287 nacl_arm_val::AddressSet* branches, 2288 nacl_arm_val::AddressSet* critical, 2289 uint32_t* next_inst_addr) const; 2290 private: 2291 NACL_DISALLOW_COPY_AND_ASSIGN( 2292 LDREXB_cccc00011101nnnntttt111110011111_case_0); 2293 }; 2294 2295 // LDREXD_cccc00011011nnnntttt111110011111_case_0: 2296 // 2297 // {Lr: 14, 2298 // Pc: 15, 2299 // Rn: Rn(19:16), 2300 // Rt: Rt(15:12), 2301 // Rt2: Rt + 1, 2302 // arch: v6K, 2303 // base: Rn, 2304 // cond: cond(31:28), 2305 // defs: {Rt, Rt2}, 2306 // fields: [cond(31:28), Rn(19:16), Rt(15:12)], 2307 // imm32: Zeros((32)), 2308 // pattern: cccc00011011nnnntttt111110011111, 2309 // rule: LDREXD, 2310 // safety: [Rt(0)=1 || 2311 // Rt == 2312 // Lr || 2313 // Rn == 2314 // Pc => UNPREDICTABLE], 2315 // uses: {Rn}, 2316 // violations: [implied by 'base']} 2317 class LDREXD_cccc00011011nnnntttt111110011111_case_0 2318 : public ClassDecoder { 2319 public: LDREXD_cccc00011011nnnntttt111110011111_case_0()2320 LDREXD_cccc00011011nnnntttt111110011111_case_0() 2321 : ClassDecoder() {} 2322 virtual Register base_address_register(Instruction i) const; 2323 virtual RegisterList defs(Instruction inst) const; 2324 virtual SafetyLevel safety(Instruction i) const; 2325 virtual RegisterList uses(Instruction i) const; 2326 virtual ViolationSet get_violations( 2327 const nacl_arm_val::DecodedInstruction& first, 2328 const nacl_arm_val::DecodedInstruction& second, 2329 const nacl_arm_val::SfiValidator& sfi, 2330 nacl_arm_val::AddressSet* branches, 2331 nacl_arm_val::AddressSet* critical, 2332 uint32_t* next_inst_addr) const; 2333 private: 2334 NACL_DISALLOW_COPY_AND_ASSIGN( 2335 LDREXD_cccc00011011nnnntttt111110011111_case_0); 2336 }; 2337 2338 // LDREX_cccc00011001nnnntttt111110011111_case_0: 2339 // 2340 // {Pc: 15, 2341 // Rn: Rn(19:16), 2342 // Rt: Rt(15:12), 2343 // arch: v6, 2344 // base: Rn, 2345 // cond: cond(31:28), 2346 // defs: {Rt}, 2347 // fields: [cond(31:28), Rn(19:16), Rt(15:12)], 2348 // imm32: Zeros((32)), 2349 // pattern: cccc00011001nnnntttt111110011111, 2350 // rule: LDREX, 2351 // safety: [Pc in {Rt, Rn} => UNPREDICTABLE], 2352 // uses: {Rn}, 2353 // violations: [implied by 'base']} 2354 class LDREX_cccc00011001nnnntttt111110011111_case_0 2355 : public ClassDecoder { 2356 public: LDREX_cccc00011001nnnntttt111110011111_case_0()2357 LDREX_cccc00011001nnnntttt111110011111_case_0() 2358 : ClassDecoder() {} 2359 virtual Register base_address_register(Instruction i) const; 2360 virtual RegisterList defs(Instruction inst) const; 2361 virtual SafetyLevel safety(Instruction i) const; 2362 virtual RegisterList uses(Instruction i) const; 2363 virtual ViolationSet get_violations( 2364 const nacl_arm_val::DecodedInstruction& first, 2365 const nacl_arm_val::DecodedInstruction& second, 2366 const nacl_arm_val::SfiValidator& sfi, 2367 nacl_arm_val::AddressSet* branches, 2368 nacl_arm_val::AddressSet* critical, 2369 uint32_t* next_inst_addr) const; 2370 private: 2371 NACL_DISALLOW_COPY_AND_ASSIGN( 2372 LDREX_cccc00011001nnnntttt111110011111_case_0); 2373 }; 2374 2375 // LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_0: 2376 // 2377 // {None: 32, 2378 // P: P(24), 2379 // Pc: 15, 2380 // Rn: Rn(19:16), 2381 // Rt: Rt(15:12), 2382 // U: U(23), 2383 // W: W(21), 2384 // add: U(23)=1, 2385 // address: offset_addr 2386 // if index 2387 // else Rn, 2388 // base: Rn, 2389 // cond: cond(31:28), 2390 // defs: {Rt, base 2391 // if wback 2392 // else None}, 2393 // fields: [cond(31:28), 2394 // P(24), 2395 // U(23), 2396 // W(21), 2397 // Rn(19:16), 2398 // Rt(15:12), 2399 // imm4H(11:8), 2400 // imm4L(3:0)], 2401 // imm32: ZeroExtend(imm4H:imm4L, 32), 2402 // imm4H: imm4H(11:8), 2403 // imm4L: imm4L(3:0), 2404 // index: P(24)=1, 2405 // offset_addr: Rn + imm32 2406 // if add 2407 // else Rn - imm32, 2408 // pattern: cccc000pu1w1nnnnttttiiii1011iiii, 2409 // rule: LDRH_immediate, 2410 // safety: [Rn(19:16)=1111 => DECODER_ERROR, 2411 // P(24)=0 && 2412 // W(21)=1 => DECODER_ERROR, 2413 // Rt == 2414 // Pc || 2415 // (wback && 2416 // Rn == 2417 // Rt) => UNPREDICTABLE, 2418 // Rt == 2419 // Pc => FORBIDDEN_OPERANDS], 2420 // small_imm_base_wb: wback, 2421 // uses: {Rn}, 2422 // violations: [implied by 'base'], 2423 // wback: (P(24)=0) || 2424 // (W(21)=1)} 2425 class LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_0 2426 : public ClassDecoder { 2427 public: LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_0()2428 LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_0() 2429 : ClassDecoder() {} 2430 virtual Register base_address_register(Instruction i) const; 2431 virtual RegisterList defs(Instruction inst) const; 2432 virtual SafetyLevel safety(Instruction i) const; 2433 virtual bool base_address_register_writeback_small_immediate( 2434 Instruction i) const; 2435 virtual RegisterList uses(Instruction i) const; 2436 virtual ViolationSet get_violations( 2437 const nacl_arm_val::DecodedInstruction& first, 2438 const nacl_arm_val::DecodedInstruction& second, 2439 const nacl_arm_val::SfiValidator& sfi, 2440 nacl_arm_val::AddressSet* branches, 2441 nacl_arm_val::AddressSet* critical, 2442 uint32_t* next_inst_addr) const; 2443 private: 2444 NACL_DISALLOW_COPY_AND_ASSIGN( 2445 LDRH_immediate_cccc000pu1w1nnnnttttiiii1011iiii_case_0); 2446 }; 2447 2448 // LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_0: 2449 // 2450 // {P: P(24), 2451 // Pc: 15, 2452 // Rt: Rt(15:12), 2453 // U: U(23), 2454 // W: W(21), 2455 // add: U(23)=1, 2456 // base: Pc, 2457 // cond: cond(31:28), 2458 // defs: {Rt}, 2459 // fields: [cond(31:28), 2460 // P(24), 2461 // U(23), 2462 // W(21), 2463 // Rt(15:12), 2464 // imm4H(11:8), 2465 // imm4L(3:0)], 2466 // imm32: ZeroExtend(imm4H:imm4L, 32), 2467 // imm4H: imm4H(11:8), 2468 // imm4L: imm4L(3:0), 2469 // is_literal_load: true, 2470 // pattern: cccc000pu1w11111ttttiiii1011iiii, 2471 // rule: LDRH_literal, 2472 // safety: [P(24)=0 && 2473 // W(21)=1 => DECODER_ERROR, 2474 // P == 2475 // W => UNPREDICTABLE, 2476 // Rt == 2477 // Pc => UNPREDICTABLE], 2478 // true: true, 2479 // uses: {Pc}, 2480 // violations: [implied by 'base']} 2481 class LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_0 2482 : public ClassDecoder { 2483 public: LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_0()2484 LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_0() 2485 : ClassDecoder() {} 2486 virtual Register base_address_register(Instruction i) const; 2487 virtual RegisterList defs(Instruction inst) const; 2488 virtual bool is_literal_load(Instruction i) const; 2489 virtual SafetyLevel safety(Instruction i) const; 2490 virtual RegisterList uses(Instruction i) const; 2491 virtual ViolationSet get_violations( 2492 const nacl_arm_val::DecodedInstruction& first, 2493 const nacl_arm_val::DecodedInstruction& second, 2494 const nacl_arm_val::SfiValidator& sfi, 2495 nacl_arm_val::AddressSet* branches, 2496 nacl_arm_val::AddressSet* critical, 2497 uint32_t* next_inst_addr) const; 2498 private: 2499 NACL_DISALLOW_COPY_AND_ASSIGN( 2500 LDRH_literal_cccc000pu1w11111ttttiiii1011iiii_case_0); 2501 }; 2502 2503 // LDRH_register_cccc000pu0w1nnnntttt00001011mmmm_case_0: 2504 // 2505 // {None: 32, 2506 // P: P(24), 2507 // Pc: 15, 2508 // Rm: Rm(3:0), 2509 // Rn: Rn(19:16), 2510 // Rt: Rt(15:12), 2511 // U: U(23), 2512 // W: W(21), 2513 // add: U(23)=1, 2514 // base: Rn, 2515 // cond: cond(31:28), 2516 // defs: {Rt, base 2517 // if wback 2518 // else None}, 2519 // fields: [cond(31:28), 2520 // P(24), 2521 // U(23), 2522 // W(21), 2523 // Rn(19:16), 2524 // Rt(15:12), 2525 // Rm(3:0)], 2526 // index: P(24)=1, 2527 // pattern: cccc000pu0w1nnnntttt00001011mmmm, 2528 // rule: LDRH_register, 2529 // safety: [P(24)=0 && 2530 // W(21)=1 => DECODER_ERROR, 2531 // Pc in {Rt, Rm} => UNPREDICTABLE, 2532 // wback && 2533 // (Rn == 2534 // Pc || 2535 // Rn == 2536 // Rt) => UNPREDICTABLE, 2537 // ArchVersion() < 2538 // 6 && 2539 // wback && 2540 // Rm == 2541 // Rn => UNPREDICTABLE, 2542 // index => FORBIDDEN], 2543 // shift_n: 0, 2544 // shift_t: SRType_LSL(), 2545 // uses: {Rn, Rm}, 2546 // violations: [implied by 'base'], 2547 // wback: (P(24)=0) || 2548 // (W(21)=1)} 2549 class LDRH_register_cccc000pu0w1nnnntttt00001011mmmm_case_0 2550 : public ClassDecoder { 2551 public: LDRH_register_cccc000pu0w1nnnntttt00001011mmmm_case_0()2552 LDRH_register_cccc000pu0w1nnnntttt00001011mmmm_case_0() 2553 : ClassDecoder() {} 2554 virtual Register base_address_register(Instruction i) const; 2555 virtual RegisterList defs(Instruction inst) const; 2556 virtual SafetyLevel safety(Instruction i) const; 2557 virtual RegisterList uses(Instruction i) const; 2558 virtual ViolationSet get_violations( 2559 const nacl_arm_val::DecodedInstruction& first, 2560 const nacl_arm_val::DecodedInstruction& second, 2561 const nacl_arm_val::SfiValidator& sfi, 2562 nacl_arm_val::AddressSet* branches, 2563 nacl_arm_val::AddressSet* critical, 2564 uint32_t* next_inst_addr) const; 2565 private: 2566 NACL_DISALLOW_COPY_AND_ASSIGN( 2567 LDRH_register_cccc000pu0w1nnnntttt00001011mmmm_case_0); 2568 }; 2569 2570 // LDRSB_immediate_cccc000pu1w1nnnnttttiiii1101iiii_case_0: 2571 // 2572 // {None: 32, 2573 // P: P(24), 2574 // Pc: 15, 2575 // Rn: Rn(19:16), 2576 // Rt: Rt(15:12), 2577 // U: U(23), 2578 // W: W(21), 2579 // add: U(23)=1, 2580 // address: offset_addr 2581 // if index 2582 // else Rn, 2583 // base: Rn, 2584 // cond: cond(31:28), 2585 // defs: {Rt, base 2586 // if wback 2587 // else None}, 2588 // fields: [cond(31:28), 2589 // P(24), 2590 // U(23), 2591 // W(21), 2592 // Rn(19:16), 2593 // Rt(15:12), 2594 // imm4H(11:8), 2595 // imm4L(3:0)], 2596 // imm32: ZeroExtend(imm4H:imm4L, 32), 2597 // imm4H: imm4H(11:8), 2598 // imm4L: imm4L(3:0), 2599 // index: P(24)=1, 2600 // offset_addr: Rn + imm32 2601 // if add 2602 // else Rn - imm32, 2603 // pattern: cccc000pu1w1nnnnttttiiii1101iiii, 2604 // rule: LDRSB_immediate, 2605 // safety: [Rn(19:16)=1111 => DECODER_ERROR, 2606 // P(24)=0 && 2607 // W(21)=1 => DECODER_ERROR, 2608 // Rt == 2609 // Pc || 2610 // (wback && 2611 // Rn == 2612 // Rt) => UNPREDICTABLE, 2613 // Rt == 2614 // Pc => FORBIDDEN_OPERANDS], 2615 // small_imm_base_wb: wback, 2616 // uses: {Rn}, 2617 // violations: [implied by 'base'], 2618 // wback: (P(24)=0) || 2619 // (W(21)=1)} 2620 class LDRSB_immediate_cccc000pu1w1nnnnttttiiii1101iiii_case_0 2621 : public ClassDecoder { 2622 public: LDRSB_immediate_cccc000pu1w1nnnnttttiiii1101iiii_case_0()2623 LDRSB_immediate_cccc000pu1w1nnnnttttiiii1101iiii_case_0() 2624 : ClassDecoder() {} 2625 virtual Register base_address_register(Instruction i) const; 2626 virtual RegisterList defs(Instruction inst) const; 2627 virtual SafetyLevel safety(Instruction i) const; 2628 virtual bool base_address_register_writeback_small_immediate( 2629 Instruction i) const; 2630 virtual RegisterList uses(Instruction i) const; 2631 virtual ViolationSet get_violations( 2632 const nacl_arm_val::DecodedInstruction& first, 2633 const nacl_arm_val::DecodedInstruction& second, 2634 const nacl_arm_val::SfiValidator& sfi, 2635 nacl_arm_val::AddressSet* branches, 2636 nacl_arm_val::AddressSet* critical, 2637 uint32_t* next_inst_addr) const; 2638 private: 2639 NACL_DISALLOW_COPY_AND_ASSIGN( 2640 LDRSB_immediate_cccc000pu1w1nnnnttttiiii1101iiii_case_0); 2641 }; 2642 2643 // LDRSB_literal_cccc0001u1011111ttttiiii1101iiii_case_0: 2644 // 2645 // {P: P(24), 2646 // Pc: 15, 2647 // Rt: Rt(15:12), 2648 // U: U(23), 2649 // W: W(21), 2650 // add: U(23)=1, 2651 // base: Pc, 2652 // cond: cond(31:28), 2653 // defs: {Rt}, 2654 // fields: [cond(31:28), 2655 // P(24), 2656 // U(23), 2657 // W(21), 2658 // Rt(15:12), 2659 // imm4H(11:8), 2660 // imm4L(3:0)], 2661 // imm32: ZeroExtend(imm4H:imm4L, 32), 2662 // imm4H: imm4H(11:8), 2663 // imm4L: imm4L(3:0), 2664 // is_literal_load: true, 2665 // pattern: cccc0001u1011111ttttiiii1101iiii, 2666 // rule: LDRSB_literal, 2667 // safety: [P(24)=0 && 2668 // W(21)=1 => DECODER_ERROR, 2669 // P == 2670 // W => UNPREDICTABLE, 2671 // Rt == 2672 // Pc => UNPREDICTABLE], 2673 // true: true, 2674 // uses: {Pc}, 2675 // violations: [implied by 'base']} 2676 class LDRSB_literal_cccc0001u1011111ttttiiii1101iiii_case_0 2677 : public ClassDecoder { 2678 public: LDRSB_literal_cccc0001u1011111ttttiiii1101iiii_case_0()2679 LDRSB_literal_cccc0001u1011111ttttiiii1101iiii_case_0() 2680 : ClassDecoder() {} 2681 virtual Register base_address_register(Instruction i) const; 2682 virtual RegisterList defs(Instruction inst) const; 2683 virtual bool is_literal_load(Instruction i) const; 2684 virtual SafetyLevel safety(Instruction i) const; 2685 virtual RegisterList uses(Instruction i) const; 2686 virtual ViolationSet get_violations( 2687 const nacl_arm_val::DecodedInstruction& first, 2688 const nacl_arm_val::DecodedInstruction& second, 2689 const nacl_arm_val::SfiValidator& sfi, 2690 nacl_arm_val::AddressSet* branches, 2691 nacl_arm_val::AddressSet* critical, 2692 uint32_t* next_inst_addr) const; 2693 private: 2694 NACL_DISALLOW_COPY_AND_ASSIGN( 2695 LDRSB_literal_cccc0001u1011111ttttiiii1101iiii_case_0); 2696 }; 2697 2698 // LDRSB_register_cccc000pu0w1nnnntttt00001101mmmm_case_0: 2699 // 2700 // {None: 32, 2701 // P: P(24), 2702 // Pc: 15, 2703 // Rm: Rm(3:0), 2704 // Rn: Rn(19:16), 2705 // Rt: Rt(15:12), 2706 // U: U(23), 2707 // W: W(21), 2708 // add: U(23)=1, 2709 // base: Rn, 2710 // cond: cond(31:28), 2711 // defs: {Rt, base 2712 // if wback 2713 // else None}, 2714 // fields: [cond(31:28), 2715 // P(24), 2716 // U(23), 2717 // W(21), 2718 // Rn(19:16), 2719 // Rt(15:12), 2720 // Rm(3:0)], 2721 // index: P(24)=1, 2722 // pattern: cccc000pu0w1nnnntttt00001101mmmm, 2723 // rule: LDRSB_register, 2724 // safety: [P(24)=0 && 2725 // W(21)=1 => DECODER_ERROR, 2726 // Pc in {Rt, Rm} => UNPREDICTABLE, 2727 // wback && 2728 // (Rn == 2729 // Pc || 2730 // Rn == 2731 // Rt) => UNPREDICTABLE, 2732 // ArchVersion() < 2733 // 6 && 2734 // wback && 2735 // Rm == 2736 // Rn => UNPREDICTABLE, 2737 // index => FORBIDDEN], 2738 // shift_n: 0, 2739 // shift_t: SRType_LSL(), 2740 // uses: {Rn, Rm}, 2741 // violations: [implied by 'base'], 2742 // wback: (P(24)=0) || 2743 // (W(21)=1)} 2744 class LDRSB_register_cccc000pu0w1nnnntttt00001101mmmm_case_0 2745 : public ClassDecoder { 2746 public: LDRSB_register_cccc000pu0w1nnnntttt00001101mmmm_case_0()2747 LDRSB_register_cccc000pu0w1nnnntttt00001101mmmm_case_0() 2748 : ClassDecoder() {} 2749 virtual Register base_address_register(Instruction i) const; 2750 virtual RegisterList defs(Instruction inst) const; 2751 virtual SafetyLevel safety(Instruction i) const; 2752 virtual RegisterList uses(Instruction i) const; 2753 virtual ViolationSet get_violations( 2754 const nacl_arm_val::DecodedInstruction& first, 2755 const nacl_arm_val::DecodedInstruction& second, 2756 const nacl_arm_val::SfiValidator& sfi, 2757 nacl_arm_val::AddressSet* branches, 2758 nacl_arm_val::AddressSet* critical, 2759 uint32_t* next_inst_addr) const; 2760 private: 2761 NACL_DISALLOW_COPY_AND_ASSIGN( 2762 LDRSB_register_cccc000pu0w1nnnntttt00001101mmmm_case_0); 2763 }; 2764 2765 // LDRSH_immediate_cccc000pu1w1nnnnttttiiii1111iiii_case_0: 2766 // 2767 // {None: 32, 2768 // P: P(24), 2769 // Pc: 15, 2770 // Rn: Rn(19:16), 2771 // Rt: Rt(15:12), 2772 // U: U(23), 2773 // W: W(21), 2774 // add: U(23)=1, 2775 // address: offset_addr 2776 // if index 2777 // else Rn, 2778 // base: Rn, 2779 // cond: cond(31:28), 2780 // defs: {Rt, base 2781 // if wback 2782 // else None}, 2783 // fields: [cond(31:28), 2784 // P(24), 2785 // U(23), 2786 // W(21), 2787 // Rn(19:16), 2788 // Rt(15:12), 2789 // imm4H(11:8), 2790 // imm4L(3:0)], 2791 // imm32: ZeroExtend(imm4H:imm4L, 32), 2792 // imm4H: imm4H(11:8), 2793 // imm4L: imm4L(3:0), 2794 // index: P(24)=1, 2795 // offset_addr: Rn + imm32 2796 // if add 2797 // else Rn - imm32, 2798 // pattern: cccc000pu1w1nnnnttttiiii1111iiii, 2799 // rule: LDRSH_immediate, 2800 // safety: [Rn(19:16)=1111 => DECODER_ERROR, 2801 // P(24)=0 && 2802 // W(21)=1 => DECODER_ERROR, 2803 // Rt == 2804 // Pc || 2805 // (wback && 2806 // Rn == 2807 // Rt) => UNPREDICTABLE, 2808 // Rt == 2809 // Pc => FORBIDDEN_OPERANDS], 2810 // small_imm_base_wb: wback, 2811 // uses: {Rn}, 2812 // violations: [implied by 'base'], 2813 // wback: (P(24)=0) || 2814 // (W(21)=1)} 2815 class LDRSH_immediate_cccc000pu1w1nnnnttttiiii1111iiii_case_0 2816 : public ClassDecoder { 2817 public: LDRSH_immediate_cccc000pu1w1nnnnttttiiii1111iiii_case_0()2818 LDRSH_immediate_cccc000pu1w1nnnnttttiiii1111iiii_case_0() 2819 : ClassDecoder() {} 2820 virtual Register base_address_register(Instruction i) const; 2821 virtual RegisterList defs(Instruction inst) const; 2822 virtual SafetyLevel safety(Instruction i) const; 2823 virtual bool base_address_register_writeback_small_immediate( 2824 Instruction i) const; 2825 virtual RegisterList uses(Instruction i) const; 2826 virtual ViolationSet get_violations( 2827 const nacl_arm_val::DecodedInstruction& first, 2828 const nacl_arm_val::DecodedInstruction& second, 2829 const nacl_arm_val::SfiValidator& sfi, 2830 nacl_arm_val::AddressSet* branches, 2831 nacl_arm_val::AddressSet* critical, 2832 uint32_t* next_inst_addr) const; 2833 private: 2834 NACL_DISALLOW_COPY_AND_ASSIGN( 2835 LDRSH_immediate_cccc000pu1w1nnnnttttiiii1111iiii_case_0); 2836 }; 2837 2838 // LDRSH_literal_cccc0001u1011111ttttiiii1111iiii_case_0: 2839 // 2840 // {P: P(24), 2841 // Pc: 15, 2842 // Rt: Rt(15:12), 2843 // U: U(23), 2844 // W: W(21), 2845 // add: U(23)=1, 2846 // base: Pc, 2847 // cond: cond(31:28), 2848 // defs: {Rt}, 2849 // fields: [cond(31:28), 2850 // P(24), 2851 // U(23), 2852 // W(21), 2853 // Rt(15:12), 2854 // imm4H(11:8), 2855 // imm4L(3:0)], 2856 // imm32: ZeroExtend(imm4H:imm4L, 32), 2857 // imm4H: imm4H(11:8), 2858 // imm4L: imm4L(3:0), 2859 // is_literal_load: true, 2860 // pattern: cccc0001u1011111ttttiiii1111iiii, 2861 // rule: LDRSH_literal, 2862 // safety: [P(24)=0 && 2863 // W(21)=1 => DECODER_ERROR, 2864 // P == 2865 // W => UNPREDICTABLE, 2866 // Rt == 2867 // Pc => UNPREDICTABLE], 2868 // true: true, 2869 // uses: {Pc}, 2870 // violations: [implied by 'base']} 2871 class LDRSH_literal_cccc0001u1011111ttttiiii1111iiii_case_0 2872 : public ClassDecoder { 2873 public: LDRSH_literal_cccc0001u1011111ttttiiii1111iiii_case_0()2874 LDRSH_literal_cccc0001u1011111ttttiiii1111iiii_case_0() 2875 : ClassDecoder() {} 2876 virtual Register base_address_register(Instruction i) const; 2877 virtual RegisterList defs(Instruction inst) const; 2878 virtual bool is_literal_load(Instruction i) const; 2879 virtual SafetyLevel safety(Instruction i) const; 2880 virtual RegisterList uses(Instruction i) const; 2881 virtual ViolationSet get_violations( 2882 const nacl_arm_val::DecodedInstruction& first, 2883 const nacl_arm_val::DecodedInstruction& second, 2884 const nacl_arm_val::SfiValidator& sfi, 2885 nacl_arm_val::AddressSet* branches, 2886 nacl_arm_val::AddressSet* critical, 2887 uint32_t* next_inst_addr) const; 2888 private: 2889 NACL_DISALLOW_COPY_AND_ASSIGN( 2890 LDRSH_literal_cccc0001u1011111ttttiiii1111iiii_case_0); 2891 }; 2892 2893 // LDRSH_register_cccc000pu0w1nnnntttt00001111mmmm_case_0: 2894 // 2895 // {None: 32, 2896 // P: P(24), 2897 // Pc: 15, 2898 // Rm: Rm(3:0), 2899 // Rn: Rn(19:16), 2900 // Rt: Rt(15:12), 2901 // U: U(23), 2902 // W: W(21), 2903 // add: U(23)=1, 2904 // base: Rn, 2905 // cond: cond(31:28), 2906 // defs: {Rt, base 2907 // if wback 2908 // else None}, 2909 // fields: [cond(31:28), 2910 // P(24), 2911 // U(23), 2912 // W(21), 2913 // Rn(19:16), 2914 // Rt(15:12), 2915 // Rm(3:0)], 2916 // index: P(24)=1, 2917 // pattern: cccc000pu0w1nnnntttt00001111mmmm, 2918 // rule: LDRSH_register, 2919 // safety: [P(24)=0 && 2920 // W(21)=1 => DECODER_ERROR, 2921 // Pc in {Rt, Rm} => UNPREDICTABLE, 2922 // wback && 2923 // (Rn == 2924 // Pc || 2925 // Rn == 2926 // Rt) => UNPREDICTABLE, 2927 // ArchVersion() < 2928 // 6 && 2929 // wback && 2930 // Rm == 2931 // Rn => UNPREDICTABLE, 2932 // index => FORBIDDEN], 2933 // shift_n: 0, 2934 // shift_t: SRType_LSL(), 2935 // uses: {Rn, Rm}, 2936 // violations: [implied by 'base'], 2937 // wback: (P(24)=0) || 2938 // (W(21)=1)} 2939 class LDRSH_register_cccc000pu0w1nnnntttt00001111mmmm_case_0 2940 : public ClassDecoder { 2941 public: LDRSH_register_cccc000pu0w1nnnntttt00001111mmmm_case_0()2942 LDRSH_register_cccc000pu0w1nnnntttt00001111mmmm_case_0() 2943 : ClassDecoder() {} 2944 virtual Register base_address_register(Instruction i) const; 2945 virtual RegisterList defs(Instruction inst) const; 2946 virtual SafetyLevel safety(Instruction i) const; 2947 virtual RegisterList uses(Instruction i) const; 2948 virtual ViolationSet get_violations( 2949 const nacl_arm_val::DecodedInstruction& first, 2950 const nacl_arm_val::DecodedInstruction& second, 2951 const nacl_arm_val::SfiValidator& sfi, 2952 nacl_arm_val::AddressSet* branches, 2953 nacl_arm_val::AddressSet* critical, 2954 uint32_t* next_inst_addr) const; 2955 private: 2956 NACL_DISALLOW_COPY_AND_ASSIGN( 2957 LDRSH_register_cccc000pu0w1nnnntttt00001111mmmm_case_0); 2958 }; 2959 2960 // LDRT_A1_cccc0100u011nnnnttttiiiiiiiiiiii_case_0: 2961 // 2962 // {defs: {}, 2963 // pattern: cccc0100u011nnnnttttiiiiiiiiiiii, 2964 // rule: LDRT_A1, 2965 // safety: [true => FORBIDDEN], 2966 // true: true, 2967 // uses: {}} 2968 class LDRT_A1_cccc0100u011nnnnttttiiiiiiiiiiii_case_0 2969 : public ClassDecoder { 2970 public: LDRT_A1_cccc0100u011nnnnttttiiiiiiiiiiii_case_0()2971 LDRT_A1_cccc0100u011nnnnttttiiiiiiiiiiii_case_0() 2972 : ClassDecoder() {} 2973 virtual RegisterList defs(Instruction inst) const; 2974 virtual SafetyLevel safety(Instruction i) const; 2975 virtual RegisterList uses(Instruction i) const; 2976 private: 2977 NACL_DISALLOW_COPY_AND_ASSIGN( 2978 LDRT_A1_cccc0100u011nnnnttttiiiiiiiiiiii_case_0); 2979 }; 2980 2981 // LDRT_A2_cccc0110u011nnnnttttiiiiitt0mmmm_case_0: 2982 // 2983 // {defs: {}, 2984 // pattern: cccc0110u011nnnnttttiiiiitt0mmmm, 2985 // rule: LDRT_A2, 2986 // safety: [true => FORBIDDEN], 2987 // true: true, 2988 // uses: {}} 2989 class LDRT_A2_cccc0110u011nnnnttttiiiiitt0mmmm_case_0 2990 : public ClassDecoder { 2991 public: LDRT_A2_cccc0110u011nnnnttttiiiiitt0mmmm_case_0()2992 LDRT_A2_cccc0110u011nnnnttttiiiiitt0mmmm_case_0() 2993 : ClassDecoder() {} 2994 virtual RegisterList defs(Instruction inst) const; 2995 virtual SafetyLevel safety(Instruction i) const; 2996 virtual RegisterList uses(Instruction i) const; 2997 private: 2998 NACL_DISALLOW_COPY_AND_ASSIGN( 2999 LDRT_A2_cccc0110u011nnnnttttiiiiitt0mmmm_case_0); 3000 }; 3001 3002 // LDR_immediate_cccc010pu0w1nnnnttttiiiiiiiiiiii_case_0: 3003 // 3004 // {None: 32, 3005 // P: P(24), 3006 // Pc: 15, 3007 // Rn: Rn(19:16), 3008 // Rt: Rt(15:12), 3009 // Tp: 9, 3010 // U: U(23), 3011 // W: W(21), 3012 // add: U(23)=1, 3013 // base: Rn, 3014 // cond: cond(31:28), 3015 // defs: {Rt, base 3016 // if wback 3017 // else None}, 3018 // fields: [cond(31:28), 3019 // P(24), 3020 // U(23), 3021 // W(21), 3022 // Rn(19:16), 3023 // Rt(15:12), 3024 // imm12(11:0)], 3025 // imm12: imm12(11:0), 3026 // imm32: ZeroExtend(imm12, 32), 3027 // index: P(24)=1, 3028 // is_load_tp: Rn == 3029 // Tp && 3030 // index && 3031 // not wback && 3032 // add && 3033 // imm12 in {0, 4}, 3034 // pattern: cccc010pu0w1nnnnttttiiiiiiiiiiii, 3035 // rule: LDR_immediate, 3036 // safety: [Rn == 3037 // Pc => DECODER_ERROR, 3038 // P(24)=0 && 3039 // W(21)=1 => DECODER_ERROR, 3040 // wback && 3041 // Rn == 3042 // Rt => UNPREDICTABLE, 3043 // Rt == 3044 // Pc => FORBIDDEN_OPERANDS], 3045 // small_imm_base_wb: wback, 3046 // uses: {Rn}, 3047 // violations: [implied by 'base'], 3048 // wback: P(24)=0 || 3049 // W(21)=1} 3050 class LDR_immediate_cccc010pu0w1nnnnttttiiiiiiiiiiii_case_0 3051 : public ClassDecoder { 3052 public: LDR_immediate_cccc010pu0w1nnnnttttiiiiiiiiiiii_case_0()3053 LDR_immediate_cccc010pu0w1nnnnttttiiiiiiiiiiii_case_0() 3054 : ClassDecoder() {} 3055 virtual Register base_address_register(Instruction i) const; 3056 virtual RegisterList defs(Instruction inst) const; 3057 virtual bool is_load_thread_address_pointer(Instruction i) const; 3058 virtual SafetyLevel safety(Instruction i) const; 3059 virtual bool base_address_register_writeback_small_immediate( 3060 Instruction i) const; 3061 virtual RegisterList uses(Instruction i) const; 3062 virtual ViolationSet get_violations( 3063 const nacl_arm_val::DecodedInstruction& first, 3064 const nacl_arm_val::DecodedInstruction& second, 3065 const nacl_arm_val::SfiValidator& sfi, 3066 nacl_arm_val::AddressSet* branches, 3067 nacl_arm_val::AddressSet* critical, 3068 uint32_t* next_inst_addr) const; 3069 private: 3070 NACL_DISALLOW_COPY_AND_ASSIGN( 3071 LDR_immediate_cccc010pu0w1nnnnttttiiiiiiiiiiii_case_0); 3072 }; 3073 3074 // LDR_literal_cccc0101u0011111ttttiiiiiiiiiiii_case_0: 3075 // 3076 // {Pc: 15, 3077 // Rt: Rt(15:12), 3078 // U: U(23), 3079 // add: U(23)=1, 3080 // base: Pc, 3081 // cond: cond(31:28), 3082 // defs: {Rt}, 3083 // fields: [cond(31:28), U(23), Rt(15:12), imm12(11:0)], 3084 // imm12: imm12(11:0), 3085 // imm32: ZeroExtend(imm12, 32), 3086 // is_literal_load: true, 3087 // pattern: cccc0101u0011111ttttiiiiiiiiiiii, 3088 // rule: LDR_literal, 3089 // safety: [Rt == 3090 // Pc => FORBIDDEN_OPERANDS], 3091 // true: true, 3092 // uses: {Pc}, 3093 // violations: [implied by 'base']} 3094 class LDR_literal_cccc0101u0011111ttttiiiiiiiiiiii_case_0 3095 : public ClassDecoder { 3096 public: LDR_literal_cccc0101u0011111ttttiiiiiiiiiiii_case_0()3097 LDR_literal_cccc0101u0011111ttttiiiiiiiiiiii_case_0() 3098 : ClassDecoder() {} 3099 virtual Register base_address_register(Instruction i) const; 3100 virtual RegisterList defs(Instruction inst) const; 3101 virtual bool is_literal_load(Instruction i) const; 3102 virtual SafetyLevel safety(Instruction i) const; 3103 virtual RegisterList uses(Instruction i) const; 3104 virtual ViolationSet get_violations( 3105 const nacl_arm_val::DecodedInstruction& first, 3106 const nacl_arm_val::DecodedInstruction& second, 3107 const nacl_arm_val::SfiValidator& sfi, 3108 nacl_arm_val::AddressSet* branches, 3109 nacl_arm_val::AddressSet* critical, 3110 uint32_t* next_inst_addr) const; 3111 private: 3112 NACL_DISALLOW_COPY_AND_ASSIGN( 3113 LDR_literal_cccc0101u0011111ttttiiiiiiiiiiii_case_0); 3114 }; 3115 3116 // LDR_register_cccc011pu0w1nnnnttttiiiiitt0mmmm_case_0: 3117 // 3118 // {None: 32, 3119 // P: P(24), 3120 // Pc: 15, 3121 // Rm: Rm(3:0), 3122 // Rn: Rn(19:16), 3123 // Rt: Rt(15:12), 3124 // U: U(23), 3125 // W: W(21), 3126 // add: U(23)=1, 3127 // base: Rn, 3128 // cond: cond(31:28), 3129 // defs: {Rt, base 3130 // if wback 3131 // else None}, 3132 // fields: [cond(31:28), 3133 // P(24), 3134 // U(23), 3135 // W(21), 3136 // Rn(19:16), 3137 // Rt(15:12), 3138 // imm5(11:7), 3139 // type(6:5), 3140 // Rm(3:0)], 3141 // imm5: imm5(11:7), 3142 // index: P(24)=1, 3143 // pattern: cccc011pu0w1nnnnttttiiiiitt0mmmm, 3144 // rule: LDR_register, 3145 // safety: [P(24)=0 && 3146 // W(21)=1 => DECODER_ERROR, 3147 // Rm == 3148 // Pc => UNPREDICTABLE, 3149 // wback && 3150 // (Rn == 3151 // Pc || 3152 // Rn == 3153 // Rt) => UNPREDICTABLE, 3154 // ArchVersion() < 3155 // 6 && 3156 // wback && 3157 // Rn == 3158 // Rm => UNPREDICTABLE, 3159 // index => FORBIDDEN, 3160 // Rt == 3161 // Pc => FORBIDDEN_OPERANDS], 3162 // shift: DecodeImmShift(type, imm5), 3163 // type: type(6:5), 3164 // uses: {Rm, Rn}, 3165 // violations: [implied by 'base'], 3166 // wback: P(24)=0 || 3167 // W(21)=1} 3168 class LDR_register_cccc011pu0w1nnnnttttiiiiitt0mmmm_case_0 3169 : public ClassDecoder { 3170 public: LDR_register_cccc011pu0w1nnnnttttiiiiitt0mmmm_case_0()3171 LDR_register_cccc011pu0w1nnnnttttiiiiitt0mmmm_case_0() 3172 : ClassDecoder() {} 3173 virtual Register base_address_register(Instruction i) const; 3174 virtual RegisterList defs(Instruction inst) const; 3175 virtual SafetyLevel safety(Instruction i) const; 3176 virtual RegisterList uses(Instruction i) const; 3177 virtual ViolationSet get_violations( 3178 const nacl_arm_val::DecodedInstruction& first, 3179 const nacl_arm_val::DecodedInstruction& second, 3180 const nacl_arm_val::SfiValidator& sfi, 3181 nacl_arm_val::AddressSet* branches, 3182 nacl_arm_val::AddressSet* critical, 3183 uint32_t* next_inst_addr) const; 3184 private: 3185 NACL_DISALLOW_COPY_AND_ASSIGN( 3186 LDR_register_cccc011pu0w1nnnnttttiiiiitt0mmmm_case_0); 3187 }; 3188 3189 // LSL_immediate_cccc0001101s0000ddddiiiii000mmmm_case_0: 3190 // 3191 // {NZCV: 16, 3192 // None: 32, 3193 // Rd: Rd(15:12), 3194 // Rm: Rm(3:0), 3195 // S: S(20), 3196 // cond: cond(31:28), 3197 // defs: {Rd, NZCV 3198 // if S 3199 // else None}, 3200 // fields: [cond(31:28), 3201 // S(20), 3202 // Rd(15:12), 3203 // imm5(11:7), 3204 // type(6:5), 3205 // Rm(3:0)], 3206 // imm5: imm5(11:7), 3207 // pattern: cccc0001101s0000ddddiiiii000mmmm, 3208 // rule: LSL_immediate, 3209 // safety: [(Rd(15:12)=1111 && 3210 // S(20)=1) => DECODER_ERROR, 3211 // imm5(11:7)=00000 => DECODER_ERROR, 3212 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 3213 // shift: DecodeImmShift(type, imm5), 3214 // type: type(6:5), 3215 // uses: {Rm}} 3216 class LSL_immediate_cccc0001101s0000ddddiiiii000mmmm_case_0 3217 : public ClassDecoder { 3218 public: LSL_immediate_cccc0001101s0000ddddiiiii000mmmm_case_0()3219 LSL_immediate_cccc0001101s0000ddddiiiii000mmmm_case_0() 3220 : ClassDecoder() {} 3221 virtual RegisterList defs(Instruction inst) const; 3222 virtual SafetyLevel safety(Instruction i) const; 3223 virtual RegisterList uses(Instruction i) const; 3224 private: 3225 NACL_DISALLOW_COPY_AND_ASSIGN( 3226 LSL_immediate_cccc0001101s0000ddddiiiii000mmmm_case_0); 3227 }; 3228 3229 // LSL_register_cccc0001101s0000ddddmmmm0001nnnn_case_0: 3230 // 3231 // {NZCV: 16, 3232 // None: 32, 3233 // Pc: 15, 3234 // Rd: Rd(15:12), 3235 // Rm: Rm(11:8), 3236 // Rn: Rn(3:0), 3237 // S: S(20), 3238 // cond: cond(31:28), 3239 // defs: {Rd, NZCV 3240 // if setflags 3241 // else None}, 3242 // fields: [cond(31:28), S(20), Rd(15:12), Rm(11:8), Rn(3:0)], 3243 // pattern: cccc0001101s0000ddddmmmm0001nnnn, 3244 // rule: LSL_register, 3245 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 3246 // setflags: S(20)=1, 3247 // uses: {Rn, Rm}} 3248 class LSL_register_cccc0001101s0000ddddmmmm0001nnnn_case_0 3249 : public ClassDecoder { 3250 public: LSL_register_cccc0001101s0000ddddmmmm0001nnnn_case_0()3251 LSL_register_cccc0001101s0000ddddmmmm0001nnnn_case_0() 3252 : ClassDecoder() {} 3253 virtual RegisterList defs(Instruction inst) const; 3254 virtual SafetyLevel safety(Instruction i) const; 3255 virtual RegisterList uses(Instruction i) const; 3256 private: 3257 NACL_DISALLOW_COPY_AND_ASSIGN( 3258 LSL_register_cccc0001101s0000ddddmmmm0001nnnn_case_0); 3259 }; 3260 3261 // LSR_immediate_cccc0001101s0000ddddiiiii010mmmm_case_0: 3262 // 3263 // {NZCV: 16, 3264 // None: 32, 3265 // Rd: Rd(15:12), 3266 // Rm: Rm(3:0), 3267 // S: S(20), 3268 // cond: cond(31:28), 3269 // defs: {Rd, NZCV 3270 // if S 3271 // else None}, 3272 // fields: [cond(31:28), 3273 // S(20), 3274 // Rd(15:12), 3275 // imm5(11:7), 3276 // type(6:5), 3277 // Rm(3:0)], 3278 // imm5: imm5(11:7), 3279 // pattern: cccc0001101s0000ddddiiiii010mmmm, 3280 // rule: LSR_immediate, 3281 // safety: [(Rd(15:12)=1111 && 3282 // S(20)=1) => DECODER_ERROR, 3283 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 3284 // shift: DecodeImmShift(type, imm5), 3285 // type: type(6:5), 3286 // uses: {Rm}} 3287 class LSR_immediate_cccc0001101s0000ddddiiiii010mmmm_case_0 3288 : public ClassDecoder { 3289 public: LSR_immediate_cccc0001101s0000ddddiiiii010mmmm_case_0()3290 LSR_immediate_cccc0001101s0000ddddiiiii010mmmm_case_0() 3291 : ClassDecoder() {} 3292 virtual RegisterList defs(Instruction inst) const; 3293 virtual SafetyLevel safety(Instruction i) const; 3294 virtual RegisterList uses(Instruction i) const; 3295 private: 3296 NACL_DISALLOW_COPY_AND_ASSIGN( 3297 LSR_immediate_cccc0001101s0000ddddiiiii010mmmm_case_0); 3298 }; 3299 3300 // LSR_register_cccc0001101s0000ddddmmmm0011nnnn_case_0: 3301 // 3302 // {NZCV: 16, 3303 // None: 32, 3304 // Pc: 15, 3305 // Rd: Rd(15:12), 3306 // Rm: Rm(11:8), 3307 // Rn: Rn(3:0), 3308 // S: S(20), 3309 // cond: cond(31:28), 3310 // defs: {Rd, NZCV 3311 // if setflags 3312 // else None}, 3313 // fields: [cond(31:28), S(20), Rd(15:12), Rm(11:8), Rn(3:0)], 3314 // pattern: cccc0001101s0000ddddmmmm0011nnnn, 3315 // rule: LSR_register, 3316 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 3317 // setflags: S(20)=1, 3318 // uses: {Rn, Rm}} 3319 class LSR_register_cccc0001101s0000ddddmmmm0011nnnn_case_0 3320 : public ClassDecoder { 3321 public: LSR_register_cccc0001101s0000ddddmmmm0011nnnn_case_0()3322 LSR_register_cccc0001101s0000ddddmmmm0011nnnn_case_0() 3323 : ClassDecoder() {} 3324 virtual RegisterList defs(Instruction inst) const; 3325 virtual SafetyLevel safety(Instruction i) const; 3326 virtual RegisterList uses(Instruction i) const; 3327 private: 3328 NACL_DISALLOW_COPY_AND_ASSIGN( 3329 LSR_register_cccc0001101s0000ddddmmmm0011nnnn_case_0); 3330 }; 3331 3332 // MCR2_11111110iii0iiiittttiiiiiii1iiii_case_0: 3333 // 3334 // {arch: v5, 3335 // defs: {}, 3336 // pattern: 11111110iii0iiiittttiiiiiii1iiii, 3337 // rule: MCR2, 3338 // safety: [true => FORBIDDEN], 3339 // true: true, 3340 // uses: {}} 3341 class MCR2_11111110iii0iiiittttiiiiiii1iiii_case_0 3342 : public ClassDecoder { 3343 public: MCR2_11111110iii0iiiittttiiiiiii1iiii_case_0()3344 MCR2_11111110iii0iiiittttiiiiiii1iiii_case_0() 3345 : ClassDecoder() {} 3346 virtual RegisterList defs(Instruction inst) const; 3347 virtual SafetyLevel safety(Instruction i) const; 3348 virtual RegisterList uses(Instruction i) const; 3349 private: 3350 NACL_DISALLOW_COPY_AND_ASSIGN( 3351 MCR2_11111110iii0iiiittttiiiiiii1iiii_case_0); 3352 }; 3353 3354 // MCRR2_111111000100ssssttttiiiiiiiiiiii_case_0: 3355 // 3356 // {arch: v6, 3357 // defs: {}, 3358 // pattern: 111111000100ssssttttiiiiiiiiiiii, 3359 // rule: MCRR2, 3360 // safety: [true => FORBIDDEN], 3361 // true: true, 3362 // uses: {}} 3363 class MCRR2_111111000100ssssttttiiiiiiiiiiii_case_0 3364 : public ClassDecoder { 3365 public: MCRR2_111111000100ssssttttiiiiiiiiiiii_case_0()3366 MCRR2_111111000100ssssttttiiiiiiiiiiii_case_0() 3367 : ClassDecoder() {} 3368 virtual RegisterList defs(Instruction inst) const; 3369 virtual SafetyLevel safety(Instruction i) const; 3370 virtual RegisterList uses(Instruction i) const; 3371 private: 3372 NACL_DISALLOW_COPY_AND_ASSIGN( 3373 MCRR2_111111000100ssssttttiiiiiiiiiiii_case_0); 3374 }; 3375 3376 // MCRR_cccc11000100ttttttttccccoooommmm_case_0: 3377 // 3378 // {arch: v5TE, 3379 // defs: {}, 3380 // pattern: cccc11000100ttttttttccccoooommmm, 3381 // rule: MCRR, 3382 // safety: [true => FORBIDDEN], 3383 // true: true, 3384 // uses: {}} 3385 class MCRR_cccc11000100ttttttttccccoooommmm_case_0 3386 : public ClassDecoder { 3387 public: MCRR_cccc11000100ttttttttccccoooommmm_case_0()3388 MCRR_cccc11000100ttttttttccccoooommmm_case_0() 3389 : ClassDecoder() {} 3390 virtual RegisterList defs(Instruction inst) const; 3391 virtual SafetyLevel safety(Instruction i) const; 3392 virtual RegisterList uses(Instruction i) const; 3393 private: 3394 NACL_DISALLOW_COPY_AND_ASSIGN( 3395 MCRR_cccc11000100ttttttttccccoooommmm_case_0); 3396 }; 3397 3398 // MCR_cccc1110ooo0nnnnttttccccooo1mmmm_case_0: 3399 // 3400 // {defs: {}, 3401 // diagnostics: [inst(31:0)=xxxx111000000111xxxx111110111010 => 3402 // error('Consider using DSB (defined in ARMv7) for memory barrier')], 3403 // inst: inst, 3404 // pattern: cccc1110ooo0nnnnttttccccooo1mmmm, 3405 // rule: MCR, 3406 // safety: [true => FORBIDDEN], 3407 // true: true, 3408 // uses: {}, 3409 // violations: [inst(31:0)=xxxx111000000111xxxx111110111010 => 3410 // error('Consider using DSB (defined in ARMv7) for memory barrier')]} 3411 class MCR_cccc1110ooo0nnnnttttccccooo1mmmm_case_0 3412 : public ClassDecoder { 3413 public: MCR_cccc1110ooo0nnnnttttccccooo1mmmm_case_0()3414 MCR_cccc1110ooo0nnnnttttccccooo1mmmm_case_0() 3415 : ClassDecoder() {} 3416 virtual RegisterList defs(Instruction inst) const; 3417 virtual void generate_diagnostics( 3418 ViolationSet violations, 3419 const nacl_arm_val::DecodedInstruction& first, 3420 const nacl_arm_val::DecodedInstruction& second, 3421 const nacl_arm_val::SfiValidator& sfi, 3422 nacl_arm_val::ProblemSink* out) const; 3423 virtual SafetyLevel safety(Instruction i) const; 3424 virtual RegisterList uses(Instruction i) const; 3425 virtual ViolationSet get_violations( 3426 const nacl_arm_val::DecodedInstruction& first, 3427 const nacl_arm_val::DecodedInstruction& second, 3428 const nacl_arm_val::SfiValidator& sfi, 3429 nacl_arm_val::AddressSet* branches, 3430 nacl_arm_val::AddressSet* critical, 3431 uint32_t* next_inst_addr) const; 3432 private: 3433 NACL_DISALLOW_COPY_AND_ASSIGN( 3434 MCR_cccc1110ooo0nnnnttttccccooo1mmmm_case_0); 3435 }; 3436 3437 // MLA_A1_cccc0000001sddddaaaammmm1001nnnn_case_0: 3438 // 3439 // {NZCV: 16, 3440 // None: 32, 3441 // Pc: 15, 3442 // Ra: Ra(15:12), 3443 // Rd: Rd(19:16), 3444 // Rm: Rm(11:8), 3445 // Rn: Rn(3:0), 3446 // S: S(20), 3447 // cond: cond(31:28), 3448 // defs: {Rd, NZCV 3449 // if setflags 3450 // else None}, 3451 // fields: [cond(31:28), 3452 // S(20), 3453 // Rd(19:16), 3454 // Ra(15:12), 3455 // Rm(11:8), 3456 // Rn(3:0)], 3457 // pattern: cccc0000001sddddaaaammmm1001nnnn, 3458 // rule: MLA_A1, 3459 // safety: [Pc in {Rd, Rn, Rm, Ra} => UNPREDICTABLE, 3460 // (ArchVersion() < 3461 // 6 && 3462 // Rd == 3463 // Rn) => UNPREDICTABLE], 3464 // setflags: S(20)=1, 3465 // uses: {Rn, Rm, Ra}} 3466 class MLA_A1_cccc0000001sddddaaaammmm1001nnnn_case_0 3467 : public ClassDecoder { 3468 public: MLA_A1_cccc0000001sddddaaaammmm1001nnnn_case_0()3469 MLA_A1_cccc0000001sddddaaaammmm1001nnnn_case_0() 3470 : ClassDecoder() {} 3471 virtual RegisterList defs(Instruction inst) const; 3472 virtual SafetyLevel safety(Instruction i) const; 3473 virtual RegisterList uses(Instruction i) const; 3474 private: 3475 NACL_DISALLOW_COPY_AND_ASSIGN( 3476 MLA_A1_cccc0000001sddddaaaammmm1001nnnn_case_0); 3477 }; 3478 3479 // MLS_A1_cccc00000110ddddaaaammmm1001nnnn_case_0: 3480 // 3481 // {Pc: 15, 3482 // Ra: Ra(15:12), 3483 // Rd: Rd(19:16), 3484 // Rm: Rm(11:8), 3485 // Rn: Rn(3:0), 3486 // arch: v6T2, 3487 // cond: cond(31:28), 3488 // defs: {Rd}, 3489 // fields: [cond(31:28), Rd(19:16), Ra(15:12), Rm(11:8), Rn(3:0)], 3490 // pattern: cccc00000110ddddaaaammmm1001nnnn, 3491 // rule: MLS_A1, 3492 // safety: [Pc in {Rd, Rn, Rm, Ra} => UNPREDICTABLE], 3493 // uses: {Rn, Rm, Ra}} 3494 class MLS_A1_cccc00000110ddddaaaammmm1001nnnn_case_0 3495 : public ClassDecoder { 3496 public: MLS_A1_cccc00000110ddddaaaammmm1001nnnn_case_0()3497 MLS_A1_cccc00000110ddddaaaammmm1001nnnn_case_0() 3498 : ClassDecoder() {} 3499 virtual RegisterList defs(Instruction inst) const; 3500 virtual SafetyLevel safety(Instruction i) const; 3501 virtual RegisterList uses(Instruction i) const; 3502 private: 3503 NACL_DISALLOW_COPY_AND_ASSIGN( 3504 MLS_A1_cccc00000110ddddaaaammmm1001nnnn_case_0); 3505 }; 3506 3507 // MOVE_scalar_to_ARM_core_register_cccc1110iii1nnnntttt1011nii10000_case_0: 3508 // 3509 // {N: N(7), 3510 // Pc: 15, 3511 // Rt: Rt(15:12), 3512 // U: U(23), 3513 // Vn: Vn(19:16), 3514 // advsimd: sel in bitset {'x1xxx', 'x0xx1'}, 3515 // arch: ['VFPv2', 'AdvSIMD'], 3516 // cond: cond(31:28), 3517 // defs: {Rt}, 3518 // esize: 8 3519 // if U:opc1:opc2(4:0)=x1xxx 3520 // else 16 3521 // if U:opc1:opc2(4:0)=x0xx1 3522 // else 32 3523 // if U:opc1:opc2(4:0)=00x00 3524 // else 0, 3525 // fields: [cond(31:28), 3526 // U(23), 3527 // opc1(22:21), 3528 // Vn(19:16), 3529 // Rt(15:12), 3530 // N(7), 3531 // opc2(6:5)], 3532 // index: opc1(0):opc2 3533 // if U:opc1:opc2(4:0)=x1xxx 3534 // else opc1(0):opc2(1) 3535 // if U:opc1:opc2(4:0)=x0xx1 3536 // else opc1(0) 3537 // if U:opc1:opc2(4:0)=00x00 3538 // else 0, 3539 // n: N:Vn, 3540 // opc1: opc1(22:21), 3541 // opc2: opc2(6:5), 3542 // pattern: cccc1110iii1nnnntttt1011nii10000, 3543 // rule: MOVE_scalar_to_ARM_core_register, 3544 // safety: [sel in bitset {'10x00', 'x0x10'} => UNDEFINED, 3545 // t == 3546 // Pc => UNPREDICTABLE], 3547 // sel: U:opc1:opc2, 3548 // t: Rt, 3549 // unsigned: U(23)=1} 3550 class MOVE_scalar_to_ARM_core_register_cccc1110iii1nnnntttt1011nii10000_case_0 3551 : public ClassDecoder { 3552 public: MOVE_scalar_to_ARM_core_register_cccc1110iii1nnnntttt1011nii10000_case_0()3553 MOVE_scalar_to_ARM_core_register_cccc1110iii1nnnntttt1011nii10000_case_0() 3554 : ClassDecoder() {} 3555 virtual RegisterList defs(Instruction inst) const; 3556 virtual SafetyLevel safety(Instruction i) const; 3557 private: 3558 NACL_DISALLOW_COPY_AND_ASSIGN( 3559 MOVE_scalar_to_ARM_core_register_cccc1110iii1nnnntttt1011nii10000_case_0); 3560 }; 3561 3562 // MOVT_cccc00110100iiiiddddiiiiiiiiiiii_case_0: 3563 // 3564 // {NZCV: 16, 3565 // None: 32, 3566 // Rd: Rd(15:12), 3567 // S: S(20), 3568 // arch: v6T2, 3569 // cond: cond(31:28), 3570 // defs: {Rd, NZCV 3571 // if S 3572 // else None}, 3573 // dynamic_code_replace_immediates: {imm4, imm12}, 3574 // fields: [cond(31:28), S(20), imm4(19:16), Rd(15:12), imm12(11:0)], 3575 // imm: imm4:imm12, 3576 // imm12: imm12(11:0), 3577 // imm4: imm4(19:16), 3578 // pattern: cccc00110100iiiiddddiiiiiiiiiiii, 3579 // rule: MOVT, 3580 // safety: [Rd(15:12)=1111 => UNPREDICTABLE], 3581 // uses: {}} 3582 class MOVT_cccc00110100iiiiddddiiiiiiiiiiii_case_0 3583 : public ClassDecoder { 3584 public: MOVT_cccc00110100iiiiddddiiiiiiiiiiii_case_0()3585 MOVT_cccc00110100iiiiddddiiiiiiiiiiii_case_0() 3586 : ClassDecoder() {} 3587 virtual RegisterList defs(Instruction inst) const; 3588 virtual Instruction dynamic_code_replacement_sentinel(Instruction i) const; 3589 virtual SafetyLevel safety(Instruction i) const; 3590 virtual RegisterList uses(Instruction i) const; 3591 private: 3592 NACL_DISALLOW_COPY_AND_ASSIGN( 3593 MOVT_cccc00110100iiiiddddiiiiiiiiiiii_case_0); 3594 }; 3595 3596 // MOVW_cccc00110000iiiiddddiiiiiiiiiiii_case_0: 3597 // 3598 // {NZCV: 16, 3599 // None: 32, 3600 // Rd: Rd(15:12), 3601 // S: S(20), 3602 // arch: v6T2, 3603 // cond: cond(31:28), 3604 // defs: {Rd, NZCV 3605 // if S 3606 // else None}, 3607 // dynamic_code_replace_immediates: {imm4, imm12}, 3608 // fields: [cond(31:28), S(20), imm4(19:16), Rd(15:12), imm12(11:0)], 3609 // imm: imm4:imm12, 3610 // imm12: imm12(11:0), 3611 // imm4: imm4(19:16), 3612 // pattern: cccc00110000iiiiddddiiiiiiiiiiii, 3613 // rule: MOVW, 3614 // safety: [Rd(15:12)=1111 => UNPREDICTABLE], 3615 // uses: {}} 3616 class MOVW_cccc00110000iiiiddddiiiiiiiiiiii_case_0 3617 : public ClassDecoder { 3618 public: MOVW_cccc00110000iiiiddddiiiiiiiiiiii_case_0()3619 MOVW_cccc00110000iiiiddddiiiiiiiiiiii_case_0() 3620 : ClassDecoder() {} 3621 virtual RegisterList defs(Instruction inst) const; 3622 virtual Instruction dynamic_code_replacement_sentinel(Instruction i) const; 3623 virtual SafetyLevel safety(Instruction i) const; 3624 virtual RegisterList uses(Instruction i) const; 3625 private: 3626 NACL_DISALLOW_COPY_AND_ASSIGN( 3627 MOVW_cccc00110000iiiiddddiiiiiiiiiiii_case_0); 3628 }; 3629 3630 // MOV_immediate_A1_cccc0011101s0000ddddiiiiiiiiiiii_case_0: 3631 // 3632 // {NZCV: 16, 3633 // None: 32, 3634 // Rd: Rd(15:12), 3635 // S: S(20), 3636 // cond: cond(31:28), 3637 // defs: {Rd, NZCV 3638 // if setflags 3639 // else None}, 3640 // dynamic_code_replace_immediates: {imm12}, 3641 // fields: [cond(31:28), S(20), Rd(15:12), imm12(11:0)], 3642 // imm12: imm12(11:0), 3643 // imm32: ARMExpandImm(imm12), 3644 // pattern: cccc0011101s0000ddddiiiiiiiiiiii, 3645 // rule: MOV_immediate_A1, 3646 // safety: [(Rd(15:12)=1111 && 3647 // S(20)=1) => DECODER_ERROR, 3648 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 3649 // setflags: S(20)=1, 3650 // uses: {}} 3651 class MOV_immediate_A1_cccc0011101s0000ddddiiiiiiiiiiii_case_0 3652 : public ClassDecoder { 3653 public: MOV_immediate_A1_cccc0011101s0000ddddiiiiiiiiiiii_case_0()3654 MOV_immediate_A1_cccc0011101s0000ddddiiiiiiiiiiii_case_0() 3655 : ClassDecoder() {} 3656 virtual RegisterList defs(Instruction inst) const; 3657 virtual Instruction dynamic_code_replacement_sentinel(Instruction i) const; 3658 virtual SafetyLevel safety(Instruction i) const; 3659 virtual RegisterList uses(Instruction i) const; 3660 private: 3661 NACL_DISALLOW_COPY_AND_ASSIGN( 3662 MOV_immediate_A1_cccc0011101s0000ddddiiiiiiiiiiii_case_0); 3663 }; 3664 3665 // MOV_register_cccc0001101s0000dddd00000000mmmm_case_0: 3666 // 3667 // {NZCV: 16, 3668 // None: 32, 3669 // Rd: Rd(15:12), 3670 // Rm: Rm(3:0), 3671 // S: S(20), 3672 // cond: cond(31:28), 3673 // defs: {Rd, NZCV 3674 // if S 3675 // else None}, 3676 // fields: [cond(31:28), S(20), Rd(15:12), Rm(3:0)], 3677 // pattern: cccc0001101s0000dddd00000000mmmm, 3678 // rule: MOV_register, 3679 // safety: [(Rd(15:12)=1111 && 3680 // S(20)=1) => DECODER_ERROR, 3681 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 3682 // uses: {Rm}} 3683 class MOV_register_cccc0001101s0000dddd00000000mmmm_case_0 3684 : public ClassDecoder { 3685 public: MOV_register_cccc0001101s0000dddd00000000mmmm_case_0()3686 MOV_register_cccc0001101s0000dddd00000000mmmm_case_0() 3687 : ClassDecoder() {} 3688 virtual RegisterList defs(Instruction inst) const; 3689 virtual SafetyLevel safety(Instruction i) const; 3690 virtual RegisterList uses(Instruction i) const; 3691 private: 3692 NACL_DISALLOW_COPY_AND_ASSIGN( 3693 MOV_register_cccc0001101s0000dddd00000000mmmm_case_0); 3694 }; 3695 3696 // MRC2_11111110iii1iiiittttiiiiiii1iiii_case_0: 3697 // 3698 // {arch: v5, 3699 // defs: {}, 3700 // pattern: 11111110iii1iiiittttiiiiiii1iiii, 3701 // rule: MRC2, 3702 // safety: [true => FORBIDDEN], 3703 // true: true, 3704 // uses: {}} 3705 class MRC2_11111110iii1iiiittttiiiiiii1iiii_case_0 3706 : public ClassDecoder { 3707 public: MRC2_11111110iii1iiiittttiiiiiii1iiii_case_0()3708 MRC2_11111110iii1iiiittttiiiiiii1iiii_case_0() 3709 : ClassDecoder() {} 3710 virtual RegisterList defs(Instruction inst) const; 3711 virtual SafetyLevel safety(Instruction i) const; 3712 virtual RegisterList uses(Instruction i) const; 3713 private: 3714 NACL_DISALLOW_COPY_AND_ASSIGN( 3715 MRC2_11111110iii1iiiittttiiiiiii1iiii_case_0); 3716 }; 3717 3718 // MRC_cccc1110ooo1nnnnttttccccooo1mmmm_case_0: 3719 // 3720 // {defs: {}, 3721 // pattern: cccc1110ooo1nnnnttttccccooo1mmmm, 3722 // rule: MRC, 3723 // safety: [true => FORBIDDEN], 3724 // true: true, 3725 // uses: {}} 3726 class MRC_cccc1110ooo1nnnnttttccccooo1mmmm_case_0 3727 : public ClassDecoder { 3728 public: MRC_cccc1110ooo1nnnnttttccccooo1mmmm_case_0()3729 MRC_cccc1110ooo1nnnnttttccccooo1mmmm_case_0() 3730 : ClassDecoder() {} 3731 virtual RegisterList defs(Instruction inst) const; 3732 virtual SafetyLevel safety(Instruction i) const; 3733 virtual RegisterList uses(Instruction i) const; 3734 private: 3735 NACL_DISALLOW_COPY_AND_ASSIGN( 3736 MRC_cccc1110ooo1nnnnttttccccooo1mmmm_case_0); 3737 }; 3738 3739 // MRRC2_111111000101ssssttttiiiiiiiiiiii_case_0: 3740 // 3741 // {arch: v6, 3742 // defs: {}, 3743 // pattern: 111111000101ssssttttiiiiiiiiiiii, 3744 // rule: MRRC2, 3745 // safety: [true => FORBIDDEN], 3746 // true: true, 3747 // uses: {}} 3748 class MRRC2_111111000101ssssttttiiiiiiiiiiii_case_0 3749 : public ClassDecoder { 3750 public: MRRC2_111111000101ssssttttiiiiiiiiiiii_case_0()3751 MRRC2_111111000101ssssttttiiiiiiiiiiii_case_0() 3752 : ClassDecoder() {} 3753 virtual RegisterList defs(Instruction inst) const; 3754 virtual SafetyLevel safety(Instruction i) const; 3755 virtual RegisterList uses(Instruction i) const; 3756 private: 3757 NACL_DISALLOW_COPY_AND_ASSIGN( 3758 MRRC2_111111000101ssssttttiiiiiiiiiiii_case_0); 3759 }; 3760 3761 // MRRC_cccc11000101ttttttttccccoooommmm_case_0: 3762 // 3763 // {arch: v5TE, 3764 // defs: {}, 3765 // pattern: cccc11000101ttttttttccccoooommmm, 3766 // rule: MRRC, 3767 // safety: [true => FORBIDDEN], 3768 // true: true, 3769 // uses: {}} 3770 class MRRC_cccc11000101ttttttttccccoooommmm_case_0 3771 : public ClassDecoder { 3772 public: MRRC_cccc11000101ttttttttccccoooommmm_case_0()3773 MRRC_cccc11000101ttttttttccccoooommmm_case_0() 3774 : ClassDecoder() {} 3775 virtual RegisterList defs(Instruction inst) const; 3776 virtual SafetyLevel safety(Instruction i) const; 3777 virtual RegisterList uses(Instruction i) const; 3778 private: 3779 NACL_DISALLOW_COPY_AND_ASSIGN( 3780 MRRC_cccc11000101ttttttttccccoooommmm_case_0); 3781 }; 3782 3783 // MRS_Banked_register_cccc00010r00mmmmdddd001m00000000_case_0: 3784 // 3785 // {arch: v7VE, 3786 // defs: {}, 3787 // pattern: cccc00010r00mmmmdddd001m00000000, 3788 // rule: MRS_Banked_register, 3789 // safety: [true => FORBIDDEN], 3790 // true: true, 3791 // uses: {}} 3792 class MRS_Banked_register_cccc00010r00mmmmdddd001m00000000_case_0 3793 : public ClassDecoder { 3794 public: MRS_Banked_register_cccc00010r00mmmmdddd001m00000000_case_0()3795 MRS_Banked_register_cccc00010r00mmmmdddd001m00000000_case_0() 3796 : ClassDecoder() {} 3797 virtual RegisterList defs(Instruction inst) const; 3798 virtual SafetyLevel safety(Instruction i) const; 3799 virtual RegisterList uses(Instruction i) const; 3800 private: 3801 NACL_DISALLOW_COPY_AND_ASSIGN( 3802 MRS_Banked_register_cccc00010r00mmmmdddd001m00000000_case_0); 3803 }; 3804 3805 // MRS_Banked_register_cccc00010r10mmmm1111001m0000nnnn_case_0: 3806 // 3807 // {arch: v7VE, 3808 // defs: {}, 3809 // pattern: cccc00010r10mmmm1111001m0000nnnn, 3810 // rule: MRS_Banked_register, 3811 // safety: [true => FORBIDDEN], 3812 // true: true, 3813 // uses: {}} 3814 class MRS_Banked_register_cccc00010r10mmmm1111001m0000nnnn_case_0 3815 : public ClassDecoder { 3816 public: MRS_Banked_register_cccc00010r10mmmm1111001m0000nnnn_case_0()3817 MRS_Banked_register_cccc00010r10mmmm1111001m0000nnnn_case_0() 3818 : ClassDecoder() {} 3819 virtual RegisterList defs(Instruction inst) const; 3820 virtual SafetyLevel safety(Instruction i) const; 3821 virtual RegisterList uses(Instruction i) const; 3822 private: 3823 NACL_DISALLOW_COPY_AND_ASSIGN( 3824 MRS_Banked_register_cccc00010r10mmmm1111001m0000nnnn_case_0); 3825 }; 3826 3827 // MRS_cccc00010r001111dddd000000000000_case_0: 3828 // 3829 // {R: R(22), 3830 // Rd: Rd(15:12), 3831 // cond: cond(31:28), 3832 // defs: {Rd}, 3833 // fields: [cond(31:28), R(22), Rd(15:12)], 3834 // pattern: cccc00010r001111dddd000000000000, 3835 // read_spsr: R(22)=1, 3836 // rule: MRS, 3837 // safety: [R(22)=1 => FORBIDDEN_OPERANDS, 3838 // Rd(15:12)=1111 => UNPREDICTABLE], 3839 // uses: {}} 3840 class MRS_cccc00010r001111dddd000000000000_case_0 3841 : public ClassDecoder { 3842 public: MRS_cccc00010r001111dddd000000000000_case_0()3843 MRS_cccc00010r001111dddd000000000000_case_0() 3844 : ClassDecoder() {} 3845 virtual RegisterList defs(Instruction inst) const; 3846 virtual SafetyLevel safety(Instruction i) const; 3847 virtual RegisterList uses(Instruction i) const; 3848 private: 3849 NACL_DISALLOW_COPY_AND_ASSIGN( 3850 MRS_cccc00010r001111dddd000000000000_case_0); 3851 }; 3852 3853 // MSR_immediate_cccc00110010mm001111iiiiiiiiiiii_case_0: 3854 // 3855 // {NZCV: 16, 3856 // None: 32, 3857 // cond: cond(31:28), 3858 // defs: {NZCV 3859 // if write_nzcvq 3860 // else None}, 3861 // fields: [cond(31:28), mask(19:18), imm12(11:0)], 3862 // imm12: imm12(11:0), 3863 // imm32: ARMExpandImm(imm12), 3864 // mask: mask(19:18), 3865 // pattern: cccc00110010mm001111iiiiiiiiiiii, 3866 // rule: MSR_immediate, 3867 // safety: [mask(19:18)=00 => DECODER_ERROR], 3868 // uses: {}, 3869 // write_g: mask(0)=1, 3870 // write_nzcvq: mask(1)=1} 3871 class MSR_immediate_cccc00110010mm001111iiiiiiiiiiii_case_0 3872 : public ClassDecoder { 3873 public: MSR_immediate_cccc00110010mm001111iiiiiiiiiiii_case_0()3874 MSR_immediate_cccc00110010mm001111iiiiiiiiiiii_case_0() 3875 : ClassDecoder() {} 3876 virtual RegisterList defs(Instruction inst) const; 3877 virtual SafetyLevel safety(Instruction i) const; 3878 virtual RegisterList uses(Instruction i) const; 3879 private: 3880 NACL_DISALLOW_COPY_AND_ASSIGN( 3881 MSR_immediate_cccc00110010mm001111iiiiiiiiiiii_case_0); 3882 }; 3883 3884 // MSR_immediate_cccc00110r10mmmm1111iiiiiiiiiiii_case_0: 3885 // 3886 // {defs: {}, 3887 // pattern: cccc00110r10mmmm1111iiiiiiiiiiii, 3888 // rule: MSR_immediate, 3889 // safety: [true => FORBIDDEN], 3890 // true: true, 3891 // uses: {}} 3892 class MSR_immediate_cccc00110r10mmmm1111iiiiiiiiiiii_case_0 3893 : public ClassDecoder { 3894 public: MSR_immediate_cccc00110r10mmmm1111iiiiiiiiiiii_case_0()3895 MSR_immediate_cccc00110r10mmmm1111iiiiiiiiiiii_case_0() 3896 : ClassDecoder() {} 3897 virtual RegisterList defs(Instruction inst) const; 3898 virtual SafetyLevel safety(Instruction i) const; 3899 virtual RegisterList uses(Instruction i) const; 3900 private: 3901 NACL_DISALLOW_COPY_AND_ASSIGN( 3902 MSR_immediate_cccc00110r10mmmm1111iiiiiiiiiiii_case_0); 3903 }; 3904 3905 // MSR_register_cccc00010010mm00111100000000nnnn_case_0: 3906 // 3907 // {NZCV: 16, 3908 // None: 32, 3909 // Pc: 15, 3910 // Rn: Rn(3:0), 3911 // cond: cond(31:28), 3912 // defs: {NZCV 3913 // if write_nzcvq 3914 // else None}, 3915 // fields: [cond(31:28), mask(19:18), Rn(3:0)], 3916 // mask: mask(19:18), 3917 // pattern: cccc00010010mm00111100000000nnnn, 3918 // rule: MSR_register, 3919 // safety: [mask(19:18)=00 => UNPREDICTABLE, 3920 // Rn == 3921 // Pc => UNPREDICTABLE], 3922 // uses: {Rn}, 3923 // write_g: mask(0)=1, 3924 // write_nzcvq: mask(1)=1} 3925 class MSR_register_cccc00010010mm00111100000000nnnn_case_0 3926 : public ClassDecoder { 3927 public: MSR_register_cccc00010010mm00111100000000nnnn_case_0()3928 MSR_register_cccc00010010mm00111100000000nnnn_case_0() 3929 : ClassDecoder() {} 3930 virtual RegisterList defs(Instruction inst) const; 3931 virtual SafetyLevel safety(Instruction i) const; 3932 virtual RegisterList uses(Instruction i) const; 3933 private: 3934 NACL_DISALLOW_COPY_AND_ASSIGN( 3935 MSR_register_cccc00010010mm00111100000000nnnn_case_0); 3936 }; 3937 3938 // MSR_register_cccc00010r10mmmm111100000000nnnn_case_0: 3939 // 3940 // {defs: {}, 3941 // pattern: cccc00010r10mmmm111100000000nnnn, 3942 // rule: MSR_register, 3943 // safety: [true => FORBIDDEN], 3944 // true: true, 3945 // uses: {}} 3946 class MSR_register_cccc00010r10mmmm111100000000nnnn_case_0 3947 : public ClassDecoder { 3948 public: MSR_register_cccc00010r10mmmm111100000000nnnn_case_0()3949 MSR_register_cccc00010r10mmmm111100000000nnnn_case_0() 3950 : ClassDecoder() {} 3951 virtual RegisterList defs(Instruction inst) const; 3952 virtual SafetyLevel safety(Instruction i) const; 3953 virtual RegisterList uses(Instruction i) const; 3954 private: 3955 NACL_DISALLOW_COPY_AND_ASSIGN( 3956 MSR_register_cccc00010r10mmmm111100000000nnnn_case_0); 3957 }; 3958 3959 // MUL_A1_cccc0000000sdddd0000mmmm1001nnnn_case_0: 3960 // 3961 // {NZCV: 16, 3962 // None: 32, 3963 // Pc: 15, 3964 // Rd: Rd(19:16), 3965 // Rm: Rm(11:8), 3966 // Rn: Rn(3:0), 3967 // S: S(20), 3968 // cond: cond(31:28), 3969 // defs: {Rd, NZCV 3970 // if setflags 3971 // else None}, 3972 // fields: [cond(31:28), S(20), Rd(19:16), Rm(11:8), Rn(3:0)], 3973 // pattern: cccc0000000sdddd0000mmmm1001nnnn, 3974 // rule: MUL_A1, 3975 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE, 3976 // (ArchVersion() < 3977 // 6 && 3978 // Rd == 3979 // Rn) => UNPREDICTABLE], 3980 // setflags: S(20)=1, 3981 // uses: {Rm, Rn}} 3982 class MUL_A1_cccc0000000sdddd0000mmmm1001nnnn_case_0 3983 : public ClassDecoder { 3984 public: MUL_A1_cccc0000000sdddd0000mmmm1001nnnn_case_0()3985 MUL_A1_cccc0000000sdddd0000mmmm1001nnnn_case_0() 3986 : ClassDecoder() {} 3987 virtual RegisterList defs(Instruction inst) const; 3988 virtual SafetyLevel safety(Instruction i) const; 3989 virtual RegisterList uses(Instruction i) const; 3990 private: 3991 NACL_DISALLOW_COPY_AND_ASSIGN( 3992 MUL_A1_cccc0000000sdddd0000mmmm1001nnnn_case_0); 3993 }; 3994 3995 // MVN_immediate_cccc0011111s0000ddddiiiiiiiiiiii_case_0: 3996 // 3997 // {NZCV: 16, 3998 // None: 32, 3999 // Rd: Rd(15:12), 4000 // S: S(20), 4001 // cond: cond(31:28), 4002 // defs: {Rd, NZCV 4003 // if setflags 4004 // else None}, 4005 // dynamic_code_replace_immediates: {imm12}, 4006 // fields: [cond(31:28), S(20), Rd(15:12), imm12(11:0)], 4007 // imm12: imm12(11:0), 4008 // imm32: ARMExpandImm(imm12), 4009 // pattern: cccc0011111s0000ddddiiiiiiiiiiii, 4010 // rule: MVN_immediate, 4011 // safety: [(Rd(15:12)=1111 && 4012 // S(20)=1) => DECODER_ERROR, 4013 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 4014 // setflags: S(20)=1, 4015 // uses: {}} 4016 class MVN_immediate_cccc0011111s0000ddddiiiiiiiiiiii_case_0 4017 : public ClassDecoder { 4018 public: MVN_immediate_cccc0011111s0000ddddiiiiiiiiiiii_case_0()4019 MVN_immediate_cccc0011111s0000ddddiiiiiiiiiiii_case_0() 4020 : ClassDecoder() {} 4021 virtual RegisterList defs(Instruction inst) const; 4022 virtual Instruction dynamic_code_replacement_sentinel(Instruction i) const; 4023 virtual SafetyLevel safety(Instruction i) const; 4024 virtual RegisterList uses(Instruction i) const; 4025 private: 4026 NACL_DISALLOW_COPY_AND_ASSIGN( 4027 MVN_immediate_cccc0011111s0000ddddiiiiiiiiiiii_case_0); 4028 }; 4029 4030 // MVN_register_cccc0001111s0000ddddiiiiitt0mmmm_case_0: 4031 // 4032 // {NZCV: 16, 4033 // None: 32, 4034 // Rd: Rd(15:12), 4035 // Rm: Rm(3:0), 4036 // S: S(20), 4037 // cond: cond(31:28), 4038 // defs: {Rd, NZCV 4039 // if S 4040 // else None}, 4041 // fields: [cond(31:28), 4042 // S(20), 4043 // Rd(15:12), 4044 // imm5(11:7), 4045 // type(6:5), 4046 // Rm(3:0)], 4047 // imm5: imm5(11:7), 4048 // pattern: cccc0001111s0000ddddiiiiitt0mmmm, 4049 // rule: MVN_register, 4050 // safety: [(Rd(15:12)=1111 && 4051 // S(20)=1) => DECODER_ERROR, 4052 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 4053 // shift: DecodeImmShift(type, imm5), 4054 // type: type(6:5), 4055 // uses: {Rm}} 4056 class MVN_register_cccc0001111s0000ddddiiiiitt0mmmm_case_0 4057 : public ClassDecoder { 4058 public: MVN_register_cccc0001111s0000ddddiiiiitt0mmmm_case_0()4059 MVN_register_cccc0001111s0000ddddiiiiitt0mmmm_case_0() 4060 : ClassDecoder() {} 4061 virtual RegisterList defs(Instruction inst) const; 4062 virtual SafetyLevel safety(Instruction i) const; 4063 virtual RegisterList uses(Instruction i) const; 4064 private: 4065 NACL_DISALLOW_COPY_AND_ASSIGN( 4066 MVN_register_cccc0001111s0000ddddiiiiitt0mmmm_case_0); 4067 }; 4068 4069 // MVN_register_shifted_register_cccc0001111s0000ddddssss0tt1mmmm_case_0: 4070 // 4071 // {NZCV: 16, 4072 // None: 32, 4073 // Pc: 15, 4074 // Rd: Rd(15:12), 4075 // Rm: Rm(3:0), 4076 // Rs: Rs(11:8), 4077 // S: S(20), 4078 // cond: cond(31:28), 4079 // defs: {Rd, NZCV 4080 // if setflags 4081 // else None}, 4082 // fields: [cond(31:28), 4083 // S(20), 4084 // Rd(15:12), 4085 // Rs(11:8), 4086 // type(6:5), 4087 // Rm(3:0)], 4088 // pattern: cccc0001111s0000ddddssss0tt1mmmm, 4089 // rule: MVN_register_shifted_register, 4090 // safety: [Pc in {Rd, Rm, Rs} => UNPREDICTABLE], 4091 // setflags: S(20)=1, 4092 // shift_t: DecodeRegShift(type), 4093 // type: type(6:5), 4094 // uses: {Rm, Rs}} 4095 class MVN_register_shifted_register_cccc0001111s0000ddddssss0tt1mmmm_case_0 4096 : public ClassDecoder { 4097 public: MVN_register_shifted_register_cccc0001111s0000ddddssss0tt1mmmm_case_0()4098 MVN_register_shifted_register_cccc0001111s0000ddddssss0tt1mmmm_case_0() 4099 : ClassDecoder() {} 4100 virtual RegisterList defs(Instruction inst) const; 4101 virtual SafetyLevel safety(Instruction i) const; 4102 virtual RegisterList uses(Instruction i) const; 4103 private: 4104 NACL_DISALLOW_COPY_AND_ASSIGN( 4105 MVN_register_shifted_register_cccc0001111s0000ddddssss0tt1mmmm_case_0); 4106 }; 4107 4108 // NOP_cccc0011001000001111000000000000_case_0: 4109 // 4110 // {arch: ['v6K', 'v6T2'], 4111 // defs: {}, 4112 // pattern: cccc0011001000001111000000000000, 4113 // rule: NOP, 4114 // uses: {}} 4115 class NOP_cccc0011001000001111000000000000_case_0 4116 : public ClassDecoder { 4117 public: NOP_cccc0011001000001111000000000000_case_0()4118 NOP_cccc0011001000001111000000000000_case_0() 4119 : ClassDecoder() {} 4120 virtual RegisterList defs(Instruction inst) const; 4121 virtual SafetyLevel safety(Instruction i) const; 4122 virtual RegisterList uses(Instruction i) const; 4123 private: 4124 NACL_DISALLOW_COPY_AND_ASSIGN( 4125 NOP_cccc0011001000001111000000000000_case_0); 4126 }; 4127 4128 // NOT_IMPLEMENTED_case_0: 4129 // 4130 // {defs: {}, 4131 // rule: NOT_IMPLEMENTED, 4132 // safety: [true => NOT_IMPLEMENTED], 4133 // true: true, 4134 // uses: {}} 4135 class NOT_IMPLEMENTED_case_0 4136 : public ClassDecoder { 4137 public: NOT_IMPLEMENTED_case_0()4138 NOT_IMPLEMENTED_case_0() 4139 : ClassDecoder() {} 4140 virtual RegisterList defs(Instruction inst) const; 4141 virtual SafetyLevel safety(Instruction i) const; 4142 virtual RegisterList uses(Instruction i) const; 4143 private: 4144 NACL_DISALLOW_COPY_AND_ASSIGN( 4145 NOT_IMPLEMENTED_case_0); 4146 }; 4147 4148 // ORR_immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_0: 4149 // 4150 // {NZCV: 16, 4151 // None: 32, 4152 // Rd: Rd(15:12), 4153 // Rn: Rn(19:16), 4154 // S: S(20), 4155 // cond: cond(31:28), 4156 // defs: {Rd, NZCV 4157 // if setflags 4158 // else None}, 4159 // dynamic_code_replace_immediates: {imm12}, 4160 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)], 4161 // imm12: imm12(11:0), 4162 // imm32: ARMExpandImm(imm12), 4163 // pattern: cccc0011100snnnnddddiiiiiiiiiiii, 4164 // rule: ORR_immediate, 4165 // safety: [(Rd(15:12)=1111 && 4166 // S(20)=1) => DECODER_ERROR, 4167 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 4168 // setflags: S(20)=1, 4169 // uses: {Rn}} 4170 class ORR_immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_0 4171 : public ClassDecoder { 4172 public: ORR_immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_0()4173 ORR_immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_0() 4174 : ClassDecoder() {} 4175 virtual RegisterList defs(Instruction inst) const; 4176 virtual Instruction dynamic_code_replacement_sentinel(Instruction i) const; 4177 virtual SafetyLevel safety(Instruction i) const; 4178 virtual RegisterList uses(Instruction i) const; 4179 private: 4180 NACL_DISALLOW_COPY_AND_ASSIGN( 4181 ORR_immediate_cccc0011100snnnnddddiiiiiiiiiiii_case_0); 4182 }; 4183 4184 // ORR_register_cccc0001100snnnnddddiiiiitt0mmmm_case_0: 4185 // 4186 // {NZCV: 16, 4187 // None: 32, 4188 // Rd: Rd(15:12), 4189 // Rm: Rm(3:0), 4190 // Rn: Rn(19:16), 4191 // S: S(20), 4192 // cond: cond(31:28), 4193 // defs: {Rd, NZCV 4194 // if S 4195 // else None}, 4196 // fields: [cond(31:28), 4197 // S(20), 4198 // Rn(19:16), 4199 // Rd(15:12), 4200 // imm5(11:7), 4201 // type(6:5), 4202 // Rm(3:0)], 4203 // imm5: imm5(11:7), 4204 // pattern: cccc0001100snnnnddddiiiiitt0mmmm, 4205 // rule: ORR_register, 4206 // safety: [(Rd(15:12)=1111 && 4207 // S(20)=1) => DECODER_ERROR, 4208 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 4209 // shift: DecodeImmShift(type, imm5), 4210 // type: type(6:5), 4211 // uses: {Rn, Rm}} 4212 class ORR_register_cccc0001100snnnnddddiiiiitt0mmmm_case_0 4213 : public ClassDecoder { 4214 public: ORR_register_cccc0001100snnnnddddiiiiitt0mmmm_case_0()4215 ORR_register_cccc0001100snnnnddddiiiiitt0mmmm_case_0() 4216 : ClassDecoder() {} 4217 virtual RegisterList defs(Instruction inst) const; 4218 virtual SafetyLevel safety(Instruction i) const; 4219 virtual RegisterList uses(Instruction i) const; 4220 private: 4221 NACL_DISALLOW_COPY_AND_ASSIGN( 4222 ORR_register_cccc0001100snnnnddddiiiiitt0mmmm_case_0); 4223 }; 4224 4225 // ORR_register_shifted_register_cccc0001100snnnnddddssss0tt1mmmm_case_0: 4226 // 4227 // {NZCV: 16, 4228 // None: 32, 4229 // Pc: 15, 4230 // Rd: Rd(15:12), 4231 // Rm: Rm(3:0), 4232 // Rn: Rn(19:16), 4233 // Rs: Rs(11:8), 4234 // S: S(20), 4235 // cond: cond(31:28), 4236 // defs: {Rd, NZCV 4237 // if setflags 4238 // else None}, 4239 // fields: [cond(31:28), 4240 // S(20), 4241 // Rn(19:16), 4242 // Rd(15:12), 4243 // Rs(11:8), 4244 // type(6:5), 4245 // Rm(3:0)], 4246 // pattern: cccc0001100snnnnddddssss0tt1mmmm, 4247 // rule: ORR_register_shifted_register, 4248 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE], 4249 // setflags: S(20)=1, 4250 // shift_t: DecodeRegShift(type), 4251 // type: type(6:5), 4252 // uses: {Rn, Rm, Rs}} 4253 class ORR_register_shifted_register_cccc0001100snnnnddddssss0tt1mmmm_case_0 4254 : public ClassDecoder { 4255 public: ORR_register_shifted_register_cccc0001100snnnnddddssss0tt1mmmm_case_0()4256 ORR_register_shifted_register_cccc0001100snnnnddddssss0tt1mmmm_case_0() 4257 : ClassDecoder() {} 4258 virtual RegisterList defs(Instruction inst) const; 4259 virtual SafetyLevel safety(Instruction i) const; 4260 virtual RegisterList uses(Instruction i) const; 4261 private: 4262 NACL_DISALLOW_COPY_AND_ASSIGN( 4263 ORR_register_shifted_register_cccc0001100snnnnddddssss0tt1mmmm_case_0); 4264 }; 4265 4266 // PKH_cccc01101000nnnnddddiiiiit01mmmm_case_0: 4267 // 4268 // {Pc: 15, 4269 // Rd: Rd(15:12), 4270 // Rm: Rm(3:0), 4271 // Rn: Rn(19:16), 4272 // arch: v6, 4273 // cond: cond(31:28), 4274 // defs: {Rd}, 4275 // fields: [cond(31:28), 4276 // Rn(19:16), 4277 // Rd(15:12), 4278 // imm5(11:7), 4279 // tb(6), 4280 // Rm(3:0)], 4281 // imm5: imm5(11:7), 4282 // pattern: cccc01101000nnnnddddiiiiit01mmmm, 4283 // rule: PKH, 4284 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 4285 // shift: DecodeImmShift(tb:'0'(0), imm5), 4286 // tb: tb(6), 4287 // tbform: tb(6)=1, 4288 // uses: {Rn, Rm}} 4289 class PKH_cccc01101000nnnnddddiiiiit01mmmm_case_0 4290 : public ClassDecoder { 4291 public: PKH_cccc01101000nnnnddddiiiiit01mmmm_case_0()4292 PKH_cccc01101000nnnnddddiiiiit01mmmm_case_0() 4293 : ClassDecoder() {} 4294 virtual RegisterList defs(Instruction inst) const; 4295 virtual SafetyLevel safety(Instruction i) const; 4296 virtual RegisterList uses(Instruction i) const; 4297 private: 4298 NACL_DISALLOW_COPY_AND_ASSIGN( 4299 PKH_cccc01101000nnnnddddiiiiit01mmmm_case_0); 4300 }; 4301 4302 // PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_0: 4303 // 4304 // {Pc: 15, 4305 // R: R(22), 4306 // Rn: Rn(19:16), 4307 // U: U(23), 4308 // add: U(23)=1, 4309 // arch: MPExt, 4310 // base: Rn, 4311 // defs: {}, 4312 // fields: [U(23), R(22), Rn(19:16), imm12(11:0)], 4313 // imm12: imm12(11:0), 4314 // imm32: ZeroExtend(imm12, 32), 4315 // is_literal_load: base == 4316 // Pc, 4317 // is_pldw: R(22)=0, 4318 // pattern: 11110101ur01nnnn1111iiiiiiiiiiii, 4319 // rule: PLD_PLDW_immediate, 4320 // safety: [Rn(19:16)=1111 => DECODER_ERROR], 4321 // true: true, 4322 // uses: {Rn}, 4323 // violations: [implied by 'base']} 4324 class PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_0 4325 : public ClassDecoder { 4326 public: PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_0()4327 PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_0() 4328 : ClassDecoder() {} 4329 virtual Register base_address_register(Instruction i) const; 4330 virtual RegisterList defs(Instruction inst) const; 4331 virtual bool is_literal_load(Instruction i) const; 4332 virtual SafetyLevel safety(Instruction i) const; 4333 virtual RegisterList uses(Instruction i) const; 4334 virtual ViolationSet get_violations( 4335 const nacl_arm_val::DecodedInstruction& first, 4336 const nacl_arm_val::DecodedInstruction& second, 4337 const nacl_arm_val::SfiValidator& sfi, 4338 nacl_arm_val::AddressSet* branches, 4339 nacl_arm_val::AddressSet* critical, 4340 uint32_t* next_inst_addr) const; 4341 private: 4342 NACL_DISALLOW_COPY_AND_ASSIGN( 4343 PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_0); 4344 }; 4345 4346 // PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_1: 4347 // 4348 // {Pc: 15, 4349 // R: R(22), 4350 // Rn: Rn(19:16), 4351 // U: U(23), 4352 // add: U(23)=1, 4353 // arch: v5TE, 4354 // base: Rn, 4355 // defs: {}, 4356 // fields: [U(23), R(22), Rn(19:16), imm12(11:0)], 4357 // imm12: imm12(11:0), 4358 // imm32: ZeroExtend(imm12, 32), 4359 // is_literal_load: base == 4360 // Pc, 4361 // is_pldw: R(22)=0, 4362 // pattern: 11110101ur01nnnn1111iiiiiiiiiiii, 4363 // rule: PLD_PLDW_immediate, 4364 // safety: [Rn(19:16)=1111 => DECODER_ERROR], 4365 // true: true, 4366 // uses: {Rn}, 4367 // violations: [implied by 'base']} 4368 class PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_1 4369 : public ClassDecoder { 4370 public: PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_1()4371 PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_1() 4372 : ClassDecoder() {} 4373 virtual Register base_address_register(Instruction i) const; 4374 virtual RegisterList defs(Instruction inst) const; 4375 virtual bool is_literal_load(Instruction i) const; 4376 virtual SafetyLevel safety(Instruction i) const; 4377 virtual RegisterList uses(Instruction i) const; 4378 virtual ViolationSet get_violations( 4379 const nacl_arm_val::DecodedInstruction& first, 4380 const nacl_arm_val::DecodedInstruction& second, 4381 const nacl_arm_val::SfiValidator& sfi, 4382 nacl_arm_val::AddressSet* branches, 4383 nacl_arm_val::AddressSet* critical, 4384 uint32_t* next_inst_addr) const; 4385 private: 4386 NACL_DISALLOW_COPY_AND_ASSIGN( 4387 PLD_PLDW_immediate_11110101ur01nnnn1111iiiiiiiiiiii_case_1); 4388 }; 4389 4390 // PLD_PLDW_register_11110111u001nnnn1111iiiiitt0mmmm_case_0: 4391 // 4392 // {Pc: 15, 4393 // R: R(22), 4394 // Rm: Rm(3:0), 4395 // Rn: Rn(19:16), 4396 // U: U(23), 4397 // add: U(23)=1, 4398 // arch: MPExt, 4399 // base: Rn, 4400 // defs: {}, 4401 // fields: [U(23), R(22), Rn(19:16), imm5(11:7), type(6:5), Rm(3:0)], 4402 // imm5: imm5(11:7), 4403 // is_pldw: R(22)=1, 4404 // pattern: 11110111u001nnnn1111iiiiitt0mmmm, 4405 // rule: PLD_PLDW_register, 4406 // safety: [Rm == 4407 // Pc || 4408 // (Rn == 4409 // Pc && 4410 // is_pldw) => UNPREDICTABLE, 4411 // true => FORBIDDEN_OPERANDS], 4412 // shift: DecodeImmShift(type, imm5), 4413 // true: true, 4414 // type: type(6:5), 4415 // uses: {Rm, Rn}, 4416 // violations: [implied by 'base']} 4417 class PLD_PLDW_register_11110111u001nnnn1111iiiiitt0mmmm_case_0 4418 : public ClassDecoder { 4419 public: PLD_PLDW_register_11110111u001nnnn1111iiiiitt0mmmm_case_0()4420 PLD_PLDW_register_11110111u001nnnn1111iiiiitt0mmmm_case_0() 4421 : ClassDecoder() {} 4422 virtual Register base_address_register(Instruction i) const; 4423 virtual RegisterList defs(Instruction inst) const; 4424 virtual SafetyLevel safety(Instruction i) const; 4425 virtual RegisterList uses(Instruction i) const; 4426 virtual ViolationSet get_violations( 4427 const nacl_arm_val::DecodedInstruction& first, 4428 const nacl_arm_val::DecodedInstruction& second, 4429 const nacl_arm_val::SfiValidator& sfi, 4430 nacl_arm_val::AddressSet* branches, 4431 nacl_arm_val::AddressSet* critical, 4432 uint32_t* next_inst_addr) const; 4433 private: 4434 NACL_DISALLOW_COPY_AND_ASSIGN( 4435 PLD_PLDW_register_11110111u001nnnn1111iiiiitt0mmmm_case_0); 4436 }; 4437 4438 // PLD_PLDW_register_11110111u101nnnn1111iiiiitt0mmmm_case_0: 4439 // 4440 // {Pc: 15, 4441 // R: R(22), 4442 // Rm: Rm(3:0), 4443 // Rn: Rn(19:16), 4444 // U: U(23), 4445 // add: U(23)=1, 4446 // arch: v5TE, 4447 // base: Rn, 4448 // defs: {}, 4449 // fields: [U(23), R(22), Rn(19:16), imm5(11:7), type(6:5), Rm(3:0)], 4450 // imm5: imm5(11:7), 4451 // is_pldw: R(22)=1, 4452 // pattern: 11110111u101nnnn1111iiiiitt0mmmm, 4453 // rule: PLD_PLDW_register, 4454 // safety: [Rm == 4455 // Pc || 4456 // (Rn == 4457 // Pc && 4458 // is_pldw) => UNPREDICTABLE, 4459 // true => FORBIDDEN_OPERANDS], 4460 // shift: DecodeImmShift(type, imm5), 4461 // true: true, 4462 // type: type(6:5), 4463 // uses: {Rm, Rn}, 4464 // violations: [implied by 'base']} 4465 class PLD_PLDW_register_11110111u101nnnn1111iiiiitt0mmmm_case_0 4466 : public ClassDecoder { 4467 public: PLD_PLDW_register_11110111u101nnnn1111iiiiitt0mmmm_case_0()4468 PLD_PLDW_register_11110111u101nnnn1111iiiiitt0mmmm_case_0() 4469 : ClassDecoder() {} 4470 virtual Register base_address_register(Instruction i) const; 4471 virtual RegisterList defs(Instruction inst) const; 4472 virtual SafetyLevel safety(Instruction i) const; 4473 virtual RegisterList uses(Instruction i) const; 4474 virtual ViolationSet get_violations( 4475 const nacl_arm_val::DecodedInstruction& first, 4476 const nacl_arm_val::DecodedInstruction& second, 4477 const nacl_arm_val::SfiValidator& sfi, 4478 nacl_arm_val::AddressSet* branches, 4479 nacl_arm_val::AddressSet* critical, 4480 uint32_t* next_inst_addr) const; 4481 private: 4482 NACL_DISALLOW_COPY_AND_ASSIGN( 4483 PLD_PLDW_register_11110111u101nnnn1111iiiiitt0mmmm_case_0); 4484 }; 4485 4486 // PLD_literal_11110101u10111111111iiiiiiiiiiii_case_0: 4487 // 4488 // {Pc: 15, 4489 // U: U(23), 4490 // add: U(23)=1, 4491 // arch: v5TE, 4492 // base: Pc, 4493 // defs: {}, 4494 // fields: [U(23), imm12(11:0)], 4495 // imm12: imm12(11:0), 4496 // imm32: ZeroExtend(imm12, 32), 4497 // is_literal_load: true, 4498 // pattern: 11110101u10111111111iiiiiiiiiiii, 4499 // rule: PLD_literal, 4500 // safety: [true => MAY_BE_SAFE], 4501 // true: true, 4502 // uses: {Pc}, 4503 // violations: [implied by 'base']} 4504 class PLD_literal_11110101u10111111111iiiiiiiiiiii_case_0 4505 : public ClassDecoder { 4506 public: PLD_literal_11110101u10111111111iiiiiiiiiiii_case_0()4507 PLD_literal_11110101u10111111111iiiiiiiiiiii_case_0() 4508 : ClassDecoder() {} 4509 virtual Register base_address_register(Instruction i) const; 4510 virtual RegisterList defs(Instruction inst) const; 4511 virtual bool is_literal_load(Instruction i) const; 4512 virtual SafetyLevel safety(Instruction i) const; 4513 virtual RegisterList uses(Instruction i) const; 4514 virtual ViolationSet get_violations( 4515 const nacl_arm_val::DecodedInstruction& first, 4516 const nacl_arm_val::DecodedInstruction& second, 4517 const nacl_arm_val::SfiValidator& sfi, 4518 nacl_arm_val::AddressSet* branches, 4519 nacl_arm_val::AddressSet* critical, 4520 uint32_t* next_inst_addr) const; 4521 private: 4522 NACL_DISALLOW_COPY_AND_ASSIGN( 4523 PLD_literal_11110101u10111111111iiiiiiiiiiii_case_0); 4524 }; 4525 4526 // PLI_immediate_literal_11110100u101nnnn1111iiiiiiiiiiii_case_0: 4527 // 4528 // {Pc: 15, 4529 // Rn: Rn(19:16), 4530 // U: U(23), 4531 // add: U(23)=1, 4532 // arch: v7, 4533 // base: Rn, 4534 // defs: {}, 4535 // fields: [U(23), Rn(19:16), imm12(11:0)], 4536 // imm12: imm12(11:0), 4537 // imm32: ZeroExtend(imm12, 32), 4538 // is_literal_load: Rn == 4539 // Pc, 4540 // pattern: 11110100u101nnnn1111iiiiiiiiiiii, 4541 // rule: PLI_immediate_literal, 4542 // safety: [true => MAY_BE_SAFE], 4543 // true: true, 4544 // uses: {Rn}, 4545 // violations: [implied by 'base']} 4546 class PLI_immediate_literal_11110100u101nnnn1111iiiiiiiiiiii_case_0 4547 : public ClassDecoder { 4548 public: PLI_immediate_literal_11110100u101nnnn1111iiiiiiiiiiii_case_0()4549 PLI_immediate_literal_11110100u101nnnn1111iiiiiiiiiiii_case_0() 4550 : ClassDecoder() {} 4551 virtual Register base_address_register(Instruction i) const; 4552 virtual RegisterList defs(Instruction inst) const; 4553 virtual bool is_literal_load(Instruction i) const; 4554 virtual SafetyLevel safety(Instruction i) const; 4555 virtual RegisterList uses(Instruction i) const; 4556 virtual ViolationSet get_violations( 4557 const nacl_arm_val::DecodedInstruction& first, 4558 const nacl_arm_val::DecodedInstruction& second, 4559 const nacl_arm_val::SfiValidator& sfi, 4560 nacl_arm_val::AddressSet* branches, 4561 nacl_arm_val::AddressSet* critical, 4562 uint32_t* next_inst_addr) const; 4563 private: 4564 NACL_DISALLOW_COPY_AND_ASSIGN( 4565 PLI_immediate_literal_11110100u101nnnn1111iiiiiiiiiiii_case_0); 4566 }; 4567 4568 // PLI_register_11110110u101nnnn1111iiiiitt0mmmm_case_0: 4569 // 4570 // {Pc: 15, 4571 // Rm: Rm(3:0), 4572 // Rn: Rn(19:16), 4573 // U: U(23), 4574 // add: U(23)=1, 4575 // arch: v7, 4576 // base: Rn, 4577 // defs: {}, 4578 // fields: [U(23), Rn(19:16), imm5(11:7), type(6:5), Rm(3:0)], 4579 // imm5: imm5(11:7), 4580 // pattern: 11110110u101nnnn1111iiiiitt0mmmm, 4581 // rule: PLI_register, 4582 // safety: [Rm == 4583 // Pc => UNPREDICTABLE, 4584 // true => FORBIDDEN_OPERANDS], 4585 // shift: DecodeImmShift(type, imm5), 4586 // true: true, 4587 // type: type(6:5), 4588 // uses: {Rm, Rn}, 4589 // violations: [implied by 'base']} 4590 class PLI_register_11110110u101nnnn1111iiiiitt0mmmm_case_0 4591 : public ClassDecoder { 4592 public: PLI_register_11110110u101nnnn1111iiiiitt0mmmm_case_0()4593 PLI_register_11110110u101nnnn1111iiiiitt0mmmm_case_0() 4594 : ClassDecoder() {} 4595 virtual Register base_address_register(Instruction i) const; 4596 virtual RegisterList defs(Instruction inst) const; 4597 virtual SafetyLevel safety(Instruction i) const; 4598 virtual RegisterList uses(Instruction i) const; 4599 virtual ViolationSet get_violations( 4600 const nacl_arm_val::DecodedInstruction& first, 4601 const nacl_arm_val::DecodedInstruction& second, 4602 const nacl_arm_val::SfiValidator& sfi, 4603 nacl_arm_val::AddressSet* branches, 4604 nacl_arm_val::AddressSet* critical, 4605 uint32_t* next_inst_addr) const; 4606 private: 4607 NACL_DISALLOW_COPY_AND_ASSIGN( 4608 PLI_register_11110110u101nnnn1111iiiiitt0mmmm_case_0); 4609 }; 4610 4611 // QADD16_cccc01100010nnnndddd11110001mmmm_case_0: 4612 // 4613 // {Pc: 15, 4614 // Rd: Rd(15:12), 4615 // Rm: Rm(3:0), 4616 // Rn: Rn(19:16), 4617 // arch: v6, 4618 // cond: cond(31:28), 4619 // defs: {Rd}, 4620 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 4621 // pattern: cccc01100010nnnndddd11110001mmmm, 4622 // rule: QADD16, 4623 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 4624 // uses: {Rn, Rm}} 4625 class QADD16_cccc01100010nnnndddd11110001mmmm_case_0 4626 : public ClassDecoder { 4627 public: QADD16_cccc01100010nnnndddd11110001mmmm_case_0()4628 QADD16_cccc01100010nnnndddd11110001mmmm_case_0() 4629 : ClassDecoder() {} 4630 virtual RegisterList defs(Instruction inst) const; 4631 virtual SafetyLevel safety(Instruction i) const; 4632 virtual RegisterList uses(Instruction i) const; 4633 private: 4634 NACL_DISALLOW_COPY_AND_ASSIGN( 4635 QADD16_cccc01100010nnnndddd11110001mmmm_case_0); 4636 }; 4637 4638 // QADD8_cccc01100010nnnndddd11111001mmmm_case_0: 4639 // 4640 // {Pc: 15, 4641 // Rd: Rd(15:12), 4642 // Rm: Rm(3:0), 4643 // Rn: Rn(19:16), 4644 // arch: v6, 4645 // cond: cond(31:28), 4646 // defs: {Rd}, 4647 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 4648 // pattern: cccc01100010nnnndddd11111001mmmm, 4649 // rule: QADD8, 4650 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 4651 // uses: {Rn, Rm}} 4652 class QADD8_cccc01100010nnnndddd11111001mmmm_case_0 4653 : public ClassDecoder { 4654 public: QADD8_cccc01100010nnnndddd11111001mmmm_case_0()4655 QADD8_cccc01100010nnnndddd11111001mmmm_case_0() 4656 : ClassDecoder() {} 4657 virtual RegisterList defs(Instruction inst) const; 4658 virtual SafetyLevel safety(Instruction i) const; 4659 virtual RegisterList uses(Instruction i) const; 4660 private: 4661 NACL_DISALLOW_COPY_AND_ASSIGN( 4662 QADD8_cccc01100010nnnndddd11111001mmmm_case_0); 4663 }; 4664 4665 // QADD_cccc00010000nnnndddd00000101mmmm_case_0: 4666 // 4667 // {Cond: Cond(31:28), 4668 // Pc: 15, 4669 // Rd: Rd(15:12), 4670 // Rm: Rm(3:0), 4671 // Rn: Rn(19:16), 4672 // arch: v5TE, 4673 // defs: {Rd}, 4674 // fields: [Cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 4675 // pattern: cccc00010000nnnndddd00000101mmmm, 4676 // rule: QADD, 4677 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 4678 // uses: {Rn, Rm}} 4679 class QADD_cccc00010000nnnndddd00000101mmmm_case_0 4680 : public ClassDecoder { 4681 public: QADD_cccc00010000nnnndddd00000101mmmm_case_0()4682 QADD_cccc00010000nnnndddd00000101mmmm_case_0() 4683 : ClassDecoder() {} 4684 virtual RegisterList defs(Instruction inst) const; 4685 virtual SafetyLevel safety(Instruction i) const; 4686 virtual RegisterList uses(Instruction i) const; 4687 private: 4688 NACL_DISALLOW_COPY_AND_ASSIGN( 4689 QADD_cccc00010000nnnndddd00000101mmmm_case_0); 4690 }; 4691 4692 // QASX_cccc01100010nnnndddd11110011mmmm_case_0: 4693 // 4694 // {Pc: 15, 4695 // Rd: Rd(15:12), 4696 // Rm: Rm(3:0), 4697 // Rn: Rn(19:16), 4698 // arch: v6, 4699 // cond: cond(31:28), 4700 // defs: {Rd}, 4701 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 4702 // pattern: cccc01100010nnnndddd11110011mmmm, 4703 // rule: QASX, 4704 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 4705 // uses: {Rn, Rm}} 4706 class QASX_cccc01100010nnnndddd11110011mmmm_case_0 4707 : public ClassDecoder { 4708 public: QASX_cccc01100010nnnndddd11110011mmmm_case_0()4709 QASX_cccc01100010nnnndddd11110011mmmm_case_0() 4710 : ClassDecoder() {} 4711 virtual RegisterList defs(Instruction inst) const; 4712 virtual SafetyLevel safety(Instruction i) const; 4713 virtual RegisterList uses(Instruction i) const; 4714 private: 4715 NACL_DISALLOW_COPY_AND_ASSIGN( 4716 QASX_cccc01100010nnnndddd11110011mmmm_case_0); 4717 }; 4718 4719 // QDADD_cccc00010100nnnndddd00000101mmmm_case_0: 4720 // 4721 // {Cond: Cond(31:28), 4722 // Pc: 15, 4723 // Rd: Rd(15:12), 4724 // Rm: Rm(3:0), 4725 // Rn: Rn(19:16), 4726 // arch: v5TE, 4727 // defs: {Rd}, 4728 // fields: [Cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 4729 // pattern: cccc00010100nnnndddd00000101mmmm, 4730 // rule: QDADD, 4731 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 4732 // uses: {Rn, Rm}} 4733 class QDADD_cccc00010100nnnndddd00000101mmmm_case_0 4734 : public ClassDecoder { 4735 public: QDADD_cccc00010100nnnndddd00000101mmmm_case_0()4736 QDADD_cccc00010100nnnndddd00000101mmmm_case_0() 4737 : ClassDecoder() {} 4738 virtual RegisterList defs(Instruction inst) const; 4739 virtual SafetyLevel safety(Instruction i) const; 4740 virtual RegisterList uses(Instruction i) const; 4741 private: 4742 NACL_DISALLOW_COPY_AND_ASSIGN( 4743 QDADD_cccc00010100nnnndddd00000101mmmm_case_0); 4744 }; 4745 4746 // QDSUB_cccc00010110nnnndddd00000101mmmm_case_0: 4747 // 4748 // {Cond: Cond(31:28), 4749 // Pc: 15, 4750 // Rd: Rd(15:12), 4751 // Rm: Rm(3:0), 4752 // Rn: Rn(19:16), 4753 // arch: v5TE, 4754 // defs: {Rd}, 4755 // fields: [Cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 4756 // pattern: cccc00010110nnnndddd00000101mmmm, 4757 // rule: QDSUB, 4758 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 4759 // uses: {Rn, Rm}} 4760 class QDSUB_cccc00010110nnnndddd00000101mmmm_case_0 4761 : public ClassDecoder { 4762 public: QDSUB_cccc00010110nnnndddd00000101mmmm_case_0()4763 QDSUB_cccc00010110nnnndddd00000101mmmm_case_0() 4764 : ClassDecoder() {} 4765 virtual RegisterList defs(Instruction inst) const; 4766 virtual SafetyLevel safety(Instruction i) const; 4767 virtual RegisterList uses(Instruction i) const; 4768 private: 4769 NACL_DISALLOW_COPY_AND_ASSIGN( 4770 QDSUB_cccc00010110nnnndddd00000101mmmm_case_0); 4771 }; 4772 4773 // QSAX_cccc01100010nnnndddd11110101mmmm_case_0: 4774 // 4775 // {Pc: 15, 4776 // Rd: Rd(15:12), 4777 // Rm: Rm(3:0), 4778 // Rn: Rn(19:16), 4779 // arch: v6, 4780 // cond: cond(31:28), 4781 // defs: {Rd}, 4782 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 4783 // pattern: cccc01100010nnnndddd11110101mmmm, 4784 // rule: QSAX, 4785 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 4786 // uses: {Rn, Rm}} 4787 class QSAX_cccc01100010nnnndddd11110101mmmm_case_0 4788 : public ClassDecoder { 4789 public: QSAX_cccc01100010nnnndddd11110101mmmm_case_0()4790 QSAX_cccc01100010nnnndddd11110101mmmm_case_0() 4791 : ClassDecoder() {} 4792 virtual RegisterList defs(Instruction inst) const; 4793 virtual SafetyLevel safety(Instruction i) const; 4794 virtual RegisterList uses(Instruction i) const; 4795 private: 4796 NACL_DISALLOW_COPY_AND_ASSIGN( 4797 QSAX_cccc01100010nnnndddd11110101mmmm_case_0); 4798 }; 4799 4800 // QSUB16_cccc01100010nnnndddd11110111mmmm_case_0: 4801 // 4802 // {Pc: 15, 4803 // Rd: Rd(15:12), 4804 // Rm: Rm(3:0), 4805 // Rn: Rn(19:16), 4806 // arch: v6, 4807 // cond: cond(31:28), 4808 // defs: {Rd}, 4809 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 4810 // pattern: cccc01100010nnnndddd11110111mmmm, 4811 // rule: QSUB16, 4812 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 4813 // uses: {Rn, Rm}} 4814 class QSUB16_cccc01100010nnnndddd11110111mmmm_case_0 4815 : public ClassDecoder { 4816 public: QSUB16_cccc01100010nnnndddd11110111mmmm_case_0()4817 QSUB16_cccc01100010nnnndddd11110111mmmm_case_0() 4818 : ClassDecoder() {} 4819 virtual RegisterList defs(Instruction inst) const; 4820 virtual SafetyLevel safety(Instruction i) const; 4821 virtual RegisterList uses(Instruction i) const; 4822 private: 4823 NACL_DISALLOW_COPY_AND_ASSIGN( 4824 QSUB16_cccc01100010nnnndddd11110111mmmm_case_0); 4825 }; 4826 4827 // QSUB8_cccc01100010nnnndddd11111111mmmm_case_0: 4828 // 4829 // {Pc: 15, 4830 // Rd: Rd(15:12), 4831 // Rm: Rm(3:0), 4832 // Rn: Rn(19:16), 4833 // arch: v6, 4834 // cond: cond(31:28), 4835 // defs: {Rd}, 4836 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 4837 // pattern: cccc01100010nnnndddd11111111mmmm, 4838 // rule: QSUB8, 4839 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 4840 // uses: {Rn, Rm}} 4841 class QSUB8_cccc01100010nnnndddd11111111mmmm_case_0 4842 : public ClassDecoder { 4843 public: QSUB8_cccc01100010nnnndddd11111111mmmm_case_0()4844 QSUB8_cccc01100010nnnndddd11111111mmmm_case_0() 4845 : ClassDecoder() {} 4846 virtual RegisterList defs(Instruction inst) const; 4847 virtual SafetyLevel safety(Instruction i) const; 4848 virtual RegisterList uses(Instruction i) const; 4849 private: 4850 NACL_DISALLOW_COPY_AND_ASSIGN( 4851 QSUB8_cccc01100010nnnndddd11111111mmmm_case_0); 4852 }; 4853 4854 // QSUB_cccc00010010nnnndddd00000101mmmm_case_0: 4855 // 4856 // {Cond: Cond(31:28), 4857 // Pc: 15, 4858 // Rd: Rd(15:12), 4859 // Rm: Rm(3:0), 4860 // Rn: Rn(19:16), 4861 // arch: v5TE, 4862 // defs: {Rd}, 4863 // fields: [Cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 4864 // pattern: cccc00010010nnnndddd00000101mmmm, 4865 // rule: QSUB, 4866 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 4867 // uses: {Rn, Rm}} 4868 class QSUB_cccc00010010nnnndddd00000101mmmm_case_0 4869 : public ClassDecoder { 4870 public: QSUB_cccc00010010nnnndddd00000101mmmm_case_0()4871 QSUB_cccc00010010nnnndddd00000101mmmm_case_0() 4872 : ClassDecoder() {} 4873 virtual RegisterList defs(Instruction inst) const; 4874 virtual SafetyLevel safety(Instruction i) const; 4875 virtual RegisterList uses(Instruction i) const; 4876 private: 4877 NACL_DISALLOW_COPY_AND_ASSIGN( 4878 QSUB_cccc00010010nnnndddd00000101mmmm_case_0); 4879 }; 4880 4881 // RBIT_cccc011011111111dddd11110011mmmm_case_0: 4882 // 4883 // {Pc: 15, 4884 // Rd: Rd(15:12), 4885 // Rm: Rm(3:0), 4886 // arch: v6T2, 4887 // cond: cond(31:28), 4888 // defs: {Rd}, 4889 // fields: [cond(31:28), Rd(15:12), Rm(3:0)], 4890 // pattern: cccc011011111111dddd11110011mmmm, 4891 // rule: RBIT, 4892 // safety: [Pc in {Rd, Rm} => UNPREDICTABLE], 4893 // uses: {Rm}} 4894 class RBIT_cccc011011111111dddd11110011mmmm_case_0 4895 : public ClassDecoder { 4896 public: RBIT_cccc011011111111dddd11110011mmmm_case_0()4897 RBIT_cccc011011111111dddd11110011mmmm_case_0() 4898 : ClassDecoder() {} 4899 virtual RegisterList defs(Instruction inst) const; 4900 virtual SafetyLevel safety(Instruction i) const; 4901 virtual RegisterList uses(Instruction i) const; 4902 private: 4903 NACL_DISALLOW_COPY_AND_ASSIGN( 4904 RBIT_cccc011011111111dddd11110011mmmm_case_0); 4905 }; 4906 4907 // REV16_cccc011010111111dddd11111011mmmm_case_0: 4908 // 4909 // {Pc: 15, 4910 // Rd: Rd(15:12), 4911 // Rm: Rm(3:0), 4912 // arch: v6, 4913 // cond: cond(31:28), 4914 // defs: {Rd}, 4915 // fields: [cond(31:28), Rd(15:12), Rm(3:0)], 4916 // pattern: cccc011010111111dddd11111011mmmm, 4917 // rule: REV16, 4918 // safety: [Pc in {Rd, Rm} => UNPREDICTABLE], 4919 // uses: {Rm}} 4920 class REV16_cccc011010111111dddd11111011mmmm_case_0 4921 : public ClassDecoder { 4922 public: REV16_cccc011010111111dddd11111011mmmm_case_0()4923 REV16_cccc011010111111dddd11111011mmmm_case_0() 4924 : ClassDecoder() {} 4925 virtual RegisterList defs(Instruction inst) const; 4926 virtual SafetyLevel safety(Instruction i) const; 4927 virtual RegisterList uses(Instruction i) const; 4928 private: 4929 NACL_DISALLOW_COPY_AND_ASSIGN( 4930 REV16_cccc011010111111dddd11111011mmmm_case_0); 4931 }; 4932 4933 // REVSH_cccc011011111111dddd11111011mmmm_case_0: 4934 // 4935 // {Pc: 15, 4936 // Rd: Rd(15:12), 4937 // Rm: Rm(3:0), 4938 // arch: v6, 4939 // cond: cond(31:28), 4940 // defs: {Rd}, 4941 // fields: [cond(31:28), Rd(15:12), Rm(3:0)], 4942 // pattern: cccc011011111111dddd11111011mmmm, 4943 // rule: REVSH, 4944 // safety: [Pc in {Rd, Rm} => UNPREDICTABLE], 4945 // uses: {Rm}} 4946 class REVSH_cccc011011111111dddd11111011mmmm_case_0 4947 : public ClassDecoder { 4948 public: REVSH_cccc011011111111dddd11111011mmmm_case_0()4949 REVSH_cccc011011111111dddd11111011mmmm_case_0() 4950 : ClassDecoder() {} 4951 virtual RegisterList defs(Instruction inst) const; 4952 virtual SafetyLevel safety(Instruction i) const; 4953 virtual RegisterList uses(Instruction i) const; 4954 private: 4955 NACL_DISALLOW_COPY_AND_ASSIGN( 4956 REVSH_cccc011011111111dddd11111011mmmm_case_0); 4957 }; 4958 4959 // REV_cccc011010111111dddd11110011mmmm_case_0: 4960 // 4961 // {Pc: 15, 4962 // Rd: Rd(15:12), 4963 // Rm: Rm(3:0), 4964 // arch: v6, 4965 // cond: cond(31:28), 4966 // defs: {Rd}, 4967 // fields: [cond(31:28), Rd(15:12), Rm(3:0)], 4968 // pattern: cccc011010111111dddd11110011mmmm, 4969 // rule: REV, 4970 // safety: [Pc in {Rd, Rm} => UNPREDICTABLE], 4971 // uses: {Rm}} 4972 class REV_cccc011010111111dddd11110011mmmm_case_0 4973 : public ClassDecoder { 4974 public: REV_cccc011010111111dddd11110011mmmm_case_0()4975 REV_cccc011010111111dddd11110011mmmm_case_0() 4976 : ClassDecoder() {} 4977 virtual RegisterList defs(Instruction inst) const; 4978 virtual SafetyLevel safety(Instruction i) const; 4979 virtual RegisterList uses(Instruction i) const; 4980 private: 4981 NACL_DISALLOW_COPY_AND_ASSIGN( 4982 REV_cccc011010111111dddd11110011mmmm_case_0); 4983 }; 4984 4985 // RFE_1111100pu0w1nnnn0000101000000000_case_0: 4986 // 4987 // {arch: v6, 4988 // defs: {}, 4989 // pattern: 1111100pu0w1nnnn0000101000000000, 4990 // rule: RFE, 4991 // safety: [true => FORBIDDEN], 4992 // true: true, 4993 // uses: {}} 4994 class RFE_1111100pu0w1nnnn0000101000000000_case_0 4995 : public ClassDecoder { 4996 public: RFE_1111100pu0w1nnnn0000101000000000_case_0()4997 RFE_1111100pu0w1nnnn0000101000000000_case_0() 4998 : ClassDecoder() {} 4999 virtual RegisterList defs(Instruction inst) const; 5000 virtual SafetyLevel safety(Instruction i) const; 5001 virtual RegisterList uses(Instruction i) const; 5002 private: 5003 NACL_DISALLOW_COPY_AND_ASSIGN( 5004 RFE_1111100pu0w1nnnn0000101000000000_case_0); 5005 }; 5006 5007 // ROR_immediate_cccc0001101s0000ddddiiiii110mmmm_case_0: 5008 // 5009 // {NZCV: 16, 5010 // None: 32, 5011 // Rd: Rd(15:12), 5012 // Rm: Rm(3:0), 5013 // S: S(20), 5014 // cond: cond(31:28), 5015 // defs: {Rd, NZCV 5016 // if S 5017 // else None}, 5018 // fields: [cond(31:28), 5019 // S(20), 5020 // Rd(15:12), 5021 // imm5(11:7), 5022 // type(6:5), 5023 // Rm(3:0)], 5024 // imm5: imm5(11:7), 5025 // pattern: cccc0001101s0000ddddiiiii110mmmm, 5026 // rule: ROR_immediate, 5027 // safety: [(Rd(15:12)=1111 && 5028 // S(20)=1) => DECODER_ERROR, 5029 // imm5(11:7)=00000 => DECODER_ERROR, 5030 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 5031 // shift: DecodeImmShift(type, imm5), 5032 // type: type(6:5), 5033 // uses: {Rm}} 5034 class ROR_immediate_cccc0001101s0000ddddiiiii110mmmm_case_0 5035 : public ClassDecoder { 5036 public: ROR_immediate_cccc0001101s0000ddddiiiii110mmmm_case_0()5037 ROR_immediate_cccc0001101s0000ddddiiiii110mmmm_case_0() 5038 : ClassDecoder() {} 5039 virtual RegisterList defs(Instruction inst) const; 5040 virtual SafetyLevel safety(Instruction i) const; 5041 virtual RegisterList uses(Instruction i) const; 5042 private: 5043 NACL_DISALLOW_COPY_AND_ASSIGN( 5044 ROR_immediate_cccc0001101s0000ddddiiiii110mmmm_case_0); 5045 }; 5046 5047 // ROR_register_cccc0001101s0000ddddmmmm0111nnnn_case_0: 5048 // 5049 // {NZCV: 16, 5050 // None: 32, 5051 // Pc: 15, 5052 // Rd: Rd(15:12), 5053 // Rm: Rm(11:8), 5054 // Rn: Rn(3:0), 5055 // S: S(20), 5056 // cond: cond(31:28), 5057 // defs: {Rd, NZCV 5058 // if setflags 5059 // else None}, 5060 // fields: [cond(31:28), S(20), Rd(15:12), Rm(11:8), Rn(3:0)], 5061 // pattern: cccc0001101s0000ddddmmmm0111nnnn, 5062 // rule: ROR_register, 5063 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 5064 // setflags: S(20)=1, 5065 // uses: {Rn, Rm}} 5066 class ROR_register_cccc0001101s0000ddddmmmm0111nnnn_case_0 5067 : public ClassDecoder { 5068 public: ROR_register_cccc0001101s0000ddddmmmm0111nnnn_case_0()5069 ROR_register_cccc0001101s0000ddddmmmm0111nnnn_case_0() 5070 : ClassDecoder() {} 5071 virtual RegisterList defs(Instruction inst) const; 5072 virtual SafetyLevel safety(Instruction i) const; 5073 virtual RegisterList uses(Instruction i) const; 5074 private: 5075 NACL_DISALLOW_COPY_AND_ASSIGN( 5076 ROR_register_cccc0001101s0000ddddmmmm0111nnnn_case_0); 5077 }; 5078 5079 // RRX_cccc0001101s0000dddd00000110mmmm_case_0: 5080 // 5081 // {NZCV: 16, 5082 // None: 32, 5083 // Rd: Rd(15:12), 5084 // Rm: Rm(3:0), 5085 // S: S(20), 5086 // cond: cond(31:28), 5087 // defs: {Rd, NZCV 5088 // if S 5089 // else None}, 5090 // fields: [cond(31:28), S(20), Rd(15:12), Rm(3:0)], 5091 // pattern: cccc0001101s0000dddd00000110mmmm, 5092 // rule: RRX, 5093 // safety: [(Rd(15:12)=1111 && 5094 // S(20)=1) => DECODER_ERROR, 5095 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 5096 // uses: {Rm}} 5097 class RRX_cccc0001101s0000dddd00000110mmmm_case_0 5098 : public ClassDecoder { 5099 public: RRX_cccc0001101s0000dddd00000110mmmm_case_0()5100 RRX_cccc0001101s0000dddd00000110mmmm_case_0() 5101 : ClassDecoder() {} 5102 virtual RegisterList defs(Instruction inst) const; 5103 virtual SafetyLevel safety(Instruction i) const; 5104 virtual RegisterList uses(Instruction i) const; 5105 private: 5106 NACL_DISALLOW_COPY_AND_ASSIGN( 5107 RRX_cccc0001101s0000dddd00000110mmmm_case_0); 5108 }; 5109 5110 // RSB_immediate_cccc0010011snnnnddddiiiiiiiiiiii_case_0: 5111 // 5112 // {NZCV: 16, 5113 // None: 32, 5114 // Rd: Rd(15:12), 5115 // Rn: Rn(19:16), 5116 // S: S(20), 5117 // cond: cond(31:28), 5118 // defs: {Rd, NZCV 5119 // if setflags 5120 // else None}, 5121 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)], 5122 // imm12: imm12(11:0), 5123 // imm32: ARMExpandImm(imm12), 5124 // pattern: cccc0010011snnnnddddiiiiiiiiiiii, 5125 // rule: RSB_immediate, 5126 // safety: [(Rd(15:12)=1111 && 5127 // S(20)=1) => DECODER_ERROR, 5128 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 5129 // setflags: S(20)=1, 5130 // uses: {Rn}} 5131 class RSB_immediate_cccc0010011snnnnddddiiiiiiiiiiii_case_0 5132 : public ClassDecoder { 5133 public: RSB_immediate_cccc0010011snnnnddddiiiiiiiiiiii_case_0()5134 RSB_immediate_cccc0010011snnnnddddiiiiiiiiiiii_case_0() 5135 : ClassDecoder() {} 5136 virtual RegisterList defs(Instruction inst) const; 5137 virtual SafetyLevel safety(Instruction i) const; 5138 virtual RegisterList uses(Instruction i) const; 5139 private: 5140 NACL_DISALLOW_COPY_AND_ASSIGN( 5141 RSB_immediate_cccc0010011snnnnddddiiiiiiiiiiii_case_0); 5142 }; 5143 5144 // RSB_register_cccc0000011snnnnddddiiiiitt0mmmm_case_0: 5145 // 5146 // {NZCV: 16, 5147 // None: 32, 5148 // Rd: Rd(15:12), 5149 // Rm: Rm(3:0), 5150 // Rn: Rn(19:16), 5151 // S: S(20), 5152 // cond: cond(31:28), 5153 // defs: {Rd, NZCV 5154 // if S 5155 // else None}, 5156 // fields: [cond(31:28), 5157 // S(20), 5158 // Rn(19:16), 5159 // Rd(15:12), 5160 // imm5(11:7), 5161 // type(6:5), 5162 // Rm(3:0)], 5163 // imm5: imm5(11:7), 5164 // pattern: cccc0000011snnnnddddiiiiitt0mmmm, 5165 // rule: RSB_register, 5166 // safety: [(Rd(15:12)=1111 && 5167 // S(20)=1) => DECODER_ERROR, 5168 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 5169 // shift: DecodeImmShift(type, imm5), 5170 // type: type(6:5), 5171 // uses: {Rn, Rm}} 5172 class RSB_register_cccc0000011snnnnddddiiiiitt0mmmm_case_0 5173 : public ClassDecoder { 5174 public: RSB_register_cccc0000011snnnnddddiiiiitt0mmmm_case_0()5175 RSB_register_cccc0000011snnnnddddiiiiitt0mmmm_case_0() 5176 : ClassDecoder() {} 5177 virtual RegisterList defs(Instruction inst) const; 5178 virtual SafetyLevel safety(Instruction i) const; 5179 virtual RegisterList uses(Instruction i) const; 5180 private: 5181 NACL_DISALLOW_COPY_AND_ASSIGN( 5182 RSB_register_cccc0000011snnnnddddiiiiitt0mmmm_case_0); 5183 }; 5184 5185 // RSB_register_shfited_register_cccc0000011snnnnddddssss0tt1mmmm_case_0: 5186 // 5187 // {NZCV: 16, 5188 // None: 32, 5189 // Pc: 15, 5190 // Rd: Rd(15:12), 5191 // Rm: Rm(3:0), 5192 // Rn: Rn(19:16), 5193 // Rs: Rs(11:8), 5194 // S: S(20), 5195 // cond: cond(31:28), 5196 // defs: {Rd, NZCV 5197 // if setflags 5198 // else None}, 5199 // fields: [cond(31:28), 5200 // S(20), 5201 // Rn(19:16), 5202 // Rd(15:12), 5203 // Rs(11:8), 5204 // type(6:5), 5205 // Rm(3:0)], 5206 // pattern: cccc0000011snnnnddddssss0tt1mmmm, 5207 // rule: RSB_register_shfited_register, 5208 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE], 5209 // setflags: S(20)=1, 5210 // shift_t: DecodeRegShift(type), 5211 // type: type(6:5), 5212 // uses: {Rn, Rm, Rs}} 5213 class RSB_register_shfited_register_cccc0000011snnnnddddssss0tt1mmmm_case_0 5214 : public ClassDecoder { 5215 public: RSB_register_shfited_register_cccc0000011snnnnddddssss0tt1mmmm_case_0()5216 RSB_register_shfited_register_cccc0000011snnnnddddssss0tt1mmmm_case_0() 5217 : ClassDecoder() {} 5218 virtual RegisterList defs(Instruction inst) const; 5219 virtual SafetyLevel safety(Instruction i) const; 5220 virtual RegisterList uses(Instruction i) const; 5221 private: 5222 NACL_DISALLOW_COPY_AND_ASSIGN( 5223 RSB_register_shfited_register_cccc0000011snnnnddddssss0tt1mmmm_case_0); 5224 }; 5225 5226 // RSC_immediate_cccc0010111snnnnddddiiiiiiiiiiii_case_0: 5227 // 5228 // {NZCV: 16, 5229 // None: 32, 5230 // Rd: Rd(15:12), 5231 // Rn: Rn(19:16), 5232 // S: S(20), 5233 // cond: cond(31:28), 5234 // defs: {Rd, NZCV 5235 // if setflags 5236 // else None}, 5237 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)], 5238 // imm12: imm12(11:0), 5239 // imm32: ARMExpandImm(imm12), 5240 // pattern: cccc0010111snnnnddddiiiiiiiiiiii, 5241 // rule: RSC_immediate, 5242 // safety: [(Rd(15:12)=1111 && 5243 // S(20)=1) => DECODER_ERROR, 5244 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 5245 // setflags: S(20)=1, 5246 // uses: {Rn}} 5247 class RSC_immediate_cccc0010111snnnnddddiiiiiiiiiiii_case_0 5248 : public ClassDecoder { 5249 public: RSC_immediate_cccc0010111snnnnddddiiiiiiiiiiii_case_0()5250 RSC_immediate_cccc0010111snnnnddddiiiiiiiiiiii_case_0() 5251 : ClassDecoder() {} 5252 virtual RegisterList defs(Instruction inst) const; 5253 virtual SafetyLevel safety(Instruction i) const; 5254 virtual RegisterList uses(Instruction i) const; 5255 private: 5256 NACL_DISALLOW_COPY_AND_ASSIGN( 5257 RSC_immediate_cccc0010111snnnnddddiiiiiiiiiiii_case_0); 5258 }; 5259 5260 // RSC_register_cccc0000111snnnnddddiiiiitt0mmmm_case_0: 5261 // 5262 // {NZCV: 16, 5263 // None: 32, 5264 // Rd: Rd(15:12), 5265 // Rm: Rm(3:0), 5266 // Rn: Rn(19:16), 5267 // S: S(20), 5268 // cond: cond(31:28), 5269 // defs: {Rd, NZCV 5270 // if S 5271 // else None}, 5272 // fields: [cond(31:28), 5273 // S(20), 5274 // Rn(19:16), 5275 // Rd(15:12), 5276 // imm5(11:7), 5277 // type(6:5), 5278 // Rm(3:0)], 5279 // imm5: imm5(11:7), 5280 // pattern: cccc0000111snnnnddddiiiiitt0mmmm, 5281 // rule: RSC_register, 5282 // safety: [(Rd(15:12)=1111 && 5283 // S(20)=1) => DECODER_ERROR, 5284 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 5285 // shift: DecodeImmShift(type, imm5), 5286 // type: type(6:5), 5287 // uses: {Rn, Rm}} 5288 class RSC_register_cccc0000111snnnnddddiiiiitt0mmmm_case_0 5289 : public ClassDecoder { 5290 public: RSC_register_cccc0000111snnnnddddiiiiitt0mmmm_case_0()5291 RSC_register_cccc0000111snnnnddddiiiiitt0mmmm_case_0() 5292 : ClassDecoder() {} 5293 virtual RegisterList defs(Instruction inst) const; 5294 virtual SafetyLevel safety(Instruction i) const; 5295 virtual RegisterList uses(Instruction i) const; 5296 private: 5297 NACL_DISALLOW_COPY_AND_ASSIGN( 5298 RSC_register_cccc0000111snnnnddddiiiiitt0mmmm_case_0); 5299 }; 5300 5301 // RSC_register_shifted_register_cccc0000111snnnnddddssss0tt1mmmm_case_0: 5302 // 5303 // {NZCV: 16, 5304 // None: 32, 5305 // Pc: 15, 5306 // Rd: Rd(15:12), 5307 // Rm: Rm(3:0), 5308 // Rn: Rn(19:16), 5309 // Rs: Rs(11:8), 5310 // S: S(20), 5311 // cond: cond(31:28), 5312 // defs: {Rd, NZCV 5313 // if setflags 5314 // else None}, 5315 // fields: [cond(31:28), 5316 // S(20), 5317 // Rn(19:16), 5318 // Rd(15:12), 5319 // Rs(11:8), 5320 // type(6:5), 5321 // Rm(3:0)], 5322 // pattern: cccc0000111snnnnddddssss0tt1mmmm, 5323 // rule: RSC_register_shifted_register, 5324 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE], 5325 // setflags: S(20)=1, 5326 // shift_t: DecodeRegShift(type), 5327 // type: type(6:5), 5328 // uses: {Rn, Rm, Rs}} 5329 class RSC_register_shifted_register_cccc0000111snnnnddddssss0tt1mmmm_case_0 5330 : public ClassDecoder { 5331 public: RSC_register_shifted_register_cccc0000111snnnnddddssss0tt1mmmm_case_0()5332 RSC_register_shifted_register_cccc0000111snnnnddddssss0tt1mmmm_case_0() 5333 : ClassDecoder() {} 5334 virtual RegisterList defs(Instruction inst) const; 5335 virtual SafetyLevel safety(Instruction i) const; 5336 virtual RegisterList uses(Instruction i) const; 5337 private: 5338 NACL_DISALLOW_COPY_AND_ASSIGN( 5339 RSC_register_shifted_register_cccc0000111snnnnddddssss0tt1mmmm_case_0); 5340 }; 5341 5342 // SADD16_cccc01100001nnnndddd11110001mmmm_case_0: 5343 // 5344 // {Pc: 15, 5345 // Rd: Rd(15:12), 5346 // Rm: Rm(3:0), 5347 // Rn: Rn(19:16), 5348 // arch: v6, 5349 // cond: cond(31:28), 5350 // defs: {Rd}, 5351 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 5352 // pattern: cccc01100001nnnndddd11110001mmmm, 5353 // rule: SADD16, 5354 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 5355 // uses: {Rn, Rm}} 5356 class SADD16_cccc01100001nnnndddd11110001mmmm_case_0 5357 : public ClassDecoder { 5358 public: SADD16_cccc01100001nnnndddd11110001mmmm_case_0()5359 SADD16_cccc01100001nnnndddd11110001mmmm_case_0() 5360 : ClassDecoder() {} 5361 virtual RegisterList defs(Instruction inst) const; 5362 virtual SafetyLevel safety(Instruction i) const; 5363 virtual RegisterList uses(Instruction i) const; 5364 private: 5365 NACL_DISALLOW_COPY_AND_ASSIGN( 5366 SADD16_cccc01100001nnnndddd11110001mmmm_case_0); 5367 }; 5368 5369 // SADD8_cccc01100001nnnndddd11111001mmmm_case_0: 5370 // 5371 // {Pc: 15, 5372 // Rd: Rd(15:12), 5373 // Rm: Rm(3:0), 5374 // Rn: Rn(19:16), 5375 // arch: v6, 5376 // cond: cond(31:28), 5377 // defs: {Rd}, 5378 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 5379 // pattern: cccc01100001nnnndddd11111001mmmm, 5380 // rule: SADD8, 5381 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 5382 // uses: {Rn, Rm}} 5383 class SADD8_cccc01100001nnnndddd11111001mmmm_case_0 5384 : public ClassDecoder { 5385 public: SADD8_cccc01100001nnnndddd11111001mmmm_case_0()5386 SADD8_cccc01100001nnnndddd11111001mmmm_case_0() 5387 : ClassDecoder() {} 5388 virtual RegisterList defs(Instruction inst) const; 5389 virtual SafetyLevel safety(Instruction i) const; 5390 virtual RegisterList uses(Instruction i) const; 5391 private: 5392 NACL_DISALLOW_COPY_AND_ASSIGN( 5393 SADD8_cccc01100001nnnndddd11111001mmmm_case_0); 5394 }; 5395 5396 // SASX_cccc01100001nnnndddd11110011mmmm_case_0: 5397 // 5398 // {Pc: 15, 5399 // Rd: Rd(15:12), 5400 // Rm: Rm(3:0), 5401 // Rn: Rn(19:16), 5402 // arch: v6, 5403 // cond: cond(31:28), 5404 // defs: {Rd}, 5405 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 5406 // pattern: cccc01100001nnnndddd11110011mmmm, 5407 // rule: SASX, 5408 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 5409 // uses: {Rn, Rm}} 5410 class SASX_cccc01100001nnnndddd11110011mmmm_case_0 5411 : public ClassDecoder { 5412 public: SASX_cccc01100001nnnndddd11110011mmmm_case_0()5413 SASX_cccc01100001nnnndddd11110011mmmm_case_0() 5414 : ClassDecoder() {} 5415 virtual RegisterList defs(Instruction inst) const; 5416 virtual SafetyLevel safety(Instruction i) const; 5417 virtual RegisterList uses(Instruction i) const; 5418 private: 5419 NACL_DISALLOW_COPY_AND_ASSIGN( 5420 SASX_cccc01100001nnnndddd11110011mmmm_case_0); 5421 }; 5422 5423 // SBC_immediate_cccc0010110snnnnddddiiiiiiiiiiii_case_0: 5424 // 5425 // {NZCV: 16, 5426 // None: 32, 5427 // Rd: Rd(15:12), 5428 // Rn: Rn(19:16), 5429 // S: S(20), 5430 // cond: cond(31:28), 5431 // defs: {Rd, NZCV 5432 // if setflags 5433 // else None}, 5434 // fields: [cond(31:28), S(20), Rn(19:16), Rd(15:12), imm12(11:0)], 5435 // imm12: imm12(11:0), 5436 // imm32: ARMExpandImm(imm12), 5437 // pattern: cccc0010110snnnnddddiiiiiiiiiiii, 5438 // rule: SBC_immediate, 5439 // safety: [(Rd(15:12)=1111 && 5440 // S(20)=1) => DECODER_ERROR, 5441 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 5442 // setflags: S(20)=1, 5443 // uses: {Rn}} 5444 class SBC_immediate_cccc0010110snnnnddddiiiiiiiiiiii_case_0 5445 : public ClassDecoder { 5446 public: SBC_immediate_cccc0010110snnnnddddiiiiiiiiiiii_case_0()5447 SBC_immediate_cccc0010110snnnnddddiiiiiiiiiiii_case_0() 5448 : ClassDecoder() {} 5449 virtual RegisterList defs(Instruction inst) const; 5450 virtual SafetyLevel safety(Instruction i) const; 5451 virtual RegisterList uses(Instruction i) const; 5452 private: 5453 NACL_DISALLOW_COPY_AND_ASSIGN( 5454 SBC_immediate_cccc0010110snnnnddddiiiiiiiiiiii_case_0); 5455 }; 5456 5457 // SBC_register_cccc0000110snnnnddddiiiiitt0mmmm_case_0: 5458 // 5459 // {NZCV: 16, 5460 // None: 32, 5461 // Rd: Rd(15:12), 5462 // Rm: Rm(3:0), 5463 // Rn: Rn(19:16), 5464 // S: S(20), 5465 // cond: cond(31:28), 5466 // defs: {Rd, NZCV 5467 // if S 5468 // else None}, 5469 // fields: [cond(31:28), 5470 // S(20), 5471 // Rn(19:16), 5472 // Rd(15:12), 5473 // imm5(11:7), 5474 // type(6:5), 5475 // Rm(3:0)], 5476 // imm5: imm5(11:7), 5477 // pattern: cccc0000110snnnnddddiiiiitt0mmmm, 5478 // rule: SBC_register, 5479 // safety: [(Rd(15:12)=1111 && 5480 // S(20)=1) => DECODER_ERROR, 5481 // Rd(15:12)=1111 => FORBIDDEN_OPERANDS], 5482 // shift: DecodeImmShift(type, imm5), 5483 // type: type(6:5), 5484 // uses: {Rn, Rm}} 5485 class SBC_register_cccc0000110snnnnddddiiiiitt0mmmm_case_0 5486 : public ClassDecoder { 5487 public: SBC_register_cccc0000110snnnnddddiiiiitt0mmmm_case_0()5488 SBC_register_cccc0000110snnnnddddiiiiitt0mmmm_case_0() 5489 : ClassDecoder() {} 5490 virtual RegisterList defs(Instruction inst) const; 5491 virtual SafetyLevel safety(Instruction i) const; 5492 virtual RegisterList uses(Instruction i) const; 5493 private: 5494 NACL_DISALLOW_COPY_AND_ASSIGN( 5495 SBC_register_cccc0000110snnnnddddiiiiitt0mmmm_case_0); 5496 }; 5497 5498 // SBC_register_shifted_register_cccc0000110snnnnddddssss0tt1mmmm_case_0: 5499 // 5500 // {NZCV: 16, 5501 // None: 32, 5502 // Pc: 15, 5503 // Rd: Rd(15:12), 5504 // Rm: Rm(3:0), 5505 // Rn: Rn(19:16), 5506 // Rs: Rs(11:8), 5507 // S: S(20), 5508 // cond: cond(31:28), 5509 // defs: {Rd, NZCV 5510 // if setflags 5511 // else None}, 5512 // fields: [cond(31:28), 5513 // S(20), 5514 // Rn(19:16), 5515 // Rd(15:12), 5516 // Rs(11:8), 5517 // type(6:5), 5518 // Rm(3:0)], 5519 // pattern: cccc0000110snnnnddddssss0tt1mmmm, 5520 // rule: SBC_register_shifted_register, 5521 // safety: [Pc in {Rn, Rd, Rm, Rs} => UNPREDICTABLE], 5522 // setflags: S(20)=1, 5523 // shift_t: DecodeRegShift(type), 5524 // type: type(6:5), 5525 // uses: {Rn, Rm, Rs}} 5526 class SBC_register_shifted_register_cccc0000110snnnnddddssss0tt1mmmm_case_0 5527 : public ClassDecoder { 5528 public: SBC_register_shifted_register_cccc0000110snnnnddddssss0tt1mmmm_case_0()5529 SBC_register_shifted_register_cccc0000110snnnnddddssss0tt1mmmm_case_0() 5530 : ClassDecoder() {} 5531 virtual RegisterList defs(Instruction inst) const; 5532 virtual SafetyLevel safety(Instruction i) const; 5533 virtual RegisterList uses(Instruction i) const; 5534 private: 5535 NACL_DISALLOW_COPY_AND_ASSIGN( 5536 SBC_register_shifted_register_cccc0000110snnnnddddssss0tt1mmmm_case_0); 5537 }; 5538 5539 // SBFX_cccc0111101wwwwwddddlllll101nnnn_case_0: 5540 // 5541 // {Pc: 15, 5542 // Rd: Rd(15:12), 5543 // Rn: Rn(3:0), 5544 // arch: v6T2, 5545 // cond: cond(31:28), 5546 // defs: {Rd}, 5547 // fields: [cond(31:28), widthm1(20:16), Rd(15:12), lsb(11:7), Rn(3:0)], 5548 // lsb: lsb(11:7), 5549 // pattern: cccc0111101wwwwwddddlllll101nnnn, 5550 // rule: SBFX, 5551 // safety: [Pc in {Rd, Rn} => UNPREDICTABLE, 5552 // lsb + widthm1 > 5553 // 31 => UNPREDICTABLE], 5554 // uses: {Rn}, 5555 // widthm1: widthm1(20:16)} 5556 class SBFX_cccc0111101wwwwwddddlllll101nnnn_case_0 5557 : public ClassDecoder { 5558 public: SBFX_cccc0111101wwwwwddddlllll101nnnn_case_0()5559 SBFX_cccc0111101wwwwwddddlllll101nnnn_case_0() 5560 : ClassDecoder() {} 5561 virtual RegisterList defs(Instruction inst) const; 5562 virtual SafetyLevel safety(Instruction i) const; 5563 virtual RegisterList uses(Instruction i) const; 5564 private: 5565 NACL_DISALLOW_COPY_AND_ASSIGN( 5566 SBFX_cccc0111101wwwwwddddlllll101nnnn_case_0); 5567 }; 5568 5569 // SDIV_cccc01110001dddd1111mmmm0001nnnn_case_0: 5570 // 5571 // {M: M(5), 5572 // Pc: 15, 5573 // Rd: Rd(19:16), 5574 // Rm: Rm(11:8), 5575 // Rn: Rn(3:0), 5576 // arch: v7VEoptv7A_v7R, 5577 // cond: cond(31:28), 5578 // defs: {Rd}, 5579 // fields: [cond(31:28), Rd(19:16), Rm(11:8), M(5), Rn(3:0)], 5580 // pattern: cccc01110001dddd1111mmmm0001nnnn, 5581 // rule: SDIV, 5582 // safety: [Pc in {Rd, Rm, Rn} => UNPREDICTABLE], 5583 // uses: {Rm, Rn}} 5584 class SDIV_cccc01110001dddd1111mmmm0001nnnn_case_0 5585 : public ClassDecoder { 5586 public: SDIV_cccc01110001dddd1111mmmm0001nnnn_case_0()5587 SDIV_cccc01110001dddd1111mmmm0001nnnn_case_0() 5588 : ClassDecoder() {} 5589 virtual RegisterList defs(Instruction inst) const; 5590 virtual SafetyLevel safety(Instruction i) const; 5591 virtual RegisterList uses(Instruction i) const; 5592 private: 5593 NACL_DISALLOW_COPY_AND_ASSIGN( 5594 SDIV_cccc01110001dddd1111mmmm0001nnnn_case_0); 5595 }; 5596 5597 // SEL_cccc01101000nnnndddd11111011mmmm_case_0: 5598 // 5599 // {Pc: 15, 5600 // Rd: Rd(15:12), 5601 // Rm: Rm(3:0), 5602 // Rn: Rn(19:16), 5603 // arch: v6, 5604 // cond: cond(31:28), 5605 // defs: {Rd}, 5606 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 5607 // pattern: cccc01101000nnnndddd11111011mmmm, 5608 // rule: SEL, 5609 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 5610 // uses: {Rn, Rm}} 5611 class SEL_cccc01101000nnnndddd11111011mmmm_case_0 5612 : public ClassDecoder { 5613 public: SEL_cccc01101000nnnndddd11111011mmmm_case_0()5614 SEL_cccc01101000nnnndddd11111011mmmm_case_0() 5615 : ClassDecoder() {} 5616 virtual RegisterList defs(Instruction inst) const; 5617 virtual SafetyLevel safety(Instruction i) const; 5618 virtual RegisterList uses(Instruction i) const; 5619 private: 5620 NACL_DISALLOW_COPY_AND_ASSIGN( 5621 SEL_cccc01101000nnnndddd11111011mmmm_case_0); 5622 }; 5623 5624 // SETEND_1111000100000001000000i000000000_case_0: 5625 // 5626 // {arch: v6, 5627 // defs: {}, 5628 // pattern: 1111000100000001000000i000000000, 5629 // rule: SETEND, 5630 // safety: [true => FORBIDDEN], 5631 // true: true, 5632 // uses: {}} 5633 class SETEND_1111000100000001000000i000000000_case_0 5634 : public ClassDecoder { 5635 public: SETEND_1111000100000001000000i000000000_case_0()5636 SETEND_1111000100000001000000i000000000_case_0() 5637 : ClassDecoder() {} 5638 virtual RegisterList defs(Instruction inst) const; 5639 virtual SafetyLevel safety(Instruction i) const; 5640 virtual RegisterList uses(Instruction i) const; 5641 private: 5642 NACL_DISALLOW_COPY_AND_ASSIGN( 5643 SETEND_1111000100000001000000i000000000_case_0); 5644 }; 5645 5646 // SEV_cccc0011001000001111000000000100_case_0: 5647 // 5648 // {arch: v6K, 5649 // defs: {}, 5650 // pattern: cccc0011001000001111000000000100, 5651 // rule: SEV, 5652 // safety: [true => FORBIDDEN], 5653 // true: true, 5654 // uses: {}} 5655 class SEV_cccc0011001000001111000000000100_case_0 5656 : public ClassDecoder { 5657 public: SEV_cccc0011001000001111000000000100_case_0()5658 SEV_cccc0011001000001111000000000100_case_0() 5659 : ClassDecoder() {} 5660 virtual RegisterList defs(Instruction inst) const; 5661 virtual SafetyLevel safety(Instruction i) const; 5662 virtual RegisterList uses(Instruction i) const; 5663 private: 5664 NACL_DISALLOW_COPY_AND_ASSIGN( 5665 SEV_cccc0011001000001111000000000100_case_0); 5666 }; 5667 5668 // SHADD16_cccc01100011nnnndddd11110001mmmm_case_0: 5669 // 5670 // {Pc: 15, 5671 // Rd: Rd(15:12), 5672 // Rm: Rm(3:0), 5673 // Rn: Rn(19:16), 5674 // arch: v6, 5675 // cond: cond(31:28), 5676 // defs: {Rd}, 5677 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 5678 // pattern: cccc01100011nnnndddd11110001mmmm, 5679 // rule: SHADD16, 5680 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 5681 // uses: {Rn, Rm}} 5682 class SHADD16_cccc01100011nnnndddd11110001mmmm_case_0 5683 : public ClassDecoder { 5684 public: SHADD16_cccc01100011nnnndddd11110001mmmm_case_0()5685 SHADD16_cccc01100011nnnndddd11110001mmmm_case_0() 5686 : ClassDecoder() {} 5687 virtual RegisterList defs(Instruction inst) const; 5688 virtual SafetyLevel safety(Instruction i) const; 5689 virtual RegisterList uses(Instruction i) const; 5690 private: 5691 NACL_DISALLOW_COPY_AND_ASSIGN( 5692 SHADD16_cccc01100011nnnndddd11110001mmmm_case_0); 5693 }; 5694 5695 // SHADD8_cccc01100011nnnndddd11111001mmmm_case_0: 5696 // 5697 // {Pc: 15, 5698 // Rd: Rd(15:12), 5699 // Rm: Rm(3:0), 5700 // Rn: Rn(19:16), 5701 // arch: v6, 5702 // cond: cond(31:28), 5703 // defs: {Rd}, 5704 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 5705 // pattern: cccc01100011nnnndddd11111001mmmm, 5706 // rule: SHADD8, 5707 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 5708 // uses: {Rn, Rm}} 5709 class SHADD8_cccc01100011nnnndddd11111001mmmm_case_0 5710 : public ClassDecoder { 5711 public: SHADD8_cccc01100011nnnndddd11111001mmmm_case_0()5712 SHADD8_cccc01100011nnnndddd11111001mmmm_case_0() 5713 : ClassDecoder() {} 5714 virtual RegisterList defs(Instruction inst) const; 5715 virtual SafetyLevel safety(Instruction i) const; 5716 virtual RegisterList uses(Instruction i) const; 5717 private: 5718 NACL_DISALLOW_COPY_AND_ASSIGN( 5719 SHADD8_cccc01100011nnnndddd11111001mmmm_case_0); 5720 }; 5721 5722 // SHASX_cccc01100011nnnndddd11110011mmmm_case_0: 5723 // 5724 // {Pc: 15, 5725 // Rd: Rd(15:12), 5726 // Rm: Rm(3:0), 5727 // Rn: Rn(19:16), 5728 // arch: v6, 5729 // cond: cond(31:28), 5730 // defs: {Rd}, 5731 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 5732 // pattern: cccc01100011nnnndddd11110011mmmm, 5733 // rule: SHASX, 5734 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 5735 // uses: {Rn, Rm}} 5736 class SHASX_cccc01100011nnnndddd11110011mmmm_case_0 5737 : public ClassDecoder { 5738 public: SHASX_cccc01100011nnnndddd11110011mmmm_case_0()5739 SHASX_cccc01100011nnnndddd11110011mmmm_case_0() 5740 : ClassDecoder() {} 5741 virtual RegisterList defs(Instruction inst) const; 5742 virtual SafetyLevel safety(Instruction i) const; 5743 virtual RegisterList uses(Instruction i) const; 5744 private: 5745 NACL_DISALLOW_COPY_AND_ASSIGN( 5746 SHASX_cccc01100011nnnndddd11110011mmmm_case_0); 5747 }; 5748 5749 // SHSAX_cccc01100011nnnndddd11110101mmmm_case_0: 5750 // 5751 // {Pc: 15, 5752 // Rd: Rd(15:12), 5753 // Rm: Rm(3:0), 5754 // Rn: Rn(19:16), 5755 // arch: v6, 5756 // cond: cond(31:28), 5757 // defs: {Rd}, 5758 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 5759 // pattern: cccc01100011nnnndddd11110101mmmm, 5760 // rule: SHSAX, 5761 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 5762 // uses: {Rn, Rm}} 5763 class SHSAX_cccc01100011nnnndddd11110101mmmm_case_0 5764 : public ClassDecoder { 5765 public: SHSAX_cccc01100011nnnndddd11110101mmmm_case_0()5766 SHSAX_cccc01100011nnnndddd11110101mmmm_case_0() 5767 : ClassDecoder() {} 5768 virtual RegisterList defs(Instruction inst) const; 5769 virtual SafetyLevel safety(Instruction i) const; 5770 virtual RegisterList uses(Instruction i) const; 5771 private: 5772 NACL_DISALLOW_COPY_AND_ASSIGN( 5773 SHSAX_cccc01100011nnnndddd11110101mmmm_case_0); 5774 }; 5775 5776 // SHSUB16_cccc01100011nnnndddd11110111mmmm_case_0: 5777 // 5778 // {Pc: 15, 5779 // Rd: Rd(15:12), 5780 // Rm: Rm(3:0), 5781 // Rn: Rn(19:16), 5782 // arch: v6, 5783 // cond: cond(31:28), 5784 // defs: {Rd}, 5785 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 5786 // pattern: cccc01100011nnnndddd11110111mmmm, 5787 // rule: SHSUB16, 5788 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 5789 // uses: {Rn, Rm}} 5790 class SHSUB16_cccc01100011nnnndddd11110111mmmm_case_0 5791 : public ClassDecoder { 5792 public: SHSUB16_cccc01100011nnnndddd11110111mmmm_case_0()5793 SHSUB16_cccc01100011nnnndddd11110111mmmm_case_0() 5794 : ClassDecoder() {} 5795 virtual RegisterList defs(Instruction inst) const; 5796 virtual SafetyLevel safety(Instruction i) const; 5797 virtual RegisterList uses(Instruction i) const; 5798 private: 5799 NACL_DISALLOW_COPY_AND_ASSIGN( 5800 SHSUB16_cccc01100011nnnndddd11110111mmmm_case_0); 5801 }; 5802 5803 // SHSUB8_cccc01100011nnnndddd11111111mmmm_case_0: 5804 // 5805 // {Pc: 15, 5806 // Rd: Rd(15:12), 5807 // Rm: Rm(3:0), 5808 // Rn: Rn(19:16), 5809 // arch: v6, 5810 // cond: cond(31:28), 5811 // defs: {Rd}, 5812 // fields: [cond(31:28), Rn(19:16), Rd(15:12), Rm(3:0)], 5813 // pattern: cccc01100011nnnndddd11111111mmmm, 5814 // rule: SHSUB8, 5815 // safety: [Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 5816 // uses: {Rn, Rm}} 5817 class SHSUB8_cccc01100011nnnndddd11111111mmmm_case_0 5818 : public ClassDecoder { 5819 public: SHSUB8_cccc01100011nnnndddd11111111mmmm_case_0()5820 SHSUB8_cccc01100011nnnndddd11111111mmmm_case_0() 5821 : ClassDecoder() {} 5822 virtual RegisterList defs(Instruction inst) const; 5823 virtual SafetyLevel safety(Instruction i) const; 5824 virtual RegisterList uses(Instruction i) const; 5825 private: 5826 NACL_DISALLOW_COPY_AND_ASSIGN( 5827 SHSUB8_cccc01100011nnnndddd11111111mmmm_case_0); 5828 }; 5829 5830 // SMC_cccc000101100000000000000111iiii_case_0: 5831 // 5832 // {arch: SE, 5833 // defs: {}, 5834 // pattern: cccc000101100000000000000111iiii, 5835 // rule: SMC, 5836 // safety: [true => FORBIDDEN], 5837 // true: true, 5838 // uses: {}} 5839 class SMC_cccc000101100000000000000111iiii_case_0 5840 : public ClassDecoder { 5841 public: SMC_cccc000101100000000000000111iiii_case_0()5842 SMC_cccc000101100000000000000111iiii_case_0() 5843 : ClassDecoder() {} 5844 virtual RegisterList defs(Instruction inst) const; 5845 virtual SafetyLevel safety(Instruction i) const; 5846 virtual RegisterList uses(Instruction i) const; 5847 private: 5848 NACL_DISALLOW_COPY_AND_ASSIGN( 5849 SMC_cccc000101100000000000000111iiii_case_0); 5850 }; 5851 5852 // SMLABB_SMLABT_SMLATB_SMLATT_cccc00010000ddddaaaammmm1xx0nnnn_case_0: 5853 // 5854 // {M: M(6), 5855 // N: N(5), 5856 // Pc: 15, 5857 // Ra: Ra(15:12), 5858 // Rd: Rd(19:16), 5859 // Rm: Rm(11:8), 5860 // Rn: Rn(3:0), 5861 // arch: v5TE, 5862 // cond: cond(31:28), 5863 // defs: {Rd}, 5864 // fields: [cond(31:28), 5865 // Rd(19:16), 5866 // Ra(15:12), 5867 // Rm(11:8), 5868 // M(6), 5869 // N(5), 5870 // Rn(3:0)], 5871 // m_high: M(6)=1, 5872 // n_high: N(5)=1, 5873 // pattern: cccc00010000ddddaaaammmm1xx0nnnn, 5874 // rule: SMLABB_SMLABT_SMLATB_SMLATT, 5875 // safety: [Pc in {Rd, Rn, Rm, Ra} => UNPREDICTABLE], 5876 // uses: {Rn, Rm, Ra}} 5877 class SMLABB_SMLABT_SMLATB_SMLATT_cccc00010000ddddaaaammmm1xx0nnnn_case_0 5878 : public ClassDecoder { 5879 public: SMLABB_SMLABT_SMLATB_SMLATT_cccc00010000ddddaaaammmm1xx0nnnn_case_0()5880 SMLABB_SMLABT_SMLATB_SMLATT_cccc00010000ddddaaaammmm1xx0nnnn_case_0() 5881 : ClassDecoder() {} 5882 virtual RegisterList defs(Instruction inst) const; 5883 virtual SafetyLevel safety(Instruction i) const; 5884 virtual RegisterList uses(Instruction i) const; 5885 private: 5886 NACL_DISALLOW_COPY_AND_ASSIGN( 5887 SMLABB_SMLABT_SMLATB_SMLATT_cccc00010000ddddaaaammmm1xx0nnnn_case_0); 5888 }; 5889 5890 // SMLAD_cccc01110000ddddaaaammmm00m1nnnn_case_0: 5891 // 5892 // {M: M(5), 5893 // Pc: 15, 5894 // Ra: Ra(15:12), 5895 // Rd: Rd(19:16), 5896 // Rm: Rm(11:8), 5897 // Rn: Rn(3:0), 5898 // arch: v6, 5899 // cond: cond(31:28), 5900 // defs: {Rd}, 5901 // fields: [cond(31:28), Rd(19:16), Ra(15:12), Rm(11:8), M(5), Rn(3:0)], 5902 // pattern: cccc01110000ddddaaaammmm00m1nnnn, 5903 // rule: SMLAD, 5904 // safety: [Ra == 5905 // Pc => DECODER_ERROR, 5906 // Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 5907 // uses: {Rn, Rm, Ra}} 5908 class SMLAD_cccc01110000ddddaaaammmm00m1nnnn_case_0 5909 : public ClassDecoder { 5910 public: SMLAD_cccc01110000ddddaaaammmm00m1nnnn_case_0()5911 SMLAD_cccc01110000ddddaaaammmm00m1nnnn_case_0() 5912 : ClassDecoder() {} 5913 virtual RegisterList defs(Instruction inst) const; 5914 virtual SafetyLevel safety(Instruction i) const; 5915 virtual RegisterList uses(Instruction i) const; 5916 private: 5917 NACL_DISALLOW_COPY_AND_ASSIGN( 5918 SMLAD_cccc01110000ddddaaaammmm00m1nnnn_case_0); 5919 }; 5920 5921 // SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_case_0: 5922 // 5923 // {M: M(6), 5924 // N: N(5), 5925 // Pc: 15, 5926 // Rd: Rd(19:16), 5927 // RdHi: RdHi(19:16), 5928 // RdLo: RdLo(15:12), 5929 // Rm: Rm(11:8), 5930 // Rn: Rn(3:0), 5931 // arch: v5TE, 5932 // cond: cond(31:28), 5933 // defs: {RdLo, RdHi}, 5934 // fields: [cond(31:28), 5935 // RdHi(19:16), 5936 // RdLo(15:12), 5937 // Rm(11:8), 5938 // M(6), 5939 // N(5), 5940 // Rn(3:0)], 5941 // m_high: M(6)=1, 5942 // n_high: N(5)=1, 5943 // pattern: cccc00010100hhhhllllmmmm1xx0nnnn, 5944 // rule: SMLALBB_SMLALBT_SMLALTB_SMLALTT, 5945 // safety: [Pc in {RdLo, RdHi, Rn, Rm} => UNPREDICTABLE, 5946 // RdHi == 5947 // RdLo => UNPREDICTABLE], 5948 // uses: {RdLo, RdHi, Rn, Rm}} 5949 class SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_case_0 5950 : public ClassDecoder { 5951 public: SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_case_0()5952 SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_case_0() 5953 : ClassDecoder() {} 5954 virtual RegisterList defs(Instruction inst) const; 5955 virtual SafetyLevel safety(Instruction i) const; 5956 virtual RegisterList uses(Instruction i) const; 5957 private: 5958 NACL_DISALLOW_COPY_AND_ASSIGN( 5959 SMLALBB_SMLALBT_SMLALTB_SMLALTT_cccc00010100hhhhllllmmmm1xx0nnnn_case_0); 5960 }; 5961 5962 // SMLALD_cccc01110100hhhhllllmmmm00m1nnnn_case_0: 5963 // 5964 // {M: M(5), 5965 // Pc: 15, 5966 // RdHi: RdHi(19:16), 5967 // RdLo: RdLo(15:12), 5968 // Rm: Rm(11:8), 5969 // Rn: Rn(3:0), 5970 // arch: v6, 5971 // cond: cond(31:28), 5972 // defs: {RdHi, RdLo}, 5973 // fields: [cond(31:28), 5974 // RdHi(19:16), 5975 // RdLo(15:12), 5976 // Rm(11:8), 5977 // M(5), 5978 // Rn(3:0)], 5979 // pattern: cccc01110100hhhhllllmmmm00m1nnnn, 5980 // rule: SMLALD, 5981 // safety: [Pc in {RdHi, RdLo, Rn, Rm} => UNPREDICTABLE, 5982 // RdHi == 5983 // RdLo => UNPREDICTABLE], 5984 // uses: {RdHi, RdLo, Rm, Rn}} 5985 class SMLALD_cccc01110100hhhhllllmmmm00m1nnnn_case_0 5986 : public ClassDecoder { 5987 public: SMLALD_cccc01110100hhhhllllmmmm00m1nnnn_case_0()5988 SMLALD_cccc01110100hhhhllllmmmm00m1nnnn_case_0() 5989 : ClassDecoder() {} 5990 virtual RegisterList defs(Instruction inst) const; 5991 virtual SafetyLevel safety(Instruction i) const; 5992 virtual RegisterList uses(Instruction i) const; 5993 private: 5994 NACL_DISALLOW_COPY_AND_ASSIGN( 5995 SMLALD_cccc01110100hhhhllllmmmm00m1nnnn_case_0); 5996 }; 5997 5998 // SMLAL_A1_cccc0000111shhhhllllmmmm1001nnnn_case_0: 5999 // 6000 // {NZCV: 16, 6001 // None: 32, 6002 // Pc: 15, 6003 // RdHi: RdHi(19:16), 6004 // RdLo: RdLo(15:12), 6005 // Rm: Rm(11:8), 6006 // Rn: Rn(3:0), 6007 // S: S(20), 6008 // cond: cond(31:28), 6009 // defs: {RdLo, RdHi, NZCV 6010 // if setflags 6011 // else None}, 6012 // fields: [cond(31:28), 6013 // S(20), 6014 // RdHi(19:16), 6015 // RdLo(15:12), 6016 // Rm(11:8), 6017 // Rn(3:0)], 6018 // pattern: cccc0000111shhhhllllmmmm1001nnnn, 6019 // rule: SMLAL_A1, 6020 // safety: [Pc in {RdLo, RdHi, Rn, Rm} => UNPREDICTABLE, 6021 // RdHi == 6022 // RdLo => UNPREDICTABLE, 6023 // (ArchVersion() < 6024 // 6 && 6025 // (RdHi == 6026 // Rn || 6027 // RdLo == 6028 // Rn)) => UNPREDICTABLE], 6029 // setflags: S(20)=1, 6030 // uses: {RdLo, RdHi, Rn, Rm}} 6031 class SMLAL_A1_cccc0000111shhhhllllmmmm1001nnnn_case_0 6032 : public ClassDecoder { 6033 public: SMLAL_A1_cccc0000111shhhhllllmmmm1001nnnn_case_0()6034 SMLAL_A1_cccc0000111shhhhllllmmmm1001nnnn_case_0() 6035 : ClassDecoder() {} 6036 virtual RegisterList defs(Instruction inst) const; 6037 virtual SafetyLevel safety(Instruction i) const; 6038 virtual RegisterList uses(Instruction i) const; 6039 private: 6040 NACL_DISALLOW_COPY_AND_ASSIGN( 6041 SMLAL_A1_cccc0000111shhhhllllmmmm1001nnnn_case_0); 6042 }; 6043 6044 // SMLAWB_SMLAWT_cccc00010010ddddaaaammmm1x00nnnn_case_0: 6045 // 6046 // {M: M(6), 6047 // N: N(5), 6048 // Pc: 15, 6049 // Ra: Ra(15:12), 6050 // Rd: Rd(19:16), 6051 // Rm: Rm(11:8), 6052 // Rn: Rn(3:0), 6053 // arch: v5TE, 6054 // cond: cond(31:28), 6055 // defs: {Rd}, 6056 // fields: [cond(31:28), 6057 // Rd(19:16), 6058 // Ra(15:12), 6059 // Rm(11:8), 6060 // M(6), 6061 // N(5), 6062 // Rn(3:0)], 6063 // m_high: M(6)=1, 6064 // n_high: N(5)=1, 6065 // pattern: cccc00010010ddddaaaammmm1x00nnnn, 6066 // rule: SMLAWB_SMLAWT, 6067 // safety: [Pc in {Rd, Rn, Rm, Ra} => UNPREDICTABLE], 6068 // uses: {Rn, Rm, Ra}} 6069 class SMLAWB_SMLAWT_cccc00010010ddddaaaammmm1x00nnnn_case_0 6070 : public ClassDecoder { 6071 public: SMLAWB_SMLAWT_cccc00010010ddddaaaammmm1x00nnnn_case_0()6072 SMLAWB_SMLAWT_cccc00010010ddddaaaammmm1x00nnnn_case_0() 6073 : ClassDecoder() {} 6074 virtual RegisterList defs(Instruction inst) const; 6075 virtual SafetyLevel safety(Instruction i) const; 6076 virtual RegisterList uses(Instruction i) const; 6077 private: 6078 NACL_DISALLOW_COPY_AND_ASSIGN( 6079 SMLAWB_SMLAWT_cccc00010010ddddaaaammmm1x00nnnn_case_0); 6080 }; 6081 6082 // SMLSD_cccc01110000ddddaaaammmm01m1nnnn_case_0: 6083 // 6084 // {M: M(5), 6085 // Pc: 15, 6086 // Ra: Ra(15:12), 6087 // Rd: Rd(19:16), 6088 // Rm: Rm(11:8), 6089 // Rn: Rn(3:0), 6090 // arch: v6, 6091 // cond: cond(31:28), 6092 // defs: {Rd}, 6093 // fields: [cond(31:28), Rd(19:16), Ra(15:12), Rm(11:8), M(5), Rn(3:0)], 6094 // pattern: cccc01110000ddddaaaammmm01m1nnnn, 6095 // rule: SMLSD, 6096 // safety: [Ra == 6097 // Pc => DECODER_ERROR, 6098 // Pc in {Rd, Rn, Rm} => UNPREDICTABLE], 6099 // uses: {Rn, Rm, Ra}} 6100 class SMLSD_cccc01110000ddddaaaammmm01m1nnnn_case_0 6101 : public ClassDecoder { 6102 public: SMLSD_cccc01110000ddddaaaammmm01m1nnnn_case_0()6103 SMLSD_cccc01110000ddddaaaammmm01m1nnnn_case_0() 6104 : ClassDecoder() {} 6105 virtual RegisterList defs(Instruction inst) const; 6106 virtual SafetyLevel safety(Instruction i) const; 6107 virtual RegisterList uses(Instruction i) const; 6108 private: 6109 NACL_DISALLOW_COPY_AND_ASSIGN( 6110 SMLSD_cccc01110000ddddaaaammmm01m1nnnn_case_0); 6111 }; 6112 6113 // SMLSLD_cccc01110100hhhhllllmmmm01m1nnnn_case_0: 6114 // 6115 // {M: M(5), 6116 // Pc: 15, 6117 // RdHi: RdHi(19:16), 6118 // RdLo: RdLo(15:12), 6119 // Rm: Rm(11:8), 6120 // Rn: Rn(3:0), 6121 // arch: v6, 6122 // cond: cond(31:28), 6123 // defs: {RdHi, RdLo}, 6124 // fields: [cond(31:28), 6125 // RdHi(19:16), 6126 // RdLo(15:12), 6127 // Rm(11:8), 6128 // M(5), 6129 // Rn(3:0)], 6130 // pattern: cccc01110100hhhhllllmmmm01m1nnnn, 6131 // rule: SMLSLD, 6132 // safety: [Pc in {RdHi, RdLo, Rn, Rm} => UNPREDICTABLE, 6133 // RdHi == 6134 // RdLo => UNPREDICTABLE], 6135 // uses: {RdHi, RdLo, Rm, Rn}} 6136 class SMLSLD_cccc01110100hhhhllllmmmm01m1nnnn_case_0 6137 : public ClassDecoder { 6138 public: SMLSLD_cccc01110100hhhhllllmmmm01m1nnnn_case_0()6139 SMLSLD_cccc01110100hhhhllllmmmm01m1nnnn_case_0() 6140 : ClassDecoder() {} 6141 virtual RegisterList defs(Instruction inst) const; 6142 virtual SafetyLevel safety(Instruction i) const; 6143 virtual RegisterList uses(Instruction i) const; 6144 private: 6145 NACL_DISALLOW_COPY_AND_ASSIGN( 6146 SMLSLD_cccc01110100hhhhllllmmmm01m1nnnn_case_0); 6147 }; 6148 6149 } // namespace nacl_arm_test 6150 6151 #endif // NATIVE_CLIENT_SRC_TRUSTED_VALIDATOR_ARM_GEN_ARM32_DECODE_BASELINES_1_H_ 6152