1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
3 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
4
5 #include <arm_mve.h>
6
7 // CHECK-LABEL: @test_vadciq_s32(
8 // CHECK-NEXT: entry:
9 // CHECK-NEXT: [[TMP0:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0)
10 // CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 1
11 // CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 29
12 // CHECK-NEXT: [[TMP3:%.*]] = and i32 1, [[TMP2]]
13 // CHECK-NEXT: store i32 [[TMP3]], i32* [[CARRY_OUT:%.*]], align 4
14 // CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 0
15 // CHECK-NEXT: ret <4 x i32> [[TMP4]]
16 //
test_vadciq_s32(int32x4_t a,int32x4_t b,unsigned * carry_out)17 int32x4_t test_vadciq_s32(int32x4_t a, int32x4_t b, unsigned *carry_out)
18 {
19 #ifdef POLYMORPHIC
20 return vadciq(a, b, carry_out);
21 #else /* POLYMORPHIC */
22 return vadciq_s32(a, b, carry_out);
23 #endif /* POLYMORPHIC */
24 }
25
26 // CHECK-LABEL: @test_vadcq_u32(
27 // CHECK-NEXT: entry:
28 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[CARRY:%.*]], align 4
29 // CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 29
30 // CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]])
31 // CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1
32 // CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29
33 // CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]
34 // CHECK-NEXT: store i32 [[TMP5]], i32* [[CARRY]], align 4
35 // CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0
36 // CHECK-NEXT: ret <4 x i32> [[TMP6]]
37 //
test_vadcq_u32(uint32x4_t a,uint32x4_t b,unsigned * carry)38 uint32x4_t test_vadcq_u32(uint32x4_t a, uint32x4_t b, unsigned *carry)
39 {
40 #ifdef POLYMORPHIC
41 return vadcq(a, b, carry);
42 #else /* POLYMORPHIC */
43 return vadcq_u32(a, b, carry);
44 #endif /* POLYMORPHIC */
45 }
46
47 // CHECK-LABEL: @test_vadciq_m_u32(
48 // CHECK-NEXT: entry:
49 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
50 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
51 // CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, <4 x i1> [[TMP1]])
52 // CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1
53 // CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29
54 // CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]
55 // CHECK-NEXT: store i32 [[TMP5]], i32* [[CARRY_OUT:%.*]], align 4
56 // CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0
57 // CHECK-NEXT: ret <4 x i32> [[TMP6]]
58 //
test_vadciq_m_u32(uint32x4_t inactive,uint32x4_t a,uint32x4_t b,unsigned * carry_out,mve_pred16_t p)59 uint32x4_t test_vadciq_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p)
60 {
61 #ifdef POLYMORPHIC
62 return vadciq_m(inactive, a, b, carry_out, p);
63 #else /* POLYMORPHIC */
64 return vadciq_m_u32(inactive, a, b, carry_out, p);
65 #endif /* POLYMORPHIC */
66 }
67
68 // CHECK-LABEL: @test_vadcq_m_s32(
69 // CHECK-NEXT: entry:
70 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[CARRY:%.*]], align 4
71 // CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 29
72 // CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
73 // CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]])
74 // CHECK-NEXT: [[TMP4:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]], <4 x i1> [[TMP3]])
75 // CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 1
76 // CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP5]], 29
77 // CHECK-NEXT: [[TMP7:%.*]] = and i32 1, [[TMP6]]
78 // CHECK-NEXT: store i32 [[TMP7]], i32* [[CARRY]], align 4
79 // CHECK-NEXT: [[TMP8:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 0
80 // CHECK-NEXT: ret <4 x i32> [[TMP8]]
81 //
test_vadcq_m_s32(int32x4_t inactive,int32x4_t a,int32x4_t b,unsigned * carry,mve_pred16_t p)82 int32x4_t test_vadcq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p)
83 {
84 #ifdef POLYMORPHIC
85 return vadcq_m(inactive, a, b, carry, p);
86 #else /* POLYMORPHIC */
87 return vadcq_m_s32(inactive, a, b, carry, p);
88 #endif /* POLYMORPHIC */
89 }
90
91 // CHECK-LABEL: @test_vsbciq_s32(
92 // CHECK-NEXT: entry:
93 // CHECK-NEXT: [[TMP0:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0)
94 // CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 1
95 // CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 29
96 // CHECK-NEXT: [[TMP3:%.*]] = and i32 1, [[TMP2]]
97 // CHECK-NEXT: store i32 [[TMP3]], i32* [[CARRY_OUT:%.*]], align 4
98 // CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 0
99 // CHECK-NEXT: ret <4 x i32> [[TMP4]]
100 //
test_vsbciq_s32(int32x4_t a,int32x4_t b,unsigned * carry_out)101 int32x4_t test_vsbciq_s32(int32x4_t a, int32x4_t b, unsigned *carry_out) {
102 #ifdef POLYMORPHIC
103 return vsbciq(a, b, carry_out);
104 #else /* POLYMORPHIC */
105 return vsbciq_s32(a, b, carry_out);
106 #endif /* POLYMORPHIC */
107 }
108
109 // CHECK-LABEL: @test_vsbciq_u32(
110 // CHECK-NEXT: entry:
111 // CHECK-NEXT: [[TMP0:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0)
112 // CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 1
113 // CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 29
114 // CHECK-NEXT: [[TMP3:%.*]] = and i32 1, [[TMP2]]
115 // CHECK-NEXT: store i32 [[TMP3]], i32* [[CARRY_OUT:%.*]], align 4
116 // CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP0]], 0
117 // CHECK-NEXT: ret <4 x i32> [[TMP4]]
118 //
test_vsbciq_u32(uint32x4_t a,uint32x4_t b,unsigned * carry_out)119 uint32x4_t test_vsbciq_u32(uint32x4_t a, uint32x4_t b, unsigned *carry_out) {
120 #ifdef POLYMORPHIC
121 return vsbciq(a, b, carry_out);
122 #else /* POLYMORPHIC */
123 return vsbciq_u32(a, b, carry_out);
124 #endif /* POLYMORPHIC */
125 }
126
127 // CHECK-LABEL: @test_vsbcq_s32(
128 // CHECK-NEXT: entry:
129 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[CARRY:%.*]], align 4
130 // CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 29
131 // CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]])
132 // CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1
133 // CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29
134 // CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]
135 // CHECK-NEXT: store i32 [[TMP5]], i32* [[CARRY]], align 4
136 // CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0
137 // CHECK-NEXT: ret <4 x i32> [[TMP6]]
138 //
test_vsbcq_s32(int32x4_t a,int32x4_t b,unsigned * carry)139 int32x4_t test_vsbcq_s32(int32x4_t a, int32x4_t b, unsigned *carry) {
140 #ifdef POLYMORPHIC
141 return vsbcq(a, b, carry);
142 #else /* POLYMORPHIC */
143 return vsbcq_s32(a, b, carry);
144 #endif /* POLYMORPHIC */
145 }
146
147 // CHECK-LABEL: @test_vsbcq_u32(
148 // CHECK-NEXT: entry:
149 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[CARRY:%.*]], align 4
150 // CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 29
151 // CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]])
152 // CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1
153 // CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29
154 // CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]
155 // CHECK-NEXT: store i32 [[TMP5]], i32* [[CARRY]], align 4
156 // CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0
157 // CHECK-NEXT: ret <4 x i32> [[TMP6]]
158 //
test_vsbcq_u32(uint32x4_t a,uint32x4_t b,unsigned * carry)159 uint32x4_t test_vsbcq_u32(uint32x4_t a, uint32x4_t b, unsigned *carry) {
160 #ifdef POLYMORPHIC
161 return vsbcq(a, b, carry);
162 #else /* POLYMORPHIC */
163 return vsbcq_u32(a, b, carry);
164 #endif /* POLYMORPHIC */
165 }
166
167 // CHECK-LABEL: @test_vsbciq_m_s32(
168 // CHECK-NEXT: entry:
169 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
170 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
171 // CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, <4 x i1> [[TMP1]])
172 // CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1
173 // CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29
174 // CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]
175 // CHECK-NEXT: store i32 [[TMP5]], i32* [[CARRY_OUT:%.*]], align 4
176 // CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0
177 // CHECK-NEXT: ret <4 x i32> [[TMP6]]
178 //
test_vsbciq_m_s32(int32x4_t inactive,int32x4_t a,int32x4_t b,unsigned * carry_out,mve_pred16_t p)179 int32x4_t test_vsbciq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry_out, mve_pred16_t p) {
180 #ifdef POLYMORPHIC
181 return vsbciq_m(inactive, a, b, carry_out, p);
182 #else /* POLYMORPHIC */
183 return vsbciq_m_s32(inactive, a, b, carry_out, p);
184 #endif /* POLYMORPHIC */
185 }
186
187 // CHECK-LABEL: @test_vsbciq_m_u32(
188 // CHECK-NEXT: entry:
189 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
190 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
191 // CHECK-NEXT: [[TMP2:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, <4 x i1> [[TMP1]])
192 // CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 1
193 // CHECK-NEXT: [[TMP4:%.*]] = lshr i32 [[TMP3]], 29
194 // CHECK-NEXT: [[TMP5:%.*]] = and i32 1, [[TMP4]]
195 // CHECK-NEXT: store i32 [[TMP5]], i32* [[CARRY_OUT:%.*]], align 4
196 // CHECK-NEXT: [[TMP6:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP2]], 0
197 // CHECK-NEXT: ret <4 x i32> [[TMP6]]
198 //
test_vsbciq_m_u32(uint32x4_t inactive,uint32x4_t a,uint32x4_t b,unsigned * carry_out,mve_pred16_t p)199 uint32x4_t test_vsbciq_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry_out, mve_pred16_t p) {
200 #ifdef POLYMORPHIC
201 return vsbciq_m(inactive, a, b, carry_out, p);
202 #else /* POLYMORPHIC */
203 return vsbciq_m_u32(inactive, a, b, carry_out, p);
204 #endif /* POLYMORPHIC */
205 }
206
207 // CHECK-LABEL: @test_vsbcq_m_s32(
208 // CHECK-NEXT: entry:
209 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[CARRY:%.*]], align 4
210 // CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 29
211 // CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
212 // CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]])
213 // CHECK-NEXT: [[TMP4:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]], <4 x i1> [[TMP3]])
214 // CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 1
215 // CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP5]], 29
216 // CHECK-NEXT: [[TMP7:%.*]] = and i32 1, [[TMP6]]
217 // CHECK-NEXT: store i32 [[TMP7]], i32* [[CARRY]], align 4
218 // CHECK-NEXT: [[TMP8:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 0
219 // CHECK-NEXT: ret <4 x i32> [[TMP8]]
220 //
test_vsbcq_m_s32(int32x4_t inactive,int32x4_t a,int32x4_t b,unsigned * carry,mve_pred16_t p)221 int32x4_t test_vsbcq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned *carry, mve_pred16_t p) {
222 #ifdef POLYMORPHIC
223 return vsbcq_m(inactive, a, b, carry, p);
224 #else /* POLYMORPHIC */
225 return vsbcq_m_s32(inactive, a, b, carry, p);
226 #endif /* POLYMORPHIC */
227 }
228
229 // CHECK-LABEL: @test_vsbcq_m_u32(
230 // CHECK-NEXT: entry:
231 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[CARRY:%.*]], align 4
232 // CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 29
233 // CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
234 // CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]])
235 // CHECK-NEXT: [[TMP4:%.*]] = call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 [[TMP1]], <4 x i1> [[TMP3]])
236 // CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 1
237 // CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP5]], 29
238 // CHECK-NEXT: [[TMP7:%.*]] = and i32 1, [[TMP6]]
239 // CHECK-NEXT: store i32 [[TMP7]], i32* [[CARRY]], align 4
240 // CHECK-NEXT: [[TMP8:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP4]], 0
241 // CHECK-NEXT: ret <4 x i32> [[TMP8]]
242 //
test_vsbcq_m_u32(uint32x4_t inactive,uint32x4_t a,uint32x4_t b,unsigned * carry,mve_pred16_t p)243 uint32x4_t test_vsbcq_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned *carry, mve_pred16_t p) {
244 #ifdef POLYMORPHIC
245 return vsbcq_m(inactive, a, b, carry, p);
246 #else /* POLYMORPHIC */
247 return vsbcq_m_u32(inactive, a, b, carry, p);
248 #endif /* POLYMORPHIC */
249 }
250