1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the Emit routines for the SelectionDAG class, which creates
10 // MachineInstrs based on the decisions of the SelectionDAG instruction
11 // selection.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "InstrEmitter.h"
16 #include "SDNodeDbgValue.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/StackMaps.h"
24 #include "llvm/CodeGen/TargetInstrInfo.h"
25 #include "llvm/CodeGen/TargetLowering.h"
26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/DebugInfo.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Target/TargetMachine.h"
33 using namespace llvm;
34
35 #define DEBUG_TYPE "instr-emitter"
36
37 /// MinRCSize - Smallest register class we allow when constraining virtual
38 /// registers. If satisfying all register class constraints would require
39 /// using a smaller register class, emit a COPY to a new virtual register
40 /// instead.
41 const unsigned MinRCSize = 4;
42
43 /// CountResults - The results of target nodes have register or immediate
44 /// operands first, then an optional chain, and optional glue operands (which do
45 /// not go into the resulting MachineInstr).
CountResults(SDNode * Node)46 unsigned InstrEmitter::CountResults(SDNode *Node) {
47 unsigned N = Node->getNumValues();
48 while (N && Node->getValueType(N - 1) == MVT::Glue)
49 --N;
50 if (N && Node->getValueType(N - 1) == MVT::Other)
51 --N; // Skip over chain result.
52 return N;
53 }
54
55 /// countOperands - The inputs to target nodes have any actual inputs first,
56 /// followed by an optional chain operand, then an optional glue operand.
57 /// Compute the number of actual operands that will go into the resulting
58 /// MachineInstr.
59 ///
60 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
61 /// the chain and glue. These operands may be implicit on the machine instr.
countOperands(SDNode * Node,unsigned NumExpUses,unsigned & NumImpUses)62 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
63 unsigned &NumImpUses) {
64 unsigned N = Node->getNumOperands();
65 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
66 --N;
67 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
68 --N; // Ignore chain if it exists.
69
70 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
71 NumImpUses = N - NumExpUses;
72 for (unsigned I = N; I > NumExpUses; --I) {
73 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
74 continue;
75 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
76 if (Register::isPhysicalRegister(RN->getReg()))
77 continue;
78 NumImpUses = N - I;
79 break;
80 }
81
82 return N;
83 }
84
85 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
86 /// implicit physical register output.
87 void InstrEmitter::
EmitCopyFromReg(SDNode * Node,unsigned ResNo,bool IsClone,bool IsCloned,Register SrcReg,DenseMap<SDValue,Register> & VRBaseMap)88 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
89 Register SrcReg, DenseMap<SDValue, Register> &VRBaseMap) {
90 Register VRBase;
91 if (SrcReg.isVirtual()) {
92 // Just use the input register directly!
93 SDValue Op(Node, ResNo);
94 if (IsClone)
95 VRBaseMap.erase(Op);
96 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
97 (void)isNew; // Silence compiler warning.
98 assert(isNew && "Node emitted out of order - early");
99 return;
100 }
101
102 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
103 // the CopyToReg'd destination register instead of creating a new vreg.
104 bool MatchReg = true;
105 const TargetRegisterClass *UseRC = nullptr;
106 MVT VT = Node->getSimpleValueType(ResNo);
107
108 // Stick to the preferred register classes for legal types.
109 if (TLI->isTypeLegal(VT))
110 UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
111
112 if (!IsClone && !IsCloned)
113 for (SDNode *User : Node->uses()) {
114 bool Match = true;
115 if (User->getOpcode() == ISD::CopyToReg &&
116 User->getOperand(2).getNode() == Node &&
117 User->getOperand(2).getResNo() == ResNo) {
118 Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
119 if (DestReg.isVirtual()) {
120 VRBase = DestReg;
121 Match = false;
122 } else if (DestReg != SrcReg)
123 Match = false;
124 } else {
125 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
126 SDValue Op = User->getOperand(i);
127 if (Op.getNode() != Node || Op.getResNo() != ResNo)
128 continue;
129 MVT VT = Node->getSimpleValueType(Op.getResNo());
130 if (VT == MVT::Other || VT == MVT::Glue)
131 continue;
132 Match = false;
133 if (User->isMachineOpcode()) {
134 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
135 const TargetRegisterClass *RC = nullptr;
136 if (i+II.getNumDefs() < II.getNumOperands()) {
137 RC = TRI->getAllocatableClass(
138 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
139 }
140 if (!UseRC)
141 UseRC = RC;
142 else if (RC) {
143 const TargetRegisterClass *ComRC =
144 TRI->getCommonSubClass(UseRC, RC);
145 // If multiple uses expect disjoint register classes, we emit
146 // copies in AddRegisterOperand.
147 if (ComRC)
148 UseRC = ComRC;
149 }
150 }
151 }
152 }
153 MatchReg &= Match;
154 if (VRBase)
155 break;
156 }
157
158 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
159 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
160
161 // Figure out the register class to create for the destreg.
162 if (VRBase) {
163 DstRC = MRI->getRegClass(VRBase);
164 } else if (UseRC) {
165 assert(TRI->isTypeLegalForClass(*UseRC, VT) &&
166 "Incompatible phys register def and uses!");
167 DstRC = UseRC;
168 } else {
169 DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
170 }
171
172 // If all uses are reading from the src physical register and copying the
173 // register is either impossible or very expensive, then don't create a copy.
174 if (MatchReg && SrcRC->getCopyCost() < 0) {
175 VRBase = SrcReg;
176 } else {
177 // Create the reg, emit the copy.
178 VRBase = MRI->createVirtualRegister(DstRC);
179 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
180 VRBase).addReg(SrcReg);
181 }
182
183 SDValue Op(Node, ResNo);
184 if (IsClone)
185 VRBaseMap.erase(Op);
186 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
187 (void)isNew; // Silence compiler warning.
188 assert(isNew && "Node emitted out of order - early");
189 }
190
CreateVirtualRegisters(SDNode * Node,MachineInstrBuilder & MIB,const MCInstrDesc & II,bool IsClone,bool IsCloned,DenseMap<SDValue,Register> & VRBaseMap)191 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
192 MachineInstrBuilder &MIB,
193 const MCInstrDesc &II,
194 bool IsClone, bool IsCloned,
195 DenseMap<SDValue, Register> &VRBaseMap) {
196 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
197 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
198
199 unsigned NumResults = CountResults(Node);
200 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
201 II.isVariadic() && II.variadicOpsAreDefs();
202 unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.getNumDefs();
203 if (Node->getMachineOpcode() == TargetOpcode::STATEPOINT)
204 NumVRegs = NumResults;
205 for (unsigned i = 0; i < NumVRegs; ++i) {
206 // If the specific node value is only used by a CopyToReg and the dest reg
207 // is a vreg in the same register class, use the CopyToReg'd destination
208 // register instead of creating a new vreg.
209 Register VRBase;
210 const TargetRegisterClass *RC =
211 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
212 // Always let the value type influence the used register class. The
213 // constraints on the instruction may be too lax to represent the value
214 // type correctly. For example, a 64-bit float (X86::FR64) can't live in
215 // the 32-bit float super-class (X86::FR32).
216 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
217 const TargetRegisterClass *VTRC = TLI->getRegClassFor(
218 Node->getSimpleValueType(i),
219 (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
220 if (RC)
221 VTRC = TRI->getCommonSubClass(RC, VTRC);
222 if (VTRC)
223 RC = VTRC;
224 }
225
226 if (II.OpInfo != nullptr && II.OpInfo[i].isOptionalDef()) {
227 // Optional def must be a physical register.
228 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
229 assert(VRBase.isPhysical());
230 MIB.addReg(VRBase, RegState::Define);
231 }
232
233 if (!VRBase && !IsClone && !IsCloned)
234 for (SDNode *User : Node->uses()) {
235 if (User->getOpcode() == ISD::CopyToReg &&
236 User->getOperand(2).getNode() == Node &&
237 User->getOperand(2).getResNo() == i) {
238 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
239 if (Register::isVirtualRegister(Reg)) {
240 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
241 if (RegRC == RC) {
242 VRBase = Reg;
243 MIB.addReg(VRBase, RegState::Define);
244 break;
245 }
246 }
247 }
248 }
249
250 // Create the result registers for this node and add the result regs to
251 // the machine instruction.
252 if (VRBase == 0) {
253 assert(RC && "Isn't a register operand!");
254 VRBase = MRI->createVirtualRegister(RC);
255 MIB.addReg(VRBase, RegState::Define);
256 }
257
258 // If this def corresponds to a result of the SDNode insert the VRBase into
259 // the lookup map.
260 if (i < NumResults) {
261 SDValue Op(Node, i);
262 if (IsClone)
263 VRBaseMap.erase(Op);
264 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
265 (void)isNew; // Silence compiler warning.
266 assert(isNew && "Node emitted out of order - early");
267 }
268 }
269 }
270
271 /// getVR - Return the virtual register corresponding to the specified result
272 /// of the specified node.
getVR(SDValue Op,DenseMap<SDValue,Register> & VRBaseMap)273 Register InstrEmitter::getVR(SDValue Op,
274 DenseMap<SDValue, Register> &VRBaseMap) {
275 if (Op.isMachineOpcode() &&
276 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
277 // Add an IMPLICIT_DEF instruction before every use.
278 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
279 // does not include operand register class info.
280 const TargetRegisterClass *RC = TLI->getRegClassFor(
281 Op.getSimpleValueType(), Op.getNode()->isDivergent());
282 Register VReg = MRI->createVirtualRegister(RC);
283 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
284 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
285 return VReg;
286 }
287
288 DenseMap<SDValue, Register>::iterator I = VRBaseMap.find(Op);
289 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
290 return I->second;
291 }
292
293
294 /// AddRegisterOperand - Add the specified register as an operand to the
295 /// specified machine instr. Insert register copies if the register is
296 /// not in the required register class.
297 void
AddRegisterOperand(MachineInstrBuilder & MIB,SDValue Op,unsigned IIOpNum,const MCInstrDesc * II,DenseMap<SDValue,Register> & VRBaseMap,bool IsDebug,bool IsClone,bool IsCloned)298 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
299 SDValue Op,
300 unsigned IIOpNum,
301 const MCInstrDesc *II,
302 DenseMap<SDValue, Register> &VRBaseMap,
303 bool IsDebug, bool IsClone, bool IsCloned) {
304 assert(Op.getValueType() != MVT::Other &&
305 Op.getValueType() != MVT::Glue &&
306 "Chain and glue operands should occur at end of operand list!");
307 // Get/emit the operand.
308 Register VReg = getVR(Op, VRBaseMap);
309
310 const MCInstrDesc &MCID = MIB->getDesc();
311 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
312 MCID.OpInfo[IIOpNum].isOptionalDef();
313
314 // If the instruction requires a register in a different class, create
315 // a new virtual register and copy the value into it, but first attempt to
316 // shrink VReg's register class within reason. For example, if VReg == GR32
317 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
318 if (II) {
319 const TargetRegisterClass *OpRC = nullptr;
320 if (IIOpNum < II->getNumOperands())
321 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
322
323 if (OpRC) {
324 const TargetRegisterClass *ConstrainedRC
325 = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
326 if (!ConstrainedRC) {
327 OpRC = TRI->getAllocatableClass(OpRC);
328 assert(OpRC && "Constraints cannot be fulfilled for allocation");
329 Register NewVReg = MRI->createVirtualRegister(OpRC);
330 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
331 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
332 VReg = NewVReg;
333 } else {
334 assert(ConstrainedRC->isAllocatable() &&
335 "Constraining an allocatable VReg produced an unallocatable class?");
336 }
337 }
338 }
339
340 // If this value has only one use, that use is a kill. This is a
341 // conservative approximation. InstrEmitter does trivial coalescing
342 // with CopyFromReg nodes, so don't emit kill flags for them.
343 // Avoid kill flags on Schedule cloned nodes, since there will be
344 // multiple uses.
345 // Tied operands are never killed, so we need to check that. And that
346 // means we need to determine the index of the operand.
347 bool isKill = Op.hasOneUse() &&
348 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
349 !IsDebug &&
350 !(IsClone || IsCloned);
351 if (isKill) {
352 unsigned Idx = MIB->getNumOperands();
353 while (Idx > 0 &&
354 MIB->getOperand(Idx-1).isReg() &&
355 MIB->getOperand(Idx-1).isImplicit())
356 --Idx;
357 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
358 if (isTied)
359 isKill = false;
360 }
361
362 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
363 getDebugRegState(IsDebug));
364 }
365
366 /// AddOperand - Add the specified operand to the specified machine instr. II
367 /// specifies the instruction information for the node, and IIOpNum is the
368 /// operand number (in the II) that we are adding.
AddOperand(MachineInstrBuilder & MIB,SDValue Op,unsigned IIOpNum,const MCInstrDesc * II,DenseMap<SDValue,Register> & VRBaseMap,bool IsDebug,bool IsClone,bool IsCloned)369 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
370 SDValue Op,
371 unsigned IIOpNum,
372 const MCInstrDesc *II,
373 DenseMap<SDValue, Register> &VRBaseMap,
374 bool IsDebug, bool IsClone, bool IsCloned) {
375 if (Op.isMachineOpcode()) {
376 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
377 IsDebug, IsClone, IsCloned);
378 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
379 MIB.addImm(C->getSExtValue());
380 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
381 MIB.addFPImm(F->getConstantFPValue());
382 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
383 Register VReg = R->getReg();
384 MVT OpVT = Op.getSimpleValueType();
385 const TargetRegisterClass *IIRC =
386 II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
387 : nullptr;
388 const TargetRegisterClass *OpRC =
389 TLI->isTypeLegal(OpVT)
390 ? TLI->getRegClassFor(OpVT,
391 Op.getNode()->isDivergent() ||
392 (IIRC && TRI->isDivergentRegClass(IIRC)))
393 : nullptr;
394
395 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) {
396 Register NewVReg = MRI->createVirtualRegister(IIRC);
397 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
398 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
399 VReg = NewVReg;
400 }
401 // Turn additional physreg operands into implicit uses on non-variadic
402 // instructions. This is used by call and return instructions passing
403 // arguments in registers.
404 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
405 MIB.addReg(VReg, getImplRegState(Imp));
406 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
407 MIB.addRegMask(RM->getRegMask());
408 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
409 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
410 TGA->getTargetFlags());
411 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
412 MIB.addMBB(BBNode->getBasicBlock());
413 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
414 MIB.addFrameIndex(FI->getIndex());
415 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
416 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
417 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
418 int Offset = CP->getOffset();
419 Align Alignment = CP->getAlign();
420
421 unsigned Idx;
422 MachineConstantPool *MCP = MF->getConstantPool();
423 if (CP->isMachineConstantPoolEntry())
424 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Alignment);
425 else
426 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Alignment);
427 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
428 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
429 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
430 } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
431 MIB.addSym(SymNode->getMCSymbol());
432 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
433 MIB.addBlockAddress(BA->getBlockAddress(),
434 BA->getOffset(),
435 BA->getTargetFlags());
436 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
437 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
438 } else {
439 assert(Op.getValueType() != MVT::Other &&
440 Op.getValueType() != MVT::Glue &&
441 "Chain and glue operands should occur at end of operand list!");
442 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
443 IsDebug, IsClone, IsCloned);
444 }
445 }
446
ConstrainForSubReg(Register VReg,unsigned SubIdx,MVT VT,bool isDivergent,const DebugLoc & DL)447 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
448 MVT VT, bool isDivergent, const DebugLoc &DL) {
449 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
450 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
451
452 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
453 // within reason.
454 if (RC && RC != VRC)
455 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
456
457 // VReg has been adjusted. It can be used with SubIdx operands now.
458 if (RC)
459 return VReg;
460
461 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
462 // register instead.
463 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
464 assert(RC && "No legal register class for VT supports that SubIdx");
465 Register NewReg = MRI->createVirtualRegister(RC);
466 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
467 .addReg(VReg);
468 return NewReg;
469 }
470
471 /// EmitSubregNode - Generate machine code for subreg nodes.
472 ///
EmitSubregNode(SDNode * Node,DenseMap<SDValue,Register> & VRBaseMap,bool IsClone,bool IsCloned)473 void InstrEmitter::EmitSubregNode(SDNode *Node,
474 DenseMap<SDValue, Register> &VRBaseMap,
475 bool IsClone, bool IsCloned) {
476 Register VRBase;
477 unsigned Opc = Node->getMachineOpcode();
478
479 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
480 // the CopyToReg'd destination register instead of creating a new vreg.
481 for (SDNode *User : Node->uses()) {
482 if (User->getOpcode() == ISD::CopyToReg &&
483 User->getOperand(2).getNode() == Node) {
484 Register DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
485 if (DestReg.isVirtual()) {
486 VRBase = DestReg;
487 break;
488 }
489 }
490 }
491
492 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
493 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
494 // constraints on the %dst register, COPY can target all legal register
495 // classes.
496 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
497 const TargetRegisterClass *TRC =
498 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
499
500 Register Reg;
501 MachineInstr *DefMI;
502 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
503 if (R && Register::isPhysicalRegister(R->getReg())) {
504 Reg = R->getReg();
505 DefMI = nullptr;
506 } else {
507 Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
508 DefMI = MRI->getVRegDef(Reg);
509 }
510
511 Register SrcReg, DstReg;
512 unsigned DefSubIdx;
513 if (DefMI &&
514 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
515 SubIdx == DefSubIdx &&
516 TRC == MRI->getRegClass(SrcReg)) {
517 // Optimize these:
518 // r1025 = s/zext r1024, 4
519 // r1026 = extract_subreg r1025, 4
520 // to a copy
521 // r1026 = copy r1024
522 VRBase = MRI->createVirtualRegister(TRC);
523 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
524 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
525 MRI->clearKillFlags(SrcReg);
526 } else {
527 // Reg may not support a SubIdx sub-register, and we may need to
528 // constrain its register class or issue a COPY to a compatible register
529 // class.
530 if (Reg.isVirtual())
531 Reg = ConstrainForSubReg(Reg, SubIdx,
532 Node->getOperand(0).getSimpleValueType(),
533 Node->isDivergent(), Node->getDebugLoc());
534 // Create the destreg if it is missing.
535 if (!VRBase)
536 VRBase = MRI->createVirtualRegister(TRC);
537
538 // Create the extract_subreg machine instruction.
539 MachineInstrBuilder CopyMI =
540 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
541 TII->get(TargetOpcode::COPY), VRBase);
542 if (Reg.isVirtual())
543 CopyMI.addReg(Reg, 0, SubIdx);
544 else
545 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
546 }
547 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
548 Opc == TargetOpcode::SUBREG_TO_REG) {
549 SDValue N0 = Node->getOperand(0);
550 SDValue N1 = Node->getOperand(1);
551 SDValue N2 = Node->getOperand(2);
552 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
553
554 // Figure out the register class to create for the destreg. It should be
555 // the largest legal register class supporting SubIdx sub-registers.
556 // RegisterCoalescer will constrain it further if it decides to eliminate
557 // the INSERT_SUBREG instruction.
558 //
559 // %dst = INSERT_SUBREG %src, %sub, SubIdx
560 //
561 // is lowered by TwoAddressInstructionPass to:
562 //
563 // %dst = COPY %src
564 // %dst:SubIdx = COPY %sub
565 //
566 // There is no constraint on the %src register class.
567 //
568 const TargetRegisterClass *SRC =
569 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
570 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
571 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
572
573 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
574 VRBase = MRI->createVirtualRegister(SRC);
575
576 // Create the insert_subreg or subreg_to_reg machine instruction.
577 MachineInstrBuilder MIB =
578 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
579
580 // If creating a subreg_to_reg, then the first input operand
581 // is an implicit value immediate, otherwise it's a register
582 if (Opc == TargetOpcode::SUBREG_TO_REG) {
583 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
584 MIB.addImm(SD->getZExtValue());
585 } else
586 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
587 IsClone, IsCloned);
588 // Add the subregister being inserted
589 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
590 IsClone, IsCloned);
591 MIB.addImm(SubIdx);
592 MBB->insert(InsertPos, MIB);
593 } else
594 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
595
596 SDValue Op(Node, 0);
597 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
598 (void)isNew; // Silence compiler warning.
599 assert(isNew && "Node emitted out of order - early");
600 }
601
602 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
603 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
604 /// register is constrained to be in a particular register class.
605 ///
606 void
EmitCopyToRegClassNode(SDNode * Node,DenseMap<SDValue,Register> & VRBaseMap)607 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
608 DenseMap<SDValue, Register> &VRBaseMap) {
609 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
610
611 // Create the new VReg in the destination class and emit a copy.
612 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
613 const TargetRegisterClass *DstRC =
614 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
615 Register NewVReg = MRI->createVirtualRegister(DstRC);
616 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
617 NewVReg).addReg(VReg);
618
619 SDValue Op(Node, 0);
620 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
621 (void)isNew; // Silence compiler warning.
622 assert(isNew && "Node emitted out of order - early");
623 }
624
625 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
626 ///
EmitRegSequence(SDNode * Node,DenseMap<SDValue,Register> & VRBaseMap,bool IsClone,bool IsCloned)627 void InstrEmitter::EmitRegSequence(SDNode *Node,
628 DenseMap<SDValue, Register> &VRBaseMap,
629 bool IsClone, bool IsCloned) {
630 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
631 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
632 Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
633 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
634 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
635 unsigned NumOps = Node->getNumOperands();
636 // If the input pattern has a chain, then the root of the corresponding
637 // output pattern will get a chain as well. This can happen to be a
638 // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
639 if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
640 --NumOps; // Ignore chain if it exists.
641
642 assert((NumOps & 1) == 1 &&
643 "REG_SEQUENCE must have an odd number of operands!");
644 for (unsigned i = 1; i != NumOps; ++i) {
645 SDValue Op = Node->getOperand(i);
646 if ((i & 1) == 0) {
647 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
648 // Skip physical registers as they don't have a vreg to get and we'll
649 // insert copies for them in TwoAddressInstructionPass anyway.
650 if (!R || !Register::isPhysicalRegister(R->getReg())) {
651 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
652 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
653 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
654 const TargetRegisterClass *SRC =
655 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
656 if (SRC && SRC != RC) {
657 MRI->setRegClass(NewVReg, SRC);
658 RC = SRC;
659 }
660 }
661 }
662 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
663 IsClone, IsCloned);
664 }
665
666 MBB->insert(InsertPos, MIB);
667 SDValue Op(Node, 0);
668 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
669 (void)isNew; // Silence compiler warning.
670 assert(isNew && "Node emitted out of order - early");
671 }
672
673 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
674 ///
675 MachineInstr *
EmitDbgValue(SDDbgValue * SD,DenseMap<SDValue,Register> & VRBaseMap)676 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
677 DenseMap<SDValue, Register> &VRBaseMap) {
678 MDNode *Var = SD->getVariable();
679 MDNode *Expr = SD->getExpression();
680 DebugLoc DL = SD->getDebugLoc();
681 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
682 "Expected inlined-at fields to agree");
683
684 SD->setIsEmitted();
685
686 if (SD->isInvalidated()) {
687 // An invalidated SDNode must generate an undef DBG_VALUE: although the
688 // original value is no longer computed, earlier DBG_VALUEs live ranges
689 // must not leak into later code.
690 auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
691 MIB.addReg(0U);
692 MIB.addReg(0U, RegState::Debug);
693 MIB.addMetadata(Var);
694 MIB.addMetadata(Expr);
695 return &*MIB;
696 }
697
698 // Attempt to produce a DBG_INSTR_REF if we've been asked to.
699 if (EmitDebugInstrRefs)
700 if (auto *InstrRef = EmitDbgInstrRef(SD, VRBaseMap))
701 return InstrRef;
702
703 if (SD->getKind() == SDDbgValue::FRAMEIX) {
704 // Stack address; this needs to be lowered in target-dependent fashion.
705 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
706 auto FrameMI = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
707 .addFrameIndex(SD->getFrameIx());
708 if (SD->isIndirect())
709 // Push [fi + 0] onto the DIExpression stack.
710 FrameMI.addImm(0);
711 else
712 // Push fi onto the DIExpression stack.
713 FrameMI.addReg(0);
714 return FrameMI.addMetadata(Var).addMetadata(Expr);
715 }
716 // Otherwise, we're going to create an instruction here.
717 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
718 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
719 if (SD->getKind() == SDDbgValue::SDNODE) {
720 SDNode *Node = SD->getSDNode();
721 SDValue Op = SDValue(Node, SD->getResNo());
722 // It's possible we replaced this SDNode with other(s) and therefore
723 // didn't generate code for it. It's better to catch these cases where
724 // they happen and transfer the debug info, but trying to guarantee that
725 // in all cases would be very fragile; this is a safeguard for any
726 // that were missed.
727 DenseMap<SDValue, Register>::iterator I = VRBaseMap.find(Op);
728 if (I==VRBaseMap.end())
729 MIB.addReg(0U); // undef
730 else
731 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
732 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
733 } else if (SD->getKind() == SDDbgValue::VREG) {
734 MIB.addReg(SD->getVReg(), RegState::Debug);
735 } else if (SD->getKind() == SDDbgValue::CONST) {
736 const Value *V = SD->getConst();
737 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
738 if (CI->getBitWidth() > 64)
739 MIB.addCImm(CI);
740 else
741 MIB.addImm(CI->getSExtValue());
742 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
743 MIB.addFPImm(CF);
744 } else if (isa<ConstantPointerNull>(V)) {
745 // Note: This assumes that all nullptr constants are zero-valued.
746 MIB.addImm(0);
747 } else {
748 // Could be an Undef. In any case insert an Undef so we can see what we
749 // dropped.
750 MIB.addReg(0U);
751 }
752 } else {
753 // Insert an Undef so we can see what we dropped.
754 MIB.addReg(0U);
755 }
756
757 // Indirect addressing is indicated by an Imm as the second parameter.
758 if (SD->isIndirect())
759 MIB.addImm(0U);
760 else
761 MIB.addReg(0U, RegState::Debug);
762
763 MIB.addMetadata(Var);
764 MIB.addMetadata(Expr);
765
766 return &*MIB;
767 }
768
769 MachineInstr *
EmitDbgInstrRef(SDDbgValue * SD,DenseMap<SDValue,Register> & VRBaseMap)770 InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
771 DenseMap<SDValue, Register> &VRBaseMap) {
772 // Instruction referencing is still in a prototype state: for now we're only
773 // going to support SDNodes within a block. Copies are not supported, they
774 // don't actually define a value.
775 if (SD->getKind() != SDDbgValue::SDNODE)
776 return nullptr;
777
778 SDNode *Node = SD->getSDNode();
779 SDValue Op = SDValue(Node, SD->getResNo());
780 DenseMap<SDValue, Register>::iterator I = VRBaseMap.find(Op);
781 if (I==VRBaseMap.end())
782 return nullptr; // undef value: let EmitDbgValue produce a DBG_VALUE $noreg.
783
784 MDNode *Var = SD->getVariable();
785 MDNode *Expr = SD->getExpression();
786 DebugLoc DL = SD->getDebugLoc();
787
788 // Try to pick out a defining instruction at this point.
789 unsigned VReg = getVR(Op, VRBaseMap);
790 MachineInstr *ResultInstr = nullptr;
791
792 // No definition corresponds to scenarios where a vreg is live-in to a block,
793 // and doesn't have a defining instruction (yet). This can be patched up
794 // later; at this early stage of implementation, fall back to using DBG_VALUE.
795 if (!MRI->hasOneDef(VReg))
796 return nullptr;
797
798 MachineInstr &DefMI = *MRI->def_instr_begin(VReg);
799 // Some target specific opcodes can become copies. As stated above, we're
800 // ignoring those for now.
801 if (DefMI.isCopy() || DefMI.getOpcode() == TargetOpcode::SUBREG_TO_REG)
802 return nullptr;
803
804 const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF);
805 auto MIB = BuildMI(*MF, DL, RefII);
806
807 // Find the operand which defines the specified VReg.
808 unsigned OperandIdx = 0;
809 for (const auto &MO : DefMI.operands()) {
810 if (MO.isReg() && MO.isDef() && MO.getReg() == VReg)
811 break;
812 ++OperandIdx;
813 }
814 assert(OperandIdx < DefMI.getNumOperands());
815
816 // Make the DBG_INSTR_REF refer to that instruction, and that operand.
817 unsigned InstrNum = DefMI.getDebugInstrNum();
818 MIB.addImm(InstrNum);
819 MIB.addImm(OperandIdx);
820 MIB.addMetadata(Var);
821 MIB.addMetadata(Expr);
822 ResultInstr = &*MIB;
823 return ResultInstr;
824 }
825
826 MachineInstr *
EmitDbgLabel(SDDbgLabel * SD)827 InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
828 MDNode *Label = SD->getLabel();
829 DebugLoc DL = SD->getDebugLoc();
830 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&
831 "Expected inlined-at fields to agree");
832
833 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
834 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
835 MIB.addMetadata(Label);
836
837 return &*MIB;
838 }
839
840 /// EmitMachineNode - Generate machine code for a target-specific node and
841 /// needed dependencies.
842 ///
843 void InstrEmitter::
EmitMachineNode(SDNode * Node,bool IsClone,bool IsCloned,DenseMap<SDValue,Register> & VRBaseMap)844 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
845 DenseMap<SDValue, Register> &VRBaseMap) {
846 unsigned Opc = Node->getMachineOpcode();
847
848 // Handle subreg insert/extract specially
849 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
850 Opc == TargetOpcode::INSERT_SUBREG ||
851 Opc == TargetOpcode::SUBREG_TO_REG) {
852 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
853 return;
854 }
855
856 // Handle COPY_TO_REGCLASS specially.
857 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
858 EmitCopyToRegClassNode(Node, VRBaseMap);
859 return;
860 }
861
862 // Handle REG_SEQUENCE specially.
863 if (Opc == TargetOpcode::REG_SEQUENCE) {
864 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
865 return;
866 }
867
868 if (Opc == TargetOpcode::IMPLICIT_DEF)
869 // We want a unique VR for each IMPLICIT_DEF use.
870 return;
871
872 const MCInstrDesc &II = TII->get(Opc);
873 unsigned NumResults = CountResults(Node);
874 unsigned NumDefs = II.getNumDefs();
875 const MCPhysReg *ScratchRegs = nullptr;
876
877 // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
878 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
879 // Stackmaps do not have arguments and do not preserve their calling
880 // convention. However, to simplify runtime support, they clobber the same
881 // scratch registers as AnyRegCC.
882 unsigned CC = CallingConv::AnyReg;
883 if (Opc == TargetOpcode::PATCHPOINT) {
884 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
885 NumDefs = NumResults;
886 }
887 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
888 } else if (Opc == TargetOpcode::STATEPOINT) {
889 NumDefs = NumResults;
890 }
891
892 unsigned NumImpUses = 0;
893 unsigned NodeOperands =
894 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
895 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
896 II.isVariadic() && II.variadicOpsAreDefs();
897 bool HasPhysRegOuts = NumResults > NumDefs &&
898 II.getImplicitDefs() != nullptr && !HasVRegVariadicDefs;
899 #ifndef NDEBUG
900 unsigned NumMIOperands = NodeOperands + NumResults;
901 if (II.isVariadic())
902 assert(NumMIOperands >= II.getNumOperands() &&
903 "Too few operands for a variadic node!");
904 else
905 assert(NumMIOperands >= II.getNumOperands() &&
906 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
907 NumImpUses &&
908 "#operands for dag node doesn't match .td file!");
909 #endif
910
911 // Create the new machine instruction.
912 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
913
914 // Add result register values for things that are defined by this
915 // instruction.
916 if (NumResults) {
917 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
918
919 // Transfer any IR flags from the SDNode to the MachineInstr
920 MachineInstr *MI = MIB.getInstr();
921 const SDNodeFlags Flags = Node->getFlags();
922 if (Flags.hasNoSignedZeros())
923 MI->setFlag(MachineInstr::MIFlag::FmNsz);
924
925 if (Flags.hasAllowReciprocal())
926 MI->setFlag(MachineInstr::MIFlag::FmArcp);
927
928 if (Flags.hasNoNaNs())
929 MI->setFlag(MachineInstr::MIFlag::FmNoNans);
930
931 if (Flags.hasNoInfs())
932 MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
933
934 if (Flags.hasAllowContract())
935 MI->setFlag(MachineInstr::MIFlag::FmContract);
936
937 if (Flags.hasApproximateFuncs())
938 MI->setFlag(MachineInstr::MIFlag::FmAfn);
939
940 if (Flags.hasAllowReassociation())
941 MI->setFlag(MachineInstr::MIFlag::FmReassoc);
942
943 if (Flags.hasNoUnsignedWrap())
944 MI->setFlag(MachineInstr::MIFlag::NoUWrap);
945
946 if (Flags.hasNoSignedWrap())
947 MI->setFlag(MachineInstr::MIFlag::NoSWrap);
948
949 if (Flags.hasExact())
950 MI->setFlag(MachineInstr::MIFlag::IsExact);
951
952 if (Flags.hasNoFPExcept())
953 MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
954 }
955
956 // Emit all of the actual operands of this instruction, adding them to the
957 // instruction as appropriate.
958 bool HasOptPRefs = NumDefs > NumResults;
959 assert((!HasOptPRefs || !HasPhysRegOuts) &&
960 "Unable to cope with optional defs and phys regs defs!");
961 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
962 for (unsigned i = NumSkip; i != NodeOperands; ++i)
963 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
964 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
965
966 // Add scratch registers as implicit def and early clobber
967 if (ScratchRegs)
968 for (unsigned i = 0; ScratchRegs[i]; ++i)
969 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
970 RegState::EarlyClobber);
971
972 // Set the memory reference descriptions of this instruction now that it is
973 // part of the function.
974 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
975
976 // Insert the instruction into position in the block. This needs to
977 // happen before any custom inserter hook is called so that the
978 // hook knows where in the block to insert the replacement code.
979 MBB->insert(InsertPos, MIB);
980
981 // The MachineInstr may also define physregs instead of virtregs. These
982 // physreg values can reach other instructions in different ways:
983 //
984 // 1. When there is a use of a Node value beyond the explicitly defined
985 // virtual registers, we emit a CopyFromReg for one of the implicitly
986 // defined physregs. This only happens when HasPhysRegOuts is true.
987 //
988 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
989 //
990 // 3. A glued instruction may implicitly use a physreg.
991 //
992 // 4. A glued instruction may use a RegisterSDNode operand.
993 //
994 // Collect all the used physreg defs, and make sure that any unused physreg
995 // defs are marked as dead.
996 SmallVector<Register, 8> UsedRegs;
997
998 // Additional results must be physical register defs.
999 if (HasPhysRegOuts) {
1000 for (unsigned i = NumDefs; i < NumResults; ++i) {
1001 Register Reg = II.getImplicitDefs()[i - NumDefs];
1002 if (!Node->hasAnyUseOfValue(i))
1003 continue;
1004 // This implicitly defined physreg has a use.
1005 UsedRegs.push_back(Reg);
1006 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
1007 }
1008 }
1009
1010 // Scan the glue chain for any used physregs.
1011 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
1012 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
1013 if (F->getOpcode() == ISD::CopyFromReg) {
1014 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
1015 continue;
1016 } else if (F->getOpcode() == ISD::CopyToReg) {
1017 // Skip CopyToReg nodes that are internal to the glue chain.
1018 continue;
1019 }
1020 // Collect declared implicit uses.
1021 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
1022 UsedRegs.append(MCID.getImplicitUses(),
1023 MCID.getImplicitUses() + MCID.getNumImplicitUses());
1024 // In addition to declared implicit uses, we must also check for
1025 // direct RegisterSDNode operands.
1026 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
1027 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
1028 Register Reg = R->getReg();
1029 if (Reg.isPhysical())
1030 UsedRegs.push_back(Reg);
1031 }
1032 }
1033 }
1034
1035 // Finally mark unused registers as dead.
1036 if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
1037 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
1038
1039 // STATEPOINT is too 'dynamic' to have meaningful machine description.
1040 // We have to manually tie operands.
1041 if (Opc == TargetOpcode::STATEPOINT && NumDefs > 0) {
1042 assert(!HasPhysRegOuts && "STATEPOINT mishandled");
1043 MachineInstr *MI = MIB;
1044 unsigned Def = 0;
1045 int First = StatepointOpers(MI).getFirstGCPtrIdx();
1046 assert(First > 0 && "Statepoint has Defs but no GC ptr list");
1047 unsigned Use = (unsigned)First;
1048 while (Def < NumDefs) {
1049 if (MI->getOperand(Use).isReg())
1050 MI->tieOperands(Def++, Use);
1051 Use = StackMaps::getNextMetaArgIdx(MI, Use);
1052 }
1053 }
1054
1055 // Run post-isel target hook to adjust this instruction if needed.
1056 if (II.hasPostISelHook())
1057 TLI->AdjustInstrPostInstrSelection(*MIB, Node);
1058 }
1059
1060 /// EmitSpecialNode - Generate machine code for a target-independent node and
1061 /// needed dependencies.
1062 void InstrEmitter::
EmitSpecialNode(SDNode * Node,bool IsClone,bool IsCloned,DenseMap<SDValue,Register> & VRBaseMap)1063 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
1064 DenseMap<SDValue, Register> &VRBaseMap) {
1065 switch (Node->getOpcode()) {
1066 default:
1067 #ifndef NDEBUG
1068 Node->dump();
1069 #endif
1070 llvm_unreachable("This target-independent node should have been selected!");
1071 case ISD::EntryToken:
1072 llvm_unreachable("EntryToken should have been excluded from the schedule!");
1073 case ISD::MERGE_VALUES:
1074 case ISD::TokenFactor: // fall thru
1075 break;
1076 case ISD::CopyToReg: {
1077 Register DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1078 SDValue SrcVal = Node->getOperand(2);
1079 if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&
1080 SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
1081 // Instead building a COPY to that vreg destination, build an
1082 // IMPLICIT_DEF instruction instead.
1083 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1084 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1085 break;
1086 }
1087 Register SrcReg;
1088 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
1089 SrcReg = R->getReg();
1090 else
1091 SrcReg = getVR(SrcVal, VRBaseMap);
1092
1093 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1094 break;
1095
1096 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1097 DestReg).addReg(SrcReg);
1098 break;
1099 }
1100 case ISD::CopyFromReg: {
1101 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1102 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1103 break;
1104 }
1105 case ISD::EH_LABEL:
1106 case ISD::ANNOTATION_LABEL: {
1107 unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1108 ? TargetOpcode::EH_LABEL
1109 : TargetOpcode::ANNOTATION_LABEL;
1110 MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1111 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1112 TII->get(Opc)).addSym(S);
1113 break;
1114 }
1115
1116 case ISD::LIFETIME_START:
1117 case ISD::LIFETIME_END: {
1118 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
1119 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
1120
1121 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
1122 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1123 .addFrameIndex(FI->getIndex());
1124 break;
1125 }
1126
1127 case ISD::INLINEASM:
1128 case ISD::INLINEASM_BR: {
1129 unsigned NumOps = Node->getNumOperands();
1130 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1131 --NumOps; // Ignore the glue operand.
1132
1133 // Create the inline asm machine instruction.
1134 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1135 ? TargetOpcode::INLINEASM_BR
1136 : TargetOpcode::INLINEASM;
1137 MachineInstrBuilder MIB =
1138 BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1139
1140 // Add the asm string as an external symbol operand.
1141 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1142 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1143 MIB.addExternalSymbol(AsmStr);
1144
1145 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1146 // bits.
1147 int64_t ExtraInfo =
1148 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1149 getZExtValue();
1150 MIB.addImm(ExtraInfo);
1151
1152 // Remember to operand index of the group flags.
1153 SmallVector<unsigned, 8> GroupIdx;
1154
1155 // Remember registers that are part of early-clobber defs.
1156 SmallVector<unsigned, 8> ECRegs;
1157
1158 // Add all of the operand registers to the instruction.
1159 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1160 unsigned Flags =
1161 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1162 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1163
1164 GroupIdx.push_back(MIB->getNumOperands());
1165 MIB.addImm(Flags);
1166 ++i; // Skip the ID value.
1167
1168 switch (InlineAsm::getKind(Flags)) {
1169 default: llvm_unreachable("Bad flags!");
1170 case InlineAsm::Kind_RegDef:
1171 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1172 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1173 // FIXME: Add dead flags for physical and virtual registers defined.
1174 // For now, mark physical register defs as implicit to help fast
1175 // regalloc. This makes inline asm look a lot like calls.
1176 MIB.addReg(Reg,
1177 RegState::Define |
1178 getImplRegState(Register::isPhysicalRegister(Reg)));
1179 }
1180 break;
1181 case InlineAsm::Kind_RegDefEarlyClobber:
1182 case InlineAsm::Kind_Clobber:
1183 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1184 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1185 MIB.addReg(Reg,
1186 RegState::Define | RegState::EarlyClobber |
1187 getImplRegState(Register::isPhysicalRegister(Reg)));
1188 ECRegs.push_back(Reg);
1189 }
1190 break;
1191 case InlineAsm::Kind_RegUse: // Use of register.
1192 case InlineAsm::Kind_Imm: // Immediate.
1193 case InlineAsm::Kind_Mem: // Addressing mode.
1194 // The addressing mode has been selected, just add all of the
1195 // operands to the machine instruction.
1196 for (unsigned j = 0; j != NumVals; ++j, ++i)
1197 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1198 /*IsDebug=*/false, IsClone, IsCloned);
1199
1200 // Manually set isTied bits.
1201 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
1202 unsigned DefGroup = 0;
1203 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1204 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1205 unsigned UseIdx = GroupIdx.back() + 1;
1206 for (unsigned j = 0; j != NumVals; ++j)
1207 MIB->tieOperands(DefIdx + j, UseIdx + j);
1208 }
1209 }
1210 break;
1211 }
1212 }
1213
1214 // GCC inline assembly allows input operands to also be early-clobber
1215 // output operands (so long as the operand is written only after it's
1216 // used), but this does not match the semantics of our early-clobber flag.
1217 // If an early-clobber operand register is also an input operand register,
1218 // then remove the early-clobber flag.
1219 for (unsigned Reg : ECRegs) {
1220 if (MIB->readsRegister(Reg, TRI)) {
1221 MachineOperand *MO =
1222 MIB->findRegisterDefOperand(Reg, false, false, TRI);
1223 assert(MO && "No def operand for clobbered register?");
1224 MO->setIsEarlyClobber(false);
1225 }
1226 }
1227
1228 // Get the mdnode from the asm if it exists and add it to the instruction.
1229 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1230 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1231 if (MD)
1232 MIB.addMetadata(MD);
1233
1234 MBB->insert(InsertPos, MIB);
1235 break;
1236 }
1237 }
1238 }
1239
1240 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1241 /// at the given position in the given block.
InstrEmitter(const TargetMachine & TM,MachineBasicBlock * mbb,MachineBasicBlock::iterator insertpos)1242 InstrEmitter::InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb,
1243 MachineBasicBlock::iterator insertpos)
1244 : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1245 TII(MF->getSubtarget().getInstrInfo()),
1246 TRI(MF->getSubtarget().getRegisterInfo()),
1247 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1248 InsertPos(insertpos) {
1249 EmitDebugInstrRefs = TM.Options.ValueTrackingVariableLocations;
1250 }
1251