1//===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the VSX extension to the PowerPC instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13// *********************************** NOTE *********************************** 14// ** For POWER8 Little Endian, the VSX swap optimization relies on knowing ** 15// ** which VMX and VSX instructions are lane-sensitive and which are not. ** 16// ** A lane-sensitive instruction relies, implicitly or explicitly, on ** 17// ** whether lanes are numbered from left to right. An instruction like ** 18// ** VADDFP is not lane-sensitive, because each lane of the result vector ** 19// ** relies only on the corresponding lane of the source vectors. However, ** 20// ** an instruction like VMULESB is lane-sensitive, because "even" and ** 21// ** "odd" lanes are different for big-endian and little-endian numbering. ** 22// ** ** 23// ** When adding new VMX and VSX instructions, please consider whether they ** 24// ** are lane-sensitive. If so, they must be added to a switch statement ** 25// ** in PPCVSXSwapRemoval::gatherVectorInstructions(). ** 26// **************************************************************************** 27 28// *********************************** NOTE *********************************** 29// ** When adding new anonymous patterns to this file, please add them to ** 30// ** the section titled Anonymous Patterns. Chances are that the existing ** 31// ** predicate blocks already contain a combination of features that you ** 32// ** are after. There is a list of blocks at the top of the section. If ** 33// ** you definitely need a new combination of predicates, please add that ** 34// ** combination to the list. ** 35// ** File Structure: ** 36// ** - Custom PPCISD node definitions ** 37// ** - Predicate definitions: predicates to specify the subtargets for ** 38// ** which an instruction or pattern can be emitted. ** 39// ** - Instruction formats: classes instantiated by the instructions. ** 40// ** These generally correspond to instruction formats in section 1.6 of ** 41// ** the ISA document. ** 42// ** - Instruction definitions: the actual definitions of the instructions ** 43// ** often including input patterns that they match. ** 44// ** - Helper DAG definitions: We define a number of dag objects to use as ** 45// ** input or output patterns for consciseness of the code. ** 46// ** - Anonymous patterns: input patterns that an instruction matches can ** 47// ** often not be specified as part of the instruction definition, so an ** 48// ** anonymous pattern must be specified mapping an input pattern to an ** 49// ** output pattern. These are generally guarded by subtarget predicates. ** 50// ** - Instruction aliases: used to define extended mnemonics for assembly ** 51// ** printing (for example: xxswapd for xxpermdi with 0x2 as the imm). ** 52// **************************************************************************** 53 54def PPCRegVSRCAsmOperand : AsmOperandClass { 55 let Name = "RegVSRC"; let PredicateMethod = "isVSRegNumber"; 56} 57def vsrc : RegisterOperand<VSRC> { 58 let ParserMatchClass = PPCRegVSRCAsmOperand; 59} 60 61def PPCRegVSFRCAsmOperand : AsmOperandClass { 62 let Name = "RegVSFRC"; let PredicateMethod = "isVSRegNumber"; 63} 64def vsfrc : RegisterOperand<VSFRC> { 65 let ParserMatchClass = PPCRegVSFRCAsmOperand; 66} 67 68def PPCRegVSSRCAsmOperand : AsmOperandClass { 69 let Name = "RegVSSRC"; let PredicateMethod = "isVSRegNumber"; 70} 71def vssrc : RegisterOperand<VSSRC> { 72 let ParserMatchClass = PPCRegVSSRCAsmOperand; 73} 74 75def PPCRegSPILLTOVSRRCAsmOperand : AsmOperandClass { 76 let Name = "RegSPILLTOVSRRC"; let PredicateMethod = "isVSRegNumber"; 77} 78 79def spilltovsrrc : RegisterOperand<SPILLTOVSRRC> { 80 let ParserMatchClass = PPCRegSPILLTOVSRRCAsmOperand; 81} 82 83def SDT_PPCldvsxlh : SDTypeProfile<1, 1, [ 84 SDTCisVT<0, v4f32>, SDTCisPtrTy<1> 85]>; 86 87def SDT_PPCfpexth : SDTypeProfile<1, 2, [ 88 SDTCisVT<0, v2f64>, SDTCisVT<1, v4f32>, SDTCisPtrTy<2> 89]>; 90 91def SDT_PPCldsplat : SDTypeProfile<1, 1, [ 92 SDTCisVec<0>, SDTCisPtrTy<1> 93]>; 94 95// Little-endian-specific nodes. 96def SDT_PPClxvd2x : SDTypeProfile<1, 1, [ 97 SDTCisVT<0, v2f64>, SDTCisPtrTy<1> 98]>; 99def SDT_PPCstxvd2x : SDTypeProfile<0, 2, [ 100 SDTCisVT<0, v2f64>, SDTCisPtrTy<1> 101]>; 102def SDT_PPCxxswapd : SDTypeProfile<1, 1, [ 103 SDTCisSameAs<0, 1> 104]>; 105def SDTVecConv : SDTypeProfile<1, 2, [ 106 SDTCisVec<0>, SDTCisVec<1>, SDTCisPtrTy<2> 107]>; 108def SDTVabsd : SDTypeProfile<1, 3, [ 109 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVT<3, i32> 110]>; 111def SDT_PPCld_vec_be : SDTypeProfile<1, 1, [ 112 SDTCisVec<0>, SDTCisPtrTy<1> 113]>; 114def SDT_PPCst_vec_be : SDTypeProfile<0, 2, [ 115 SDTCisVec<0>, SDTCisPtrTy<1> 116]>; 117 118//--------------------------- Custom PPC nodes -------------------------------// 119def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def PPCstxvd2x : SDNode<"PPCISD::STXVD2X", SDT_PPCstxvd2x, 122 [SDNPHasChain, SDNPMayStore]>; 123def PPCld_vec_be : SDNode<"PPCISD::LOAD_VEC_BE", SDT_PPCld_vec_be, 124 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 125def PPCst_vec_be : SDNode<"PPCISD::STORE_VEC_BE", SDT_PPCst_vec_be, 126 [SDNPHasChain, SDNPMayStore]>; 127def PPCxxswapd : SDNode<"PPCISD::XXSWAPD", SDT_PPCxxswapd, [SDNPHasChain]>; 128def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>; 129def PPCmtvsra : SDNode<"PPCISD::MTVSRA", SDTUnaryOp, []>; 130def PPCmtvsrz : SDNode<"PPCISD::MTVSRZ", SDTUnaryOp, []>; 131def PPCsvec2fp : SDNode<"PPCISD::SINT_VEC_TO_FP", SDTVecConv, []>; 132def PPCuvec2fp: SDNode<"PPCISD::UINT_VEC_TO_FP", SDTVecConv, []>; 133def PPCswapNoChain : SDNode<"PPCISD::SWAP_NO_CHAIN", SDT_PPCxxswapd>; 134def PPCvabsd : SDNode<"PPCISD::VABSD", SDTVabsd, []>; 135 136def PPCfpexth : SDNode<"PPCISD::FP_EXTEND_HALF", SDT_PPCfpexth, []>; 137def PPCldvsxlh : SDNode<"PPCISD::LD_VSX_LH", SDT_PPCldvsxlh, 138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 139def PPCldsplat : SDNode<"PPCISD::LD_SPLAT", SDT_PPCldsplat, 140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 141def PPCSToV : SDNode<"PPCISD::SCALAR_TO_VECTOR_PERMUTED", 142 SDTypeProfile<1, 1, []>, []>; 143 144//-------------------------- Predicate definitions ---------------------------// 145def HasVSX : Predicate<"Subtarget->hasVSX()">; 146def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">; 147def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">; 148def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">; 149def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">; 150def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">; 151def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">; 152def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">; 153def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">; 154 155//--------------------- VSX-specific instruction formats ---------------------// 156// By default, all VSX instructions are to be selected over their Altivec 157// counter parts and they do not have unmodeled sideeffects. 158let AddedComplexity = 400, hasSideEffects = 0 in { 159multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, string asmbase, 160 string asmstr, InstrItinClass itin, Intrinsic Int, 161 ValueType OutTy, ValueType InTy> { 162 let BaseName = asmbase in { 163 def NAME : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 164 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 165 [(set OutTy:$XT, (Int InTy:$XA, InTy:$XB))]>; 166 let Defs = [CR6] in 167 def _rec : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 168 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 169 [(set InTy:$XT, 170 (InTy (PPCvcmp_rec InTy:$XA, InTy:$XB, xo)))]>, 171 isRecordForm; 172 } 173} 174 175// Instruction form with a single input register for instructions such as 176// XXPERMDI. The reason for defining this is that specifying multiple chained 177// operands (such as loads) to an instruction will perform both chained 178// operations rather than coalescing them into a single register - even though 179// the source memory location is the same. This simply forces the instruction 180// to use the same register for both inputs. 181// For example, an output DAG such as this: 182// (XXPERMDI (LXSIBZX xoaddr:$src), (LXSIBZX xoaddr:$src ), 0)) 183// would result in two load instructions emitted and used as separate inputs 184// to the XXPERMDI instruction. 185class XX3Form_2s<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 186 InstrItinClass itin, list<dag> pattern> 187 : XX3Form_2<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 188 let XB = XA; 189} 190 191let Predicates = [HasVSX, HasP9Vector] in { 192class X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 193 list<dag> pattern> 194 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vrrc:$vB), 195 !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>; 196 197// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /] 198class X_VT5_XO5_VB5_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 199 list<dag> pattern> 200 : X_VT5_XO5_VB5<opcode, xo2, xo, opc, pattern>, isRecordForm; 201 202// [PO VRT XO VRB XO /], but the VRB is only used the left 64 bits (or less), 203// So we use different operand class for VRB 204class X_VT5_XO5_VB5_TyVB<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 205 RegisterOperand vbtype, list<dag> pattern> 206 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vbtype:$vB), 207 !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>; 208 209// [PO VRT XO VRB XO /] 210class X_VT5_XO5_VB5_VSFR<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 211 list<dag> pattern> 212 : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vfrc:$vT), (ins vrrc:$vB), 213 !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>; 214 215// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /] 216class X_VT5_XO5_VB5_VSFR_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc, 217 list<dag> pattern> 218 : X_VT5_XO5_VB5_VSFR<opcode, xo2, xo, opc, pattern>, isRecordForm; 219 220// [PO T XO B XO BX /] 221class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc, 222 list<dag> pattern> 223 : XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$rT), (ins vsfrc:$XB), 224 !strconcat(opc, " $rT, $XB"), IIC_VecFP, pattern>; 225 226// [PO T XO B XO BX TX] 227class XX2_XT6_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc, 228 RegisterOperand vtype, list<dag> pattern> 229 : XX2_RD6_XO5_RS6<opcode, xo2, xo, (outs vtype:$XT), (ins vtype:$XB), 230 !strconcat(opc, " $XT, $XB"), IIC_VecFP, pattern>; 231 232// [PO T A B XO AX BX TX], src and dest register use different operand class 233class XX3_XT5_XA5_XB5<bits<6> opcode, bits<8> xo, string opc, 234 RegisterOperand xty, RegisterOperand aty, RegisterOperand bty, 235 InstrItinClass itin, list<dag> pattern> 236 : XX3Form<opcode, xo, (outs xty:$XT), (ins aty:$XA, bty:$XB), 237 !strconcat(opc, " $XT, $XA, $XB"), itin, pattern>; 238 239// [PO VRT VRA VRB XO /] 240class X_VT5_VA5_VB5<bits<6> opcode, bits<10> xo, string opc, 241 list<dag> pattern> 242 : XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB), 243 !strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>; 244 245// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /] 246class X_VT5_VA5_VB5_Ro<bits<6> opcode, bits<10> xo, string opc, 247 list<dag> pattern> 248 : X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isRecordForm; 249 250// [PO VRT VRA VRB XO /] 251class X_VT5_VA5_VB5_FMA<bits<6> opcode, bits<10> xo, string opc, 252 list<dag> pattern> 253 : XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vTi, vrrc:$vA, vrrc:$vB), 254 !strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>, 255 RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">; 256 257// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /] 258class X_VT5_VA5_VB5_FMA_Ro<bits<6> opcode, bits<10> xo, string opc, 259 list<dag> pattern> 260 : X_VT5_VA5_VB5_FMA<opcode, xo, opc, pattern>, isRecordForm; 261 262class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc, 263 list<dag> pattern> 264 : Z23Form_8<opcode, xo, 265 (outs vrrc:$vT), (ins u1imm:$r, vrrc:$vB, u2imm:$rmc), 266 !strconcat(opc, " $r, $vT, $vB, $rmc"), IIC_VecFP, pattern> { 267 let RC = ex; 268} 269 270// [PO BF // VRA VRB XO /] 271class X_BF3_VA5_VB5<bits<6> opcode, bits<10> xo, string opc, 272 list<dag> pattern> 273 : XForm_17<opcode, xo, (outs crrc:$crD), (ins vrrc:$VA, vrrc:$VB), 274 !strconcat(opc, " $crD, $VA, $VB"), IIC_FPCompare> { 275 let Pattern = pattern; 276} 277 278// [PO T RA RB XO TX] almost equal to [PO S RA RB XO SX], but has different 279// "out" and "in" dag 280class X_XT6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, 281 RegisterOperand vtype, list<dag> pattern> 282 : XX1Form_memOp<opcode, xo, (outs vtype:$XT), (ins memrr:$src), 283 !strconcat(opc, " $XT, $src"), IIC_LdStLFD, pattern>; 284 285// [PO S RA RB XO SX] 286class X_XS6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, 287 RegisterOperand vtype, list<dag> pattern> 288 : XX1Form_memOp<opcode, xo, (outs), (ins vtype:$XT, memrr:$dst), 289 !strconcat(opc, " $XT, $dst"), IIC_LdStSTFD, pattern>; 290} // Predicates = HasP9Vector 291} // AddedComplexity = 400, hasSideEffects = 0 292 293multiclass ScalToVecWPermute<ValueType Ty, dag In, dag NonPermOut, dag PermOut> { 294 def : Pat<(Ty (scalar_to_vector In)), (Ty NonPermOut)>; 295 def : Pat<(Ty (PPCSToV In)), (Ty PermOut)>; 296} 297 298//-------------------------- Instruction definitions -------------------------// 299// VSX instructions require the VSX feature, they are to be selected over 300// equivalent Altivec patterns (as they address a larger register set) and 301// they do not have unmodeled side effects. 302let Predicates = [HasVSX], AddedComplexity = 400 in { 303let hasSideEffects = 0 in { 304 305 // Load indexed instructions 306 let mayLoad = 1, mayStore = 0 in { 307 let CodeSize = 3 in 308 def LXSDX : XX1Form_memOp<31, 588, 309 (outs vsfrc:$XT), (ins memrr:$src), 310 "lxsdx $XT, $src", IIC_LdStLFD, 311 []>; 312 313 // Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later 314 let CodeSize = 3 in 315 def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), 316 "#XFLOADf64", 317 [(set f64:$XT, (load xoaddr:$src))]>; 318 319 let Predicates = [HasVSX, HasOnlySwappingMemOps] in 320 def LXVD2X : XX1Form_memOp<31, 844, 321 (outs vsrc:$XT), (ins memrr:$src), 322 "lxvd2x $XT, $src", IIC_LdStLFD, 323 [(set v2f64:$XT, (int_ppc_vsx_lxvd2x xoaddr:$src))]>; 324 325 def LXVDSX : XX1Form_memOp<31, 332, 326 (outs vsrc:$XT), (ins memrr:$src), 327 "lxvdsx $XT, $src", IIC_LdStLFD, []>; 328 329 let Predicates = [HasVSX, HasOnlySwappingMemOps] in 330 def LXVW4X : XX1Form_memOp<31, 780, 331 (outs vsrc:$XT), (ins memrr:$src), 332 "lxvw4x $XT, $src", IIC_LdStLFD, 333 []>; 334 } // mayLoad 335 336 // Store indexed instructions 337 let mayStore = 1, mayLoad = 0 in { 338 let CodeSize = 3 in 339 def STXSDX : XX1Form_memOp<31, 716, 340 (outs), (ins vsfrc:$XT, memrr:$dst), 341 "stxsdx $XT, $dst", IIC_LdStSTFD, 342 []>; 343 344 // Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later 345 let CodeSize = 3 in 346 def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), 347 "#XFSTOREf64", 348 [(store f64:$XT, xoaddr:$dst)]>; 349 350 let Predicates = [HasVSX, HasOnlySwappingMemOps] in { 351 // The behaviour of this instruction is endianness-specific so we provide no 352 // pattern to match it without considering endianness. 353 def STXVD2X : XX1Form_memOp<31, 972, 354 (outs), (ins vsrc:$XT, memrr:$dst), 355 "stxvd2x $XT, $dst", IIC_LdStSTFD, 356 []>; 357 358 def STXVW4X : XX1Form_memOp<31, 908, 359 (outs), (ins vsrc:$XT, memrr:$dst), 360 "stxvw4x $XT, $dst", IIC_LdStSTFD, 361 []>; 362 } 363 } // mayStore 364 365 let mayRaiseFPException = 1 in { 366 let Uses = [RM] in { 367 // Add/Mul Instructions 368 let isCommutable = 1 in { 369 def XSADDDP : XX3Form<60, 32, 370 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 371 "xsadddp $XT, $XA, $XB", IIC_VecFP, 372 [(set f64:$XT, (any_fadd f64:$XA, f64:$XB))]>; 373 def XSMULDP : XX3Form<60, 48, 374 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 375 "xsmuldp $XT, $XA, $XB", IIC_VecFP, 376 [(set f64:$XT, (any_fmul f64:$XA, f64:$XB))]>; 377 378 def XVADDDP : XX3Form<60, 96, 379 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 380 "xvadddp $XT, $XA, $XB", IIC_VecFP, 381 [(set v2f64:$XT, (any_fadd v2f64:$XA, v2f64:$XB))]>; 382 383 def XVADDSP : XX3Form<60, 64, 384 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 385 "xvaddsp $XT, $XA, $XB", IIC_VecFP, 386 [(set v4f32:$XT, (any_fadd v4f32:$XA, v4f32:$XB))]>; 387 388 def XVMULDP : XX3Form<60, 112, 389 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 390 "xvmuldp $XT, $XA, $XB", IIC_VecFP, 391 [(set v2f64:$XT, (any_fmul v2f64:$XA, v2f64:$XB))]>; 392 393 def XVMULSP : XX3Form<60, 80, 394 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 395 "xvmulsp $XT, $XA, $XB", IIC_VecFP, 396 [(set v4f32:$XT, (any_fmul v4f32:$XA, v4f32:$XB))]>; 397 } 398 399 // Subtract Instructions 400 def XSSUBDP : XX3Form<60, 40, 401 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 402 "xssubdp $XT, $XA, $XB", IIC_VecFP, 403 [(set f64:$XT, (any_fsub f64:$XA, f64:$XB))]>; 404 405 def XVSUBDP : XX3Form<60, 104, 406 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 407 "xvsubdp $XT, $XA, $XB", IIC_VecFP, 408 [(set v2f64:$XT, (any_fsub v2f64:$XA, v2f64:$XB))]>; 409 def XVSUBSP : XX3Form<60, 72, 410 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 411 "xvsubsp $XT, $XA, $XB", IIC_VecFP, 412 [(set v4f32:$XT, (any_fsub v4f32:$XA, v4f32:$XB))]>; 413 414 // FMA Instructions 415 let BaseName = "XSMADDADP" in { 416 let isCommutable = 1 in 417 def XSMADDADP : XX3Form<60, 33, 418 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 419 "xsmaddadp $XT, $XA, $XB", IIC_VecFP, 420 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, f64:$XTi))]>, 421 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 422 AltVSXFMARel; 423 let IsVSXFMAAlt = 1 in 424 def XSMADDMDP : XX3Form<60, 41, 425 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 426 "xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 427 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 428 AltVSXFMARel; 429 } 430 431 let BaseName = "XSMSUBADP" in { 432 let isCommutable = 1 in 433 def XSMSUBADP : XX3Form<60, 49, 434 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 435 "xsmsubadp $XT, $XA, $XB", IIC_VecFP, 436 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>, 437 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 438 AltVSXFMARel; 439 let IsVSXFMAAlt = 1 in 440 def XSMSUBMDP : XX3Form<60, 57, 441 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 442 "xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 443 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 444 AltVSXFMARel; 445 } 446 447 let BaseName = "XSNMADDADP" in { 448 let isCommutable = 1 in 449 def XSNMADDADP : XX3Form<60, 161, 450 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 451 "xsnmaddadp $XT, $XA, $XB", IIC_VecFP, 452 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, f64:$XTi)))]>, 453 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 454 AltVSXFMARel; 455 let IsVSXFMAAlt = 1 in 456 def XSNMADDMDP : XX3Form<60, 169, 457 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 458 "xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 459 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 460 AltVSXFMARel; 461 } 462 463 let BaseName = "XSNMSUBADP" in { 464 let isCommutable = 1 in 465 def XSNMSUBADP : XX3Form<60, 177, 466 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 467 "xsnmsubadp $XT, $XA, $XB", IIC_VecFP, 468 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>, 469 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 470 AltVSXFMARel; 471 let IsVSXFMAAlt = 1 in 472 def XSNMSUBMDP : XX3Form<60, 185, 473 (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB), 474 "xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 475 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 476 AltVSXFMARel; 477 } 478 479 let BaseName = "XVMADDADP" in { 480 let isCommutable = 1 in 481 def XVMADDADP : XX3Form<60, 97, 482 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 483 "xvmaddadp $XT, $XA, $XB", IIC_VecFP, 484 [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>, 485 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 486 AltVSXFMARel; 487 let IsVSXFMAAlt = 1 in 488 def XVMADDMDP : XX3Form<60, 105, 489 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 490 "xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 491 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 492 AltVSXFMARel; 493 } 494 495 let BaseName = "XVMADDASP" in { 496 let isCommutable = 1 in 497 def XVMADDASP : XX3Form<60, 65, 498 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 499 "xvmaddasp $XT, $XA, $XB", IIC_VecFP, 500 [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>, 501 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 502 AltVSXFMARel; 503 let IsVSXFMAAlt = 1 in 504 def XVMADDMSP : XX3Form<60, 73, 505 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 506 "xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 507 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 508 AltVSXFMARel; 509 } 510 511 let BaseName = "XVMSUBADP" in { 512 let isCommutable = 1 in 513 def XVMSUBADP : XX3Form<60, 113, 514 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 515 "xvmsubadp $XT, $XA, $XB", IIC_VecFP, 516 [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>, 517 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 518 AltVSXFMARel; 519 let IsVSXFMAAlt = 1 in 520 def XVMSUBMDP : XX3Form<60, 121, 521 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 522 "xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 523 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 524 AltVSXFMARel; 525 } 526 527 let BaseName = "XVMSUBASP" in { 528 let isCommutable = 1 in 529 def XVMSUBASP : XX3Form<60, 81, 530 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 531 "xvmsubasp $XT, $XA, $XB", IIC_VecFP, 532 [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>, 533 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 534 AltVSXFMARel; 535 let IsVSXFMAAlt = 1 in 536 def XVMSUBMSP : XX3Form<60, 89, 537 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 538 "xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 539 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 540 AltVSXFMARel; 541 } 542 543 let BaseName = "XVNMADDADP" in { 544 let isCommutable = 1 in 545 def XVNMADDADP : XX3Form<60, 225, 546 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 547 "xvnmaddadp $XT, $XA, $XB", IIC_VecFP, 548 [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>, 549 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 550 AltVSXFMARel; 551 let IsVSXFMAAlt = 1 in 552 def XVNMADDMDP : XX3Form<60, 233, 553 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 554 "xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>, 555 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 556 AltVSXFMARel; 557 } 558 559 let BaseName = "XVNMADDASP" in { 560 let isCommutable = 1 in 561 def XVNMADDASP : XX3Form<60, 193, 562 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 563 "xvnmaddasp $XT, $XA, $XB", IIC_VecFP, 564 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>, 565 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 566 AltVSXFMARel; 567 let IsVSXFMAAlt = 1 in 568 def XVNMADDMSP : XX3Form<60, 201, 569 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 570 "xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 571 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 572 AltVSXFMARel; 573 } 574 575 let BaseName = "XVNMSUBADP" in { 576 let isCommutable = 1 in 577 def XVNMSUBADP : XX3Form<60, 241, 578 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 579 "xvnmsubadp $XT, $XA, $XB", IIC_VecFP, 580 [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>, 581 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 582 AltVSXFMARel; 583 let IsVSXFMAAlt = 1 in 584 def XVNMSUBMDP : XX3Form<60, 249, 585 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 586 "xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>, 587 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 588 AltVSXFMARel; 589 } 590 591 let BaseName = "XVNMSUBASP" in { 592 let isCommutable = 1 in 593 def XVNMSUBASP : XX3Form<60, 209, 594 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 595 "xvnmsubasp $XT, $XA, $XB", IIC_VecFP, 596 [(set v4f32:$XT, (fneg (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>, 597 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 598 AltVSXFMARel; 599 let IsVSXFMAAlt = 1 in 600 def XVNMSUBMSP : XX3Form<60, 217, 601 (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB), 602 "xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 603 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 604 AltVSXFMARel; 605 } 606 607 // Division Instructions 608 def XSDIVDP : XX3Form<60, 56, 609 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 610 "xsdivdp $XT, $XA, $XB", IIC_FPDivD, 611 [(set f64:$XT, (any_fdiv f64:$XA, f64:$XB))]>; 612 def XSSQRTDP : XX2Form<60, 75, 613 (outs vsfrc:$XT), (ins vsfrc:$XB), 614 "xssqrtdp $XT, $XB", IIC_FPSqrtD, 615 [(set f64:$XT, (any_fsqrt f64:$XB))]>; 616 617 def XSREDP : XX2Form<60, 90, 618 (outs vsfrc:$XT), (ins vsfrc:$XB), 619 "xsredp $XT, $XB", IIC_VecFP, 620 [(set f64:$XT, (PPCfre f64:$XB))]>; 621 def XSRSQRTEDP : XX2Form<60, 74, 622 (outs vsfrc:$XT), (ins vsfrc:$XB), 623 "xsrsqrtedp $XT, $XB", IIC_VecFP, 624 [(set f64:$XT, (PPCfrsqrte f64:$XB))]>; 625 626 let mayRaiseFPException = 0 in { 627 def XSTDIVDP : XX3Form_1<60, 61, 628 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), 629 "xstdivdp $crD, $XA, $XB", IIC_FPCompare, []>; 630 def XSTSQRTDP : XX2Form_1<60, 106, 631 (outs crrc:$crD), (ins vsfrc:$XB), 632 "xstsqrtdp $crD, $XB", IIC_FPCompare, []>; 633 def XVTDIVDP : XX3Form_1<60, 125, 634 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB), 635 "xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>; 636 def XVTDIVSP : XX3Form_1<60, 93, 637 (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB), 638 "xvtdivsp $crD, $XA, $XB", IIC_FPCompare, []>; 639 640 def XVTSQRTDP : XX2Form_1<60, 234, 641 (outs crrc:$crD), (ins vsrc:$XB), 642 "xvtsqrtdp $crD, $XB", IIC_FPCompare, []>; 643 def XVTSQRTSP : XX2Form_1<60, 170, 644 (outs crrc:$crD), (ins vsrc:$XB), 645 "xvtsqrtsp $crD, $XB", IIC_FPCompare, []>; 646 } 647 648 def XVDIVDP : XX3Form<60, 120, 649 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 650 "xvdivdp $XT, $XA, $XB", IIC_FPDivD, 651 [(set v2f64:$XT, (any_fdiv v2f64:$XA, v2f64:$XB))]>; 652 def XVDIVSP : XX3Form<60, 88, 653 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 654 "xvdivsp $XT, $XA, $XB", IIC_FPDivS, 655 [(set v4f32:$XT, (any_fdiv v4f32:$XA, v4f32:$XB))]>; 656 657 def XVSQRTDP : XX2Form<60, 203, 658 (outs vsrc:$XT), (ins vsrc:$XB), 659 "xvsqrtdp $XT, $XB", IIC_FPSqrtD, 660 [(set v2f64:$XT, (any_fsqrt v2f64:$XB))]>; 661 def XVSQRTSP : XX2Form<60, 139, 662 (outs vsrc:$XT), (ins vsrc:$XB), 663 "xvsqrtsp $XT, $XB", IIC_FPSqrtS, 664 [(set v4f32:$XT, (any_fsqrt v4f32:$XB))]>; 665 666 def XVREDP : XX2Form<60, 218, 667 (outs vsrc:$XT), (ins vsrc:$XB), 668 "xvredp $XT, $XB", IIC_VecFP, 669 [(set v2f64:$XT, (PPCfre v2f64:$XB))]>; 670 def XVRESP : XX2Form<60, 154, 671 (outs vsrc:$XT), (ins vsrc:$XB), 672 "xvresp $XT, $XB", IIC_VecFP, 673 [(set v4f32:$XT, (PPCfre v4f32:$XB))]>; 674 675 def XVRSQRTEDP : XX2Form<60, 202, 676 (outs vsrc:$XT), (ins vsrc:$XB), 677 "xvrsqrtedp $XT, $XB", IIC_VecFP, 678 [(set v2f64:$XT, (PPCfrsqrte v2f64:$XB))]>; 679 def XVRSQRTESP : XX2Form<60, 138, 680 (outs vsrc:$XT), (ins vsrc:$XB), 681 "xvrsqrtesp $XT, $XB", IIC_VecFP, 682 [(set v4f32:$XT, (PPCfrsqrte v4f32:$XB))]>; 683 684 // Compare Instructions 685 def XSCMPODP : XX3Form_1<60, 43, 686 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), 687 "xscmpodp $crD, $XA, $XB", IIC_FPCompare, []>; 688 def XSCMPUDP : XX3Form_1<60, 35, 689 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), 690 "xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>; 691 692 defm XVCMPEQDP : XX3Form_Rcr<60, 99, 693 "xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare, 694 int_ppc_vsx_xvcmpeqdp, v2i64, v2f64>; 695 defm XVCMPEQSP : XX3Form_Rcr<60, 67, 696 "xvcmpeqsp", "$XT, $XA, $XB", IIC_VecFPCompare, 697 int_ppc_vsx_xvcmpeqsp, v4i32, v4f32>; 698 defm XVCMPGEDP : XX3Form_Rcr<60, 115, 699 "xvcmpgedp", "$XT, $XA, $XB", IIC_VecFPCompare, 700 int_ppc_vsx_xvcmpgedp, v2i64, v2f64>; 701 defm XVCMPGESP : XX3Form_Rcr<60, 83, 702 "xvcmpgesp", "$XT, $XA, $XB", IIC_VecFPCompare, 703 int_ppc_vsx_xvcmpgesp, v4i32, v4f32>; 704 defm XVCMPGTDP : XX3Form_Rcr<60, 107, 705 "xvcmpgtdp", "$XT, $XA, $XB", IIC_VecFPCompare, 706 int_ppc_vsx_xvcmpgtdp, v2i64, v2f64>; 707 defm XVCMPGTSP : XX3Form_Rcr<60, 75, 708 "xvcmpgtsp", "$XT, $XA, $XB", IIC_VecFPCompare, 709 int_ppc_vsx_xvcmpgtsp, v4i32, v4f32>; 710 711 // Move Instructions 712 let mayRaiseFPException = 0 in { 713 def XSABSDP : XX2Form<60, 345, 714 (outs vsfrc:$XT), (ins vsfrc:$XB), 715 "xsabsdp $XT, $XB", IIC_VecFP, 716 [(set f64:$XT, (fabs f64:$XB))]>; 717 def XSNABSDP : XX2Form<60, 361, 718 (outs vsfrc:$XT), (ins vsfrc:$XB), 719 "xsnabsdp $XT, $XB", IIC_VecFP, 720 [(set f64:$XT, (fneg (fabs f64:$XB)))]>; 721 def XSNEGDP : XX2Form<60, 377, 722 (outs vsfrc:$XT), (ins vsfrc:$XB), 723 "xsnegdp $XT, $XB", IIC_VecFP, 724 [(set f64:$XT, (fneg f64:$XB))]>; 725 def XSCPSGNDP : XX3Form<60, 176, 726 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 727 "xscpsgndp $XT, $XA, $XB", IIC_VecFP, 728 [(set f64:$XT, (fcopysign f64:$XB, f64:$XA))]>; 729 730 def XVABSDP : XX2Form<60, 473, 731 (outs vsrc:$XT), (ins vsrc:$XB), 732 "xvabsdp $XT, $XB", IIC_VecFP, 733 [(set v2f64:$XT, (fabs v2f64:$XB))]>; 734 735 def XVABSSP : XX2Form<60, 409, 736 (outs vsrc:$XT), (ins vsrc:$XB), 737 "xvabssp $XT, $XB", IIC_VecFP, 738 [(set v4f32:$XT, (fabs v4f32:$XB))]>; 739 740 def XVCPSGNDP : XX3Form<60, 240, 741 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 742 "xvcpsgndp $XT, $XA, $XB", IIC_VecFP, 743 [(set v2f64:$XT, (fcopysign v2f64:$XB, v2f64:$XA))]>; 744 def XVCPSGNSP : XX3Form<60, 208, 745 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 746 "xvcpsgnsp $XT, $XA, $XB", IIC_VecFP, 747 [(set v4f32:$XT, (fcopysign v4f32:$XB, v4f32:$XA))]>; 748 749 def XVNABSDP : XX2Form<60, 489, 750 (outs vsrc:$XT), (ins vsrc:$XB), 751 "xvnabsdp $XT, $XB", IIC_VecFP, 752 [(set v2f64:$XT, (fneg (fabs v2f64:$XB)))]>; 753 def XVNABSSP : XX2Form<60, 425, 754 (outs vsrc:$XT), (ins vsrc:$XB), 755 "xvnabssp $XT, $XB", IIC_VecFP, 756 [(set v4f32:$XT, (fneg (fabs v4f32:$XB)))]>; 757 758 def XVNEGDP : XX2Form<60, 505, 759 (outs vsrc:$XT), (ins vsrc:$XB), 760 "xvnegdp $XT, $XB", IIC_VecFP, 761 [(set v2f64:$XT, (fneg v2f64:$XB))]>; 762 def XVNEGSP : XX2Form<60, 441, 763 (outs vsrc:$XT), (ins vsrc:$XB), 764 "xvnegsp $XT, $XB", IIC_VecFP, 765 [(set v4f32:$XT, (fneg v4f32:$XB))]>; 766 } 767 768 // Conversion Instructions 769 def XSCVDPSP : XX2Form<60, 265, 770 (outs vsfrc:$XT), (ins vsfrc:$XB), 771 "xscvdpsp $XT, $XB", IIC_VecFP, []>; 772 def XSCVDPSXDS : XX2Form<60, 344, 773 (outs vsfrc:$XT), (ins vsfrc:$XB), 774 "xscvdpsxds $XT, $XB", IIC_VecFP, 775 [(set f64:$XT, (PPCany_fctidz f64:$XB))]>; 776 let isCodeGenOnly = 1 in 777 def XSCVDPSXDSs : XX2Form<60, 344, 778 (outs vssrc:$XT), (ins vssrc:$XB), 779 "xscvdpsxds $XT, $XB", IIC_VecFP, 780 [(set f32:$XT, (PPCany_fctidz f32:$XB))]>; 781 def XSCVDPSXWS : XX2Form<60, 88, 782 (outs vsfrc:$XT), (ins vsfrc:$XB), 783 "xscvdpsxws $XT, $XB", IIC_VecFP, 784 [(set f64:$XT, (PPCany_fctiwz f64:$XB))]>; 785 let isCodeGenOnly = 1 in 786 def XSCVDPSXWSs : XX2Form<60, 88, 787 (outs vssrc:$XT), (ins vssrc:$XB), 788 "xscvdpsxws $XT, $XB", IIC_VecFP, 789 [(set f32:$XT, (PPCany_fctiwz f32:$XB))]>; 790 def XSCVDPUXDS : XX2Form<60, 328, 791 (outs vsfrc:$XT), (ins vsfrc:$XB), 792 "xscvdpuxds $XT, $XB", IIC_VecFP, 793 [(set f64:$XT, (PPCany_fctiduz f64:$XB))]>; 794 let isCodeGenOnly = 1 in 795 def XSCVDPUXDSs : XX2Form<60, 328, 796 (outs vssrc:$XT), (ins vssrc:$XB), 797 "xscvdpuxds $XT, $XB", IIC_VecFP, 798 [(set f32:$XT, (PPCany_fctiduz f32:$XB))]>; 799 def XSCVDPUXWS : XX2Form<60, 72, 800 (outs vsfrc:$XT), (ins vsfrc:$XB), 801 "xscvdpuxws $XT, $XB", IIC_VecFP, 802 [(set f64:$XT, (PPCany_fctiwuz f64:$XB))]>; 803 let isCodeGenOnly = 1 in 804 def XSCVDPUXWSs : XX2Form<60, 72, 805 (outs vssrc:$XT), (ins vssrc:$XB), 806 "xscvdpuxws $XT, $XB", IIC_VecFP, 807 [(set f32:$XT, (PPCany_fctiwuz f32:$XB))]>; 808 def XSCVSPDP : XX2Form<60, 329, 809 (outs vsfrc:$XT), (ins vsfrc:$XB), 810 "xscvspdp $XT, $XB", IIC_VecFP, []>; 811 def XSCVSXDDP : XX2Form<60, 376, 812 (outs vsfrc:$XT), (ins vsfrc:$XB), 813 "xscvsxddp $XT, $XB", IIC_VecFP, 814 [(set f64:$XT, (PPCany_fcfid f64:$XB))]>; 815 def XSCVUXDDP : XX2Form<60, 360, 816 (outs vsfrc:$XT), (ins vsfrc:$XB), 817 "xscvuxddp $XT, $XB", IIC_VecFP, 818 [(set f64:$XT, (PPCany_fcfidu f64:$XB))]>; 819 820 def XVCVDPSP : XX2Form<60, 393, 821 (outs vsrc:$XT), (ins vsrc:$XB), 822 "xvcvdpsp $XT, $XB", IIC_VecFP, 823 [(set v4f32:$XT, (int_ppc_vsx_xvcvdpsp v2f64:$XB))]>; 824 def XVCVDPSXDS : XX2Form<60, 472, 825 (outs vsrc:$XT), (ins vsrc:$XB), 826 "xvcvdpsxds $XT, $XB", IIC_VecFP, 827 [(set v2i64:$XT, (any_fp_to_sint v2f64:$XB))]>; 828 def XVCVDPSXWS : XX2Form<60, 216, 829 (outs vsrc:$XT), (ins vsrc:$XB), 830 "xvcvdpsxws $XT, $XB", IIC_VecFP, 831 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>; 832 def XVCVDPUXDS : XX2Form<60, 456, 833 (outs vsrc:$XT), (ins vsrc:$XB), 834 "xvcvdpuxds $XT, $XB", IIC_VecFP, 835 [(set v2i64:$XT, (any_fp_to_uint v2f64:$XB))]>; 836 def XVCVDPUXWS : XX2Form<60, 200, 837 (outs vsrc:$XT), (ins vsrc:$XB), 838 "xvcvdpuxws $XT, $XB", IIC_VecFP, 839 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpuxws v2f64:$XB))]>; 840 841 def XVCVSPDP : XX2Form<60, 457, 842 (outs vsrc:$XT), (ins vsrc:$XB), 843 "xvcvspdp $XT, $XB", IIC_VecFP, 844 [(set v2f64:$XT, (int_ppc_vsx_xvcvspdp v4f32:$XB))]>; 845 def XVCVSPSXDS : XX2Form<60, 408, 846 (outs vsrc:$XT), (ins vsrc:$XB), 847 "xvcvspsxds $XT, $XB", IIC_VecFP, []>; 848 def XVCVSPSXWS : XX2Form<60, 152, 849 (outs vsrc:$XT), (ins vsrc:$XB), 850 "xvcvspsxws $XT, $XB", IIC_VecFP, 851 [(set v4i32:$XT, (any_fp_to_sint v4f32:$XB))]>; 852 def XVCVSPUXDS : XX2Form<60, 392, 853 (outs vsrc:$XT), (ins vsrc:$XB), 854 "xvcvspuxds $XT, $XB", IIC_VecFP, []>; 855 def XVCVSPUXWS : XX2Form<60, 136, 856 (outs vsrc:$XT), (ins vsrc:$XB), 857 "xvcvspuxws $XT, $XB", IIC_VecFP, 858 [(set v4i32:$XT, (any_fp_to_uint v4f32:$XB))]>; 859 def XVCVSXDDP : XX2Form<60, 504, 860 (outs vsrc:$XT), (ins vsrc:$XB), 861 "xvcvsxddp $XT, $XB", IIC_VecFP, 862 [(set v2f64:$XT, (any_sint_to_fp v2i64:$XB))]>; 863 def XVCVSXDSP : XX2Form<60, 440, 864 (outs vsrc:$XT), (ins vsrc:$XB), 865 "xvcvsxdsp $XT, $XB", IIC_VecFP, 866 [(set v4f32:$XT, (int_ppc_vsx_xvcvsxdsp v2i64:$XB))]>; 867 def XVCVSXWSP : XX2Form<60, 184, 868 (outs vsrc:$XT), (ins vsrc:$XB), 869 "xvcvsxwsp $XT, $XB", IIC_VecFP, 870 [(set v4f32:$XT, (any_sint_to_fp v4i32:$XB))]>; 871 def XVCVUXDDP : XX2Form<60, 488, 872 (outs vsrc:$XT), (ins vsrc:$XB), 873 "xvcvuxddp $XT, $XB", IIC_VecFP, 874 [(set v2f64:$XT, (any_uint_to_fp v2i64:$XB))]>; 875 def XVCVUXDSP : XX2Form<60, 424, 876 (outs vsrc:$XT), (ins vsrc:$XB), 877 "xvcvuxdsp $XT, $XB", IIC_VecFP, 878 [(set v4f32:$XT, (int_ppc_vsx_xvcvuxdsp v2i64:$XB))]>; 879 def XVCVUXWSP : XX2Form<60, 168, 880 (outs vsrc:$XT), (ins vsrc:$XB), 881 "xvcvuxwsp $XT, $XB", IIC_VecFP, 882 [(set v4f32:$XT, (any_uint_to_fp v4i32:$XB))]>; 883 884 let mayRaiseFPException = 0 in { 885 def XVCVSXWDP : XX2Form<60, 248, 886 (outs vsrc:$XT), (ins vsrc:$XB), 887 "xvcvsxwdp $XT, $XB", IIC_VecFP, 888 [(set v2f64:$XT, (int_ppc_vsx_xvcvsxwdp v4i32:$XB))]>; 889 def XVCVUXWDP : XX2Form<60, 232, 890 (outs vsrc:$XT), (ins vsrc:$XB), 891 "xvcvuxwdp $XT, $XB", IIC_VecFP, 892 [(set v2f64:$XT, (int_ppc_vsx_xvcvuxwdp v4i32:$XB))]>; 893 } 894 895 // Rounding Instructions respecting current rounding mode 896 def XSRDPIC : XX2Form<60, 107, 897 (outs vsfrc:$XT), (ins vsfrc:$XB), 898 "xsrdpic $XT, $XB", IIC_VecFP, 899 [(set f64:$XT, (fnearbyint f64:$XB))]>; 900 def XVRDPIC : XX2Form<60, 235, 901 (outs vsrc:$XT), (ins vsrc:$XB), 902 "xvrdpic $XT, $XB", IIC_VecFP, 903 [(set v2f64:$XT, (fnearbyint v2f64:$XB))]>; 904 def XVRSPIC : XX2Form<60, 171, 905 (outs vsrc:$XT), (ins vsrc:$XB), 906 "xvrspic $XT, $XB", IIC_VecFP, 907 [(set v4f32:$XT, (fnearbyint v4f32:$XB))]>; 908 // Max/Min Instructions 909 let isCommutable = 1 in { 910 def XSMAXDP : XX3Form<60, 160, 911 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 912 "xsmaxdp $XT, $XA, $XB", IIC_VecFP, 913 [(set vsfrc:$XT, 914 (int_ppc_vsx_xsmaxdp vsfrc:$XA, vsfrc:$XB))]>; 915 def XSMINDP : XX3Form<60, 168, 916 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 917 "xsmindp $XT, $XA, $XB", IIC_VecFP, 918 [(set vsfrc:$XT, 919 (int_ppc_vsx_xsmindp vsfrc:$XA, vsfrc:$XB))]>; 920 921 def XVMAXDP : XX3Form<60, 224, 922 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 923 "xvmaxdp $XT, $XA, $XB", IIC_VecFP, 924 [(set vsrc:$XT, 925 (int_ppc_vsx_xvmaxdp vsrc:$XA, vsrc:$XB))]>; 926 def XVMINDP : XX3Form<60, 232, 927 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 928 "xvmindp $XT, $XA, $XB", IIC_VecFP, 929 [(set vsrc:$XT, 930 (int_ppc_vsx_xvmindp vsrc:$XA, vsrc:$XB))]>; 931 932 def XVMAXSP : XX3Form<60, 192, 933 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 934 "xvmaxsp $XT, $XA, $XB", IIC_VecFP, 935 [(set vsrc:$XT, 936 (int_ppc_vsx_xvmaxsp vsrc:$XA, vsrc:$XB))]>; 937 def XVMINSP : XX3Form<60, 200, 938 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 939 "xvminsp $XT, $XA, $XB", IIC_VecFP, 940 [(set vsrc:$XT, 941 (int_ppc_vsx_xvminsp vsrc:$XA, vsrc:$XB))]>; 942 } // isCommutable 943 } // Uses = [RM] 944 945 // Rounding Instructions with static direction. 946 def XSRDPI : XX2Form<60, 73, 947 (outs vsfrc:$XT), (ins vsfrc:$XB), 948 "xsrdpi $XT, $XB", IIC_VecFP, 949 [(set f64:$XT, (any_fround f64:$XB))]>; 950 def XSRDPIM : XX2Form<60, 121, 951 (outs vsfrc:$XT), (ins vsfrc:$XB), 952 "xsrdpim $XT, $XB", IIC_VecFP, 953 [(set f64:$XT, (any_ffloor f64:$XB))]>; 954 def XSRDPIP : XX2Form<60, 105, 955 (outs vsfrc:$XT), (ins vsfrc:$XB), 956 "xsrdpip $XT, $XB", IIC_VecFP, 957 [(set f64:$XT, (any_fceil f64:$XB))]>; 958 def XSRDPIZ : XX2Form<60, 89, 959 (outs vsfrc:$XT), (ins vsfrc:$XB), 960 "xsrdpiz $XT, $XB", IIC_VecFP, 961 [(set f64:$XT, (any_ftrunc f64:$XB))]>; 962 963 def XVRDPI : XX2Form<60, 201, 964 (outs vsrc:$XT), (ins vsrc:$XB), 965 "xvrdpi $XT, $XB", IIC_VecFP, 966 [(set v2f64:$XT, (any_fround v2f64:$XB))]>; 967 def XVRDPIM : XX2Form<60, 249, 968 (outs vsrc:$XT), (ins vsrc:$XB), 969 "xvrdpim $XT, $XB", IIC_VecFP, 970 [(set v2f64:$XT, (any_ffloor v2f64:$XB))]>; 971 def XVRDPIP : XX2Form<60, 233, 972 (outs vsrc:$XT), (ins vsrc:$XB), 973 "xvrdpip $XT, $XB", IIC_VecFP, 974 [(set v2f64:$XT, (any_fceil v2f64:$XB))]>; 975 def XVRDPIZ : XX2Form<60, 217, 976 (outs vsrc:$XT), (ins vsrc:$XB), 977 "xvrdpiz $XT, $XB", IIC_VecFP, 978 [(set v2f64:$XT, (any_ftrunc v2f64:$XB))]>; 979 980 def XVRSPI : XX2Form<60, 137, 981 (outs vsrc:$XT), (ins vsrc:$XB), 982 "xvrspi $XT, $XB", IIC_VecFP, 983 [(set v4f32:$XT, (any_fround v4f32:$XB))]>; 984 def XVRSPIM : XX2Form<60, 185, 985 (outs vsrc:$XT), (ins vsrc:$XB), 986 "xvrspim $XT, $XB", IIC_VecFP, 987 [(set v4f32:$XT, (any_ffloor v4f32:$XB))]>; 988 def XVRSPIP : XX2Form<60, 169, 989 (outs vsrc:$XT), (ins vsrc:$XB), 990 "xvrspip $XT, $XB", IIC_VecFP, 991 [(set v4f32:$XT, (any_fceil v4f32:$XB))]>; 992 def XVRSPIZ : XX2Form<60, 153, 993 (outs vsrc:$XT), (ins vsrc:$XB), 994 "xvrspiz $XT, $XB", IIC_VecFP, 995 [(set v4f32:$XT, (any_ftrunc v4f32:$XB))]>; 996 } // mayRaiseFPException 997 998 // Logical Instructions 999 let isCommutable = 1 in 1000 def XXLAND : XX3Form<60, 130, 1001 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1002 "xxland $XT, $XA, $XB", IIC_VecGeneral, 1003 [(set v4i32:$XT, (and v4i32:$XA, v4i32:$XB))]>; 1004 def XXLANDC : XX3Form<60, 138, 1005 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1006 "xxlandc $XT, $XA, $XB", IIC_VecGeneral, 1007 [(set v4i32:$XT, (and v4i32:$XA, 1008 (vnot_ppc v4i32:$XB)))]>; 1009 let isCommutable = 1 in { 1010 def XXLNOR : XX3Form<60, 162, 1011 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1012 "xxlnor $XT, $XA, $XB", IIC_VecGeneral, 1013 [(set v4i32:$XT, (vnot_ppc (or v4i32:$XA, 1014 v4i32:$XB)))]>; 1015 def XXLOR : XX3Form<60, 146, 1016 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1017 "xxlor $XT, $XA, $XB", IIC_VecGeneral, 1018 [(set v4i32:$XT, (or v4i32:$XA, v4i32:$XB))]>; 1019 let isCodeGenOnly = 1 in 1020 def XXLORf: XX3Form<60, 146, 1021 (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB), 1022 "xxlor $XT, $XA, $XB", IIC_VecGeneral, []>; 1023 def XXLXOR : XX3Form<60, 154, 1024 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1025 "xxlxor $XT, $XA, $XB", IIC_VecGeneral, 1026 [(set v4i32:$XT, (xor v4i32:$XA, v4i32:$XB))]>; 1027 } // isCommutable 1028 1029 let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 1030 isReMaterializable = 1 in { 1031 def XXLXORz : XX3Form_SameOp<60, 154, (outs vsrc:$XT), (ins), 1032 "xxlxor $XT, $XT, $XT", IIC_VecGeneral, 1033 [(set v4i32:$XT, (v4i32 immAllZerosV))]>; 1034 def XXLXORdpz : XX3Form_SameOp<60, 154, 1035 (outs vsfrc:$XT), (ins), 1036 "xxlxor $XT, $XT, $XT", IIC_VecGeneral, 1037 [(set f64:$XT, (fpimm0))]>; 1038 def XXLXORspz : XX3Form_SameOp<60, 154, 1039 (outs vssrc:$XT), (ins), 1040 "xxlxor $XT, $XT, $XT", IIC_VecGeneral, 1041 [(set f32:$XT, (fpimm0))]>; 1042 } 1043 1044 // Permutation Instructions 1045 def XXMRGHW : XX3Form<60, 18, 1046 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1047 "xxmrghw $XT, $XA, $XB", IIC_VecPerm, []>; 1048 def XXMRGLW : XX3Form<60, 50, 1049 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1050 "xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>; 1051 1052 def XXPERMDI : XX3Form_2<60, 10, 1053 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM), 1054 "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm, 1055 [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB, 1056 imm32SExt16:$DM))]>; 1057 let isCodeGenOnly = 1 in 1058 def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM), 1059 "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>; 1060 def XXSEL : XX4Form<60, 3, 1061 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC), 1062 "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>; 1063 1064 def XXSLDWI : XX3Form_2<60, 2, 1065 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW), 1066 "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, 1067 [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB, 1068 imm32SExt16:$SHW))]>; 1069 1070 let isCodeGenOnly = 1 in 1071 def XXSLDWIs : XX3Form_2s<60, 2, 1072 (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$SHW), 1073 "xxsldwi $XT, $XA, $XA, $SHW", IIC_VecPerm, []>; 1074 1075 def XXSPLTW : XX2Form_2<60, 164, 1076 (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM), 1077 "xxspltw $XT, $XB, $UIM", IIC_VecPerm, 1078 [(set v4i32:$XT, 1079 (PPCxxsplt v4i32:$XB, imm32SExt16:$UIM))]>; 1080 let isCodeGenOnly = 1 in 1081 def XXSPLTWs : XX2Form_2<60, 164, 1082 (outs vsrc:$XT), (ins vsfrc:$XB, u2imm:$UIM), 1083 "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>; 1084 1085// The following VSX instructions were introduced in Power ISA 2.07 1086let Predicates = [HasVSX, HasP8Vector] in { 1087 let isCommutable = 1 in { 1088 def XXLEQV : XX3Form<60, 186, 1089 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1090 "xxleqv $XT, $XA, $XB", IIC_VecGeneral, 1091 [(set v4i32:$XT, (vnot_ppc (xor v4i32:$XA, v4i32:$XB)))]>; 1092 def XXLNAND : XX3Form<60, 178, 1093 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1094 "xxlnand $XT, $XA, $XB", IIC_VecGeneral, 1095 [(set v4i32:$XT, (vnot_ppc (and v4i32:$XA, 1096 v4i32:$XB)))]>; 1097 } // isCommutable 1098 1099 let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, 1100 isReMaterializable = 1 in { 1101 def XXLEQVOnes : XX3Form_SameOp<60, 186, (outs vsrc:$XT), (ins), 1102 "xxleqv $XT, $XT, $XT", IIC_VecGeneral, 1103 [(set v4i32:$XT, (bitconvert (v16i8 immAllOnesV)))]>; 1104 } 1105 1106 def XXLORC : XX3Form<60, 170, 1107 (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB), 1108 "xxlorc $XT, $XA, $XB", IIC_VecGeneral, 1109 [(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>; 1110 1111 // VSX scalar loads introduced in ISA 2.07 1112 let mayLoad = 1, mayStore = 0 in { 1113 let CodeSize = 3 in 1114 def LXSSPX : XX1Form_memOp<31, 524, (outs vssrc:$XT), (ins memrr:$src), 1115 "lxsspx $XT, $src", IIC_LdStLFD, []>; 1116 def LXSIWAX : XX1Form_memOp<31, 76, (outs vsfrc:$XT), (ins memrr:$src), 1117 "lxsiwax $XT, $src", IIC_LdStLFD, []>; 1118 def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins memrr:$src), 1119 "lxsiwzx $XT, $src", IIC_LdStLFD, []>; 1120 1121 // Pseudo instruction XFLOADf32 will be expanded to LXSSPX or LFSX later 1122 let CodeSize = 3 in 1123 def XFLOADf32 : PseudoXFormMemOp<(outs vssrc:$XT), (ins memrr:$src), 1124 "#XFLOADf32", 1125 [(set f32:$XT, (load xoaddr:$src))]>; 1126 // Pseudo instruction LIWAX will be expanded to LXSIWAX or LFIWAX later 1127 def LIWAX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), 1128 "#LIWAX", 1129 [(set f64:$XT, (PPClfiwax xoaddr:$src))]>; 1130 // Pseudo instruction LIWZX will be expanded to LXSIWZX or LFIWZX later 1131 def LIWZX : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), 1132 "#LIWZX", 1133 [(set f64:$XT, (PPClfiwzx xoaddr:$src))]>; 1134 } // mayLoad 1135 1136 // VSX scalar stores introduced in ISA 2.07 1137 let mayStore = 1, mayLoad = 0 in { 1138 let CodeSize = 3 in 1139 def STXSSPX : XX1Form_memOp<31, 652, (outs), (ins vssrc:$XT, memrr:$dst), 1140 "stxsspx $XT, $dst", IIC_LdStSTFD, []>; 1141 def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst), 1142 "stxsiwx $XT, $dst", IIC_LdStSTFD, []>; 1143 1144 // Pseudo instruction XFSTOREf32 will be expanded to STXSSPX or STFSX later 1145 let CodeSize = 3 in 1146 def XFSTOREf32 : PseudoXFormMemOp<(outs), (ins vssrc:$XT, memrr:$dst), 1147 "#XFSTOREf32", 1148 [(store f32:$XT, xoaddr:$dst)]>; 1149 // Pseudo instruction STIWX will be expanded to STXSIWX or STFIWX later 1150 def STIWX : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), 1151 "#STIWX", 1152 [(PPCstfiwx f64:$XT, xoaddr:$dst)]>; 1153 } // mayStore 1154 1155 // VSX Elementary Scalar FP arithmetic (SP) 1156 let mayRaiseFPException = 1 in { 1157 let isCommutable = 1 in { 1158 def XSADDSP : XX3Form<60, 0, 1159 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 1160 "xsaddsp $XT, $XA, $XB", IIC_VecFP, 1161 [(set f32:$XT, (any_fadd f32:$XA, f32:$XB))]>; 1162 def XSMULSP : XX3Form<60, 16, 1163 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 1164 "xsmulsp $XT, $XA, $XB", IIC_VecFP, 1165 [(set f32:$XT, (any_fmul f32:$XA, f32:$XB))]>; 1166 } // isCommutable 1167 1168 def XSSUBSP : XX3Form<60, 8, 1169 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 1170 "xssubsp $XT, $XA, $XB", IIC_VecFP, 1171 [(set f32:$XT, (any_fsub f32:$XA, f32:$XB))]>; 1172 def XSDIVSP : XX3Form<60, 24, 1173 (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB), 1174 "xsdivsp $XT, $XA, $XB", IIC_FPDivS, 1175 [(set f32:$XT, (any_fdiv f32:$XA, f32:$XB))]>; 1176 1177 def XSRESP : XX2Form<60, 26, 1178 (outs vssrc:$XT), (ins vssrc:$XB), 1179 "xsresp $XT, $XB", IIC_VecFP, 1180 [(set f32:$XT, (PPCfre f32:$XB))]>; 1181 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1182 let hasSideEffects = 1 in 1183 def XSRSP : XX2Form<60, 281, 1184 (outs vssrc:$XT), (ins vsfrc:$XB), 1185 "xsrsp $XT, $XB", IIC_VecFP, 1186 [(set f32:$XT, (any_fpround f64:$XB))]>; 1187 def XSSQRTSP : XX2Form<60, 11, 1188 (outs vssrc:$XT), (ins vssrc:$XB), 1189 "xssqrtsp $XT, $XB", IIC_FPSqrtS, 1190 [(set f32:$XT, (any_fsqrt f32:$XB))]>; 1191 def XSRSQRTESP : XX2Form<60, 10, 1192 (outs vssrc:$XT), (ins vssrc:$XB), 1193 "xsrsqrtesp $XT, $XB", IIC_VecFP, 1194 [(set f32:$XT, (PPCfrsqrte f32:$XB))]>; 1195 1196 // FMA Instructions 1197 let BaseName = "XSMADDASP" in { 1198 let isCommutable = 1 in 1199 def XSMADDASP : XX3Form<60, 1, 1200 (outs vssrc:$XT), 1201 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1202 "xsmaddasp $XT, $XA, $XB", IIC_VecFP, 1203 [(set f32:$XT, (any_fma f32:$XA, f32:$XB, f32:$XTi))]>, 1204 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1205 AltVSXFMARel; 1206 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1207 let IsVSXFMAAlt = 1, hasSideEffects = 1 in 1208 def XSMADDMSP : XX3Form<60, 9, 1209 (outs vssrc:$XT), 1210 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1211 "xsmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 1212 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1213 AltVSXFMARel; 1214 } 1215 1216 let BaseName = "XSMSUBASP" in { 1217 let isCommutable = 1 in 1218 def XSMSUBASP : XX3Form<60, 17, 1219 (outs vssrc:$XT), 1220 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1221 "xsmsubasp $XT, $XA, $XB", IIC_VecFP, 1222 [(set f32:$XT, (any_fma f32:$XA, f32:$XB, 1223 (fneg f32:$XTi)))]>, 1224 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1225 AltVSXFMARel; 1226 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1227 let IsVSXFMAAlt = 1, hasSideEffects = 1 in 1228 def XSMSUBMSP : XX3Form<60, 25, 1229 (outs vssrc:$XT), 1230 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1231 "xsmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 1232 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1233 AltVSXFMARel; 1234 } 1235 1236 let BaseName = "XSNMADDASP" in { 1237 let isCommutable = 1 in 1238 def XSNMADDASP : XX3Form<60, 129, 1239 (outs vssrc:$XT), 1240 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1241 "xsnmaddasp $XT, $XA, $XB", IIC_VecFP, 1242 [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB, 1243 f32:$XTi)))]>, 1244 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1245 AltVSXFMARel; 1246 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1247 let IsVSXFMAAlt = 1, hasSideEffects = 1 in 1248 def XSNMADDMSP : XX3Form<60, 137, 1249 (outs vssrc:$XT), 1250 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1251 "xsnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>, 1252 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1253 AltVSXFMARel; 1254 } 1255 1256 let BaseName = "XSNMSUBASP" in { 1257 let isCommutable = 1 in 1258 def XSNMSUBASP : XX3Form<60, 145, 1259 (outs vssrc:$XT), 1260 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1261 "xsnmsubasp $XT, $XA, $XB", IIC_VecFP, 1262 [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB, 1263 (fneg f32:$XTi))))]>, 1264 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1265 AltVSXFMARel; 1266 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1267 let IsVSXFMAAlt = 1, hasSideEffects = 1 in 1268 def XSNMSUBMSP : XX3Form<60, 153, 1269 (outs vssrc:$XT), 1270 (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB), 1271 "xsnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>, 1272 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">, 1273 AltVSXFMARel; 1274 } 1275 1276 // Single Precision Conversions (FP <-> INT) 1277 def XSCVSXDSP : XX2Form<60, 312, 1278 (outs vssrc:$XT), (ins vsfrc:$XB), 1279 "xscvsxdsp $XT, $XB", IIC_VecFP, 1280 [(set f32:$XT, (PPCany_fcfids f64:$XB))]>; 1281 def XSCVUXDSP : XX2Form<60, 296, 1282 (outs vssrc:$XT), (ins vsfrc:$XB), 1283 "xscvuxdsp $XT, $XB", IIC_VecFP, 1284 [(set f32:$XT, (PPCany_fcfidus f64:$XB))]>; 1285 } // mayRaiseFPException 1286 1287 // Conversions between vector and scalar single precision 1288 def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB), 1289 "xscvdpspn $XT, $XB", IIC_VecFP, []>; 1290 def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB), 1291 "xscvspdpn $XT, $XB", IIC_VecFP, []>; 1292 1293 let Predicates = [HasVSX, HasDirectMove] in { 1294 // VSX direct move instructions 1295 def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT), 1296 "mfvsrd $rA, $XT", IIC_VecGeneral, 1297 [(set i64:$rA, (PPCmfvsr f64:$XT))]>, 1298 Requires<[In64BitMode]>; 1299 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1300 let isCodeGenOnly = 1, hasSideEffects = 1 in 1301 def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsrc:$XT), 1302 "mfvsrd $rA, $XT", IIC_VecGeneral, 1303 []>, 1304 Requires<[In64BitMode]>; 1305 def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT), 1306 "mfvsrwz $rA, $XT", IIC_VecGeneral, 1307 [(set i32:$rA, (PPCmfvsr f64:$XT))]>; 1308 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1309 let isCodeGenOnly = 1, hasSideEffects = 1 in 1310 def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT), 1311 "mfvsrwz $rA, $XT", IIC_VecGeneral, 1312 []>; 1313 def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA), 1314 "mtvsrd $XT, $rA", IIC_VecGeneral, 1315 [(set f64:$XT, (PPCmtvsra i64:$rA))]>, 1316 Requires<[In64BitMode]>; 1317 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1318 let isCodeGenOnly = 1, hasSideEffects = 1 in 1319 def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$rA), 1320 "mtvsrd $XT, $rA", IIC_VecGeneral, 1321 []>, 1322 Requires<[In64BitMode]>; 1323 def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA), 1324 "mtvsrwa $XT, $rA", IIC_VecGeneral, 1325 [(set f64:$XT, (PPCmtvsra i32:$rA))]>; 1326 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1327 let isCodeGenOnly = 1, hasSideEffects = 1 in 1328 def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$rA), 1329 "mtvsrwa $XT, $rA", IIC_VecGeneral, 1330 []>; 1331 def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA), 1332 "mtvsrwz $XT, $rA", IIC_VecGeneral, 1333 [(set f64:$XT, (PPCmtvsrz i32:$rA))]>; 1334 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1335 let isCodeGenOnly = 1, hasSideEffects = 1 in 1336 def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$rA), 1337 "mtvsrwz $XT, $rA", IIC_VecGeneral, 1338 []>; 1339 } // HasDirectMove 1340 1341} // HasVSX, HasP8Vector 1342 1343let Predicates = [HasVSX, IsISA3_0, HasDirectMove] in { 1344def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA), 1345 "mtvsrws $XT, $rA", IIC_VecGeneral, []>; 1346 1347def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$rA, g8rc:$rB), 1348 "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral, 1349 []>, Requires<[In64BitMode]>; 1350 1351def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT), 1352 "mfvsrld $rA, $XT", IIC_VecGeneral, 1353 []>, Requires<[In64BitMode]>; 1354 1355} // HasVSX, IsISA3_0, HasDirectMove 1356 1357let Predicates = [HasVSX, HasP9Vector] in { 1358 // Quad-Precision Scalar Move Instructions: 1359 // Copy Sign 1360 def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp", 1361 [(set f128:$vT, 1362 (fcopysign f128:$vB, f128:$vA))]>; 1363 1364 // Absolute/Negative-Absolute/Negate 1365 def XSABSQP : X_VT5_XO5_VB5<63, 0, 804, "xsabsqp", 1366 [(set f128:$vT, (fabs f128:$vB))]>; 1367 def XSNABSQP : X_VT5_XO5_VB5<63, 8, 804, "xsnabsqp", 1368 [(set f128:$vT, (fneg (fabs f128:$vB)))]>; 1369 def XSNEGQP : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp", 1370 [(set f128:$vT, (fneg f128:$vB))]>; 1371 1372 //===--------------------------------------------------------------------===// 1373 // Quad-Precision Scalar Floating-Point Arithmetic Instructions: 1374 1375 // Add/Divide/Multiply/Subtract 1376 let mayRaiseFPException = 1 in { 1377 let isCommutable = 1 in { 1378 def XSADDQP : X_VT5_VA5_VB5 <63, 4, "xsaddqp", 1379 [(set f128:$vT, (any_fadd f128:$vA, f128:$vB))]>; 1380 def XSMULQP : X_VT5_VA5_VB5 <63, 36, "xsmulqp", 1381 [(set f128:$vT, (any_fmul f128:$vA, f128:$vB))]>; 1382 } 1383 def XSSUBQP : X_VT5_VA5_VB5 <63, 516, "xssubqp" , 1384 [(set f128:$vT, (any_fsub f128:$vA, f128:$vB))]>; 1385 def XSDIVQP : X_VT5_VA5_VB5 <63, 548, "xsdivqp", 1386 [(set f128:$vT, (any_fdiv f128:$vA, f128:$vB))]>; 1387 // Square-Root 1388 def XSSQRTQP : X_VT5_XO5_VB5 <63, 27, 804, "xssqrtqp", 1389 [(set f128:$vT, (any_fsqrt f128:$vB))]>; 1390 // (Negative) Multiply-{Add/Subtract} 1391 def XSMADDQP : X_VT5_VA5_VB5_FMA <63, 388, "xsmaddqp", 1392 [(set f128:$vT, 1393 (any_fma f128:$vA, f128:$vB, f128:$vTi))]>; 1394 def XSMSUBQP : X_VT5_VA5_VB5_FMA <63, 420, "xsmsubqp" , 1395 [(set f128:$vT, 1396 (any_fma f128:$vA, f128:$vB, 1397 (fneg f128:$vTi)))]>; 1398 def XSNMADDQP : X_VT5_VA5_VB5_FMA <63, 452, "xsnmaddqp", 1399 [(set f128:$vT, 1400 (fneg (any_fma f128:$vA, f128:$vB, 1401 f128:$vTi)))]>; 1402 def XSNMSUBQP : X_VT5_VA5_VB5_FMA <63, 484, "xsnmsubqp", 1403 [(set f128:$vT, 1404 (fneg (any_fma f128:$vA, f128:$vB, 1405 (fneg f128:$vTi))))]>; 1406 1407 let isCommutable = 1 in { 1408 def XSADDQPO : X_VT5_VA5_VB5_Ro<63, 4, "xsaddqpo", 1409 [(set f128:$vT, 1410 (int_ppc_addf128_round_to_odd 1411 f128:$vA, f128:$vB))]>; 1412 def XSMULQPO : X_VT5_VA5_VB5_Ro<63, 36, "xsmulqpo", 1413 [(set f128:$vT, 1414 (int_ppc_mulf128_round_to_odd 1415 f128:$vA, f128:$vB))]>; 1416 } 1417 def XSSUBQPO : X_VT5_VA5_VB5_Ro<63, 516, "xssubqpo", 1418 [(set f128:$vT, 1419 (int_ppc_subf128_round_to_odd 1420 f128:$vA, f128:$vB))]>; 1421 def XSDIVQPO : X_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo", 1422 [(set f128:$vT, 1423 (int_ppc_divf128_round_to_odd 1424 f128:$vA, f128:$vB))]>; 1425 def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo", 1426 [(set f128:$vT, 1427 (int_ppc_sqrtf128_round_to_odd f128:$vB))]>; 1428 1429 1430 def XSMADDQPO : X_VT5_VA5_VB5_FMA_Ro<63, 388, "xsmaddqpo", 1431 [(set f128:$vT, 1432 (int_ppc_fmaf128_round_to_odd 1433 f128:$vA,f128:$vB,f128:$vTi))]>; 1434 1435 def XSMSUBQPO : X_VT5_VA5_VB5_FMA_Ro<63, 420, "xsmsubqpo" , 1436 [(set f128:$vT, 1437 (int_ppc_fmaf128_round_to_odd 1438 f128:$vA, f128:$vB, (fneg f128:$vTi)))]>; 1439 def XSNMADDQPO: X_VT5_VA5_VB5_FMA_Ro<63, 452, "xsnmaddqpo", 1440 [(set f128:$vT, 1441 (fneg (int_ppc_fmaf128_round_to_odd 1442 f128:$vA, f128:$vB, f128:$vTi)))]>; 1443 def XSNMSUBQPO: X_VT5_VA5_VB5_FMA_Ro<63, 484, "xsnmsubqpo", 1444 [(set f128:$vT, 1445 (fneg (int_ppc_fmaf128_round_to_odd 1446 f128:$vA, f128:$vB, (fneg f128:$vTi))))]>; 1447 } // mayRaiseFPException 1448 1449 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1450 // QP Compare Ordered/Unordered 1451 let hasSideEffects = 1 in { 1452 // DP/QP Compare Exponents 1453 def XSCMPEXPDP : XX3Form_1<60, 59, 1454 (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), 1455 "xscmpexpdp $crD, $XA, $XB", IIC_FPCompare, []>; 1456 def XSCMPEXPQP : X_BF3_VA5_VB5<63, 164, "xscmpexpqp", []>; 1457 1458 let mayRaiseFPException = 1 in { 1459 def XSCMPOQP : X_BF3_VA5_VB5<63, 132, "xscmpoqp", []>; 1460 def XSCMPUQP : X_BF3_VA5_VB5<63, 644, "xscmpuqp", []>; 1461 1462 // DP Compare ==, >=, >, != 1463 // Use vsrc for XT, because the entire register of XT is set. 1464 // XT.dword[1] = 0x0000_0000_0000_0000 1465 def XSCMPEQDP : XX3_XT5_XA5_XB5<60, 3, "xscmpeqdp", vsrc, vsfrc, vsfrc, 1466 IIC_FPCompare, []>; 1467 def XSCMPGEDP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vsfrc, vsfrc, 1468 IIC_FPCompare, []>; 1469 def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc, 1470 IIC_FPCompare, []>; 1471 } 1472 } 1473 1474 //===--------------------------------------------------------------------===// 1475 // Quad-Precision Floating-Point Conversion Instructions: 1476 1477 let mayRaiseFPException = 1 in { 1478 // Convert DP -> QP 1479 def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc, 1480 [(set f128:$vT, (any_fpextend f64:$vB))]>; 1481 1482 // Round & Convert QP -> DP (dword[1] is set to zero) 1483 def XSCVQPDP : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>; 1484 def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo", 1485 [(set f64:$vT, 1486 (int_ppc_truncf128_round_to_odd 1487 f128:$vB))]>; 1488 } 1489 1490 // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero) 1491 let mayRaiseFPException = 1 in { 1492 def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>; 1493 def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz", []>; 1494 def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>; 1495 def XSCVQPUWZ : X_VT5_XO5_VB5<63, 1, 836, "xscvqpuwz", []>; 1496 } 1497 1498 // Convert (Un)Signed DWord -> QP. 1499 def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>; 1500 def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vfrc, []>; 1501 1502 // (Round &) Convert DP <-> HP 1503 // Note! xscvdphp's src and dest register both use the left 64 bits, so we use 1504 // vsfrc for src and dest register. xscvhpdp's src only use the left 16 bits, 1505 // but we still use vsfrc for it. 1506 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1507 let hasSideEffects = 1, mayRaiseFPException = 1 in { 1508 def XSCVDPHP : XX2_XT6_XO5_XB6<60, 17, 347, "xscvdphp", vsfrc, []>; 1509 def XSCVHPDP : XX2_XT6_XO5_XB6<60, 16, 347, "xscvhpdp", vsfrc, []>; 1510 } 1511 1512 let mayRaiseFPException = 1 in { 1513 // Vector HP -> SP 1514 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1515 let hasSideEffects = 1 in 1516 def XVCVHPSP : XX2_XT6_XO5_XB6<60, 24, 475, "xvcvhpsp", vsrc, []>; 1517 def XVCVSPHP : XX2_XT6_XO5_XB6<60, 25, 475, "xvcvsphp", vsrc, 1518 [(set v4f32:$XT, 1519 (int_ppc_vsx_xvcvsphp v4f32:$XB))]>; 1520 1521 // Round to Quad-Precision Integer [with Inexact] 1522 def XSRQPI : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 0, "xsrqpi" , []>; 1523 def XSRQPIX : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 1, "xsrqpix", []>; 1524 1525 // Round Quad-Precision to Double-Extended Precision (fp80) 1526 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1527 let hasSideEffects = 1 in 1528 def XSRQPXP : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>; 1529 } 1530 1531 //===--------------------------------------------------------------------===// 1532 // Insert/Extract Instructions 1533 1534 // Insert Exponent DP/QP 1535 // XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU 1536 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1537 let hasSideEffects = 1 in { 1538 def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB), 1539 "xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>; 1540 // vB NOTE: only vB.dword[0] is used, that's why we don't use 1541 // X_VT5_VA5_VB5 form 1542 def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$vT), (ins vrrc:$vA, vsfrc:$vB), 1543 "xsiexpqp $vT, $vA, $vB", IIC_VecFP, []>; 1544 } 1545 1546 // Extract Exponent/Significand DP/QP 1547 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1548 let hasSideEffects = 1 in { 1549 def XSXEXPDP : XX2_RT5_XO5_XB6<60, 0, 347, "xsxexpdp", []>; 1550 def XSXSIGDP : XX2_RT5_XO5_XB6<60, 1, 347, "xsxsigdp", []>; 1551 1552 def XSXEXPQP : X_VT5_XO5_VB5 <63, 2, 804, "xsxexpqp", []>; 1553 def XSXSIGQP : X_VT5_XO5_VB5 <63, 18, 804, "xsxsigqp", []>; 1554 } 1555 1556 // Vector Insert Word 1557 // XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB. 1558 def XXINSERTW : 1559 XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT), 1560 (ins vsrc:$XTi, vsrc:$XB, u4imm:$UIM), 1561 "xxinsertw $XT, $XB, $UIM", IIC_VecFP, 1562 [(set v4i32:$XT, (PPCvecinsert v4i32:$XTi, v4i32:$XB, 1563 imm32SExt16:$UIM))]>, 1564 RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; 1565 1566 // Vector Extract Unsigned Word 1567 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1568 let hasSideEffects = 1 in 1569 def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165, 1570 (outs vsfrc:$XT), (ins vsrc:$XB, u4imm:$UIMM), 1571 "xxextractuw $XT, $XB, $UIMM", IIC_VecFP, []>; 1572 1573 // Vector Insert Exponent DP/SP 1574 def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc, 1575 IIC_VecFP, [(set v2f64: $XT,(int_ppc_vsx_xviexpdp v2i64:$XA, v2i64:$XB))]>; 1576 def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc, 1577 IIC_VecFP, [(set v4f32: $XT,(int_ppc_vsx_xviexpsp v4i32:$XA, v4i32:$XB))]>; 1578 1579 // Vector Extract Exponent/Significand DP/SP 1580 def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc, 1581 [(set v2i64: $XT, 1582 (int_ppc_vsx_xvxexpdp v2f64:$XB))]>; 1583 def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc, 1584 [(set v4i32: $XT, 1585 (int_ppc_vsx_xvxexpsp v4f32:$XB))]>; 1586 def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc, 1587 [(set v2i64: $XT, 1588 (int_ppc_vsx_xvxsigdp v2f64:$XB))]>; 1589 def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc, 1590 [(set v4i32: $XT, 1591 (int_ppc_vsx_xvxsigsp v4f32:$XB))]>; 1592 1593 // Test Data Class SP/DP/QP 1594 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1595 let hasSideEffects = 1 in { 1596 def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298, 1597 (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB), 1598 "xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>; 1599 def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362, 1600 (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB), 1601 "xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>; 1602 def XSTSTDCQP : X_BF3_DCMX7_RS5 <63, 708, 1603 (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$vB), 1604 "xststdcqp $BF, $vB, $DCMX", IIC_VecFP, []>; 1605 } 1606 1607 // Vector Test Data Class SP/DP 1608 def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5, 1609 (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB), 1610 "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, 1611 [(set v4i32: $XT, 1612 (int_ppc_vsx_xvtstdcsp v4f32:$XB, timm:$DCMX))]>; 1613 def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5, 1614 (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB), 1615 "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP, 1616 [(set v2i64: $XT, 1617 (int_ppc_vsx_xvtstdcdp v2f64:$XB, timm:$DCMX))]>; 1618 1619 // Maximum/Minimum Type-C/Type-J DP 1620 let mayRaiseFPException = 1 in { 1621 def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vsfrc, vsfrc, vsfrc, 1622 IIC_VecFP, 1623 [(set f64:$XT, (PPCxsmaxc f64:$XA, f64:$XB))]>; 1624 def XSMINCDP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", vsfrc, vsfrc, vsfrc, 1625 IIC_VecFP, 1626 [(set f64:$XT, (PPCxsminc f64:$XA, f64:$XB))]>; 1627 1628 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1629 let hasSideEffects = 1 in { 1630 def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsrc, vsfrc, vsfrc, 1631 IIC_VecFP, []>; 1632 def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsrc, vsfrc, vsfrc, 1633 IIC_VecFP, []>; 1634 } 1635 } 1636 1637 // Vector Byte-Reverse H/W/D/Q Word 1638 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1639 let hasSideEffects = 1 in 1640 def XXBRH : XX2_XT6_XO5_XB6<60, 7, 475, "xxbrh", vsrc, []>; 1641 def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", vsrc, 1642 [(set v4i32:$XT, (bswap v4i32:$XB))]>; 1643 def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc, 1644 [(set v2i64:$XT, (bswap v2i64:$XB))]>; 1645 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1646 let hasSideEffects = 1 in 1647 def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>; 1648 1649 // Vector Permute 1650 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1651 let hasSideEffects = 1 in { 1652 def XXPERM : XX3_XT5_XA5_XB5<60, 26, "xxperm" , vsrc, vsrc, vsrc, 1653 IIC_VecPerm, []>; 1654 def XXPERMR : XX3_XT5_XA5_XB5<60, 58, "xxpermr", vsrc, vsrc, vsrc, 1655 IIC_VecPerm, []>; 1656 } 1657 1658 // Vector Splat Immediate Byte 1659 // FIXME: Setting the hasSideEffects flag here to match current behaviour. 1660 let hasSideEffects = 1 in 1661 def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8), 1662 "xxspltib $XT, $IMM8", IIC_VecPerm, []>; 1663 1664 // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in 1665 // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging. 1666 let mayLoad = 1, mayStore = 0 in { 1667 // Load Vector 1668 def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$src), 1669 "lxv $XT, $src", IIC_LdStLFD, []>; 1670 // Load DWord 1671 def LXSD : DSForm_1<57, 2, (outs vfrc:$vD), (ins memrix:$src), 1672 "lxsd $vD, $src", IIC_LdStLFD, []>; 1673 // Load SP from src, convert it to DP, and place in dword[0] 1674 def LXSSP : DSForm_1<57, 3, (outs vfrc:$vD), (ins memrix:$src), 1675 "lxssp $vD, $src", IIC_LdStLFD, []>; 1676 1677 // Load as Integer Byte/Halfword & Zero Indexed 1678 def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc, 1679 [(set f64:$XT, (PPClxsizx xoaddr:$src, 1))]>; 1680 def LXSIHZX : X_XT6_RA5_RB5<31, 813, "lxsihzx", vsfrc, 1681 [(set f64:$XT, (PPClxsizx xoaddr:$src, 2))]>; 1682 1683 // Load Vector Halfword*8/Byte*16 Indexed 1684 def LXVH8X : X_XT6_RA5_RB5<31, 812, "lxvh8x" , vsrc, []>; 1685 def LXVB16X : X_XT6_RA5_RB5<31, 876, "lxvb16x", vsrc, []>; 1686 1687 // Load Vector Indexed 1688 def LXVX : X_XT6_RA5_RB5<31, 268, "lxvx" , vsrc, 1689 [(set v2f64:$XT, (load xaddrX16:$src))]>; 1690 // Load Vector (Left-justified) with Length 1691 def LXVL : XX1Form_memOp<31, 269, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB), 1692 "lxvl $XT, $src, $rB", IIC_LdStLoad, 1693 [(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$src, i64:$rB))]>; 1694 def LXVLL : XX1Form_memOp<31,301, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB), 1695 "lxvll $XT, $src, $rB", IIC_LdStLoad, 1696 [(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$src, i64:$rB))]>; 1697 1698 // Load Vector Word & Splat Indexed 1699 def LXVWSX : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>; 1700 } // mayLoad 1701 1702 // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in 1703 // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging. 1704 let mayStore = 1, mayLoad = 0 in { 1705 // Store Vector 1706 def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$dst), 1707 "stxv $XT, $dst", IIC_LdStSTFD, []>; 1708 // Store DWord 1709 def STXSD : DSForm_1<61, 2, (outs), (ins vfrc:$vS, memrix:$dst), 1710 "stxsd $vS, $dst", IIC_LdStSTFD, []>; 1711 // Convert DP of dword[0] to SP, and Store to dst 1712 def STXSSP : DSForm_1<61, 3, (outs), (ins vfrc:$vS, memrix:$dst), 1713 "stxssp $vS, $dst", IIC_LdStSTFD, []>; 1714 1715 // Store as Integer Byte/Halfword Indexed 1716 def STXSIBX : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsfrc, 1717 [(PPCstxsix f64:$XT, xoaddr:$dst, 1)]>; 1718 def STXSIHX : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsfrc, 1719 [(PPCstxsix f64:$XT, xoaddr:$dst, 2)]>; 1720 let isCodeGenOnly = 1 in { 1721 def STXSIBXv : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsrc, []>; 1722 def STXSIHXv : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsrc, []>; 1723 } 1724 1725 // Store Vector Halfword*8/Byte*16 Indexed 1726 def STXVH8X : X_XS6_RA5_RB5<31, 940, "stxvh8x" , vsrc, []>; 1727 def STXVB16X : X_XS6_RA5_RB5<31, 1004, "stxvb16x", vsrc, []>; 1728 1729 // Store Vector Indexed 1730 def STXVX : X_XS6_RA5_RB5<31, 396, "stxvx" , vsrc, 1731 [(store v2f64:$XT, xaddrX16:$dst)]>; 1732 1733 // Store Vector (Left-justified) with Length 1734 def STXVL : XX1Form_memOp<31, 397, (outs), 1735 (ins vsrc:$XT, memr:$dst, g8rc:$rB), 1736 "stxvl $XT, $dst, $rB", IIC_LdStLoad, 1737 [(int_ppc_vsx_stxvl v4i32:$XT, addr:$dst, 1738 i64:$rB)]>; 1739 def STXVLL : XX1Form_memOp<31, 429, (outs), 1740 (ins vsrc:$XT, memr:$dst, g8rc:$rB), 1741 "stxvll $XT, $dst, $rB", IIC_LdStLoad, 1742 [(int_ppc_vsx_stxvll v4i32:$XT, addr:$dst, 1743 i64:$rB)]>; 1744 } // mayStore 1745 1746 def DFLOADf32 : PPCPostRAExpPseudo<(outs vssrc:$XT), (ins memrix:$src), 1747 "#DFLOADf32", 1748 [(set f32:$XT, (load iaddrX4:$src))]>; 1749 def DFLOADf64 : PPCPostRAExpPseudo<(outs vsfrc:$XT), (ins memrix:$src), 1750 "#DFLOADf64", 1751 [(set f64:$XT, (load iaddrX4:$src))]>; 1752 def DFSTOREf32 : PPCPostRAExpPseudo<(outs), (ins vssrc:$XT, memrix:$dst), 1753 "#DFSTOREf32", 1754 [(store f32:$XT, iaddrX4:$dst)]>; 1755 def DFSTOREf64 : PPCPostRAExpPseudo<(outs), (ins vsfrc:$XT, memrix:$dst), 1756 "#DFSTOREf64", 1757 [(store f64:$XT, iaddrX4:$dst)]>; 1758 1759 let mayStore = 1 in { 1760 def SPILLTOVSR_STX : PseudoXFormMemOp<(outs), 1761 (ins spilltovsrrc:$XT, memrr:$dst), 1762 "#SPILLTOVSR_STX", []>; 1763 def SPILLTOVSR_ST : PPCPostRAExpPseudo<(outs), (ins spilltovsrrc:$XT, memrix:$dst), 1764 "#SPILLTOVSR_ST", []>; 1765 } 1766 let mayLoad = 1 in { 1767 def SPILLTOVSR_LDX : PseudoXFormMemOp<(outs spilltovsrrc:$XT), 1768 (ins memrr:$src), 1769 "#SPILLTOVSR_LDX", []>; 1770 def SPILLTOVSR_LD : PPCPostRAExpPseudo<(outs spilltovsrrc:$XT), (ins memrix:$src), 1771 "#SPILLTOVSR_LD", []>; 1772 1773 } 1774 } // HasP9Vector 1775} // hasSideEffects = 0 1776 1777let PPC970_Single = 1, AddedComplexity = 400 in { 1778 1779 def SELECT_CC_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst), 1780 (ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC), 1781 "#SELECT_CC_VSRC", 1782 []>; 1783 def SELECT_VSRC: PPCCustomInserterPseudo<(outs vsrc:$dst), 1784 (ins crbitrc:$cond, vsrc:$T, vsrc:$F), 1785 "#SELECT_VSRC", 1786 [(set v2f64:$dst, 1787 (select i1:$cond, v2f64:$T, v2f64:$F))]>; 1788 def SELECT_CC_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst), 1789 (ins crrc:$cond, f8rc:$T, f8rc:$F, 1790 i32imm:$BROPC), "#SELECT_CC_VSFRC", 1791 []>; 1792 def SELECT_VSFRC: PPCCustomInserterPseudo<(outs f8rc:$dst), 1793 (ins crbitrc:$cond, f8rc:$T, f8rc:$F), 1794 "#SELECT_VSFRC", 1795 [(set f64:$dst, 1796 (select i1:$cond, f64:$T, f64:$F))]>; 1797 def SELECT_CC_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst), 1798 (ins crrc:$cond, f4rc:$T, f4rc:$F, 1799 i32imm:$BROPC), "#SELECT_CC_VSSRC", 1800 []>; 1801 def SELECT_VSSRC: PPCCustomInserterPseudo<(outs f4rc:$dst), 1802 (ins crbitrc:$cond, f4rc:$T, f4rc:$F), 1803 "#SELECT_VSSRC", 1804 [(set f32:$dst, 1805 (select i1:$cond, f32:$T, f32:$F))]>; 1806} 1807} 1808 1809//----------------------------- DAG Definitions ------------------------------// 1810def FpMinMax { 1811 dag F32Min = (COPY_TO_REGCLASS (XSMINDP (COPY_TO_REGCLASS $A, VSFRC), 1812 (COPY_TO_REGCLASS $B, VSFRC)), 1813 VSSRC); 1814 dag F32Max = (COPY_TO_REGCLASS (XSMAXDP (COPY_TO_REGCLASS $A, VSFRC), 1815 (COPY_TO_REGCLASS $B, VSFRC)), 1816 VSSRC); 1817} 1818 1819def ScalarLoads { 1820 dag Li8 = (i32 (extloadi8 xoaddr:$src)); 1821 dag ZELi8 = (i32 (zextloadi8 xoaddr:$src)); 1822 dag ZELi8i64 = (i64 (zextloadi8 xoaddr:$src)); 1823 dag SELi8 = (i32 (sext_inreg (extloadi8 xoaddr:$src), i8)); 1824 dag SELi8i64 = (i64 (sext_inreg (extloadi8 xoaddr:$src), i8)); 1825 1826 dag Li16 = (i32 (extloadi16 xoaddr:$src)); 1827 dag ZELi16 = (i32 (zextloadi16 xoaddr:$src)); 1828 dag ZELi16i64 = (i64 (zextloadi16 xoaddr:$src)); 1829 dag SELi16 = (i32 (sextloadi16 xoaddr:$src)); 1830 dag SELi16i64 = (i64 (sextloadi16 xoaddr:$src)); 1831 1832 dag Li32 = (i32 (load xoaddr:$src)); 1833} 1834 1835def DWToSPExtractConv { 1836 dag El0US1 = (f32 (PPCfcfidus 1837 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0)))))); 1838 dag El1US1 = (f32 (PPCfcfidus 1839 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1)))))); 1840 dag El0US2 = (f32 (PPCfcfidus 1841 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0)))))); 1842 dag El1US2 = (f32 (PPCfcfidus 1843 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1)))))); 1844 dag El0SS1 = (f32 (PPCfcfids 1845 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 0)))))); 1846 dag El1SS1 = (f32 (PPCfcfids 1847 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S1, 1)))))); 1848 dag El0SS2 = (f32 (PPCfcfids 1849 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 0)))))); 1850 dag El1SS2 = (f32 (PPCfcfids 1851 (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S2, 1)))))); 1852 dag BVU = (v4f32 (build_vector El0US1, El1US1, El0US2, El1US2)); 1853 dag BVS = (v4f32 (build_vector El0SS1, El1SS1, El0SS2, El1SS2)); 1854} 1855 1856def WToDPExtractConv { 1857 dag El0S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 0)))); 1858 dag El1S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 1)))); 1859 dag El2S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 2)))); 1860 dag El3S = (f64 (PPCfcfid (PPCmtvsra (extractelt v4i32:$A, 3)))); 1861 dag El0U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 0)))); 1862 dag El1U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 1)))); 1863 dag El2U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 2)))); 1864 dag El3U = (f64 (PPCfcfidu (PPCmtvsrz (extractelt v4i32:$A, 3)))); 1865 dag BV02S = (v2f64 (build_vector El0S, El2S)); 1866 dag BV13S = (v2f64 (build_vector El1S, El3S)); 1867 dag BV02U = (v2f64 (build_vector El0U, El2U)); 1868 dag BV13U = (v2f64 (build_vector El1U, El3U)); 1869} 1870 1871/* Direct moves of various widths from GPR's into VSR's. Each move lines 1872 the value up into element 0 (both BE and LE). Namely, entities smaller than 1873 a doubleword are shifted left and moved for BE. For LE, they're moved, then 1874 swapped to go into the least significant element of the VSR. 1875*/ 1876def MovesToVSR { 1877 dag BE_BYTE_0 = 1878 (MTVSRD 1879 (RLDICR 1880 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 56, 7)); 1881 dag BE_HALF_0 = 1882 (MTVSRD 1883 (RLDICR 1884 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 48, 15)); 1885 dag BE_WORD_0 = 1886 (MTVSRD 1887 (RLDICR 1888 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32), 32, 31)); 1889 dag BE_DWORD_0 = (MTVSRD $A); 1890 1891 dag LE_MTVSRW = (MTVSRD (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32)); 1892 dag LE_WORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 1893 LE_MTVSRW, sub_64)); 1894 dag LE_WORD_0 = (XXPERMDI LE_WORD_1, LE_WORD_1, 2); 1895 dag LE_DWORD_1 = (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), 1896 BE_DWORD_0, sub_64)); 1897 dag LE_DWORD_0 = (XXPERMDI LE_DWORD_1, LE_DWORD_1, 2); 1898} 1899 1900/* Patterns for extracting elements out of vectors. Integer elements are 1901 extracted using direct move operations. Patterns for extracting elements 1902 whose indices are not available at compile time are also provided with 1903 various _VARIABLE_ patterns. 1904 The numbering for the DAG's is for LE, but when used on BE, the correct 1905 LE element can just be used (i.e. LE_BYTE_2 == BE_BYTE_13). 1906*/ 1907def VectorExtractions { 1908 // Doubleword extraction 1909 dag LE_DWORD_0 = 1910 (MFVSRD 1911 (EXTRACT_SUBREG 1912 (XXPERMDI (COPY_TO_REGCLASS $S, VSRC), 1913 (COPY_TO_REGCLASS $S, VSRC), 2), sub_64)); 1914 dag LE_DWORD_1 = (MFVSRD 1915 (EXTRACT_SUBREG 1916 (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64)); 1917 1918 // Word extraction 1919 dag LE_WORD_0 = (MFVSRWZ (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64)); 1920 dag LE_WORD_1 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 1), sub_64)); 1921 dag LE_WORD_2 = (MFVSRWZ (EXTRACT_SUBREG 1922 (v2i64 (COPY_TO_REGCLASS $S, VSRC)), sub_64)); 1923 dag LE_WORD_3 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 3), sub_64)); 1924 1925 // Halfword extraction 1926 dag LE_HALF_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 48), sub_32)); 1927 dag LE_HALF_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 48), sub_32)); 1928 dag LE_HALF_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 48), sub_32)); 1929 dag LE_HALF_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 48), sub_32)); 1930 dag LE_HALF_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 48), sub_32)); 1931 dag LE_HALF_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 48), sub_32)); 1932 dag LE_HALF_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 48), sub_32)); 1933 dag LE_HALF_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 48), sub_32)); 1934 1935 // Byte extraction 1936 dag LE_BYTE_0 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 0, 56), sub_32)); 1937 dag LE_BYTE_1 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 56, 56), sub_32)); 1938 dag LE_BYTE_2 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 48, 56), sub_32)); 1939 dag LE_BYTE_3 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 40, 56), sub_32)); 1940 dag LE_BYTE_4 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 32, 56), sub_32)); 1941 dag LE_BYTE_5 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 24, 56), sub_32)); 1942 dag LE_BYTE_6 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 16, 56), sub_32)); 1943 dag LE_BYTE_7 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_0, 8, 56), sub_32)); 1944 dag LE_BYTE_8 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 0, 56), sub_32)); 1945 dag LE_BYTE_9 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 56, 56), sub_32)); 1946 dag LE_BYTE_10 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 48, 56), sub_32)); 1947 dag LE_BYTE_11 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 40, 56), sub_32)); 1948 dag LE_BYTE_12 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 32, 56), sub_32)); 1949 dag LE_BYTE_13 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 24, 56), sub_32)); 1950 dag LE_BYTE_14 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 16, 56), sub_32)); 1951 dag LE_BYTE_15 = (i32 (EXTRACT_SUBREG (RLDICL LE_DWORD_1, 8, 56), sub_32)); 1952 1953 /* Variable element number (BE and LE patterns must be specified separately) 1954 This is a rather involved process. 1955 1956 Conceptually, this is how the move is accomplished: 1957 1. Identify which doubleword contains the element 1958 2. Shift in the VMX register so that the correct doubleword is correctly 1959 lined up for the MFVSRD 1960 3. Perform the move so that the element (along with some extra stuff) 1961 is in the GPR 1962 4. Right shift within the GPR so that the element is right-justified 1963 1964 Of course, the index is an element number which has a different meaning 1965 on LE/BE so the patterns have to be specified separately. 1966 1967 Note: The final result will be the element right-justified with high 1968 order bits being arbitrarily defined (namely, whatever was in the 1969 vector register to the left of the value originally). 1970 */ 1971 1972 /* LE variable byte 1973 Number 1. above: 1974 - For elements 0-7, we shift left by 8 bytes since they're on the right 1975 - For elements 8-15, we need not shift (shift left by zero bytes) 1976 This is accomplished by inverting the bits of the index and AND-ing 1977 with 0x8 (i.e. clearing all bits of the index and inverting bit 60). 1978 */ 1979 dag LE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDC8 (LI8 8), $Idx))); 1980 1981 // Number 2. above: 1982 // - Now that we set up the shift amount, we shift in the VMX register 1983 dag LE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, LE_VBYTE_PERM_VEC)); 1984 1985 // Number 3. above: 1986 // - The doubleword containing our element is moved to a GPR 1987 dag LE_MV_VBYTE = (MFVSRD 1988 (EXTRACT_SUBREG 1989 (v2i64 (COPY_TO_REGCLASS LE_VBYTE_PERMUTE, VSRC)), 1990 sub_64)); 1991 1992 /* Number 4. above: 1993 - Truncate the element number to the range 0-7 (8-15 are symmetrical 1994 and out of range values are truncated accordingly) 1995 - Multiply by 8 as we need to shift right by the number of bits, not bytes 1996 - Shift right in the GPR by the calculated value 1997 */ 1998 dag LE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 7), $Idx), 3, 60), 1999 sub_32); 2000 dag LE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD LE_MV_VBYTE, LE_VBYTE_SHIFT), 2001 sub_32); 2002 2003 /* LE variable halfword 2004 Number 1. above: 2005 - For elements 0-3, we shift left by 8 since they're on the right 2006 - For elements 4-7, we need not shift (shift left by zero bytes) 2007 Similarly to the byte pattern, we invert the bits of the index, but we 2008 AND with 0x4 (i.e. clear all bits of the index and invert bit 61). 2009 Of course, the shift is still by 8 bytes, so we must multiply by 2. 2010 */ 2011 dag LE_VHALF_PERM_VEC = 2012 (v16i8 (LVSL ZERO8, (RLDICR (ANDC8 (LI8 4), $Idx), 1, 62))); 2013 2014 // Number 2. above: 2015 // - Now that we set up the shift amount, we shift in the VMX register 2016 dag LE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, LE_VHALF_PERM_VEC)); 2017 2018 // Number 3. above: 2019 // - The doubleword containing our element is moved to a GPR 2020 dag LE_MV_VHALF = (MFVSRD 2021 (EXTRACT_SUBREG 2022 (v2i64 (COPY_TO_REGCLASS LE_VHALF_PERMUTE, VSRC)), 2023 sub_64)); 2024 2025 /* Number 4. above: 2026 - Truncate the element number to the range 0-3 (4-7 are symmetrical 2027 and out of range values are truncated accordingly) 2028 - Multiply by 16 as we need to shift right by the number of bits 2029 - Shift right in the GPR by the calculated value 2030 */ 2031 dag LE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 3), $Idx), 4, 59), 2032 sub_32); 2033 dag LE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD LE_MV_VHALF, LE_VHALF_SHIFT), 2034 sub_32); 2035 2036 /* LE variable word 2037 Number 1. above: 2038 - For elements 0-1, we shift left by 8 since they're on the right 2039 - For elements 2-3, we need not shift 2040 */ 2041 dag LE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8, 2042 (RLDICR (ANDC8 (LI8 2), $Idx), 2, 61))); 2043 2044 // Number 2. above: 2045 // - Now that we set up the shift amount, we shift in the VMX register 2046 dag LE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VWORD_PERM_VEC)); 2047 2048 // Number 3. above: 2049 // - The doubleword containing our element is moved to a GPR 2050 dag LE_MV_VWORD = (MFVSRD 2051 (EXTRACT_SUBREG 2052 (v2i64 (COPY_TO_REGCLASS LE_VWORD_PERMUTE, VSRC)), 2053 sub_64)); 2054 2055 /* Number 4. above: 2056 - Truncate the element number to the range 0-1 (2-3 are symmetrical 2057 and out of range values are truncated accordingly) 2058 - Multiply by 32 as we need to shift right by the number of bits 2059 - Shift right in the GPR by the calculated value 2060 */ 2061 dag LE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (AND8 (LI8 1), $Idx), 5, 58), 2062 sub_32); 2063 dag LE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD LE_MV_VWORD, LE_VWORD_SHIFT), 2064 sub_32); 2065 2066 /* LE variable doubleword 2067 Number 1. above: 2068 - For element 0, we shift left by 8 since it's on the right 2069 - For element 1, we need not shift 2070 */ 2071 dag LE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8, 2072 (RLDICR (ANDC8 (LI8 1), $Idx), 3, 60))); 2073 2074 // Number 2. above: 2075 // - Now that we set up the shift amount, we shift in the VMX register 2076 dag LE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, LE_VDWORD_PERM_VEC)); 2077 2078 // Number 3. above: 2079 // - The doubleword containing our element is moved to a GPR 2080 // - Number 4. is not needed for the doubleword as the value is 64-bits 2081 dag LE_VARIABLE_DWORD = 2082 (MFVSRD (EXTRACT_SUBREG 2083 (v2i64 (COPY_TO_REGCLASS LE_VDWORD_PERMUTE, VSRC)), 2084 sub_64)); 2085 2086 /* LE variable float 2087 - Shift the vector to line up the desired element to BE Word 0 2088 - Convert 32-bit float to a 64-bit single precision float 2089 */ 2090 dag LE_VFLOAT_PERM_VEC = (v16i8 (LVSL ZERO8, 2091 (RLDICR (XOR8 (LI8 3), $Idx), 2, 61))); 2092 dag LE_VFLOAT_PERMUTE = (VPERM $S, $S, LE_VFLOAT_PERM_VEC); 2093 dag LE_VARIABLE_FLOAT = (XSCVSPDPN LE_VFLOAT_PERMUTE); 2094 2095 /* LE variable double 2096 Same as the LE doubleword except there is no move. 2097 */ 2098 dag LE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 2099 (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 2100 LE_VDWORD_PERM_VEC)); 2101 dag LE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS LE_VDOUBLE_PERMUTE, VSRC); 2102 2103 /* BE variable byte 2104 The algorithm here is the same as the LE variable byte except: 2105 - The shift in the VMX register is by 0/8 for opposite element numbers so 2106 we simply AND the element number with 0x8 2107 - The order of elements after the move to GPR is reversed, so we invert 2108 the bits of the index prior to truncating to the range 0-7 2109 */ 2110 dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDI8_rec $Idx, 8))); 2111 dag BE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, BE_VBYTE_PERM_VEC)); 2112 dag BE_MV_VBYTE = (MFVSRD 2113 (EXTRACT_SUBREG 2114 (v2i64 (COPY_TO_REGCLASS BE_VBYTE_PERMUTE, VSRC)), 2115 sub_64)); 2116 dag BE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 7), $Idx), 3, 60), 2117 sub_32); 2118 dag BE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD BE_MV_VBYTE, BE_VBYTE_SHIFT), 2119 sub_32); 2120 2121 /* BE variable halfword 2122 The algorithm here is the same as the LE variable halfword except: 2123 - The shift in the VMX register is by 0/8 for opposite element numbers so 2124 we simply AND the element number with 0x4 and multiply by 2 2125 - The order of elements after the move to GPR is reversed, so we invert 2126 the bits of the index prior to truncating to the range 0-3 2127 */ 2128 dag BE_VHALF_PERM_VEC = (v16i8 (LVSL ZERO8, 2129 (RLDICR (ANDI8_rec $Idx, 4), 1, 62))); 2130 dag BE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, BE_VHALF_PERM_VEC)); 2131 dag BE_MV_VHALF = (MFVSRD 2132 (EXTRACT_SUBREG 2133 (v2i64 (COPY_TO_REGCLASS BE_VHALF_PERMUTE, VSRC)), 2134 sub_64)); 2135 dag BE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 3), $Idx), 4, 59), 2136 sub_32); 2137 dag BE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD BE_MV_VHALF, BE_VHALF_SHIFT), 2138 sub_32); 2139 2140 /* BE variable word 2141 The algorithm is the same as the LE variable word except: 2142 - The shift in the VMX register happens for opposite element numbers 2143 - The order of elements after the move to GPR is reversed, so we invert 2144 the bits of the index prior to truncating to the range 0-1 2145 */ 2146 dag BE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8, 2147 (RLDICR (ANDI8_rec $Idx, 2), 2, 61))); 2148 dag BE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VWORD_PERM_VEC)); 2149 dag BE_MV_VWORD = (MFVSRD 2150 (EXTRACT_SUBREG 2151 (v2i64 (COPY_TO_REGCLASS BE_VWORD_PERMUTE, VSRC)), 2152 sub_64)); 2153 dag BE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 1), $Idx), 5, 58), 2154 sub_32); 2155 dag BE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD BE_MV_VWORD, BE_VWORD_SHIFT), 2156 sub_32); 2157 2158 /* BE variable doubleword 2159 Same as the LE doubleword except we shift in the VMX register for opposite 2160 element indices. 2161 */ 2162 dag BE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8, 2163 (RLDICR (ANDI8_rec $Idx, 1), 3, 60))); 2164 dag BE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VDWORD_PERM_VEC)); 2165 dag BE_VARIABLE_DWORD = 2166 (MFVSRD (EXTRACT_SUBREG 2167 (v2i64 (COPY_TO_REGCLASS BE_VDWORD_PERMUTE, VSRC)), 2168 sub_64)); 2169 2170 /* BE variable float 2171 - Shift the vector to line up the desired element to BE Word 0 2172 - Convert 32-bit float to a 64-bit single precision float 2173 */ 2174 dag BE_VFLOAT_PERM_VEC = (v16i8 (LVSL ZERO8, (RLDICR $Idx, 2, 61))); 2175 dag BE_VFLOAT_PERMUTE = (VPERM $S, $S, BE_VFLOAT_PERM_VEC); 2176 dag BE_VARIABLE_FLOAT = (XSCVSPDPN BE_VFLOAT_PERMUTE); 2177 2178 /* BE variable double 2179 Same as the BE doubleword except there is no move. 2180 */ 2181 dag BE_VDOUBLE_PERMUTE = (v16i8 (VPERM (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 2182 (v16i8 (COPY_TO_REGCLASS $S, VRRC)), 2183 BE_VDWORD_PERM_VEC)); 2184 dag BE_VARIABLE_DOUBLE = (COPY_TO_REGCLASS BE_VDOUBLE_PERMUTE, VSRC); 2185} 2186 2187def AlignValues { 2188 dag F32_TO_BE_WORD1 = (v4f32 (XXSLDWI (XSCVDPSPN $B), (XSCVDPSPN $B), 3)); 2189 dag I32_TO_BE_WORD1 = (COPY_TO_REGCLASS (MTVSRWZ $B), VSRC); 2190} 2191 2192// Integer extend helper dags 32 -> 64 2193def AnyExts { 2194 dag A = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $A, sub_32); 2195 dag B = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $B, sub_32); 2196 dag C = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $C, sub_32); 2197 dag D = (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $D, sub_32); 2198} 2199 2200def DblToFlt { 2201 dag A0 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 0)))); 2202 dag A1 = (f32 (any_fpround (f64 (extractelt v2f64:$A, 1)))); 2203 dag B0 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 0)))); 2204 dag B1 = (f32 (any_fpround (f64 (extractelt v2f64:$B, 1)))); 2205} 2206 2207def ExtDbl { 2208 dag A0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 0)))))); 2209 dag A1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$A, 1)))))); 2210 dag B0S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 0)))))); 2211 dag B1S = (i32 (PPCmfvsr (f64 (PPCfctiwz (f64 (extractelt v2f64:$B, 1)))))); 2212 dag A0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 0)))))); 2213 dag A1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$A, 1)))))); 2214 dag B0U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 0)))))); 2215 dag B1U = (i32 (PPCmfvsr (f64 (PPCfctiwuz (f64 (extractelt v2f64:$B, 1)))))); 2216} 2217 2218def ByteToWord { 2219 dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 0)), i8)); 2220 dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 4)), i8)); 2221 dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 8)), i8)); 2222 dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 12)), i8)); 2223 dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 3)), i8)); 2224 dag BE_A1 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 7)), i8)); 2225 dag BE_A2 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 11)), i8)); 2226 dag BE_A3 = (i32 (sext_inreg (i32 (vector_extract v16i8:$A, 15)), i8)); 2227} 2228 2229def ByteToDWord { 2230 dag LE_A0 = (i64 (sext_inreg 2231 (i64 (anyext (i32 (vector_extract v16i8:$A, 0)))), i8)); 2232 dag LE_A1 = (i64 (sext_inreg 2233 (i64 (anyext (i32 (vector_extract v16i8:$A, 8)))), i8)); 2234 dag BE_A0 = (i64 (sext_inreg 2235 (i64 (anyext (i32 (vector_extract v16i8:$A, 7)))), i8)); 2236 dag BE_A1 = (i64 (sext_inreg 2237 (i64 (anyext (i32 (vector_extract v16i8:$A, 15)))), i8)); 2238} 2239 2240def HWordToWord { 2241 dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 0)), i16)); 2242 dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 2)), i16)); 2243 dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 4)), i16)); 2244 dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 6)), i16)); 2245 dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 1)), i16)); 2246 dag BE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 3)), i16)); 2247 dag BE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 5)), i16)); 2248 dag BE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 7)), i16)); 2249} 2250 2251def HWordToDWord { 2252 dag LE_A0 = (i64 (sext_inreg 2253 (i64 (anyext (i32 (vector_extract v8i16:$A, 0)))), i16)); 2254 dag LE_A1 = (i64 (sext_inreg 2255 (i64 (anyext (i32 (vector_extract v8i16:$A, 4)))), i16)); 2256 dag BE_A0 = (i64 (sext_inreg 2257 (i64 (anyext (i32 (vector_extract v8i16:$A, 3)))), i16)); 2258 dag BE_A1 = (i64 (sext_inreg 2259 (i64 (anyext (i32 (vector_extract v8i16:$A, 7)))), i16)); 2260} 2261 2262def WordToDWord { 2263 dag LE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 0)))); 2264 dag LE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 2)))); 2265 dag BE_A0 = (i64 (sext (i32 (vector_extract v4i32:$A, 1)))); 2266 dag BE_A1 = (i64 (sext (i32 (vector_extract v4i32:$A, 3)))); 2267} 2268 2269def FltToIntLoad { 2270 dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (extloadf32 xoaddr:$A))))); 2271} 2272def FltToUIntLoad { 2273 dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (extloadf32 xoaddr:$A))))); 2274} 2275def FltToLongLoad { 2276 dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 xoaddr:$A))))); 2277} 2278def FltToLongLoadP9 { 2279 dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (extloadf32 iaddrX4:$A))))); 2280} 2281def FltToULongLoad { 2282 dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 xoaddr:$A))))); 2283} 2284def FltToULongLoadP9 { 2285 dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (extloadf32 iaddrX4:$A))))); 2286} 2287def FltToLong { 2288 dag A = (i64 (PPCmfvsr (f64 (PPCfctidz (fpextend f32:$A))))); 2289} 2290def FltToULong { 2291 dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz (fpextend f32:$A))))); 2292} 2293def DblToInt { 2294 dag A = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$A)))); 2295 dag B = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$B)))); 2296 dag C = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$C)))); 2297 dag D = (i32 (PPCmfvsr (f64 (PPCfctiwz f64:$D)))); 2298} 2299def DblToUInt { 2300 dag A = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$A)))); 2301 dag B = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$B)))); 2302 dag C = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$C)))); 2303 dag D = (i32 (PPCmfvsr (f64 (PPCfctiwuz f64:$D)))); 2304} 2305def DblToLong { 2306 dag A = (i64 (PPCmfvsr (f64 (PPCfctidz f64:$A)))); 2307} 2308def DblToULong { 2309 dag A = (i64 (PPCmfvsr (f64 (PPCfctiduz f64:$A)))); 2310} 2311def DblToIntLoad { 2312 dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load xoaddr:$A))))); 2313} 2314def DblToIntLoadP9 { 2315 dag A = (i32 (PPCmfvsr (PPCfctiwz (f64 (load iaddrX4:$A))))); 2316} 2317def DblToUIntLoad { 2318 dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load xoaddr:$A))))); 2319} 2320def DblToUIntLoadP9 { 2321 dag A = (i32 (PPCmfvsr (PPCfctiwuz (f64 (load iaddrX4:$A))))); 2322} 2323def DblToLongLoad { 2324 dag A = (i64 (PPCmfvsr (PPCfctidz (f64 (load xoaddr:$A))))); 2325} 2326def DblToULongLoad { 2327 dag A = (i64 (PPCmfvsr (PPCfctiduz (f64 (load xoaddr:$A))))); 2328} 2329 2330// FP load dags (for f32 -> v4f32) 2331def LoadFP { 2332 dag A = (f32 (load xoaddr:$A)); 2333 dag B = (f32 (load xoaddr:$B)); 2334 dag C = (f32 (load xoaddr:$C)); 2335 dag D = (f32 (load xoaddr:$D)); 2336} 2337 2338// FP merge dags (for f32 -> v4f32) 2339def MrgFP { 2340 dag LD32A = (COPY_TO_REGCLASS (LIWZX xoaddr:$A), VSRC); 2341 dag LD32B = (COPY_TO_REGCLASS (LIWZX xoaddr:$B), VSRC); 2342 dag LD32C = (COPY_TO_REGCLASS (LIWZX xoaddr:$C), VSRC); 2343 dag LD32D = (COPY_TO_REGCLASS (LIWZX xoaddr:$D), VSRC); 2344 dag AC = (XVCVDPSP (XXPERMDI (COPY_TO_REGCLASS $A, VSRC), 2345 (COPY_TO_REGCLASS $C, VSRC), 0)); 2346 dag BD = (XVCVDPSP (XXPERMDI (COPY_TO_REGCLASS $B, VSRC), 2347 (COPY_TO_REGCLASS $D, VSRC), 0)); 2348 dag ABhToFlt = (XVCVDPSP (XXPERMDI $A, $B, 0)); 2349 dag ABlToFlt = (XVCVDPSP (XXPERMDI $A, $B, 3)); 2350 dag BAhToFlt = (XVCVDPSP (XXPERMDI $B, $A, 0)); 2351 dag BAlToFlt = (XVCVDPSP (XXPERMDI $B, $A, 3)); 2352} 2353 2354// Word-element merge dags - conversions from f64 to i32 merged into vectors. 2355def MrgWords { 2356 // For big endian, we merge low and hi doublewords (A, B). 2357 dag A0B0 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 0)); 2358 dag A1B1 = (v2f64 (XXPERMDI v2f64:$A, v2f64:$B, 3)); 2359 dag CVA1B1S = (v4i32 (XVCVDPSXWS A1B1)); 2360 dag CVA0B0S = (v4i32 (XVCVDPSXWS A0B0)); 2361 dag CVA1B1U = (v4i32 (XVCVDPUXWS A1B1)); 2362 dag CVA0B0U = (v4i32 (XVCVDPUXWS A0B0)); 2363 2364 // For little endian, we merge low and hi doublewords (B, A). 2365 dag B1A1 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 0)); 2366 dag B0A0 = (v2f64 (XXPERMDI v2f64:$B, v2f64:$A, 3)); 2367 dag CVB1A1S = (v4i32 (XVCVDPSXWS B1A1)); 2368 dag CVB0A0S = (v4i32 (XVCVDPSXWS B0A0)); 2369 dag CVB1A1U = (v4i32 (XVCVDPUXWS B1A1)); 2370 dag CVB0A0U = (v4i32 (XVCVDPUXWS B0A0)); 2371 2372 // For big endian, we merge hi doublewords of (A, C) and (B, D), convert 2373 // then merge. 2374 dag AC = (v2f64 (XXPERMDI (COPY_TO_REGCLASS f64:$A, VSRC), 2375 (COPY_TO_REGCLASS f64:$C, VSRC), 0)); 2376 dag BD = (v2f64 (XXPERMDI (COPY_TO_REGCLASS f64:$B, VSRC), 2377 (COPY_TO_REGCLASS f64:$D, VSRC), 0)); 2378 dag CVACS = (v4i32 (XVCVDPSXWS AC)); 2379 dag CVBDS = (v4i32 (XVCVDPSXWS BD)); 2380 dag CVACU = (v4i32 (XVCVDPUXWS AC)); 2381 dag CVBDU = (v4i32 (XVCVDPUXWS BD)); 2382 2383 // For little endian, we merge hi doublewords of (D, B) and (C, A), convert 2384 // then merge. 2385 dag DB = (v2f64 (XXPERMDI (COPY_TO_REGCLASS f64:$D, VSRC), 2386 (COPY_TO_REGCLASS f64:$B, VSRC), 0)); 2387 dag CA = (v2f64 (XXPERMDI (COPY_TO_REGCLASS f64:$C, VSRC), 2388 (COPY_TO_REGCLASS f64:$A, VSRC), 0)); 2389 dag CVDBS = (v4i32 (XVCVDPSXWS DB)); 2390 dag CVCAS = (v4i32 (XVCVDPSXWS CA)); 2391 dag CVDBU = (v4i32 (XVCVDPUXWS DB)); 2392 dag CVCAU = (v4i32 (XVCVDPUXWS CA)); 2393} 2394 2395//---------------------------- Anonymous Patterns ----------------------------// 2396// Predicate combinations are kept in roughly chronological order in terms of 2397// instruction availability in the architecture. For example, VSX came in with 2398// ISA 2.06 (Power7). There have since been additions in ISA 2.07 (Power8) and 2399// ISA 3.0 (Power9). However, the granularity of features on later subtargets 2400// is finer for various reasons. For example, we have Power8Vector, 2401// Power8Altivec, DirectMove that all came in with ISA 2.07. The situation is 2402// similar with ISA 3.0 with Power9Vector, Power9Altivec, IsISA3_0. Then there 2403// are orthogonal predicates such as endianness for which the order was 2404// arbitrarily chosen to be Big, Little. 2405// 2406// Predicate combinations available: 2407// [HasVSX] 2408// [HasVSX, IsBigEndian] 2409// [HasVSX, IsLittleEndian] 2410// [HasVSX, NoP9Vector] 2411// [HasVSX, HasOnlySwappingMemOps] 2412// [HasVSX, HasOnlySwappingMemOps, IsBigEndian] 2413// [HasVSX, HasP8Vector] 2414// [HasVSX, HasP8Vector, IsBigEndian] 2415// [HasVSX, HasP8Vector, IsLittleEndian] 2416// [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian] 2417// [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian] 2418// [HasVSX, HasDirectMove] 2419// [HasVSX, HasDirectMove, IsBigEndian] 2420// [HasVSX, HasDirectMove, IsLittleEndian] 2421// [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian] 2422// [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian] 2423// [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian] 2424// [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian] 2425// [HasVSX, HasP9Vector] 2426// [HasVSX, HasP9Vector, IsBigEndian] 2427// [HasVSX, HasP9Vector, IsLittleEndian] 2428// [HasVSX, HasP9Altivec] 2429// [HasVSX, HasP9Altivec, IsBigEndian] 2430// [HasVSX, HasP9Altivec, IsLittleEndian] 2431// [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian] 2432// [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian] 2433 2434let AddedComplexity = 400 in { 2435// Valid for any VSX subtarget, regardless of endianness. 2436let Predicates = [HasVSX] in { 2437def : Pat<(v4i32 (vnot_ppc v4i32:$A)), 2438 (v4i32 (XXLNOR $A, $A))>; 2439def : Pat<(v4i32 (or (and (vnot_ppc v4i32:$C), v4i32:$A), 2440 (and v4i32:$B, v4i32:$C))), 2441 (v4i32 (XXSEL $A, $B, $C))>; 2442 2443// Additional fnmsub pattern for PPC specific ISD opcode 2444def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C), 2445 (XSNMSUBADP $C, $A, $B)>; 2446def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)), 2447 (XSMSUBADP $C, $A, $B)>; 2448def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)), 2449 (XSNMADDADP $C, $A, $B)>; 2450 2451def : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C), 2452 (XVNMSUBADP $C, $A, $B)>; 2453def : Pat<(fneg (PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C)), 2454 (XVMSUBADP $C, $A, $B)>; 2455def : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, (fneg v2f64:$C)), 2456 (XVNMADDADP $C, $A, $B)>; 2457 2458def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C), 2459 (XVNMSUBASP $C, $A, $B)>; 2460def : Pat<(fneg (PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C)), 2461 (XVMSUBASP $C, $A, $B)>; 2462def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, (fneg v4f32:$C)), 2463 (XVNMADDASP $C, $A, $B)>; 2464 2465def : Pat<(v2f64 (bitconvert v4f32:$A)), 2466 (COPY_TO_REGCLASS $A, VSRC)>; 2467def : Pat<(v2f64 (bitconvert v4i32:$A)), 2468 (COPY_TO_REGCLASS $A, VSRC)>; 2469def : Pat<(v2f64 (bitconvert v8i16:$A)), 2470 (COPY_TO_REGCLASS $A, VSRC)>; 2471def : Pat<(v2f64 (bitconvert v16i8:$A)), 2472 (COPY_TO_REGCLASS $A, VSRC)>; 2473 2474def : Pat<(v4f32 (bitconvert v2f64:$A)), 2475 (COPY_TO_REGCLASS $A, VRRC)>; 2476def : Pat<(v4i32 (bitconvert v2f64:$A)), 2477 (COPY_TO_REGCLASS $A, VRRC)>; 2478def : Pat<(v8i16 (bitconvert v2f64:$A)), 2479 (COPY_TO_REGCLASS $A, VRRC)>; 2480def : Pat<(v16i8 (bitconvert v2f64:$A)), 2481 (COPY_TO_REGCLASS $A, VRRC)>; 2482 2483def : Pat<(v2i64 (bitconvert v4f32:$A)), 2484 (COPY_TO_REGCLASS $A, VSRC)>; 2485def : Pat<(v2i64 (bitconvert v4i32:$A)), 2486 (COPY_TO_REGCLASS $A, VSRC)>; 2487def : Pat<(v2i64 (bitconvert v8i16:$A)), 2488 (COPY_TO_REGCLASS $A, VSRC)>; 2489def : Pat<(v2i64 (bitconvert v16i8:$A)), 2490 (COPY_TO_REGCLASS $A, VSRC)>; 2491 2492def : Pat<(v4f32 (bitconvert v2i64:$A)), 2493 (COPY_TO_REGCLASS $A, VRRC)>; 2494def : Pat<(v4i32 (bitconvert v2i64:$A)), 2495 (COPY_TO_REGCLASS $A, VRRC)>; 2496def : Pat<(v8i16 (bitconvert v2i64:$A)), 2497 (COPY_TO_REGCLASS $A, VRRC)>; 2498def : Pat<(v16i8 (bitconvert v2i64:$A)), 2499 (COPY_TO_REGCLASS $A, VRRC)>; 2500 2501def : Pat<(v2f64 (bitconvert v2i64:$A)), 2502 (COPY_TO_REGCLASS $A, VRRC)>; 2503def : Pat<(v2i64 (bitconvert v2f64:$A)), 2504 (COPY_TO_REGCLASS $A, VRRC)>; 2505 2506def : Pat<(v2f64 (bitconvert v1i128:$A)), 2507 (COPY_TO_REGCLASS $A, VRRC)>; 2508def : Pat<(v1i128 (bitconvert v2f64:$A)), 2509 (COPY_TO_REGCLASS $A, VRRC)>; 2510 2511def : Pat<(v2i64 (bitconvert f128:$A)), 2512 (COPY_TO_REGCLASS $A, VRRC)>; 2513def : Pat<(v4i32 (bitconvert f128:$A)), 2514 (COPY_TO_REGCLASS $A, VRRC)>; 2515def : Pat<(v8i16 (bitconvert f128:$A)), 2516 (COPY_TO_REGCLASS $A, VRRC)>; 2517def : Pat<(v16i8 (bitconvert f128:$A)), 2518 (COPY_TO_REGCLASS $A, VRRC)>; 2519 2520def : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 0)), 2521 (v2f64 (XVCVSXWDP (v2i64 (XXMRGHW $C, $C))))>; 2522def : Pat<(v2f64 (PPCsvec2fp v4i32:$C, 1)), 2523 (v2f64 (XVCVSXWDP (v2i64 (XXMRGLW $C, $C))))>; 2524 2525def : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 0)), 2526 (v2f64 (XVCVUXWDP (v2i64 (XXMRGHW $C, $C))))>; 2527def : Pat<(v2f64 (PPCuvec2fp v4i32:$C, 1)), 2528 (v2f64 (XVCVUXWDP (v2i64 (XXMRGLW $C, $C))))>; 2529 2530def : Pat<(v2f64 (PPCfpexth v4f32:$C, 0)), (XVCVSPDP (XXMRGHW $C, $C))>; 2531def : Pat<(v2f64 (PPCfpexth v4f32:$C, 1)), (XVCVSPDP (XXMRGLW $C, $C))>; 2532 2533// Permutes. 2534def : Pat<(v2f64 (PPCxxswapd v2f64:$src)), (XXPERMDI $src, $src, 2)>; 2535def : Pat<(v2i64 (PPCxxswapd v2i64:$src)), (XXPERMDI $src, $src, 2)>; 2536def : Pat<(v4f32 (PPCxxswapd v4f32:$src)), (XXPERMDI $src, $src, 2)>; 2537def : Pat<(v4i32 (PPCxxswapd v4i32:$src)), (XXPERMDI $src, $src, 2)>; 2538def : Pat<(v2f64 (PPCswapNoChain v2f64:$src)), (XXPERMDI $src, $src, 2)>; 2539 2540// PPCvecshl XT, XA, XA, 2 can be selected to both XXSLDWI XT,XA,XA,2 and 2541// XXSWAPD XT,XA (i.e. XXPERMDI XT,XA,XA,2), the later one is more profitable. 2542def : Pat<(v4i32 (PPCvecshl v4i32:$src, v4i32:$src, 2)), 2543 (XXPERMDI $src, $src, 2)>; 2544 2545// Selects. 2546def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)), 2547 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 2548def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULT)), 2549 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 2550def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)), 2551 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>; 2552def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETULE)), 2553 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>; 2554def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)), 2555 (SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>; 2556def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)), 2557 (SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>; 2558def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGE)), 2559 (SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>; 2560def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)), 2561 (SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 2562def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETUGT)), 2563 (SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 2564def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)), 2565 (SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>; 2566 2567def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 2568 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>; 2569def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 2570 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>; 2571def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 2572 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>; 2573def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 2574 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>; 2575def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 2576 (SELECT_VSFRC (CREQV $lhs, $rhs), $tval, $fval)>; 2577def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 2578 (SELECT_VSFRC (CRORC $rhs, $lhs), $tval, $fval)>; 2579def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 2580 (SELECT_VSFRC (CRORC $lhs, $rhs), $tval, $fval)>; 2581def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 2582 (SELECT_VSFRC (CRANDC $rhs, $lhs), $tval, $fval)>; 2583def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 2584 (SELECT_VSFRC (CRANDC $lhs, $rhs), $tval, $fval)>; 2585def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 2586 (SELECT_VSFRC (CRXOR $lhs, $rhs), $tval, $fval)>; 2587 2588// Divides. 2589def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B), 2590 (XVDIVSP $A, $B)>; 2591def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B), 2592 (XVDIVDP $A, $B)>; 2593 2594// Vector test for software divide and sqrt. 2595def : Pat<(i32 (int_ppc_vsx_xvtdivdp v2f64:$A, v2f64:$B)), 2596 (COPY_TO_REGCLASS (XVTDIVDP $A, $B), GPRC)>; 2597def : Pat<(i32 (int_ppc_vsx_xvtdivsp v4f32:$A, v4f32:$B)), 2598 (COPY_TO_REGCLASS (XVTDIVSP $A, $B), GPRC)>; 2599def : Pat<(i32 (int_ppc_vsx_xvtsqrtdp v2f64:$A)), 2600 (COPY_TO_REGCLASS (XVTSQRTDP $A), GPRC)>; 2601def : Pat<(i32 (int_ppc_vsx_xvtsqrtsp v4f32:$A)), 2602 (COPY_TO_REGCLASS (XVTSQRTSP $A), GPRC)>; 2603 2604// Reciprocal estimate 2605def : Pat<(int_ppc_vsx_xvresp v4f32:$A), 2606 (XVRESP $A)>; 2607def : Pat<(int_ppc_vsx_xvredp v2f64:$A), 2608 (XVREDP $A)>; 2609 2610// Recip. square root estimate 2611def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A), 2612 (XVRSQRTESP $A)>; 2613def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A), 2614 (XVRSQRTEDP $A)>; 2615 2616// Vector selection 2617def : Pat<(v16i8 (vselect v16i8:$vA, v16i8:$vB, v16i8:$vC)), 2618 (COPY_TO_REGCLASS 2619 (XXSEL (COPY_TO_REGCLASS $vC, VSRC), 2620 (COPY_TO_REGCLASS $vB, VSRC), 2621 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 2622def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)), 2623 (COPY_TO_REGCLASS 2624 (XXSEL (COPY_TO_REGCLASS $vC, VSRC), 2625 (COPY_TO_REGCLASS $vB, VSRC), 2626 (COPY_TO_REGCLASS $vA, VSRC)), VRRC)>; 2627def : Pat<(vselect v4i32:$vA, v4i32:$vB, v4i32:$vC), 2628 (XXSEL $vC, $vB, $vA)>; 2629def : Pat<(vselect v2i64:$vA, v2i64:$vB, v2i64:$vC), 2630 (XXSEL $vC, $vB, $vA)>; 2631def : Pat<(vselect v4i32:$vA, v4f32:$vB, v4f32:$vC), 2632 (XXSEL $vC, $vB, $vA)>; 2633def : Pat<(vselect v2i64:$vA, v2f64:$vB, v2f64:$vC), 2634 (XXSEL $vC, $vB, $vA)>; 2635 2636def : Pat<(v4f32 (any_fmaxnum v4f32:$src1, v4f32:$src2)), 2637 (v4f32 (XVMAXSP $src1, $src2))>; 2638def : Pat<(v4f32 (any_fminnum v4f32:$src1, v4f32:$src2)), 2639 (v4f32 (XVMINSP $src1, $src2))>; 2640def : Pat<(v2f64 (any_fmaxnum v2f64:$src1, v2f64:$src2)), 2641 (v2f64 (XVMAXDP $src1, $src2))>; 2642def : Pat<(v2f64 (any_fminnum v2f64:$src1, v2f64:$src2)), 2643 (v2f64 (XVMINDP $src1, $src2))>; 2644 2645// f32 abs 2646def : Pat<(f32 (fabs f32:$S)), 2647 (f32 (COPY_TO_REGCLASS (XSABSDP 2648 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2649 2650// f32 nabs 2651def : Pat<(f32 (fneg (fabs f32:$S))), 2652 (f32 (COPY_TO_REGCLASS (XSNABSDP 2653 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2654 2655// f32 Min. 2656def : Pat<(f32 (fminnum_ieee f32:$A, f32:$B)), 2657 (f32 FpMinMax.F32Min)>; 2658def : Pat<(f32 (fminnum_ieee (fcanonicalize f32:$A), f32:$B)), 2659 (f32 FpMinMax.F32Min)>; 2660def : Pat<(f32 (fminnum_ieee f32:$A, (fcanonicalize f32:$B))), 2661 (f32 FpMinMax.F32Min)>; 2662def : Pat<(f32 (fminnum_ieee (fcanonicalize f32:$A), (fcanonicalize f32:$B))), 2663 (f32 FpMinMax.F32Min)>; 2664// F32 Max. 2665def : Pat<(f32 (fmaxnum_ieee f32:$A, f32:$B)), 2666 (f32 FpMinMax.F32Max)>; 2667def : Pat<(f32 (fmaxnum_ieee (fcanonicalize f32:$A), f32:$B)), 2668 (f32 FpMinMax.F32Max)>; 2669def : Pat<(f32 (fmaxnum_ieee f32:$A, (fcanonicalize f32:$B))), 2670 (f32 FpMinMax.F32Max)>; 2671def : Pat<(f32 (fmaxnum_ieee (fcanonicalize f32:$A), (fcanonicalize f32:$B))), 2672 (f32 FpMinMax.F32Max)>; 2673 2674// f64 Min. 2675def : Pat<(f64 (fminnum_ieee f64:$A, f64:$B)), 2676 (f64 (XSMINDP $A, $B))>; 2677def : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), f64:$B)), 2678 (f64 (XSMINDP $A, $B))>; 2679def : Pat<(f64 (fminnum_ieee f64:$A, (fcanonicalize f64:$B))), 2680 (f64 (XSMINDP $A, $B))>; 2681def : Pat<(f64 (fminnum_ieee (fcanonicalize f64:$A), (fcanonicalize f64:$B))), 2682 (f64 (XSMINDP $A, $B))>; 2683// f64 Max. 2684def : Pat<(f64 (fmaxnum_ieee f64:$A, f64:$B)), 2685 (f64 (XSMAXDP $A, $B))>; 2686def : Pat<(f64 (fmaxnum_ieee (fcanonicalize f64:$A), f64:$B)), 2687 (f64 (XSMAXDP $A, $B))>; 2688def : Pat<(f64 (fmaxnum_ieee f64:$A, (fcanonicalize f64:$B))), 2689 (f64 (XSMAXDP $A, $B))>; 2690def : Pat<(f64 (fmaxnum_ieee (fcanonicalize f64:$A), (fcanonicalize f64:$B))), 2691 (f64 (XSMAXDP $A, $B))>; 2692 2693def : Pat<(int_ppc_vsx_stxvd2x_be v2f64:$rS, xoaddr:$dst), 2694 (STXVD2X $rS, xoaddr:$dst)>; 2695def : Pat<(int_ppc_vsx_stxvw4x_be v4i32:$rS, xoaddr:$dst), 2696 (STXVW4X $rS, xoaddr:$dst)>; 2697def : Pat<(v4i32 (int_ppc_vsx_lxvw4x_be xoaddr:$src)), (LXVW4X xoaddr:$src)>; 2698def : Pat<(v2f64 (int_ppc_vsx_lxvd2x_be xoaddr:$src)), (LXVD2X xoaddr:$src)>; 2699 2700// Rounding for single precision. 2701def : Pat<(f32 (any_fround f32:$S)), 2702 (f32 (COPY_TO_REGCLASS (XSRDPI 2703 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2704def : Pat<(f32 (fnearbyint f32:$S)), 2705 (f32 (COPY_TO_REGCLASS (XSRDPIC 2706 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2707def : Pat<(f32 (any_ffloor f32:$S)), 2708 (f32 (COPY_TO_REGCLASS (XSRDPIM 2709 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2710def : Pat<(f32 (any_fceil f32:$S)), 2711 (f32 (COPY_TO_REGCLASS (XSRDPIP 2712 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2713def : Pat<(f32 (any_ftrunc f32:$S)), 2714 (f32 (COPY_TO_REGCLASS (XSRDPIZ 2715 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2716def : Pat<(f32 (any_frint f32:$S)), 2717 (f32 (COPY_TO_REGCLASS (XSRDPIC 2718 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 2719def : Pat<(v4f32 (any_frint v4f32:$S)), (v4f32 (XVRSPIC $S))>; 2720 2721// Rounding for double precision. 2722def : Pat<(f64 (any_frint f64:$S)), (f64 (XSRDPIC $S))>; 2723def : Pat<(v2f64 (any_frint v2f64:$S)), (v2f64 (XVRDPIC $S))>; 2724 2725// Materialize a zero-vector of long long 2726def : Pat<(v2i64 immAllZerosV), 2727 (v2i64 (XXLXORz))>; 2728 2729// Build vectors of floating point converted to i32. 2730def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.A, 2731 DblToInt.A, DblToInt.A)), 2732 (v4i32 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPSXWS $A), VSRC), 1))>; 2733def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.A, 2734 DblToUInt.A, DblToUInt.A)), 2735 (v4i32 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPUXWS $A), VSRC), 1))>; 2736def : Pat<(v2i64 (build_vector DblToLong.A, DblToLong.A)), 2737 (v2i64 (XXPERMDI (COPY_TO_REGCLASS (XSCVDPSXDS $A), VSRC), 2738 (COPY_TO_REGCLASS (XSCVDPSXDS $A), VSRC), 0))>; 2739def : Pat<(v2i64 (build_vector DblToULong.A, DblToULong.A)), 2740 (v2i64 (XXPERMDI (COPY_TO_REGCLASS (XSCVDPUXDS $A), VSRC), 2741 (COPY_TO_REGCLASS (XSCVDPUXDS $A), VSRC), 0))>; 2742defm : ScalToVecWPermute< 2743 v4i32, FltToIntLoad.A, 2744 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPSXWSs (XFLOADf32 xoaddr:$A)), VSRC), 1), 2745 (COPY_TO_REGCLASS (XSCVDPSXWSs (XFLOADf32 xoaddr:$A)), VSRC)>; 2746defm : ScalToVecWPermute< 2747 v4i32, FltToUIntLoad.A, 2748 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPUXWSs (XFLOADf32 xoaddr:$A)), VSRC), 1), 2749 (COPY_TO_REGCLASS (XSCVDPUXWSs (XFLOADf32 xoaddr:$A)), VSRC)>; 2750def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)), 2751 (v4f32 (XXSPLTW (v4f32 (XSCVDPSPN $A)), 0))>; 2752def : Pat<(v2f64 (PPCldsplat xoaddr:$A)), 2753 (v2f64 (LXVDSX xoaddr:$A))>; 2754def : Pat<(v2i64 (PPCldsplat xoaddr:$A)), 2755 (v2i64 (LXVDSX xoaddr:$A))>; 2756 2757// Build vectors of floating point converted to i64. 2758def : Pat<(v2i64 (build_vector FltToLong.A, FltToLong.A)), 2759 (v2i64 (XXPERMDIs 2760 (COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), 0))>; 2761def : Pat<(v2i64 (build_vector FltToULong.A, FltToULong.A)), 2762 (v2i64 (XXPERMDIs 2763 (COPY_TO_REGCLASS (XSCVDPUXDSs $A), VSFRC), 0))>; 2764defm : ScalToVecWPermute< 2765 v2i64, DblToLongLoad.A, 2766 (XVCVDPSXDS (LXVDSX xoaddr:$A)), (XVCVDPSXDS (LXVDSX xoaddr:$A))>; 2767defm : ScalToVecWPermute< 2768 v2i64, DblToULongLoad.A, 2769 (XVCVDPUXDS (LXVDSX xoaddr:$A)), (XVCVDPUXDS (LXVDSX xoaddr:$A))>; 2770} // HasVSX 2771 2772// Any big endian VSX subtarget. 2773let Predicates = [HasVSX, IsBigEndian] in { 2774def : Pat<(v2f64 (scalar_to_vector f64:$A)), 2775 (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>; 2776 2777def : Pat<(f64 (extractelt v2f64:$S, 0)), 2778 (f64 (EXTRACT_SUBREG $S, sub_64))>; 2779def : Pat<(f64 (extractelt v2f64:$S, 1)), 2780 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>; 2781def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))), 2782 (f64 (XSCVSXDDP (COPY_TO_REGCLASS $S, VSFRC)))>; 2783def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))), 2784 (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; 2785def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))), 2786 (f64 (XSCVUXDDP (COPY_TO_REGCLASS $S, VSFRC)))>; 2787def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))), 2788 (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; 2789 2790def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)), 2791 (f64 VectorExtractions.BE_VARIABLE_DOUBLE)>; 2792 2793def : Pat<(v2f64 (build_vector f64:$A, f64:$B)), 2794 (v2f64 (XXPERMDI 2795 (COPY_TO_REGCLASS $A, VSRC), 2796 (COPY_TO_REGCLASS $B, VSRC), 0))>; 2797// Using VMRGEW to assemble the final vector would be a lower latency 2798// solution. However, we choose to go with the slightly higher latency 2799// XXPERMDI for 2 reasons: 2800// 1. This is likely to occur in unrolled loops where regpressure is high, 2801// so we want to use the latter as it has access to all 64 VSX registers. 2802// 2. Using Altivec instructions in this sequence would likely cause the 2803// allocation of Altivec registers even for the loads which in turn would 2804// force the use of LXSIWZX for the loads, adding a cycle of latency to 2805// each of the loads which would otherwise be able to use LFIWZX. 2806def : Pat<(v4f32 (build_vector LoadFP.A, LoadFP.B, LoadFP.C, LoadFP.D)), 2807 (v4f32 (XXPERMDI (XXMRGHW MrgFP.LD32A, MrgFP.LD32B), 2808 (XXMRGHW MrgFP.LD32C, MrgFP.LD32D), 3))>; 2809def : Pat<(v4f32 (build_vector f32:$A, f32:$B, f32:$C, f32:$D)), 2810 (VMRGEW MrgFP.AC, MrgFP.BD)>; 2811def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1, 2812 DblToFlt.B0, DblToFlt.B1)), 2813 (v4f32 (VMRGEW MrgFP.ABhToFlt, MrgFP.ABlToFlt))>; 2814 2815// Convert 4 doubles to a vector of ints. 2816def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B, 2817 DblToInt.C, DblToInt.D)), 2818 (v4i32 (VMRGEW MrgWords.CVACS, MrgWords.CVBDS))>; 2819def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B, 2820 DblToUInt.C, DblToUInt.D)), 2821 (v4i32 (VMRGEW MrgWords.CVACU, MrgWords.CVBDU))>; 2822def : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S, 2823 ExtDbl.B0S, ExtDbl.B1S)), 2824 (v4i32 (VMRGEW MrgWords.CVA0B0S, MrgWords.CVA1B1S))>; 2825def : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U, 2826 ExtDbl.B0U, ExtDbl.B1U)), 2827 (v4i32 (VMRGEW MrgWords.CVA0B0U, MrgWords.CVA1B1U))>; 2828def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 2829 (f64 (fpextend (extractelt v4f32:$A, 1))))), 2830 (v2f64 (XVCVSPDP (XXMRGHW $A, $A)))>; 2831def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 2832 (f64 (fpextend (extractelt v4f32:$A, 0))))), 2833 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGHW $A, $A)), 2834 (XVCVSPDP (XXMRGHW $A, $A)), 2))>; 2835def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 2836 (f64 (fpextend (extractelt v4f32:$A, 2))))), 2837 (v2f64 (XVCVSPDP $A))>; 2838def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 2839 (f64 (fpextend (extractelt v4f32:$A, 3))))), 2840 (v2f64 (XVCVSPDP (XXSLDWI $A, $A, 3)))>; 2841def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 2))), 2842 (f64 (fpextend (extractelt v4f32:$A, 3))))), 2843 (v2f64 (XVCVSPDP (XXMRGLW $A, $A)))>; 2844def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))), 2845 (f64 (fpextend (extractelt v4f32:$A, 2))))), 2846 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGLW $A, $A)), 2847 (XVCVSPDP (XXMRGLW $A, $A)), 2))>; 2848def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 2849 (f64 (fpextend (extractelt v4f32:$B, 0))))), 2850 (v2f64 (XVCVSPDP (XXPERMDI $A, $B, 0)))>; 2851def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))), 2852 (f64 (fpextend (extractelt v4f32:$B, 3))))), 2853 (v2f64 (XVCVSPDP (XXSLDWI (XXPERMDI $A, $B, 3), 2854 (XXPERMDI $A, $B, 3), 1)))>; 2855def : Pat<WToDPExtractConv.BV02S, 2856 (v2f64 (XVCVSXWDP $A))>; 2857def : Pat<WToDPExtractConv.BV13S, 2858 (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 3)))>; 2859def : Pat<WToDPExtractConv.BV02U, 2860 (v2f64 (XVCVUXWDP $A))>; 2861def : Pat<WToDPExtractConv.BV13U, 2862 (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 3)))>; 2863} // HasVSX, IsBigEndian 2864 2865// Any little endian VSX subtarget. 2866let Predicates = [HasVSX, IsLittleEndian] in { 2867defm : ScalToVecWPermute<v2f64, (f64 f64:$A), 2868 (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64), 2869 (SUBREG_TO_REG (i64 1), $A, sub_64), 0), 2870 (SUBREG_TO_REG (i64 1), $A, sub_64)>; 2871 2872def : Pat<(f64 (extractelt v2f64:$S, 0)), 2873 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>; 2874def : Pat<(f64 (extractelt v2f64:$S, 1)), 2875 (f64 (EXTRACT_SUBREG $S, sub_64))>; 2876 2877def : Pat<(v2f64 (PPCld_vec_be xoaddr:$src)), (LXVD2X xoaddr:$src)>; 2878def : Pat<(PPCst_vec_be v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>; 2879def : Pat<(v4f32 (PPCld_vec_be xoaddr:$src)), (LXVW4X xoaddr:$src)>; 2880def : Pat<(PPCst_vec_be v4f32:$rS, xoaddr:$dst), (STXVW4X $rS, xoaddr:$dst)>; 2881def : Pat<(v2i64 (PPCld_vec_be xoaddr:$src)), (LXVD2X xoaddr:$src)>; 2882def : Pat<(PPCst_vec_be v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>; 2883def : Pat<(v4i32 (PPCld_vec_be xoaddr:$src)), (LXVW4X xoaddr:$src)>; 2884def : Pat<(PPCst_vec_be v4i32:$rS, xoaddr:$dst), (STXVW4X $rS, xoaddr:$dst)>; 2885def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))), 2886 (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; 2887def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))), 2888 (f64 (XSCVSXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>; 2889def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))), 2890 (f64 (XSCVUXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; 2891def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))), 2892 (f64 (XSCVUXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>; 2893 2894def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)), 2895 (f64 VectorExtractions.LE_VARIABLE_DOUBLE)>; 2896 2897// Little endian, available on all targets with VSX 2898def : Pat<(v2f64 (build_vector f64:$A, f64:$B)), 2899 (v2f64 (XXPERMDI 2900 (COPY_TO_REGCLASS $B, VSRC), 2901 (COPY_TO_REGCLASS $A, VSRC), 0))>; 2902// Using VMRGEW to assemble the final vector would be a lower latency 2903// solution. However, we choose to go with the slightly higher latency 2904// XXPERMDI for 2 reasons: 2905// 1. This is likely to occur in unrolled loops where regpressure is high, 2906// so we want to use the latter as it has access to all 64 VSX registers. 2907// 2. Using Altivec instructions in this sequence would likely cause the 2908// allocation of Altivec registers even for the loads which in turn would 2909// force the use of LXSIWZX for the loads, adding a cycle of latency to 2910// each of the loads which would otherwise be able to use LFIWZX. 2911def : Pat<(v4f32 (build_vector LoadFP.A, LoadFP.B, LoadFP.C, LoadFP.D)), 2912 (v4f32 (XXPERMDI (XXMRGHW MrgFP.LD32D, MrgFP.LD32C), 2913 (XXMRGHW MrgFP.LD32B, MrgFP.LD32A), 3))>; 2914def : Pat<(v4f32 (build_vector f32:$D, f32:$C, f32:$B, f32:$A)), 2915 (VMRGEW MrgFP.AC, MrgFP.BD)>; 2916def : Pat<(v4f32 (build_vector DblToFlt.A0, DblToFlt.A1, 2917 DblToFlt.B0, DblToFlt.B1)), 2918 (v4f32 (VMRGEW MrgFP.BAhToFlt, MrgFP.BAlToFlt))>; 2919 2920// Convert 4 doubles to a vector of ints. 2921def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.B, 2922 DblToInt.C, DblToInt.D)), 2923 (v4i32 (VMRGEW MrgWords.CVDBS, MrgWords.CVCAS))>; 2924def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.B, 2925 DblToUInt.C, DblToUInt.D)), 2926 (v4i32 (VMRGEW MrgWords.CVDBU, MrgWords.CVCAU))>; 2927def : Pat<(v4i32 (build_vector ExtDbl.A0S, ExtDbl.A1S, 2928 ExtDbl.B0S, ExtDbl.B1S)), 2929 (v4i32 (VMRGEW MrgWords.CVB1A1S, MrgWords.CVB0A0S))>; 2930def : Pat<(v4i32 (build_vector ExtDbl.A0U, ExtDbl.A1U, 2931 ExtDbl.B0U, ExtDbl.B1U)), 2932 (v4i32 (VMRGEW MrgWords.CVB1A1U, MrgWords.CVB0A0U))>; 2933def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 2934 (f64 (fpextend (extractelt v4f32:$A, 1))))), 2935 (v2f64 (XVCVSPDP (XXMRGLW $A, $A)))>; 2936def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 2937 (f64 (fpextend (extractelt v4f32:$A, 0))))), 2938 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGLW $A, $A)), 2939 (XVCVSPDP (XXMRGLW $A, $A)), 2))>; 2940def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 2941 (f64 (fpextend (extractelt v4f32:$A, 2))))), 2942 (v2f64 (XVCVSPDP (XXSLDWI $A, $A, 1)))>; 2943def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 1))), 2944 (f64 (fpextend (extractelt v4f32:$A, 3))))), 2945 (v2f64 (XVCVSPDP $A))>; 2946def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 2))), 2947 (f64 (fpextend (extractelt v4f32:$A, 3))))), 2948 (v2f64 (XVCVSPDP (XXMRGHW $A, $A)))>; 2949def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))), 2950 (f64 (fpextend (extractelt v4f32:$A, 2))))), 2951 (v2f64 (XXPERMDI (XVCVSPDP (XXMRGHW $A, $A)), 2952 (XVCVSPDP (XXMRGHW $A, $A)), 2))>; 2953def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 0))), 2954 (f64 (fpextend (extractelt v4f32:$B, 0))))), 2955 (v2f64 (XVCVSPDP (XXSLDWI (XXPERMDI $B, $A, 3), 2956 (XXPERMDI $B, $A, 3), 1)))>; 2957def : Pat<(v2f64 (build_vector (f64 (fpextend (extractelt v4f32:$A, 3))), 2958 (f64 (fpextend (extractelt v4f32:$B, 3))))), 2959 (v2f64 (XVCVSPDP (XXPERMDI $B, $A, 0)))>; 2960def : Pat<WToDPExtractConv.BV02S, 2961 (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 1)))>; 2962def : Pat<WToDPExtractConv.BV13S, 2963 (v2f64 (XVCVSXWDP $A))>; 2964def : Pat<WToDPExtractConv.BV02U, 2965 (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 1)))>; 2966def : Pat<WToDPExtractConv.BV13U, 2967 (v2f64 (XVCVUXWDP $A))>; 2968} // HasVSX, IsLittleEndian 2969 2970// Any pre-Power9 VSX subtarget. 2971let Predicates = [HasVSX, NoP9Vector] in { 2972def : Pat<(PPCstore_scal_int_from_vsr 2973 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xoaddr:$dst, 8), 2974 (STXSDX (XSCVDPSXDS f64:$src), xoaddr:$dst)>; 2975def : Pat<(PPCstore_scal_int_from_vsr 2976 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 8), 2977 (STXSDX (XSCVDPUXDS f64:$src), xoaddr:$dst)>; 2978 2979// Load-and-splat with fp-to-int conversion (using X-Form VSX/FP loads). 2980defm : ScalToVecWPermute< 2981 v4i32, DblToIntLoad.A, 2982 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPSXWS (XFLOADf64 xoaddr:$A)), VSRC), 1), 2983 (COPY_TO_REGCLASS (XSCVDPSXWS (XFLOADf64 xoaddr:$A)), VSRC)>; 2984defm : ScalToVecWPermute< 2985 v4i32, DblToUIntLoad.A, 2986 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPUXWS (XFLOADf64 xoaddr:$A)), VSRC), 1), 2987 (COPY_TO_REGCLASS (XSCVDPUXWS (XFLOADf64 xoaddr:$A)), VSRC)>; 2988defm : ScalToVecWPermute< 2989 v2i64, FltToLongLoad.A, 2990 (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 xoaddr:$A), VSFRC)), 0), 2991 (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 xoaddr:$A), 2992 VSFRC)), sub_64)>; 2993defm : ScalToVecWPermute< 2994 v2i64, FltToULongLoad.A, 2995 (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 xoaddr:$A), VSFRC)), 0), 2996 (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 xoaddr:$A), 2997 VSFRC)), sub_64)>; 2998} // HasVSX, NoP9Vector 2999 3000// Any VSX subtarget that only has loads and stores that load in big endian 3001// order regardless of endianness. This is really pre-Power9 subtargets. 3002let Predicates = [HasVSX, HasOnlySwappingMemOps] in { 3003 def : Pat<(v2f64 (PPClxvd2x xoaddr:$src)), (LXVD2X xoaddr:$src)>; 3004 3005 // Stores. 3006 def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst), 3007 (STXVD2X $rS, xoaddr:$dst)>; 3008 def : Pat<(PPCstxvd2x v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>; 3009} // HasVSX, HasOnlySwappingMemOps 3010 3011// Big endian VSX subtarget that only has loads and stores that always load 3012// in big endian order. Really big endian pre-Power9 subtargets. 3013let Predicates = [HasVSX, HasOnlySwappingMemOps, IsBigEndian] in { 3014 def : Pat<(v2f64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>; 3015 def : Pat<(v2i64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>; 3016 def : Pat<(v4i32 (load xoaddr:$src)), (LXVW4X xoaddr:$src)>; 3017 def : Pat<(v4i32 (int_ppc_vsx_lxvw4x xoaddr:$src)), (LXVW4X xoaddr:$src)>; 3018 def : Pat<(store v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>; 3019 def : Pat<(store v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>; 3020 def : Pat<(store v4i32:$XT, xoaddr:$dst), (STXVW4X $XT, xoaddr:$dst)>; 3021 def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xoaddr:$dst), 3022 (STXVW4X $rS, xoaddr:$dst)>; 3023} // HasVSX, HasOnlySwappingMemOps, IsBigEndian 3024 3025// Any Power8 VSX subtarget. 3026let Predicates = [HasVSX, HasP8Vector] in { 3027def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B), 3028 (XXLEQV $A, $B)>; 3029def : Pat<(f64 (extloadf32 xoaddr:$src)), 3030 (COPY_TO_REGCLASS (XFLOADf32 xoaddr:$src), VSFRC)>; 3031def : Pat<(f32 (fpround (f64 (extloadf32 xoaddr:$src)))), 3032 (f32 (XFLOADf32 xoaddr:$src))>; 3033def : Pat<(f64 (any_fpextend f32:$src)), 3034 (COPY_TO_REGCLASS $src, VSFRC)>; 3035 3036def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 3037 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 3038def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 3039 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 3040def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 3041 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>; 3042def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 3043 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>; 3044def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 3045 (SELECT_VSSRC (CREQV $lhs, $rhs), $tval, $fval)>; 3046def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 3047 (SELECT_VSSRC (CRORC $rhs, $lhs), $tval, $fval)>; 3048def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 3049 (SELECT_VSSRC (CRORC $lhs, $rhs), $tval, $fval)>; 3050def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 3051 (SELECT_VSSRC (CRANDC $rhs, $lhs), $tval, $fval)>; 3052def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 3053 (SELECT_VSSRC (CRANDC $lhs, $rhs), $tval, $fval)>; 3054def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 3055 (SELECT_VSSRC (CRXOR $lhs, $rhs), $tval, $fval)>; 3056 3057// Additional fnmsub pattern for PPC specific ISD opcode 3058def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C), 3059 (XSNMSUBASP $C, $A, $B)>; 3060def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)), 3061 (XSMSUBASP $C, $A, $B)>; 3062def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)), 3063 (XSNMADDASP $C, $A, $B)>; 3064 3065// f32 neg 3066// Although XSNEGDP is available in P7, we want to select it starting from P8, 3067// so that FNMSUBS can be selected for fneg-fmsub pattern on P7. (VSX version, 3068// XSNMSUBASP, is available since P8) 3069def : Pat<(f32 (fneg f32:$S)), 3070 (f32 (COPY_TO_REGCLASS (XSNEGDP 3071 (COPY_TO_REGCLASS $S, VSFRC)), VSSRC))>; 3072 3073// Instructions for converting float to i32 feeding a store. 3074def : Pat<(PPCstore_scal_int_from_vsr 3075 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xoaddr:$dst, 4), 3076 (STIWX (XSCVDPSXWS f64:$src), xoaddr:$dst)>; 3077def : Pat<(PPCstore_scal_int_from_vsr 3078 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 4), 3079 (STIWX (XSCVDPUXWS f64:$src), xoaddr:$dst)>; 3080 3081def : Pat<(v2i64 (smax v2i64:$src1, v2i64:$src2)), 3082 (v2i64 (VMAXSD (COPY_TO_REGCLASS $src1, VRRC), 3083 (COPY_TO_REGCLASS $src2, VRRC)))>; 3084def : Pat<(v2i64 (umax v2i64:$src1, v2i64:$src2)), 3085 (v2i64 (VMAXUD (COPY_TO_REGCLASS $src1, VRRC), 3086 (COPY_TO_REGCLASS $src2, VRRC)))>; 3087def : Pat<(v2i64 (smin v2i64:$src1, v2i64:$src2)), 3088 (v2i64 (VMINSD (COPY_TO_REGCLASS $src1, VRRC), 3089 (COPY_TO_REGCLASS $src2, VRRC)))>; 3090def : Pat<(v2i64 (umin v2i64:$src1, v2i64:$src2)), 3091 (v2i64 (VMINUD (COPY_TO_REGCLASS $src1, VRRC), 3092 (COPY_TO_REGCLASS $src2, VRRC)))>; 3093 3094def : Pat<(v1i128 (bitconvert (v16i8 immAllOnesV))), 3095 (v1i128 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>; 3096def : Pat<(v2i64 (bitconvert (v16i8 immAllOnesV))), 3097 (v2i64 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>; 3098def : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))), 3099 (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>; 3100def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))), 3101 (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>; 3102} // HasVSX, HasP8Vector 3103 3104// Big endian Power8 VSX subtarget. 3105let Predicates = [HasVSX, HasP8Vector, IsBigEndian] in { 3106def : Pat<DWToSPExtractConv.El0SS1, 3107 (f32 (XSCVSXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>; 3108def : Pat<DWToSPExtractConv.El1SS1, 3109 (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; 3110def : Pat<DWToSPExtractConv.El0US1, 3111 (f32 (XSCVUXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>; 3112def : Pat<DWToSPExtractConv.El1US1, 3113 (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; 3114 3115// v4f32 scalar <-> vector conversions (BE) 3116def : Pat<(v4f32 (scalar_to_vector f32:$A)), 3117 (v4f32 (XSCVDPSPN $A))>; 3118def : Pat<(f32 (vector_extract v4f32:$S, 0)), 3119 (f32 (XSCVSPDPN $S))>; 3120def : Pat<(f32 (vector_extract v4f32:$S, 1)), 3121 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>; 3122def : Pat<(f32 (vector_extract v4f32:$S, 2)), 3123 (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>; 3124def : Pat<(f32 (vector_extract v4f32:$S, 3)), 3125 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>; 3126def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)), 3127 (f32 VectorExtractions.BE_VARIABLE_FLOAT)>; 3128 3129def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))), 3130 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>; 3131def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))), 3132 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>; 3133def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))), 3134 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>; 3135def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))), 3136 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>; 3137def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))), 3138 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>; 3139def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))), 3140 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>; 3141def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))), 3142 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>; 3143def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))), 3144 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>; 3145 3146// LIWAX - This instruction is used for sign extending i32 -> i64. 3147// LIWZX - This instruction will be emitted for i32, f32, and when 3148// zero-extending i32 to i64 (zext i32 -> i64). 3149def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 xoaddr:$src)))), 3150 (v2i64 (COPY_TO_REGCLASS (LIWAX xoaddr:$src), VSRC))>; 3151def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 xoaddr:$src)))), 3152 (v2i64 (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC))>; 3153def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))), 3154 (v4i32 (XXSLDWIs 3155 (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 1))>; 3156def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))), 3157 (v4f32 (XXSLDWIs 3158 (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 1))>; 3159 3160def : Pat<DWToSPExtractConv.BVU, 3161 (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3), 3162 (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3)))>; 3163def : Pat<DWToSPExtractConv.BVS, 3164 (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3), 3165 (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3)))>; 3166def : Pat<(store (i32 (extractelt v4i32:$A, 1)), xoaddr:$src), 3167 (STIWX (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>; 3168def : Pat<(store (f32 (extractelt v4f32:$A, 1)), xoaddr:$src), 3169 (STIWX (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>; 3170 3171// Elements in a register on a BE system are in order <0, 1, 2, 3>. 3172// The store instructions store the second word from the left. 3173// So to align element zero, we need to modulo-left-shift by 3 words. 3174// Similar logic applies for elements 2 and 3. 3175foreach Idx = [ [0,3], [2,1], [3,2] ] in { 3176 def : Pat<(store (i32 (extractelt v4i32:$A, !head(Idx))), xoaddr:$src), 3177 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))), 3178 sub_64), xoaddr:$src)>; 3179 def : Pat<(store (f32 (extractelt v4f32:$A, !head(Idx))), xoaddr:$src), 3180 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))), 3181 sub_64), xoaddr:$src)>; 3182} 3183} // HasVSX, HasP8Vector, IsBigEndian 3184 3185// Little endian Power8 VSX subtarget. 3186let Predicates = [HasVSX, HasP8Vector, IsLittleEndian] in { 3187def : Pat<DWToSPExtractConv.El0SS1, 3188 (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; 3189def : Pat<DWToSPExtractConv.El1SS1, 3190 (f32 (XSCVSXDSP (COPY_TO_REGCLASS 3191 (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>; 3192def : Pat<DWToSPExtractConv.El0US1, 3193 (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>; 3194def : Pat<DWToSPExtractConv.El1US1, 3195 (f32 (XSCVUXDSP (COPY_TO_REGCLASS 3196 (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>; 3197 3198// v4f32 scalar <-> vector conversions (LE) 3199 // The permuted version is no better than the version that puts the value 3200 // into the right element because XSCVDPSPN is different from all the other 3201 // instructions used for PPCSToV. 3202 defm : ScalToVecWPermute<v4f32, (f32 f32:$A), 3203 (XXSLDWI (XSCVDPSPN $A), (XSCVDPSPN $A), 1), 3204 (XXSLDWI (XSCVDPSPN $A), (XSCVDPSPN $A), 3)>; 3205def : Pat<(f32 (vector_extract v4f32:$S, 0)), 3206 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>; 3207def : Pat<(f32 (vector_extract v4f32:$S, 1)), 3208 (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>; 3209def : Pat<(f32 (vector_extract v4f32:$S, 2)), 3210 (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>; 3211def : Pat<(f32 (vector_extract v4f32:$S, 3)), 3212 (f32 (XSCVSPDPN $S))>; 3213def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)), 3214 (f32 VectorExtractions.LE_VARIABLE_FLOAT)>; 3215 3216def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))), 3217 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 3))))>; 3218def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))), 3219 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 2))))>; 3220def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))), 3221 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 1))))>; 3222def : Pat<(f32 (PPCfcfids (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))), 3223 (f32 (XSCVSPDPN (XVCVSXWSP (XXSPLTW $A, 0))))>; 3224def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 0)))))), 3225 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 3)), VSFRC))>; 3226def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 1)))))), 3227 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 2)), VSFRC))>; 3228def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 2)))))), 3229 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 1)), VSFRC))>; 3230def : Pat<(f64 (PPCfcfid (f64 (PPCmtvsra (i32 (extractelt v4i32:$A, 3)))))), 3231 (f64 (COPY_TO_REGCLASS (XVCVSXWDP (XXSPLTW $A, 0)), VSFRC))>; 3232 3233// LIWAX - This instruction is used for sign extending i32 -> i64. 3234// LIWZX - This instruction will be emitted for i32, f32, and when 3235// zero-extending i32 to i64 (zext i32 -> i64). 3236defm : ScalToVecWPermute< 3237 v2i64, (i64 (sextloadi32 xoaddr:$src)), 3238 (XXPERMDIs (COPY_TO_REGCLASS (LIWAX xoaddr:$src), VSFRC), 2), 3239 (SUBREG_TO_REG (i64 1), (LIWAX xoaddr:$src), sub_64)>; 3240 3241defm : ScalToVecWPermute< 3242 v2i64, (i64 (zextloadi32 xoaddr:$src)), 3243 (XXPERMDIs (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSFRC), 2), 3244 (SUBREG_TO_REG (i64 1), (LIWZX xoaddr:$src), sub_64)>; 3245 3246defm : ScalToVecWPermute< 3247 v4i32, (i32 (load xoaddr:$src)), 3248 (XXPERMDIs (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSFRC), 2), 3249 (SUBREG_TO_REG (i64 1), (LIWZX xoaddr:$src), sub_64)>; 3250 3251defm : ScalToVecWPermute< 3252 v4f32, (f32 (load xoaddr:$src)), 3253 (XXPERMDIs (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSFRC), 2), 3254 (SUBREG_TO_REG (i64 1), (LIWZX xoaddr:$src), sub_64)>; 3255 3256def : Pat<DWToSPExtractConv.BVU, 3257 (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3), 3258 (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3)))>; 3259def : Pat<DWToSPExtractConv.BVS, 3260 (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3), 3261 (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3)))>; 3262def : Pat<(store (i32 (extractelt v4i32:$A, 2)), xoaddr:$src), 3263 (STIWX (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>; 3264def : Pat<(store (f32 (extractelt v4f32:$A, 2)), xoaddr:$src), 3265 (STIWX (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>; 3266 3267// Elements in a register on a LE system are in order <3, 2, 1, 0>. 3268// The store instructions store the second word from the left. 3269// So to align element 3, we need to modulo-left-shift by 3 words. 3270// Similar logic applies for elements 0 and 1. 3271foreach Idx = [ [0,2], [1,1], [3,3] ] in { 3272 def : Pat<(store (i32 (extractelt v4i32:$A, !head(Idx))), xoaddr:$src), 3273 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))), 3274 sub_64), xoaddr:$src)>; 3275 def : Pat<(store (f32 (extractelt v4f32:$A, !head(Idx))), xoaddr:$src), 3276 (STIWX (EXTRACT_SUBREG (XXSLDWI $A, $A, !head(!tail(Idx))), 3277 sub_64), xoaddr:$src)>; 3278} 3279} // HasVSX, HasP8Vector, IsLittleEndian 3280 3281// Big endian pre-Power9 VSX subtarget. 3282let Predicates = [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian] in { 3283def : Pat<(store (i64 (extractelt v2i64:$A, 0)), xoaddr:$src), 3284 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>; 3285def : Pat<(store (f64 (extractelt v2f64:$A, 0)), xoaddr:$src), 3286 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>; 3287def : Pat<(store (i64 (extractelt v2i64:$A, 1)), xoaddr:$src), 3288 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 3289 xoaddr:$src)>; 3290def : Pat<(store (f64 (extractelt v2f64:$A, 1)), xoaddr:$src), 3291 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 3292 xoaddr:$src)>; 3293} // HasVSX, HasP8Vector, NoP9Vector, IsBigEndian 3294 3295// Little endian pre-Power9 VSX subtarget. 3296let Predicates = [HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian] in { 3297def : Pat<(store (i64 (extractelt v2i64:$A, 0)), xoaddr:$src), 3298 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 3299 xoaddr:$src)>; 3300def : Pat<(store (f64 (extractelt v2f64:$A, 0)), xoaddr:$src), 3301 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 3302 xoaddr:$src)>; 3303def : Pat<(store (i64 (extractelt v2i64:$A, 1)), xoaddr:$src), 3304 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>; 3305def : Pat<(store (f64 (extractelt v2f64:$A, 1)), xoaddr:$src), 3306 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xoaddr:$src)>; 3307} // HasVSX, HasP8Vector, NoP9Vector, IsLittleEndian 3308 3309// Any VSX target with direct moves. 3310let Predicates = [HasVSX, HasDirectMove] in { 3311// bitconvert f32 -> i32 3312// (convert to 32-bit fp single, shift right 1 word, move to GPR) 3313def : Pat<(i32 (bitconvert f32:$S)), 3314 (i32 (MFVSRWZ (EXTRACT_SUBREG 3315 (XXSLDWI (XSCVDPSPN $S), (XSCVDPSPN $S), 3), 3316 sub_64)))>; 3317// bitconvert i32 -> f32 3318// (move to FPR, shift left 1 word, convert to 64-bit fp single) 3319def : Pat<(f32 (bitconvert i32:$A)), 3320 (f32 (XSCVSPDPN 3321 (XXSLDWI MovesToVSR.LE_WORD_1, MovesToVSR.LE_WORD_1, 1)))>; 3322 3323// bitconvert f64 -> i64 3324// (move to GPR, nothing else needed) 3325def : Pat<(i64 (bitconvert f64:$S)), 3326 (i64 (MFVSRD $S))>; 3327 3328// bitconvert i64 -> f64 3329// (move to FPR, nothing else needed) 3330def : Pat<(f64 (bitconvert i64:$S)), 3331 (f64 (MTVSRD $S))>; 3332 3333// Rounding to integer. 3334def : Pat<(i64 (lrint f64:$S)), 3335 (i64 (MFVSRD (FCTID $S)))>; 3336def : Pat<(i64 (lrint f32:$S)), 3337 (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>; 3338def : Pat<(i64 (llrint f64:$S)), 3339 (i64 (MFVSRD (FCTID $S)))>; 3340def : Pat<(i64 (llrint f32:$S)), 3341 (i64 (MFVSRD (FCTID (COPY_TO_REGCLASS $S, F8RC))))>; 3342def : Pat<(i64 (lround f64:$S)), 3343 (i64 (MFVSRD (FCTID (XSRDPI $S))))>; 3344def : Pat<(i64 (lround f32:$S)), 3345 (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>; 3346def : Pat<(i64 (llround f64:$S)), 3347 (i64 (MFVSRD (FCTID (XSRDPI $S))))>; 3348def : Pat<(i64 (llround f32:$S)), 3349 (i64 (MFVSRD (FCTID (XSRDPI (COPY_TO_REGCLASS $S, VSFRC)))))>; 3350 3351// Alternate patterns for PPCmtvsrz where the output is v8i16 or v16i8 instead 3352// of f64 3353def : Pat<(v8i16 (PPCmtvsrz i32:$A)), 3354 (v8i16 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>; 3355def : Pat<(v16i8 (PPCmtvsrz i32:$A)), 3356 (v16i8 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>; 3357 3358// Endianness-neutral constant splat on P8 and newer targets. The reason 3359// for this pattern is that on targets with direct moves, we don't expand 3360// BUILD_VECTOR nodes for v4i32. 3361def : Pat<(v4i32 (build_vector immSExt5NonZero:$A, immSExt5NonZero:$A, 3362 immSExt5NonZero:$A, immSExt5NonZero:$A)), 3363 (v4i32 (VSPLTISW imm:$A))>; 3364} // HasVSX, HasDirectMove 3365 3366// Big endian VSX subtarget with direct moves. 3367let Predicates = [HasVSX, HasDirectMove, IsBigEndian] in { 3368// v16i8 scalar <-> vector conversions (BE) 3369def : Pat<(v16i8 (scalar_to_vector i32:$A)), 3370 (v16i8 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64))>; 3371def : Pat<(v8i16 (scalar_to_vector i32:$A)), 3372 (v8i16 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_HALF_0, sub_64))>; 3373def : Pat<(v4i32 (scalar_to_vector i32:$A)), 3374 (v4i32 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64))>; 3375def : Pat<(v2i64 (scalar_to_vector i64:$A)), 3376 (v2i64 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_DWORD_0, sub_64))>; 3377 3378// v2i64 scalar <-> vector conversions (BE) 3379def : Pat<(i64 (vector_extract v2i64:$S, 0)), 3380 (i64 VectorExtractions.LE_DWORD_1)>; 3381def : Pat<(i64 (vector_extract v2i64:$S, 1)), 3382 (i64 VectorExtractions.LE_DWORD_0)>; 3383def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)), 3384 (i64 VectorExtractions.BE_VARIABLE_DWORD)>; 3385} // HasVSX, HasDirectMove, IsBigEndian 3386 3387// Little endian VSX subtarget with direct moves. 3388let Predicates = [HasVSX, HasDirectMove, IsLittleEndian] in { 3389 // v16i8 scalar <-> vector conversions (LE) 3390 defm : ScalToVecWPermute<v16i8, (i32 i32:$A), 3391 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC), 3392 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>; 3393 defm : ScalToVecWPermute<v8i16, (i32 i32:$A), 3394 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC), 3395 (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>; 3396 defm : ScalToVecWPermute<v4i32, (i32 i32:$A), MovesToVSR.LE_WORD_0, 3397 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; 3398 defm : ScalToVecWPermute<v2i64, (i64 i64:$A), MovesToVSR.LE_DWORD_0, 3399 MovesToVSR.LE_DWORD_1>; 3400 3401 // v2i64 scalar <-> vector conversions (LE) 3402 def : Pat<(i64 (vector_extract v2i64:$S, 0)), 3403 (i64 VectorExtractions.LE_DWORD_0)>; 3404 def : Pat<(i64 (vector_extract v2i64:$S, 1)), 3405 (i64 VectorExtractions.LE_DWORD_1)>; 3406 def : Pat<(i64 (vector_extract v2i64:$S, i64:$Idx)), 3407 (i64 VectorExtractions.LE_VARIABLE_DWORD)>; 3408} // HasVSX, HasDirectMove, IsLittleEndian 3409 3410// Big endian pre-P9 VSX subtarget with direct moves. 3411let Predicates = [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian] in { 3412def : Pat<(i32 (vector_extract v16i8:$S, 0)), 3413 (i32 VectorExtractions.LE_BYTE_15)>; 3414def : Pat<(i32 (vector_extract v16i8:$S, 1)), 3415 (i32 VectorExtractions.LE_BYTE_14)>; 3416def : Pat<(i32 (vector_extract v16i8:$S, 2)), 3417 (i32 VectorExtractions.LE_BYTE_13)>; 3418def : Pat<(i32 (vector_extract v16i8:$S, 3)), 3419 (i32 VectorExtractions.LE_BYTE_12)>; 3420def : Pat<(i32 (vector_extract v16i8:$S, 4)), 3421 (i32 VectorExtractions.LE_BYTE_11)>; 3422def : Pat<(i32 (vector_extract v16i8:$S, 5)), 3423 (i32 VectorExtractions.LE_BYTE_10)>; 3424def : Pat<(i32 (vector_extract v16i8:$S, 6)), 3425 (i32 VectorExtractions.LE_BYTE_9)>; 3426def : Pat<(i32 (vector_extract v16i8:$S, 7)), 3427 (i32 VectorExtractions.LE_BYTE_8)>; 3428def : Pat<(i32 (vector_extract v16i8:$S, 8)), 3429 (i32 VectorExtractions.LE_BYTE_7)>; 3430def : Pat<(i32 (vector_extract v16i8:$S, 9)), 3431 (i32 VectorExtractions.LE_BYTE_6)>; 3432def : Pat<(i32 (vector_extract v16i8:$S, 10)), 3433 (i32 VectorExtractions.LE_BYTE_5)>; 3434def : Pat<(i32 (vector_extract v16i8:$S, 11)), 3435 (i32 VectorExtractions.LE_BYTE_4)>; 3436def : Pat<(i32 (vector_extract v16i8:$S, 12)), 3437 (i32 VectorExtractions.LE_BYTE_3)>; 3438def : Pat<(i32 (vector_extract v16i8:$S, 13)), 3439 (i32 VectorExtractions.LE_BYTE_2)>; 3440def : Pat<(i32 (vector_extract v16i8:$S, 14)), 3441 (i32 VectorExtractions.LE_BYTE_1)>; 3442def : Pat<(i32 (vector_extract v16i8:$S, 15)), 3443 (i32 VectorExtractions.LE_BYTE_0)>; 3444def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 3445 (i32 VectorExtractions.BE_VARIABLE_BYTE)>; 3446 3447// v8i16 scalar <-> vector conversions (BE) 3448def : Pat<(i32 (vector_extract v8i16:$S, 0)), 3449 (i32 VectorExtractions.LE_HALF_7)>; 3450def : Pat<(i32 (vector_extract v8i16:$S, 1)), 3451 (i32 VectorExtractions.LE_HALF_6)>; 3452def : Pat<(i32 (vector_extract v8i16:$S, 2)), 3453 (i32 VectorExtractions.LE_HALF_5)>; 3454def : Pat<(i32 (vector_extract v8i16:$S, 3)), 3455 (i32 VectorExtractions.LE_HALF_4)>; 3456def : Pat<(i32 (vector_extract v8i16:$S, 4)), 3457 (i32 VectorExtractions.LE_HALF_3)>; 3458def : Pat<(i32 (vector_extract v8i16:$S, 5)), 3459 (i32 VectorExtractions.LE_HALF_2)>; 3460def : Pat<(i32 (vector_extract v8i16:$S, 6)), 3461 (i32 VectorExtractions.LE_HALF_1)>; 3462def : Pat<(i32 (vector_extract v8i16:$S, 7)), 3463 (i32 VectorExtractions.LE_HALF_0)>; 3464def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 3465 (i32 VectorExtractions.BE_VARIABLE_HALF)>; 3466 3467// v4i32 scalar <-> vector conversions (BE) 3468def : Pat<(i32 (vector_extract v4i32:$S, 0)), 3469 (i32 VectorExtractions.LE_WORD_3)>; 3470def : Pat<(i32 (vector_extract v4i32:$S, 1)), 3471 (i32 VectorExtractions.LE_WORD_2)>; 3472def : Pat<(i32 (vector_extract v4i32:$S, 2)), 3473 (i32 VectorExtractions.LE_WORD_1)>; 3474def : Pat<(i32 (vector_extract v4i32:$S, 3)), 3475 (i32 VectorExtractions.LE_WORD_0)>; 3476def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 3477 (i32 VectorExtractions.BE_VARIABLE_WORD)>; 3478} // HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian 3479 3480// Little endian pre-P9 VSX subtarget with direct moves. 3481let Predicates = [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian] in { 3482def : Pat<(i32 (vector_extract v16i8:$S, 0)), 3483 (i32 VectorExtractions.LE_BYTE_0)>; 3484def : Pat<(i32 (vector_extract v16i8:$S, 1)), 3485 (i32 VectorExtractions.LE_BYTE_1)>; 3486def : Pat<(i32 (vector_extract v16i8:$S, 2)), 3487 (i32 VectorExtractions.LE_BYTE_2)>; 3488def : Pat<(i32 (vector_extract v16i8:$S, 3)), 3489 (i32 VectorExtractions.LE_BYTE_3)>; 3490def : Pat<(i32 (vector_extract v16i8:$S, 4)), 3491 (i32 VectorExtractions.LE_BYTE_4)>; 3492def : Pat<(i32 (vector_extract v16i8:$S, 5)), 3493 (i32 VectorExtractions.LE_BYTE_5)>; 3494def : Pat<(i32 (vector_extract v16i8:$S, 6)), 3495 (i32 VectorExtractions.LE_BYTE_6)>; 3496def : Pat<(i32 (vector_extract v16i8:$S, 7)), 3497 (i32 VectorExtractions.LE_BYTE_7)>; 3498def : Pat<(i32 (vector_extract v16i8:$S, 8)), 3499 (i32 VectorExtractions.LE_BYTE_8)>; 3500def : Pat<(i32 (vector_extract v16i8:$S, 9)), 3501 (i32 VectorExtractions.LE_BYTE_9)>; 3502def : Pat<(i32 (vector_extract v16i8:$S, 10)), 3503 (i32 VectorExtractions.LE_BYTE_10)>; 3504def : Pat<(i32 (vector_extract v16i8:$S, 11)), 3505 (i32 VectorExtractions.LE_BYTE_11)>; 3506def : Pat<(i32 (vector_extract v16i8:$S, 12)), 3507 (i32 VectorExtractions.LE_BYTE_12)>; 3508def : Pat<(i32 (vector_extract v16i8:$S, 13)), 3509 (i32 VectorExtractions.LE_BYTE_13)>; 3510def : Pat<(i32 (vector_extract v16i8:$S, 14)), 3511 (i32 VectorExtractions.LE_BYTE_14)>; 3512def : Pat<(i32 (vector_extract v16i8:$S, 15)), 3513 (i32 VectorExtractions.LE_BYTE_15)>; 3514def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 3515 (i32 VectorExtractions.LE_VARIABLE_BYTE)>; 3516 3517// v8i16 scalar <-> vector conversions (LE) 3518def : Pat<(i32 (vector_extract v8i16:$S, 0)), 3519 (i32 VectorExtractions.LE_HALF_0)>; 3520def : Pat<(i32 (vector_extract v8i16:$S, 1)), 3521 (i32 VectorExtractions.LE_HALF_1)>; 3522def : Pat<(i32 (vector_extract v8i16:$S, 2)), 3523 (i32 VectorExtractions.LE_HALF_2)>; 3524def : Pat<(i32 (vector_extract v8i16:$S, 3)), 3525 (i32 VectorExtractions.LE_HALF_3)>; 3526def : Pat<(i32 (vector_extract v8i16:$S, 4)), 3527 (i32 VectorExtractions.LE_HALF_4)>; 3528def : Pat<(i32 (vector_extract v8i16:$S, 5)), 3529 (i32 VectorExtractions.LE_HALF_5)>; 3530def : Pat<(i32 (vector_extract v8i16:$S, 6)), 3531 (i32 VectorExtractions.LE_HALF_6)>; 3532def : Pat<(i32 (vector_extract v8i16:$S, 7)), 3533 (i32 VectorExtractions.LE_HALF_7)>; 3534def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 3535 (i32 VectorExtractions.LE_VARIABLE_HALF)>; 3536 3537// v4i32 scalar <-> vector conversions (LE) 3538def : Pat<(i32 (vector_extract v4i32:$S, 0)), 3539 (i32 VectorExtractions.LE_WORD_0)>; 3540def : Pat<(i32 (vector_extract v4i32:$S, 1)), 3541 (i32 VectorExtractions.LE_WORD_1)>; 3542def : Pat<(i32 (vector_extract v4i32:$S, 2)), 3543 (i32 VectorExtractions.LE_WORD_2)>; 3544def : Pat<(i32 (vector_extract v4i32:$S, 3)), 3545 (i32 VectorExtractions.LE_WORD_3)>; 3546def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 3547 (i32 VectorExtractions.LE_VARIABLE_WORD)>; 3548} // HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian 3549 3550// Big endian pre-Power9 VSX subtarget that has direct moves. 3551let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian] in { 3552// Big endian integer vectors using direct moves. 3553def : Pat<(v2i64 (build_vector i64:$A, i64:$B)), 3554 (v2i64 (XXPERMDI 3555 (COPY_TO_REGCLASS (MTVSRD $A), VSRC), 3556 (COPY_TO_REGCLASS (MTVSRD $B), VSRC), 0))>; 3557def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), 3558 (XXPERMDI 3559 (COPY_TO_REGCLASS 3560 (MTVSRD (RLDIMI AnyExts.B, AnyExts.A, 32, 0)), VSRC), 3561 (COPY_TO_REGCLASS 3562 (MTVSRD (RLDIMI AnyExts.D, AnyExts.C, 32, 0)), VSRC), 0)>; 3563def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), 3564 (XXSPLTW (COPY_TO_REGCLASS (MTVSRWZ $A), VSRC), 1)>; 3565} // HasVSX, HasDirectMove, NoP9Vector, IsBigEndian 3566 3567// Little endian pre-Power9 VSX subtarget that has direct moves. 3568let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian] in { 3569// Little endian integer vectors using direct moves. 3570def : Pat<(v2i64 (build_vector i64:$A, i64:$B)), 3571 (v2i64 (XXPERMDI 3572 (COPY_TO_REGCLASS (MTVSRD $B), VSRC), 3573 (COPY_TO_REGCLASS (MTVSRD $A), VSRC), 0))>; 3574def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), 3575 (XXPERMDI 3576 (COPY_TO_REGCLASS 3577 (MTVSRD (RLDIMI AnyExts.C, AnyExts.D, 32, 0)), VSRC), 3578 (COPY_TO_REGCLASS 3579 (MTVSRD (RLDIMI AnyExts.A, AnyExts.B, 32, 0)), VSRC), 0)>; 3580def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), 3581 (XXSPLTW (COPY_TO_REGCLASS (MTVSRWZ $A), VSRC), 1)>; 3582} 3583 3584// Any Power9 VSX subtarget. 3585let Predicates = [HasVSX, HasP9Vector] in { 3586// Additional fnmsub pattern for PPC specific ISD opcode 3587def : Pat<(PPCfnmsub f128:$A, f128:$B, f128:$C), 3588 (XSNMSUBQP $C, $A, $B)>; 3589def : Pat<(fneg (PPCfnmsub f128:$A, f128:$B, f128:$C)), 3590 (XSMSUBQP $C, $A, $B)>; 3591def : Pat<(PPCfnmsub f128:$A, f128:$B, (fneg f128:$C)), 3592 (XSNMADDQP $C, $A, $B)>; 3593 3594def : Pat<(f128 (any_sint_to_fp i64:$src)), 3595 (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; 3596def : Pat<(f128 (any_sint_to_fp (i64 (PPCmfvsr f64:$src)))), 3597 (f128 (XSCVSDQP $src))>; 3598def : Pat<(f128 (any_sint_to_fp (i32 (PPCmfvsr f64:$src)))), 3599 (f128 (XSCVSDQP (VEXTSW2Ds $src)))>; 3600def : Pat<(f128 (any_uint_to_fp i64:$src)), 3601 (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; 3602def : Pat<(f128 (any_uint_to_fp (i64 (PPCmfvsr f64:$src)))), 3603 (f128 (XSCVUDQP $src))>; 3604 3605// Convert (Un)Signed Word -> QP. 3606def : Pat<(f128 (any_sint_to_fp i32:$src)), 3607 (f128 (XSCVSDQP (MTVSRWA $src)))>; 3608def : Pat<(f128 (any_sint_to_fp (i32 (load xoaddr:$src)))), 3609 (f128 (XSCVSDQP (LIWAX xoaddr:$src)))>; 3610def : Pat<(f128 (any_uint_to_fp i32:$src)), 3611 (f128 (XSCVUDQP (MTVSRWZ $src)))>; 3612def : Pat<(f128 (any_uint_to_fp (i32 (load xoaddr:$src)))), 3613 (f128 (XSCVUDQP (LIWZX xoaddr:$src)))>; 3614 3615// Pattern for matching Vector HP -> Vector SP intrinsic. Defined as a 3616// separate pattern so that it can convert the input register class from 3617// VRRC(v8i16) to VSRC. 3618def : Pat<(v4f32 (int_ppc_vsx_xvcvhpsp v8i16:$A)), 3619 (v4f32 (XVCVHPSP (COPY_TO_REGCLASS $A, VSRC)))>; 3620 3621// Use current rounding mode 3622def : Pat<(f128 (any_fnearbyint f128:$vB)), (f128 (XSRQPI 0, $vB, 3))>; 3623// Round to nearest, ties away from zero 3624def : Pat<(f128 (any_fround f128:$vB)), (f128 (XSRQPI 0, $vB, 0))>; 3625// Round towards Zero 3626def : Pat<(f128 (any_ftrunc f128:$vB)), (f128 (XSRQPI 1, $vB, 1))>; 3627// Round towards +Inf 3628def : Pat<(f128 (any_fceil f128:$vB)), (f128 (XSRQPI 1, $vB, 2))>; 3629// Round towards -Inf 3630def : Pat<(f128 (any_ffloor f128:$vB)), (f128 (XSRQPI 1, $vB, 3))>; 3631// Use current rounding mode, [with Inexact] 3632def : Pat<(f128 (any_frint f128:$vB)), (f128 (XSRQPIX 0, $vB, 3))>; 3633 3634def : Pat<(f128 (int_ppc_scalar_insert_exp_qp f128:$vA, i64:$vB)), 3635 (f128 (XSIEXPQP $vA, (MTVSRD $vB)))>; 3636 3637def : Pat<(i64 (int_ppc_scalar_extract_expq f128:$vA)), 3638 (i64 (MFVSRD (EXTRACT_SUBREG 3639 (v2i64 (XSXEXPQP $vA)), sub_64)))>; 3640 3641// Extra patterns expanding to vector Extract Word/Insert Word 3642def : Pat<(v4i32 (int_ppc_vsx_xxinsertw v4i32:$A, v2i64:$B, imm:$IMM)), 3643 (v4i32 (XXINSERTW $A, $B, imm:$IMM))>; 3644def : Pat<(v2i64 (int_ppc_vsx_xxextractuw v2i64:$A, imm:$IMM)), 3645 (v2i64 (COPY_TO_REGCLASS (XXEXTRACTUW $A, imm:$IMM), VSRC))>; 3646 3647// Vector Reverse 3648def : Pat<(v8i16 (bswap v8i16 :$A)), 3649 (v8i16 (COPY_TO_REGCLASS (XXBRH (COPY_TO_REGCLASS $A, VSRC)), VRRC))>; 3650def : Pat<(v1i128 (bswap v1i128 :$A)), 3651 (v1i128 (COPY_TO_REGCLASS (XXBRQ (COPY_TO_REGCLASS $A, VSRC)), VRRC))>; 3652 3653// D-Form Load/Store 3654def : Pat<(v4i32 (quadwOffsetLoad iaddrX16:$src)), (LXV memrix16:$src)>; 3655def : Pat<(v4f32 (quadwOffsetLoad iaddrX16:$src)), (LXV memrix16:$src)>; 3656def : Pat<(v2i64 (quadwOffsetLoad iaddrX16:$src)), (LXV memrix16:$src)>; 3657def : Pat<(v2f64 (quadwOffsetLoad iaddrX16:$src)), (LXV memrix16:$src)>; 3658def : Pat<(f128 (quadwOffsetLoad iaddrX16:$src)), 3659 (COPY_TO_REGCLASS (LXV memrix16:$src), VRRC)>; 3660def : Pat<(v4i32 (int_ppc_vsx_lxvw4x iaddrX16:$src)), (LXV memrix16:$src)>; 3661def : Pat<(v2f64 (int_ppc_vsx_lxvd2x iaddrX16:$src)), (LXV memrix16:$src)>; 3662 3663def : Pat<(quadwOffsetStore v4f32:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>; 3664def : Pat<(quadwOffsetStore v4i32:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>; 3665def : Pat<(quadwOffsetStore v2f64:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>; 3666def : Pat<(quadwOffsetStore f128:$rS, iaddrX16:$dst), 3667 (STXV (COPY_TO_REGCLASS $rS, VSRC), memrix16:$dst)>; 3668def : Pat<(quadwOffsetStore v2i64:$rS, iaddrX16:$dst), (STXV $rS, memrix16:$dst)>; 3669def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, iaddrX16:$dst), 3670 (STXV $rS, memrix16:$dst)>; 3671def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, iaddrX16:$dst), 3672 (STXV $rS, memrix16:$dst)>; 3673 3674def : Pat<(v2f64 (nonQuadwOffsetLoad xoaddr:$src)), (LXVX xoaddr:$src)>; 3675def : Pat<(v2i64 (nonQuadwOffsetLoad xoaddr:$src)), (LXVX xoaddr:$src)>; 3676def : Pat<(v4f32 (nonQuadwOffsetLoad xoaddr:$src)), (LXVX xoaddr:$src)>; 3677def : Pat<(v4i32 (nonQuadwOffsetLoad xoaddr:$src)), (LXVX xoaddr:$src)>; 3678def : Pat<(v4i32 (int_ppc_vsx_lxvw4x xoaddr:$src)), (LXVX xoaddr:$src)>; 3679def : Pat<(v2f64 (int_ppc_vsx_lxvd2x xoaddr:$src)), (LXVX xoaddr:$src)>; 3680def : Pat<(f128 (nonQuadwOffsetLoad xoaddr:$src)), 3681 (COPY_TO_REGCLASS (LXVX xoaddr:$src), VRRC)>; 3682def : Pat<(nonQuadwOffsetStore f128:$rS, xoaddr:$dst), 3683 (STXVX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$dst)>; 3684def : Pat<(nonQuadwOffsetStore v2f64:$rS, xoaddr:$dst), 3685 (STXVX $rS, xoaddr:$dst)>; 3686def : Pat<(nonQuadwOffsetStore v2i64:$rS, xoaddr:$dst), 3687 (STXVX $rS, xoaddr:$dst)>; 3688def : Pat<(nonQuadwOffsetStore v4f32:$rS, xoaddr:$dst), 3689 (STXVX $rS, xoaddr:$dst)>; 3690def : Pat<(nonQuadwOffsetStore v4i32:$rS, xoaddr:$dst), 3691 (STXVX $rS, xoaddr:$dst)>; 3692def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xoaddr:$dst), 3693 (STXVX $rS, xoaddr:$dst)>; 3694def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst), 3695 (STXVX $rS, xoaddr:$dst)>; 3696 3697// Build vectors from i8 loads 3698defm : ScalToVecWPermute<v16i8, ScalarLoads.Li8, 3699 (VSPLTBs 7, (LXSIBZX xoaddr:$src)), 3700 (VSPLTBs 7, (LXSIBZX xoaddr:$src))>; 3701defm : ScalToVecWPermute<v8i16, ScalarLoads.ZELi8, 3702 (VSPLTHs 3, (LXSIBZX xoaddr:$src)), 3703 (VSPLTHs 3, (LXSIBZX xoaddr:$src))>; 3704defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi8, 3705 (XXSPLTWs (LXSIBZX xoaddr:$src), 1), 3706 (XXSPLTWs (LXSIBZX xoaddr:$src), 1)>; 3707defm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi8i64, 3708 (XXPERMDIs (LXSIBZX xoaddr:$src), 0), 3709 (XXPERMDIs (LXSIBZX xoaddr:$src), 0)>; 3710defm : ScalToVecWPermute<v4i32, ScalarLoads.SELi8, 3711 (XXSPLTWs (VEXTSB2Ws (LXSIBZX xoaddr:$src)), 1), 3712 (XXSPLTWs (VEXTSB2Ws (LXSIBZX xoaddr:$src)), 1)>; 3713defm : ScalToVecWPermute<v2i64, ScalarLoads.SELi8i64, 3714 (XXPERMDIs (VEXTSB2Ds (LXSIBZX xoaddr:$src)), 0), 3715 (XXPERMDIs (VEXTSB2Ds (LXSIBZX xoaddr:$src)), 0)>; 3716 3717// Build vectors from i16 loads 3718defm : ScalToVecWPermute<v8i16, ScalarLoads.Li16, 3719 (VSPLTHs 3, (LXSIHZX xoaddr:$src)), 3720 (VSPLTHs 3, (LXSIHZX xoaddr:$src))>; 3721defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi16, 3722 (XXSPLTWs (LXSIHZX xoaddr:$src), 1), 3723 (XXSPLTWs (LXSIHZX xoaddr:$src), 1)>; 3724defm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi16i64, 3725 (XXPERMDIs (LXSIHZX xoaddr:$src), 0), 3726 (XXPERMDIs (LXSIHZX xoaddr:$src), 0)>; 3727defm : ScalToVecWPermute<v4i32, ScalarLoads.SELi16, 3728 (XXSPLTWs (VEXTSH2Ws (LXSIHZX xoaddr:$src)), 1), 3729 (XXSPLTWs (VEXTSH2Ws (LXSIHZX xoaddr:$src)), 1)>; 3730defm : ScalToVecWPermute<v2i64, ScalarLoads.SELi16i64, 3731 (XXPERMDIs (VEXTSH2Ds (LXSIHZX xoaddr:$src)), 0), 3732 (XXPERMDIs (VEXTSH2Ds (LXSIHZX xoaddr:$src)), 0)>; 3733 3734// Load/convert and convert/store patterns for f16. 3735def : Pat<(f64 (extloadf16 xoaddr:$src)), 3736 (f64 (XSCVHPDP (LXSIHZX xoaddr:$src)))>; 3737def : Pat<(truncstoref16 f64:$src, xoaddr:$dst), 3738 (STXSIHX (XSCVDPHP $src), xoaddr:$dst)>; 3739def : Pat<(f32 (extloadf16 xoaddr:$src)), 3740 (f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX xoaddr:$src)), VSSRC))>; 3741def : Pat<(truncstoref16 f32:$src, xoaddr:$dst), 3742 (STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)), xoaddr:$dst)>; 3743def : Pat<(f64 (f16_to_fp i32:$A)), 3744 (f64 (XSCVHPDP (MTVSRWZ $A)))>; 3745def : Pat<(f32 (f16_to_fp i32:$A)), 3746 (f32 (COPY_TO_REGCLASS (XSCVHPDP (MTVSRWZ $A)), VSSRC))>; 3747def : Pat<(i32 (fp_to_f16 f32:$A)), 3748 (i32 (MFVSRWZ (XSCVDPHP (COPY_TO_REGCLASS $A, VSFRC))))>; 3749def : Pat<(i32 (fp_to_f16 f64:$A)), (i32 (MFVSRWZ (XSCVDPHP $A)))>; 3750 3751// Vector sign extensions 3752def : Pat<(f64 (PPCVexts f64:$A, 1)), 3753 (f64 (COPY_TO_REGCLASS (VEXTSB2Ds $A), VSFRC))>; 3754def : Pat<(f64 (PPCVexts f64:$A, 2)), 3755 (f64 (COPY_TO_REGCLASS (VEXTSH2Ds $A), VSFRC))>; 3756 3757def : Pat<(f64 (extloadf32 iaddrX4:$src)), 3758 (COPY_TO_REGCLASS (DFLOADf32 iaddrX4:$src), VSFRC)>; 3759def : Pat<(f32 (fpround (f64 (extloadf32 iaddrX4:$src)))), 3760 (f32 (DFLOADf32 iaddrX4:$src))>; 3761 3762def : Pat<(v4f32 (PPCldvsxlh xaddr:$src)), 3763 (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC)>; 3764def : Pat<(v4f32 (PPCldvsxlh iaddrX4:$src)), 3765 (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC)>; 3766 3767// Convert (Un)Signed DWord in memory -> QP 3768def : Pat<(f128 (sint_to_fp (i64 (load xaddrX4:$src)))), 3769 (f128 (XSCVSDQP (LXSDX xaddrX4:$src)))>; 3770def : Pat<(f128 (sint_to_fp (i64 (load iaddrX4:$src)))), 3771 (f128 (XSCVSDQP (LXSD iaddrX4:$src)))>; 3772def : Pat<(f128 (uint_to_fp (i64 (load xaddrX4:$src)))), 3773 (f128 (XSCVUDQP (LXSDX xaddrX4:$src)))>; 3774def : Pat<(f128 (uint_to_fp (i64 (load iaddrX4:$src)))), 3775 (f128 (XSCVUDQP (LXSD iaddrX4:$src)))>; 3776 3777// Convert Unsigned HWord in memory -> QP 3778def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi16)), 3779 (f128 (XSCVUDQP (LXSIHZX xaddr:$src)))>; 3780 3781// Convert Unsigned Byte in memory -> QP 3782def : Pat<(f128 (uint_to_fp ScalarLoads.ZELi8)), 3783 (f128 (XSCVUDQP (LXSIBZX xoaddr:$src)))>; 3784 3785// Truncate & Convert QP -> (Un)Signed (D)Word. 3786def : Pat<(i64 (any_fp_to_sint f128:$src)), (i64 (MFVRD (XSCVQPSDZ $src)))>; 3787def : Pat<(i64 (any_fp_to_uint f128:$src)), (i64 (MFVRD (XSCVQPUDZ $src)))>; 3788def : Pat<(i32 (any_fp_to_sint f128:$src)), 3789 (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC)))>; 3790def : Pat<(i32 (any_fp_to_uint f128:$src)), 3791 (i32 (MFVSRWZ (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC)))>; 3792 3793// Instructions for store(fptosi). 3794// The 8-byte version is repeated here due to availability of D-Form STXSD. 3795def : Pat<(PPCstore_scal_int_from_vsr 3796 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), xaddrX4:$dst, 8), 3797 (STXSDX (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), 3798 xaddrX4:$dst)>; 3799def : Pat<(PPCstore_scal_int_from_vsr 3800 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), iaddrX4:$dst, 8), 3801 (STXSD (COPY_TO_REGCLASS (XSCVQPSDZ f128:$src), VFRC), 3802 iaddrX4:$dst)>; 3803def : Pat<(PPCstore_scal_int_from_vsr 3804 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), xoaddr:$dst, 4), 3805 (STXSIWX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), xoaddr:$dst)>; 3806def : Pat<(PPCstore_scal_int_from_vsr 3807 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), xoaddr:$dst, 2), 3808 (STXSIHX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), xoaddr:$dst)>; 3809def : Pat<(PPCstore_scal_int_from_vsr 3810 (f64 (PPCcv_fp_to_sint_in_vsr f128:$src)), xoaddr:$dst, 1), 3811 (STXSIBX (COPY_TO_REGCLASS (XSCVQPSWZ $src), VFRC), xoaddr:$dst)>; 3812def : Pat<(PPCstore_scal_int_from_vsr 3813 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xaddrX4:$dst, 8), 3814 (STXSDX (XSCVDPSXDS f64:$src), xaddrX4:$dst)>; 3815def : Pat<(PPCstore_scal_int_from_vsr 3816 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), iaddrX4:$dst, 8), 3817 (STXSD (XSCVDPSXDS f64:$src), iaddrX4:$dst)>; 3818def : Pat<(PPCstore_scal_int_from_vsr 3819 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xoaddr:$dst, 2), 3820 (STXSIHX (XSCVDPSXWS f64:$src), xoaddr:$dst)>; 3821def : Pat<(PPCstore_scal_int_from_vsr 3822 (f64 (PPCcv_fp_to_sint_in_vsr f64:$src)), xoaddr:$dst, 1), 3823 (STXSIBX (XSCVDPSXWS f64:$src), xoaddr:$dst)>; 3824 3825// Instructions for store(fptoui). 3826def : Pat<(PPCstore_scal_int_from_vsr 3827 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xaddrX4:$dst, 8), 3828 (STXSDX (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), 3829 xaddrX4:$dst)>; 3830def : Pat<(PPCstore_scal_int_from_vsr 3831 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), iaddrX4:$dst, 8), 3832 (STXSD (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), 3833 iaddrX4:$dst)>; 3834def : Pat<(PPCstore_scal_int_from_vsr 3835 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xoaddr:$dst, 4), 3836 (STXSIWX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), xoaddr:$dst)>; 3837def : Pat<(PPCstore_scal_int_from_vsr 3838 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xoaddr:$dst, 2), 3839 (STXSIHX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), xoaddr:$dst)>; 3840def : Pat<(PPCstore_scal_int_from_vsr 3841 (f64 (PPCcv_fp_to_uint_in_vsr f128:$src)), xoaddr:$dst, 1), 3842 (STXSIBX (COPY_TO_REGCLASS (XSCVQPUWZ $src), VFRC), xoaddr:$dst)>; 3843def : Pat<(PPCstore_scal_int_from_vsr 3844 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xaddrX4:$dst, 8), 3845 (STXSDX (XSCVDPUXDS f64:$src), xaddrX4:$dst)>; 3846def : Pat<(PPCstore_scal_int_from_vsr 3847 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), iaddrX4:$dst, 8), 3848 (STXSD (XSCVDPUXDS f64:$src), iaddrX4:$dst)>; 3849def : Pat<(PPCstore_scal_int_from_vsr 3850 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 2), 3851 (STXSIHX (XSCVDPUXWS f64:$src), xoaddr:$dst)>; 3852def : Pat<(PPCstore_scal_int_from_vsr 3853 (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 1), 3854 (STXSIBX (XSCVDPUXWS f64:$src), xoaddr:$dst)>; 3855 3856// Round & Convert QP -> DP/SP 3857def : Pat<(f64 (any_fpround f128:$src)), (f64 (XSCVQPDP $src))>; 3858def : Pat<(f32 (any_fpround f128:$src)), (f32 (XSRSP (XSCVQPDPO $src)))>; 3859 3860// Convert SP -> QP 3861def : Pat<(f128 (any_fpextend f32:$src)), 3862 (f128 (XSCVDPQP (COPY_TO_REGCLASS $src, VFRC)))>; 3863 3864def : Pat<(f32 (PPCxsmaxc f32:$XA, f32:$XB)), 3865 (f32 (COPY_TO_REGCLASS (XSMAXCDP (COPY_TO_REGCLASS $XA, VSSRC), 3866 (COPY_TO_REGCLASS $XB, VSSRC)), 3867 VSSRC))>; 3868def : Pat<(f32 (PPCxsminc f32:$XA, f32:$XB)), 3869 (f32 (COPY_TO_REGCLASS (XSMINCDP (COPY_TO_REGCLASS $XA, VSSRC), 3870 (COPY_TO_REGCLASS $XB, VSSRC)), 3871 VSSRC))>; 3872 3873// Endianness-neutral patterns for const splats with ISA 3.0 instructions. 3874defm : ScalToVecWPermute<v4i32, (i32 i32:$A), (MTVSRWS $A), (MTVSRWS $A)>; 3875def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), 3876 (v4i32 (MTVSRWS $A))>; 3877def : Pat<(v16i8 (build_vector immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 3878 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 3879 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 3880 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 3881 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 3882 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 3883 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, 3884 immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A)), 3885 (v16i8 (COPY_TO_REGCLASS (XXSPLTIB imm:$A), VSRC))>; 3886defm : ScalToVecWPermute<v4i32, FltToIntLoad.A, 3887 (XVCVSPSXWS (LXVWSX xoaddr:$A)), 3888 (XVCVSPSXWS (LXVWSX xoaddr:$A))>; 3889defm : ScalToVecWPermute<v4i32, FltToUIntLoad.A, 3890 (XVCVSPUXWS (LXVWSX xoaddr:$A)), 3891 (XVCVSPUXWS (LXVWSX xoaddr:$A))>; 3892defm : ScalToVecWPermute< 3893 v4i32, DblToIntLoadP9.A, 3894 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPSXWS (DFLOADf64 iaddrX4:$A)), VSRC), 1), 3895 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 iaddrX4:$A)), sub_64)>; 3896defm : ScalToVecWPermute< 3897 v4i32, DblToUIntLoadP9.A, 3898 (XXSPLTW (COPY_TO_REGCLASS (XSCVDPUXWS (DFLOADf64 iaddrX4:$A)), VSRC), 1), 3899 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 iaddrX4:$A)), sub_64)>; 3900defm : ScalToVecWPermute< 3901 v2i64, FltToLongLoadP9.A, 3902 (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 iaddrX4:$A), VSFRC)), 0), 3903 (SUBREG_TO_REG 3904 (i64 1), 3905 (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 iaddrX4:$A), VSFRC)), sub_64)>; 3906defm : ScalToVecWPermute< 3907 v2i64, FltToULongLoadP9.A, 3908 (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 iaddrX4:$A), VSFRC)), 0), 3909 (SUBREG_TO_REG 3910 (i64 1), 3911 (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 iaddrX4:$A), VSFRC)), sub_64)>; 3912def : Pat<(v4f32 (PPCldsplat xoaddr:$A)), 3913 (v4f32 (LXVWSX xoaddr:$A))>; 3914def : Pat<(v4i32 (PPCldsplat xoaddr:$A)), 3915 (v4i32 (LXVWSX xoaddr:$A))>; 3916} // HasVSX, HasP9Vector 3917 3918// Big endian Power9 subtarget. 3919let Predicates = [HasVSX, HasP9Vector, IsBigEndian] in { 3920def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), 3921 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>; 3922def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))), 3923 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>; 3924def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))), 3925 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>; 3926def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))), 3927 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>; 3928def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), 3929 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>; 3930def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))), 3931 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>; 3932def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))), 3933 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>; 3934def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))), 3935 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>; 3936def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)), 3937 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>; 3938def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)), 3939 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>; 3940def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)), 3941 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>; 3942def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)), 3943 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>; 3944def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)), 3945 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>; 3946def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)), 3947 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>; 3948def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)), 3949 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>; 3950def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)), 3951 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>; 3952 3953// Scalar stores of i8 3954def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), xoaddr:$dst), 3955 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), xoaddr:$dst)>; 3956def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), xoaddr:$dst), 3957 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), xoaddr:$dst)>; 3958def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), xoaddr:$dst), 3959 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), xoaddr:$dst)>; 3960def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), xoaddr:$dst), 3961 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), xoaddr:$dst)>; 3962def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), xoaddr:$dst), 3963 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), xoaddr:$dst)>; 3964def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), xoaddr:$dst), 3965 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), xoaddr:$dst)>; 3966def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), xoaddr:$dst), 3967 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), xoaddr:$dst)>; 3968def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), xoaddr:$dst), 3969 (STXSIBXv (COPY_TO_REGCLASS $S, VSRC), xoaddr:$dst)>; 3970def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), xoaddr:$dst), 3971 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), xoaddr:$dst)>; 3972def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), xoaddr:$dst), 3973 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), xoaddr:$dst)>; 3974def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), xoaddr:$dst), 3975 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), xoaddr:$dst)>; 3976def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), xoaddr:$dst), 3977 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), xoaddr:$dst)>; 3978def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), xoaddr:$dst), 3979 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), xoaddr:$dst)>; 3980def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), xoaddr:$dst), 3981 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), xoaddr:$dst)>; 3982def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), xoaddr:$dst), 3983 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), xoaddr:$dst)>; 3984def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), xoaddr:$dst), 3985 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), xoaddr:$dst)>; 3986 3987// Scalar stores of i16 3988def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), xoaddr:$dst), 3989 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), xoaddr:$dst)>; 3990def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), xoaddr:$dst), 3991 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), xoaddr:$dst)>; 3992def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), xoaddr:$dst), 3993 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), xoaddr:$dst)>; 3994def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), xoaddr:$dst), 3995 (STXSIHXv (COPY_TO_REGCLASS $S, VSRC), xoaddr:$dst)>; 3996def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), xoaddr:$dst), 3997 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), xoaddr:$dst)>; 3998def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), xoaddr:$dst), 3999 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), xoaddr:$dst)>; 4000def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), xoaddr:$dst), 4001 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), xoaddr:$dst)>; 4002def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), xoaddr:$dst), 4003 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), xoaddr:$dst)>; 4004 4005def : Pat<(v2i64 (scalar_to_vector (i64 (load iaddrX4:$src)))), 4006 (v2i64 (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC))>; 4007def : Pat<(v2i64 (scalar_to_vector (i64 (load xaddrX4:$src)))), 4008 (v2i64 (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSRC))>; 4009 4010def : Pat<(v2f64 (scalar_to_vector (f64 (load iaddrX4:$src)))), 4011 (v2f64 (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSRC))>; 4012def : Pat<(v2f64 (scalar_to_vector (f64 (load xaddrX4:$src)))), 4013 (v2f64 (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSRC))>; 4014def : Pat<(store (i64 (extractelt v2i64:$A, 1)), xaddrX4:$src), 4015 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4016 sub_64), xaddrX4:$src)>; 4017def : Pat<(store (f64 (extractelt v2f64:$A, 1)), xaddrX4:$src), 4018 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4019 sub_64), xaddrX4:$src)>; 4020def : Pat<(store (i64 (extractelt v2i64:$A, 0)), xaddrX4:$src), 4021 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xaddrX4:$src)>; 4022def : Pat<(store (f64 (extractelt v2f64:$A, 0)), xaddrX4:$src), 4023 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xaddrX4:$src)>; 4024def : Pat<(store (i64 (extractelt v2i64:$A, 1)), iaddrX4:$src), 4025 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4026 sub_64), iaddrX4:$src)>; 4027def : Pat<(store (f64 (extractelt v2f64:$A, 1)), iaddrX4:$src), 4028 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4029 sub_64), iaddrX4:$src)>; 4030def : Pat<(store (i64 (extractelt v2i64:$A, 0)), iaddrX4:$src), 4031 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), iaddrX4:$src)>; 4032def : Pat<(store (f64 (extractelt v2f64:$A, 0)), iaddrX4:$src), 4033 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), iaddrX4:$src)>; 4034 4035// (Un)Signed DWord vector extract -> QP 4036def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))), 4037 (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; 4038def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))), 4039 (f128 (XSCVSDQP 4040 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; 4041def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))), 4042 (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; 4043def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))), 4044 (f128 (XSCVUDQP 4045 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; 4046 4047// (Un)Signed Word vector extract -> QP 4048def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 1)))), 4049 (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>; 4050foreach Idx = [0,2,3] in { 4051 def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, Idx)))), 4052 (f128 (XSCVSDQP (EXTRACT_SUBREG 4053 (VEXTSW2D (VSPLTW Idx, $src)), sub_64)))>; 4054} 4055foreach Idx = 0-3 in { 4056 def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, Idx)))), 4057 (f128 (XSCVUDQP (XXEXTRACTUW $src, !shl(Idx, 2))))>; 4058} 4059 4060// (Un)Signed HWord vector extract -> QP 4061foreach Idx = 0-7 in { 4062 def : Pat<(f128 (sint_to_fp 4063 (i32 (sext_inreg 4064 (vector_extract v8i16:$src, Idx), i16)))), 4065 (f128 (XSCVSDQP (EXTRACT_SUBREG 4066 (VEXTSH2D (VEXTRACTUH !add(Idx, Idx), $src)), 4067 sub_64)))>; 4068 // The SDAG adds the `and` since an `i16` is being extracted as an `i32`. 4069 def : Pat<(f128 (uint_to_fp 4070 (and (i32 (vector_extract v8i16:$src, Idx)), 65535))), 4071 (f128 (XSCVUDQP (EXTRACT_SUBREG 4072 (VEXTRACTUH !add(Idx, Idx), $src), sub_64)))>; 4073} 4074 4075// (Un)Signed Byte vector extract -> QP 4076foreach Idx = 0-15 in { 4077 def : Pat<(f128 (sint_to_fp 4078 (i32 (sext_inreg (vector_extract v16i8:$src, Idx), 4079 i8)))), 4080 (f128 (XSCVSDQP (EXTRACT_SUBREG 4081 (VEXTSB2D (VEXTRACTUB Idx, $src)), sub_64)))>; 4082 def : Pat<(f128 (uint_to_fp 4083 (and (i32 (vector_extract v16i8:$src, Idx)), 255))), 4084 (f128 (XSCVUDQP 4085 (EXTRACT_SUBREG (VEXTRACTUB Idx, $src), sub_64)))>; 4086} 4087 4088// Unsiged int in vsx register -> QP 4089def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))), 4090 (f128 (XSCVUDQP 4091 (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 4)))>; 4092} // HasVSX, HasP9Vector, IsBigEndian 4093 4094// Little endian Power9 subtarget. 4095let Predicates = [HasVSX, HasP9Vector, IsLittleEndian] in { 4096def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), 4097 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>; 4098def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))), 4099 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>; 4100def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))), 4101 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>; 4102def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))), 4103 (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>; 4104def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), 4105 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 12)))>; 4106def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))), 4107 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 8)))>; 4108def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))), 4109 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 4)))>; 4110def : Pat<(f64 (PPCfcfidu (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 3)))))), 4111 (f64 (XSCVUXDDP (XXEXTRACTUW $A, 0)))>; 4112def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)), 4113 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>; 4114def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)), 4115 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>; 4116def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)), 4117 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>; 4118def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)), 4119 (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>; 4120def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)), 4121 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>; 4122def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 1)), 4123 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 8))>; 4124def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 2)), 4125 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 4))>; 4126def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)), 4127 (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>; 4128 4129def : Pat<(v8i16 (PPCld_vec_be xoaddr:$src)), 4130 (COPY_TO_REGCLASS (LXVH8X xoaddr:$src), VRRC)>; 4131def : Pat<(PPCst_vec_be v8i16:$rS, xoaddr:$dst), 4132 (STXVH8X (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$dst)>; 4133 4134def : Pat<(v16i8 (PPCld_vec_be xoaddr:$src)), 4135 (COPY_TO_REGCLASS (LXVB16X xoaddr:$src), VRRC)>; 4136def : Pat<(PPCst_vec_be v16i8:$rS, xoaddr:$dst), 4137 (STXVB16X (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$dst)>; 4138 4139// Scalar stores of i8 4140def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), xoaddr:$dst), 4141 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), xoaddr:$dst)>; 4142def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 1)), xoaddr:$dst), 4143 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 7)), VSRC), xoaddr:$dst)>; 4144def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 2)), xoaddr:$dst), 4145 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), xoaddr:$dst)>; 4146def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 3)), xoaddr:$dst), 4147 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 5)), VSRC), xoaddr:$dst)>; 4148def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 4)), xoaddr:$dst), 4149 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), xoaddr:$dst)>; 4150def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 5)), xoaddr:$dst), 4151 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 3)), VSRC), xoaddr:$dst)>; 4152def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 6)), xoaddr:$dst), 4153 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), xoaddr:$dst)>; 4154def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 7)), xoaddr:$dst), 4155 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 1)), VSRC), xoaddr:$dst)>; 4156def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 8)), xoaddr:$dst), 4157 (STXSIBXv (COPY_TO_REGCLASS $S, VSRC), xoaddr:$dst)>; 4158def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 9)), xoaddr:$dst), 4159 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 15)), VSRC), xoaddr:$dst)>; 4160def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 10)), xoaddr:$dst), 4161 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), xoaddr:$dst)>; 4162def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 11)), xoaddr:$dst), 4163 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 13)), VSRC), xoaddr:$dst)>; 4164def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 12)), xoaddr:$dst), 4165 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), xoaddr:$dst)>; 4166def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 13)), xoaddr:$dst), 4167 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 11)), VSRC), xoaddr:$dst)>; 4168def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 14)), xoaddr:$dst), 4169 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), xoaddr:$dst)>; 4170def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 15)), xoaddr:$dst), 4171 (STXSIBXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 9)), VSRC), xoaddr:$dst)>; 4172 4173// Scalar stores of i16 4174def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 0)), xoaddr:$dst), 4175 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 8)), VSRC), xoaddr:$dst)>; 4176def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 1)), xoaddr:$dst), 4177 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 6)), VSRC), xoaddr:$dst)>; 4178def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 2)), xoaddr:$dst), 4179 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 4)), VSRC), xoaddr:$dst)>; 4180def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 3)), xoaddr:$dst), 4181 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 2)), VSRC), xoaddr:$dst)>; 4182def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 4)), xoaddr:$dst), 4183 (STXSIHXv (COPY_TO_REGCLASS $S, VSRC), xoaddr:$dst)>; 4184def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 5)), xoaddr:$dst), 4185 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 14)), VSRC), xoaddr:$dst)>; 4186def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 6)), xoaddr:$dst), 4187 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 12)), VSRC), xoaddr:$dst)>; 4188def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), xoaddr:$dst), 4189 (STXSIHXv (COPY_TO_REGCLASS (v16i8 (VSLDOI $S, $S, 10)), VSRC), xoaddr:$dst)>; 4190 4191defm : ScalToVecWPermute< 4192 v2i64, (i64 (load iaddrX4:$src)), 4193 (XXPERMDIs (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSFRC), 2), 4194 (SUBREG_TO_REG (i64 1), (DFLOADf64 iaddrX4:$src), sub_64)>; 4195defm : ScalToVecWPermute< 4196 v2i64, (i64 (load xaddrX4:$src)), 4197 (XXPERMDIs (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSFRC), 2), 4198 (SUBREG_TO_REG (i64 1), (XFLOADf64 xaddrX4:$src), sub_64)>; 4199defm : ScalToVecWPermute< 4200 v2f64, (f64 (load iaddrX4:$src)), 4201 (XXPERMDIs (COPY_TO_REGCLASS (DFLOADf64 iaddrX4:$src), VSFRC), 2), 4202 (SUBREG_TO_REG (i64 1), (DFLOADf64 iaddrX4:$src), sub_64)>; 4203defm : ScalToVecWPermute< 4204 v2f64, (f64 (load xaddrX4:$src)), 4205 (XXPERMDIs (COPY_TO_REGCLASS (XFLOADf64 xaddrX4:$src), VSFRC), 2), 4206 (SUBREG_TO_REG (i64 1), (XFLOADf64 xaddrX4:$src), sub_64)>; 4207 4208def : Pat<(store (i64 (extractelt v2i64:$A, 0)), xaddrX4:$src), 4209 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4210 sub_64), xaddrX4:$src)>; 4211def : Pat<(store (f64 (extractelt v2f64:$A, 0)), xaddrX4:$src), 4212 (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4213 sub_64), xaddrX4:$src)>; 4214def : Pat<(store (i64 (extractelt v2i64:$A, 1)), xaddrX4:$src), 4215 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xaddrX4:$src)>; 4216def : Pat<(store (f64 (extractelt v2f64:$A, 1)), xaddrX4:$src), 4217 (XFSTOREf64 (EXTRACT_SUBREG $A, sub_64), xaddrX4:$src)>; 4218def : Pat<(store (i64 (extractelt v2i64:$A, 0)), iaddrX4:$src), 4219 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), 4220 sub_64), iaddrX4:$src)>; 4221def : Pat<(store (f64 (extractelt v2f64:$A, 0)), iaddrX4:$src), 4222 (DFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), 4223 iaddrX4:$src)>; 4224def : Pat<(store (i64 (extractelt v2i64:$A, 1)), iaddrX4:$src), 4225 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), iaddrX4:$src)>; 4226def : Pat<(store (f64 (extractelt v2f64:$A, 1)), iaddrX4:$src), 4227 (DFSTOREf64 (EXTRACT_SUBREG $A, sub_64), iaddrX4:$src)>; 4228 4229// (Un)Signed DWord vector extract -> QP 4230def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))), 4231 (f128 (XSCVSDQP 4232 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; 4233def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))), 4234 (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; 4235def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))), 4236 (f128 (XSCVUDQP 4237 (EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>; 4238def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))), 4239 (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; 4240 4241// (Un)Signed Word vector extract -> QP 4242foreach Idx = [[0,3],[1,2],[3,0]] in { 4243 def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))), 4244 (f128 (XSCVSDQP (EXTRACT_SUBREG 4245 (VEXTSW2D (VSPLTW !head(!tail(Idx)), $src)), 4246 sub_64)))>; 4247} 4248def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 2)))), 4249 (f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>; 4250 4251foreach Idx = [[0,12],[1,8],[2,4],[3,0]] in { 4252 def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))), 4253 (f128 (XSCVUDQP (XXEXTRACTUW $src, !head(!tail(Idx)))))>; 4254} 4255 4256// (Un)Signed HWord vector extract -> QP 4257// The Nested foreach lists identifies the vector element and corresponding 4258// register byte location. 4259foreach Idx = [[0,14],[1,12],[2,10],[3,8],[4,6],[5,4],[6,2],[7,0]] in { 4260 def : Pat<(f128 (sint_to_fp 4261 (i32 (sext_inreg 4262 (vector_extract v8i16:$src, !head(Idx)), i16)))), 4263 (f128 (XSCVSDQP 4264 (EXTRACT_SUBREG (VEXTSH2D 4265 (VEXTRACTUH !head(!tail(Idx)), $src)), 4266 sub_64)))>; 4267 def : Pat<(f128 (uint_to_fp 4268 (and (i32 (vector_extract v8i16:$src, !head(Idx))), 4269 65535))), 4270 (f128 (XSCVUDQP (EXTRACT_SUBREG 4271 (VEXTRACTUH !head(!tail(Idx)), $src), sub_64)))>; 4272} 4273 4274// (Un)Signed Byte vector extract -> QP 4275foreach Idx = [[0,15],[1,14],[2,13],[3,12],[4,11],[5,10],[6,9],[7,8],[8,7], 4276 [9,6],[10,5],[11,4],[12,3],[13,2],[14,1],[15,0]] in { 4277 def : Pat<(f128 (sint_to_fp 4278 (i32 (sext_inreg 4279 (vector_extract v16i8:$src, !head(Idx)), i8)))), 4280 (f128 (XSCVSDQP 4281 (EXTRACT_SUBREG 4282 (VEXTSB2D (VEXTRACTUB !head(!tail(Idx)), $src)), 4283 sub_64)))>; 4284 def : Pat<(f128 (uint_to_fp 4285 (and (i32 (vector_extract v16i8:$src, !head(Idx))), 4286 255))), 4287 (f128 (XSCVUDQP 4288 (EXTRACT_SUBREG 4289 (VEXTRACTUB !head(!tail(Idx)), $src), sub_64)))>; 4290} 4291 4292// Unsiged int in vsx register -> QP 4293def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))), 4294 (f128 (XSCVUDQP 4295 (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 8)))>; 4296} // HasVSX, HasP9Vector, IsLittleEndian 4297 4298// Any Power9 VSX subtarget that supports Power9 Altivec. 4299let Predicates = [HasVSX, HasP9Altivec] in { 4300// Put this P9Altivec related definition here since it's possible to be 4301// selected to VSX instruction xvnegsp, avoid possible undef. 4302def : Pat<(v4i32 (PPCvabsd v4i32:$A, v4i32:$B, (i32 0))), 4303 (v4i32 (VABSDUW $A, $B))>; 4304 4305def : Pat<(v8i16 (PPCvabsd v8i16:$A, v8i16:$B, (i32 0))), 4306 (v8i16 (VABSDUH $A, $B))>; 4307 4308def : Pat<(v16i8 (PPCvabsd v16i8:$A, v16i8:$B, (i32 0))), 4309 (v16i8 (VABSDUB $A, $B))>; 4310 4311// As PPCVABSD description, the last operand indicates whether do the 4312// sign bit flip. 4313def : Pat<(v4i32 (PPCvabsd v4i32:$A, v4i32:$B, (i32 1))), 4314 (v4i32 (VABSDUW (XVNEGSP $A), (XVNEGSP $B)))>; 4315} // HasVSX, HasP9Altivec 4316 4317// Big endian Power9 VSX subtargets with P9 Altivec support. 4318let Predicates = [HasVSX, HasP9Altivec, IsBigEndian] in { 4319def : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))), 4320 (VEXTUBLX $Idx, $S)>; 4321 4322def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, i64:$Idx)))), 4323 (VEXTUHLX (RLWINM8 $Idx, 1, 28, 30), $S)>; 4324def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))), 4325 (VEXTUHLX (LI8 0), $S)>; 4326def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))), 4327 (VEXTUHLX (LI8 2), $S)>; 4328def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 2)))), 4329 (VEXTUHLX (LI8 4), $S)>; 4330def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 3)))), 4331 (VEXTUHLX (LI8 6), $S)>; 4332def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 4)))), 4333 (VEXTUHLX (LI8 8), $S)>; 4334def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 5)))), 4335 (VEXTUHLX (LI8 10), $S)>; 4336def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 6)))), 4337 (VEXTUHLX (LI8 12), $S)>; 4338def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 7)))), 4339 (VEXTUHLX (LI8 14), $S)>; 4340 4341def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, i64:$Idx)))), 4342 (VEXTUWLX (RLWINM8 $Idx, 2, 28, 29), $S)>; 4343def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 0)))), 4344 (VEXTUWLX (LI8 0), $S)>; 4345 4346// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX 4347def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 1)))), 4348 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 4349 (i32 VectorExtractions.LE_WORD_2), sub_32)>; 4350def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 2)))), 4351 (VEXTUWLX (LI8 8), $S)>; 4352def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 3)))), 4353 (VEXTUWLX (LI8 12), $S)>; 4354 4355def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, i64:$Idx)))), 4356 (EXTSW (VEXTUWLX (RLWINM8 $Idx, 2, 28, 29), $S))>; 4357def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 0)))), 4358 (EXTSW (VEXTUWLX (LI8 0), $S))>; 4359// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX 4360def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 1)))), 4361 (EXTSW (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 4362 (i32 VectorExtractions.LE_WORD_2), sub_32))>; 4363def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 2)))), 4364 (EXTSW (VEXTUWLX (LI8 8), $S))>; 4365def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 3)))), 4366 (EXTSW (VEXTUWLX (LI8 12), $S))>; 4367 4368def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 4369 (i32 (EXTRACT_SUBREG (VEXTUBLX $Idx, $S), sub_32))>; 4370def : Pat<(i32 (vector_extract v16i8:$S, 0)), 4371 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 0), $S), sub_32))>; 4372def : Pat<(i32 (vector_extract v16i8:$S, 1)), 4373 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 1), $S), sub_32))>; 4374def : Pat<(i32 (vector_extract v16i8:$S, 2)), 4375 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 2), $S), sub_32))>; 4376def : Pat<(i32 (vector_extract v16i8:$S, 3)), 4377 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 3), $S), sub_32))>; 4378def : Pat<(i32 (vector_extract v16i8:$S, 4)), 4379 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 4), $S), sub_32))>; 4380def : Pat<(i32 (vector_extract v16i8:$S, 5)), 4381 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 5), $S), sub_32))>; 4382def : Pat<(i32 (vector_extract v16i8:$S, 6)), 4383 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 6), $S), sub_32))>; 4384def : Pat<(i32 (vector_extract v16i8:$S, 7)), 4385 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 7), $S), sub_32))>; 4386def : Pat<(i32 (vector_extract v16i8:$S, 8)), 4387 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 8), $S), sub_32))>; 4388def : Pat<(i32 (vector_extract v16i8:$S, 9)), 4389 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 9), $S), sub_32))>; 4390def : Pat<(i32 (vector_extract v16i8:$S, 10)), 4391 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 10), $S), sub_32))>; 4392def : Pat<(i32 (vector_extract v16i8:$S, 11)), 4393 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 11), $S), sub_32))>; 4394def : Pat<(i32 (vector_extract v16i8:$S, 12)), 4395 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 12), $S), sub_32))>; 4396def : Pat<(i32 (vector_extract v16i8:$S, 13)), 4397 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 13), $S), sub_32))>; 4398def : Pat<(i32 (vector_extract v16i8:$S, 14)), 4399 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 14), $S), sub_32))>; 4400def : Pat<(i32 (vector_extract v16i8:$S, 15)), 4401 (i32 (EXTRACT_SUBREG (VEXTUBLX (LI8 15), $S), sub_32))>; 4402 4403def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 4404 (i32 (EXTRACT_SUBREG (VEXTUHLX 4405 (RLWINM8 $Idx, 1, 28, 30), $S), sub_32))>; 4406def : Pat<(i32 (vector_extract v8i16:$S, 0)), 4407 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 0), $S), sub_32))>; 4408def : Pat<(i32 (vector_extract v8i16:$S, 1)), 4409 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 2), $S), sub_32))>; 4410def : Pat<(i32 (vector_extract v8i16:$S, 2)), 4411 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 4), $S), sub_32))>; 4412def : Pat<(i32 (vector_extract v8i16:$S, 3)), 4413 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 6), $S), sub_32))>; 4414def : Pat<(i32 (vector_extract v8i16:$S, 4)), 4415 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 8), $S), sub_32))>; 4416def : Pat<(i32 (vector_extract v8i16:$S, 5)), 4417 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 10), $S), sub_32))>; 4418def : Pat<(i32 (vector_extract v8i16:$S, 6)), 4419 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 12), $S), sub_32))>; 4420def : Pat<(i32 (vector_extract v8i16:$S, 6)), 4421 (i32 (EXTRACT_SUBREG (VEXTUHLX (LI8 14), $S), sub_32))>; 4422 4423def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 4424 (i32 (EXTRACT_SUBREG (VEXTUWLX 4425 (RLWINM8 $Idx, 2, 28, 29), $S), sub_32))>; 4426def : Pat<(i32 (vector_extract v4i32:$S, 0)), 4427 (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 0), $S), sub_32))>; 4428// For extracting BE word 1, MFVSRWZ is better than VEXTUWLX 4429def : Pat<(i32 (vector_extract v4i32:$S, 1)), 4430 (i32 VectorExtractions.LE_WORD_2)>; 4431def : Pat<(i32 (vector_extract v4i32:$S, 2)), 4432 (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 8), $S), sub_32))>; 4433def : Pat<(i32 (vector_extract v4i32:$S, 3)), 4434 (i32 (EXTRACT_SUBREG (VEXTUWLX (LI8 12), $S), sub_32))>; 4435 4436// P9 Altivec instructions that can be used to build vectors. 4437// Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete 4438// with complexities of existing build vector patterns in this file. 4439def : Pat<(v2i64 (build_vector WordToDWord.BE_A0, WordToDWord.BE_A1)), 4440 (v2i64 (VEXTSW2D $A))>; 4441def : Pat<(v2i64 (build_vector HWordToDWord.BE_A0, HWordToDWord.BE_A1)), 4442 (v2i64 (VEXTSH2D $A))>; 4443def : Pat<(v4i32 (build_vector HWordToWord.BE_A0, HWordToWord.BE_A1, 4444 HWordToWord.BE_A2, HWordToWord.BE_A3)), 4445 (v4i32 (VEXTSH2W $A))>; 4446def : Pat<(v4i32 (build_vector ByteToWord.BE_A0, ByteToWord.BE_A1, 4447 ByteToWord.BE_A2, ByteToWord.BE_A3)), 4448 (v4i32 (VEXTSB2W $A))>; 4449def : Pat<(v2i64 (build_vector ByteToDWord.BE_A0, ByteToDWord.BE_A1)), 4450 (v2i64 (VEXTSB2D $A))>; 4451} // HasVSX, HasP9Altivec, IsBigEndian 4452 4453// Little endian Power9 VSX subtargets with P9 Altivec support. 4454let Predicates = [HasVSX, HasP9Altivec, IsLittleEndian] in { 4455def : Pat<(i64 (anyext (i32 (vector_extract v16i8:$S, i64:$Idx)))), 4456 (VEXTUBRX $Idx, $S)>; 4457 4458def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, i64:$Idx)))), 4459 (VEXTUHRX (RLWINM8 $Idx, 1, 28, 30), $S)>; 4460def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 0)))), 4461 (VEXTUHRX (LI8 0), $S)>; 4462def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 1)))), 4463 (VEXTUHRX (LI8 2), $S)>; 4464def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 2)))), 4465 (VEXTUHRX (LI8 4), $S)>; 4466def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 3)))), 4467 (VEXTUHRX (LI8 6), $S)>; 4468def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 4)))), 4469 (VEXTUHRX (LI8 8), $S)>; 4470def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 5)))), 4471 (VEXTUHRX (LI8 10), $S)>; 4472def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 6)))), 4473 (VEXTUHRX (LI8 12), $S)>; 4474def : Pat<(i64 (anyext (i32 (vector_extract v8i16:$S, 7)))), 4475 (VEXTUHRX (LI8 14), $S)>; 4476 4477def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, i64:$Idx)))), 4478 (VEXTUWRX (RLWINM8 $Idx, 2, 28, 29), $S)>; 4479def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 0)))), 4480 (VEXTUWRX (LI8 0), $S)>; 4481def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 1)))), 4482 (VEXTUWRX (LI8 4), $S)>; 4483// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX 4484def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 2)))), 4485 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 4486 (i32 VectorExtractions.LE_WORD_2), sub_32)>; 4487def : Pat<(i64 (zext (i32 (vector_extract v4i32:$S, 3)))), 4488 (VEXTUWRX (LI8 12), $S)>; 4489 4490def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, i64:$Idx)))), 4491 (EXTSW (VEXTUWRX (RLWINM8 $Idx, 2, 28, 29), $S))>; 4492def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 0)))), 4493 (EXTSW (VEXTUWRX (LI8 0), $S))>; 4494def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 1)))), 4495 (EXTSW (VEXTUWRX (LI8 4), $S))>; 4496// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX 4497def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 2)))), 4498 (EXTSW (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 4499 (i32 VectorExtractions.LE_WORD_2), sub_32))>; 4500def : Pat<(i64 (sext (i32 (vector_extract v4i32:$S, 3)))), 4501 (EXTSW (VEXTUWRX (LI8 12), $S))>; 4502 4503def : Pat<(i32 (vector_extract v16i8:$S, i64:$Idx)), 4504 (i32 (EXTRACT_SUBREG (VEXTUBRX $Idx, $S), sub_32))>; 4505def : Pat<(i32 (vector_extract v16i8:$S, 0)), 4506 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 0), $S), sub_32))>; 4507def : Pat<(i32 (vector_extract v16i8:$S, 1)), 4508 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 1), $S), sub_32))>; 4509def : Pat<(i32 (vector_extract v16i8:$S, 2)), 4510 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 2), $S), sub_32))>; 4511def : Pat<(i32 (vector_extract v16i8:$S, 3)), 4512 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 3), $S), sub_32))>; 4513def : Pat<(i32 (vector_extract v16i8:$S, 4)), 4514 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 4), $S), sub_32))>; 4515def : Pat<(i32 (vector_extract v16i8:$S, 5)), 4516 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 5), $S), sub_32))>; 4517def : Pat<(i32 (vector_extract v16i8:$S, 6)), 4518 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 6), $S), sub_32))>; 4519def : Pat<(i32 (vector_extract v16i8:$S, 7)), 4520 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 7), $S), sub_32))>; 4521def : Pat<(i32 (vector_extract v16i8:$S, 8)), 4522 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 8), $S), sub_32))>; 4523def : Pat<(i32 (vector_extract v16i8:$S, 9)), 4524 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 9), $S), sub_32))>; 4525def : Pat<(i32 (vector_extract v16i8:$S, 10)), 4526 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 10), $S), sub_32))>; 4527def : Pat<(i32 (vector_extract v16i8:$S, 11)), 4528 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 11), $S), sub_32))>; 4529def : Pat<(i32 (vector_extract v16i8:$S, 12)), 4530 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 12), $S), sub_32))>; 4531def : Pat<(i32 (vector_extract v16i8:$S, 13)), 4532 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 13), $S), sub_32))>; 4533def : Pat<(i32 (vector_extract v16i8:$S, 14)), 4534 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 14), $S), sub_32))>; 4535def : Pat<(i32 (vector_extract v16i8:$S, 15)), 4536 (i32 (EXTRACT_SUBREG (VEXTUBRX (LI8 15), $S), sub_32))>; 4537 4538def : Pat<(i32 (vector_extract v8i16:$S, i64:$Idx)), 4539 (i32 (EXTRACT_SUBREG (VEXTUHRX 4540 (RLWINM8 $Idx, 1, 28, 30), $S), sub_32))>; 4541def : Pat<(i32 (vector_extract v8i16:$S, 0)), 4542 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 0), $S), sub_32))>; 4543def : Pat<(i32 (vector_extract v8i16:$S, 1)), 4544 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 2), $S), sub_32))>; 4545def : Pat<(i32 (vector_extract v8i16:$S, 2)), 4546 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 4), $S), sub_32))>; 4547def : Pat<(i32 (vector_extract v8i16:$S, 3)), 4548 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 6), $S), sub_32))>; 4549def : Pat<(i32 (vector_extract v8i16:$S, 4)), 4550 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 8), $S), sub_32))>; 4551def : Pat<(i32 (vector_extract v8i16:$S, 5)), 4552 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 10), $S), sub_32))>; 4553def : Pat<(i32 (vector_extract v8i16:$S, 6)), 4554 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 12), $S), sub_32))>; 4555def : Pat<(i32 (vector_extract v8i16:$S, 6)), 4556 (i32 (EXTRACT_SUBREG (VEXTUHRX (LI8 14), $S), sub_32))>; 4557 4558def : Pat<(i32 (vector_extract v4i32:$S, i64:$Idx)), 4559 (i32 (EXTRACT_SUBREG (VEXTUWRX 4560 (RLWINM8 $Idx, 2, 28, 29), $S), sub_32))>; 4561def : Pat<(i32 (vector_extract v4i32:$S, 0)), 4562 (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 0), $S), sub_32))>; 4563def : Pat<(i32 (vector_extract v4i32:$S, 1)), 4564 (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 4), $S), sub_32))>; 4565// For extracting LE word 2, MFVSRWZ is better than VEXTUWRX 4566def : Pat<(i32 (vector_extract v4i32:$S, 2)), 4567 (i32 VectorExtractions.LE_WORD_2)>; 4568def : Pat<(i32 (vector_extract v4i32:$S, 3)), 4569 (i32 (EXTRACT_SUBREG (VEXTUWRX (LI8 12), $S), sub_32))>; 4570 4571// P9 Altivec instructions that can be used to build vectors. 4572// Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete 4573// with complexities of existing build vector patterns in this file. 4574def : Pat<(v2i64 (build_vector WordToDWord.LE_A0, WordToDWord.LE_A1)), 4575 (v2i64 (VEXTSW2D $A))>; 4576def : Pat<(v2i64 (build_vector HWordToDWord.LE_A0, HWordToDWord.LE_A1)), 4577 (v2i64 (VEXTSH2D $A))>; 4578def : Pat<(v4i32 (build_vector HWordToWord.LE_A0, HWordToWord.LE_A1, 4579 HWordToWord.LE_A2, HWordToWord.LE_A3)), 4580 (v4i32 (VEXTSH2W $A))>; 4581def : Pat<(v4i32 (build_vector ByteToWord.LE_A0, ByteToWord.LE_A1, 4582 ByteToWord.LE_A2, ByteToWord.LE_A3)), 4583 (v4i32 (VEXTSB2W $A))>; 4584def : Pat<(v2i64 (build_vector ByteToDWord.LE_A0, ByteToDWord.LE_A1)), 4585 (v2i64 (VEXTSB2D $A))>; 4586} // HasVSX, HasP9Altivec, IsLittleEndian 4587 4588// Big endian VSX subtarget that supports additional direct moves from ISA3.0. 4589let Predicates = [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian] in { 4590def : Pat<(i64 (extractelt v2i64:$A, 1)), 4591 (i64 (MFVSRLD $A))>; 4592// Better way to build integer vectors if we have MTVSRDD. Big endian. 4593def : Pat<(v2i64 (build_vector i64:$rB, i64:$rA)), 4594 (v2i64 (MTVSRDD $rB, $rA))>; 4595def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), 4596 (MTVSRDD 4597 (RLDIMI AnyExts.B, AnyExts.A, 32, 0), 4598 (RLDIMI AnyExts.D, AnyExts.C, 32, 0))>; 4599 4600def : Pat<(f128 (PPCbuild_fp128 i64:$rB, i64:$rA)), 4601 (f128 (COPY_TO_REGCLASS (MTVSRDD $rB, $rA), VRRC))>; 4602} // HasVSX, IsISA3_0, HasDirectMove, IsBigEndian 4603 4604// Little endian VSX subtarget that supports direct moves from ISA3.0. 4605let Predicates = [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian] in { 4606def : Pat<(i64 (extractelt v2i64:$A, 0)), 4607 (i64 (MFVSRLD $A))>; 4608// Better way to build integer vectors if we have MTVSRDD. Little endian. 4609def : Pat<(v2i64 (build_vector i64:$rA, i64:$rB)), 4610 (v2i64 (MTVSRDD $rB, $rA))>; 4611def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), 4612 (MTVSRDD 4613 (RLDIMI AnyExts.C, AnyExts.D, 32, 0), 4614 (RLDIMI AnyExts.A, AnyExts.B, 32, 0))>; 4615 4616def : Pat<(f128 (PPCbuild_fp128 i64:$rA, i64:$rB)), 4617 (f128 (COPY_TO_REGCLASS (MTVSRDD $rB, $rA), VRRC))>; 4618} // HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian 4619} // AddedComplexity = 400 4620 4621//---------------------------- Instruction aliases ---------------------------// 4622def : InstAlias<"xvmovdp $XT, $XB", 4623 (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>; 4624def : InstAlias<"xvmovsp $XT, $XB", 4625 (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB)>; 4626 4627def : InstAlias<"xxspltd $XT, $XB, 0", 4628 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0)>; 4629def : InstAlias<"xxspltd $XT, $XB, 1", 4630 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3)>; 4631def : InstAlias<"xxmrghd $XT, $XA, $XB", 4632 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>; 4633def : InstAlias<"xxmrgld $XT, $XA, $XB", 4634 (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>; 4635def : InstAlias<"xxswapd $XT, $XB", 4636 (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>; 4637def : InstAlias<"xxspltd $XT, $XB, 0", 4638 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0)>; 4639def : InstAlias<"xxspltd $XT, $XB, 1", 4640 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3)>; 4641def : InstAlias<"xxswapd $XT, $XB", 4642 (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2)>; 4643def : InstAlias<"mfvrd $rA, $XT", 4644 (MFVRD g8rc:$rA, vrrc:$XT), 0>; 4645def : InstAlias<"mffprd $rA, $src", 4646 (MFVSRD g8rc:$rA, f8rc:$src)>; 4647def : InstAlias<"mtvrd $XT, $rA", 4648 (MTVRD vrrc:$XT, g8rc:$rA), 0>; 4649def : InstAlias<"mtfprd $dst, $rA", 4650 (MTVSRD f8rc:$dst, g8rc:$rA)>; 4651def : InstAlias<"mfvrwz $rA, $XT", 4652 (MFVRWZ gprc:$rA, vrrc:$XT), 0>; 4653def : InstAlias<"mffprwz $rA, $src", 4654 (MFVSRWZ gprc:$rA, f8rc:$src)>; 4655def : InstAlias<"mtvrwa $XT, $rA", 4656 (MTVRWA vrrc:$XT, gprc:$rA), 0>; 4657def : InstAlias<"mtfprwa $dst, $rA", 4658 (MTVSRWA f8rc:$dst, gprc:$rA)>; 4659def : InstAlias<"mtvrwz $XT, $rA", 4660 (MTVRWZ vrrc:$XT, gprc:$rA), 0>; 4661def : InstAlias<"mtfprwz $dst, $rA", 4662 (MTVSRWZ f8rc:$dst, gprc:$rA)>; 4663