1 //===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "RISCVFrameLowering.h"
14 #include "RISCVMachineFunctionInfo.h"
15 #include "RISCVSubtarget.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/RegisterScavenging.h"
21 #include "llvm/IR/DiagnosticInfo.h"
22 #include "llvm/MC/MCDwarf.h"
23
24 using namespace llvm;
25
26 // For now we use x18, a.k.a s2, as pointer to shadow call stack.
27 // User should explicitly set -ffixed-x18 and not use x18 in their asm.
emitSCSPrologue(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const DebugLoc & DL)28 static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
29 MachineBasicBlock::iterator MI,
30 const DebugLoc &DL) {
31 if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
32 return;
33
34 const auto &STI = MF.getSubtarget<RISCVSubtarget>();
35 Register RAReg = STI.getRegisterInfo()->getRARegister();
36
37 // Do not save RA to the SCS if it's not saved to the regular stack,
38 // i.e. RA is not at risk of being overwritten.
39 std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
40 if (std::none_of(CSI.begin(), CSI.end(),
41 [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
42 return;
43
44 Register SCSPReg = RISCVABI::getSCSPReg();
45
46 auto &Ctx = MF.getFunction().getContext();
47 if (!STI.isRegisterReservedByUser(SCSPReg)) {
48 Ctx.diagnose(DiagnosticInfoUnsupported{
49 MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."});
50 return;
51 }
52
53 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
54 if (RVFI->useSaveRestoreLibCalls(MF)) {
55 Ctx.diagnose(DiagnosticInfoUnsupported{
56 MF.getFunction(),
57 "Shadow Call Stack cannot be combined with Save/Restore LibCalls."});
58 return;
59 }
60
61 const RISCVInstrInfo *TII = STI.getInstrInfo();
62 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
63 int64_t SlotSize = STI.getXLen() / 8;
64 // Store return address to shadow call stack
65 // s[w|d] ra, 0(s2)
66 // addi s2, s2, [4|8]
67 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
68 .addReg(RAReg)
69 .addReg(SCSPReg)
70 .addImm(0);
71 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
72 .addReg(SCSPReg, RegState::Define)
73 .addReg(SCSPReg)
74 .addImm(SlotSize);
75 }
76
emitSCSEpilogue(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const DebugLoc & DL)77 static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator MI,
79 const DebugLoc &DL) {
80 if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
81 return;
82
83 const auto &STI = MF.getSubtarget<RISCVSubtarget>();
84 Register RAReg = STI.getRegisterInfo()->getRARegister();
85
86 // See emitSCSPrologue() above.
87 std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
88 if (std::none_of(CSI.begin(), CSI.end(),
89 [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
90 return;
91
92 Register SCSPReg = RISCVABI::getSCSPReg();
93
94 auto &Ctx = MF.getFunction().getContext();
95 if (!STI.isRegisterReservedByUser(SCSPReg)) {
96 Ctx.diagnose(DiagnosticInfoUnsupported{
97 MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."});
98 return;
99 }
100
101 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
102 if (RVFI->useSaveRestoreLibCalls(MF)) {
103 Ctx.diagnose(DiagnosticInfoUnsupported{
104 MF.getFunction(),
105 "Shadow Call Stack cannot be combined with Save/Restore LibCalls."});
106 return;
107 }
108
109 const RISCVInstrInfo *TII = STI.getInstrInfo();
110 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
111 int64_t SlotSize = STI.getXLen() / 8;
112 // Load return address from shadow call stack
113 // l[w|d] ra, -[4|8](s2)
114 // addi s2, s2, -[4|8]
115 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW))
116 .addReg(RAReg, RegState::Define)
117 .addReg(SCSPReg)
118 .addImm(-SlotSize);
119 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
120 .addReg(SCSPReg, RegState::Define)
121 .addReg(SCSPReg)
122 .addImm(-SlotSize);
123 }
124
125 // Get the ID of the libcall used for spilling and restoring callee saved
126 // registers. The ID is representative of the number of registers saved or
127 // restored by the libcall, except it is zero-indexed - ID 0 corresponds to a
128 // single register.
getLibCallID(const MachineFunction & MF,const std::vector<CalleeSavedInfo> & CSI)129 static int getLibCallID(const MachineFunction &MF,
130 const std::vector<CalleeSavedInfo> &CSI) {
131 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
132
133 if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF))
134 return -1;
135
136 Register MaxReg = RISCV::NoRegister;
137 for (auto &CS : CSI)
138 // RISCVRegisterInfo::hasReservedSpillSlot assigns negative frame indexes to
139 // registers which can be saved by libcall.
140 if (CS.getFrameIdx() < 0)
141 MaxReg = std::max(MaxReg.id(), CS.getReg());
142
143 if (MaxReg == RISCV::NoRegister)
144 return -1;
145
146 switch (MaxReg) {
147 default:
148 llvm_unreachable("Something has gone wrong!");
149 case /*s11*/ RISCV::X27: return 12;
150 case /*s10*/ RISCV::X26: return 11;
151 case /*s9*/ RISCV::X25: return 10;
152 case /*s8*/ RISCV::X24: return 9;
153 case /*s7*/ RISCV::X23: return 8;
154 case /*s6*/ RISCV::X22: return 7;
155 case /*s5*/ RISCV::X21: return 6;
156 case /*s4*/ RISCV::X20: return 5;
157 case /*s3*/ RISCV::X19: return 4;
158 case /*s2*/ RISCV::X18: return 3;
159 case /*s1*/ RISCV::X9: return 2;
160 case /*s0*/ RISCV::X8: return 1;
161 case /*ra*/ RISCV::X1: return 0;
162 }
163 }
164
165 // Get the name of the libcall used for spilling callee saved registers.
166 // If this function will not use save/restore libcalls, then return a nullptr.
167 static const char *
getSpillLibCallName(const MachineFunction & MF,const std::vector<CalleeSavedInfo> & CSI)168 getSpillLibCallName(const MachineFunction &MF,
169 const std::vector<CalleeSavedInfo> &CSI) {
170 static const char *const SpillLibCalls[] = {
171 "__riscv_save_0",
172 "__riscv_save_1",
173 "__riscv_save_2",
174 "__riscv_save_3",
175 "__riscv_save_4",
176 "__riscv_save_5",
177 "__riscv_save_6",
178 "__riscv_save_7",
179 "__riscv_save_8",
180 "__riscv_save_9",
181 "__riscv_save_10",
182 "__riscv_save_11",
183 "__riscv_save_12"
184 };
185
186 int LibCallID = getLibCallID(MF, CSI);
187 if (LibCallID == -1)
188 return nullptr;
189 return SpillLibCalls[LibCallID];
190 }
191
192 // Get the name of the libcall used for restoring callee saved registers.
193 // If this function will not use save/restore libcalls, then return a nullptr.
194 static const char *
getRestoreLibCallName(const MachineFunction & MF,const std::vector<CalleeSavedInfo> & CSI)195 getRestoreLibCallName(const MachineFunction &MF,
196 const std::vector<CalleeSavedInfo> &CSI) {
197 static const char *const RestoreLibCalls[] = {
198 "__riscv_restore_0",
199 "__riscv_restore_1",
200 "__riscv_restore_2",
201 "__riscv_restore_3",
202 "__riscv_restore_4",
203 "__riscv_restore_5",
204 "__riscv_restore_6",
205 "__riscv_restore_7",
206 "__riscv_restore_8",
207 "__riscv_restore_9",
208 "__riscv_restore_10",
209 "__riscv_restore_11",
210 "__riscv_restore_12"
211 };
212
213 int LibCallID = getLibCallID(MF, CSI);
214 if (LibCallID == -1)
215 return nullptr;
216 return RestoreLibCalls[LibCallID];
217 }
218
hasFP(const MachineFunction & MF) const219 bool RISCVFrameLowering::hasFP(const MachineFunction &MF) const {
220 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
221
222 const MachineFrameInfo &MFI = MF.getFrameInfo();
223 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
224 RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() ||
225 MFI.isFrameAddressTaken();
226 }
227
hasBP(const MachineFunction & MF) const228 bool RISCVFrameLowering::hasBP(const MachineFunction &MF) const {
229 const MachineFrameInfo &MFI = MF.getFrameInfo();
230 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
231
232 return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF);
233 }
234
235 // Determines the size of the frame and maximum call frame size.
determineFrameLayout(MachineFunction & MF) const236 void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
237 MachineFrameInfo &MFI = MF.getFrameInfo();
238 const RISCVRegisterInfo *RI = STI.getRegisterInfo();
239
240 // Get the number of bytes to allocate from the FrameInfo.
241 uint64_t FrameSize = MFI.getStackSize();
242
243 // Get the alignment.
244 Align StackAlign = getStackAlign();
245 if (RI->needsStackRealignment(MF)) {
246 Align MaxStackAlign = std::max(StackAlign, MFI.getMaxAlign());
247 FrameSize += (MaxStackAlign.value() - StackAlign.value());
248 StackAlign = MaxStackAlign;
249 }
250
251 // Set Max Call Frame Size
252 uint64_t MaxCallSize = alignTo(MFI.getMaxCallFrameSize(), StackAlign);
253 MFI.setMaxCallFrameSize(MaxCallSize);
254
255 // Make sure the frame is aligned.
256 FrameSize = alignTo(FrameSize, StackAlign);
257
258 // Update frame info.
259 MFI.setStackSize(FrameSize);
260 }
261
adjustReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const DebugLoc & DL,Register DestReg,Register SrcReg,int64_t Val,MachineInstr::MIFlag Flag) const262 void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB,
263 MachineBasicBlock::iterator MBBI,
264 const DebugLoc &DL, Register DestReg,
265 Register SrcReg, int64_t Val,
266 MachineInstr::MIFlag Flag) const {
267 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
268 const RISCVInstrInfo *TII = STI.getInstrInfo();
269
270 if (DestReg == SrcReg && Val == 0)
271 return;
272
273 if (isInt<12>(Val)) {
274 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
275 .addReg(SrcReg)
276 .addImm(Val)
277 .setMIFlag(Flag);
278 } else {
279 unsigned Opc = RISCV::ADD;
280 bool isSub = Val < 0;
281 if (isSub) {
282 Val = -Val;
283 Opc = RISCV::SUB;
284 }
285
286 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
287 TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);
288 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
289 .addReg(SrcReg)
290 .addReg(ScratchReg, RegState::Kill)
291 .setMIFlag(Flag);
292 }
293 }
294
295 // Returns the register used to hold the frame pointer.
getFPReg(const RISCVSubtarget & STI)296 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }
297
298 // Returns the register used to hold the stack pointer.
getSPReg(const RISCVSubtarget & STI)299 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }
300
301 static SmallVector<CalleeSavedInfo, 8>
getNonLibcallCSI(const std::vector<CalleeSavedInfo> & CSI)302 getNonLibcallCSI(const std::vector<CalleeSavedInfo> &CSI) {
303 SmallVector<CalleeSavedInfo, 8> NonLibcallCSI;
304
305 for (auto &CS : CSI)
306 if (CS.getFrameIdx() >= 0)
307 NonLibcallCSI.push_back(CS);
308
309 return NonLibcallCSI;
310 }
311
emitPrologue(MachineFunction & MF,MachineBasicBlock & MBB) const312 void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
313 MachineBasicBlock &MBB) const {
314 MachineFrameInfo &MFI = MF.getFrameInfo();
315 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
316 const RISCVRegisterInfo *RI = STI.getRegisterInfo();
317 const RISCVInstrInfo *TII = STI.getInstrInfo();
318 MachineBasicBlock::iterator MBBI = MBB.begin();
319
320 Register FPReg = getFPReg(STI);
321 Register SPReg = getSPReg(STI);
322 Register BPReg = RISCVABI::getBPReg();
323
324 // Debug location must be unknown since the first debug location is used
325 // to determine the end of the prologue.
326 DebugLoc DL;
327
328 // Emit prologue for shadow call stack.
329 emitSCSPrologue(MF, MBB, MBBI, DL);
330
331 // Since spillCalleeSavedRegisters may have inserted a libcall, skip past
332 // any instructions marked as FrameSetup
333 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
334 ++MBBI;
335
336 // Determine the correct frame layout
337 determineFrameLayout(MF);
338
339 // If libcalls are used to spill and restore callee-saved registers, the frame
340 // has two sections; the opaque section managed by the libcalls, and the
341 // section managed by MachineFrameInfo which can also hold callee saved
342 // registers in fixed stack slots, both of which have negative frame indices.
343 // This gets even more complicated when incoming arguments are passed via the
344 // stack, as these too have negative frame indices. An example is detailed
345 // below:
346 //
347 // | incoming arg | <- FI[-3]
348 // | libcallspill |
349 // | calleespill | <- FI[-2]
350 // | calleespill | <- FI[-1]
351 // | this_frame | <- FI[0]
352 //
353 // For negative frame indices, the offset from the frame pointer will differ
354 // depending on which of these groups the frame index applies to.
355 // The following calculates the correct offset knowing the number of callee
356 // saved registers spilt by the two methods.
357 if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) {
358 // Calculate the size of the frame managed by the libcall. The libcalls are
359 // implemented such that the stack will always be 16 byte aligned.
360 unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16);
361 RVFI->setLibCallStackSize(LibCallFrameSize);
362 }
363
364 // FIXME (note copied from Lanai): This appears to be overallocating. Needs
365 // investigation. Get the number of bytes to allocate from the FrameInfo.
366 uint64_t StackSize = MFI.getStackSize();
367 uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize();
368
369 // Early exit if there is no need to allocate on the stack
370 if (RealStackSize == 0 && !MFI.adjustsStack())
371 return;
372
373 // If the stack pointer has been marked as reserved, then produce an error if
374 // the frame requires stack allocation
375 if (STI.isRegisterReservedByUser(SPReg))
376 MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
377 MF.getFunction(), "Stack pointer required, but has been reserved."});
378
379 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
380 // Split the SP adjustment to reduce the offsets of callee saved spill.
381 if (FirstSPAdjustAmount) {
382 StackSize = FirstSPAdjustAmount;
383 RealStackSize = FirstSPAdjustAmount;
384 }
385
386 // Allocate space on the stack if necessary.
387 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);
388
389 // Emit ".cfi_def_cfa_offset RealStackSize"
390 unsigned CFIIndex = MF.addFrameInst(
391 MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize));
392 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
393 .addCFIIndex(CFIIndex);
394
395 const auto &CSI = MFI.getCalleeSavedInfo();
396
397 // The frame pointer is callee-saved, and code has been generated for us to
398 // save it to the stack. We need to skip over the storing of callee-saved
399 // registers as the frame pointer must be modified after it has been saved
400 // to the stack, not before.
401 // FIXME: assumes exactly one instruction is used to save each callee-saved
402 // register.
403 std::advance(MBBI, getNonLibcallCSI(CSI).size());
404
405 // Iterate over list of callee-saved registers and emit .cfi_offset
406 // directives.
407 for (const auto &Entry : CSI) {
408 int FrameIdx = Entry.getFrameIdx();
409 int64_t Offset;
410 // Offsets for objects with fixed locations (IE: those saved by libcall) are
411 // simply calculated from the frame index.
412 if (FrameIdx < 0)
413 Offset = FrameIdx * (int64_t) STI.getXLen() / 8;
414 else
415 Offset = MFI.getObjectOffset(Entry.getFrameIdx()) -
416 RVFI->getLibCallStackSize();
417 Register Reg = Entry.getReg();
418 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
419 nullptr, RI->getDwarfRegNum(Reg, true), Offset));
420 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
421 .addCFIIndex(CFIIndex);
422 }
423
424 // Generate new FP.
425 if (hasFP(MF)) {
426 if (STI.isRegisterReservedByUser(FPReg))
427 MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
428 MF.getFunction(), "Frame pointer required, but has been reserved."});
429
430 adjustReg(MBB, MBBI, DL, FPReg, SPReg,
431 RealStackSize - RVFI->getVarArgsSaveSize(),
432 MachineInstr::FrameSetup);
433
434 // Emit ".cfi_def_cfa $fp, RVFI->getVarArgsSaveSize()"
435 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
436 nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize()));
437 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
438 .addCFIIndex(CFIIndex);
439 }
440
441 // Emit the second SP adjustment after saving callee saved registers.
442 if (FirstSPAdjustAmount) {
443 uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
444 assert(SecondSPAdjustAmount > 0 &&
445 "SecondSPAdjustAmount should be greater than zero");
446 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount,
447 MachineInstr::FrameSetup);
448
449 // If we are using a frame-pointer, and thus emitted ".cfi_def_cfa fp, 0",
450 // don't emit an sp-based .cfi_def_cfa_offset
451 if (!hasFP(MF)) {
452 // Emit ".cfi_def_cfa_offset StackSize"
453 unsigned CFIIndex = MF.addFrameInst(
454 MCCFIInstruction::cfiDefCfaOffset(nullptr, MFI.getStackSize()));
455 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
456 .addCFIIndex(CFIIndex);
457 }
458 }
459
460 if (hasFP(MF)) {
461 // Realign Stack
462 const RISCVRegisterInfo *RI = STI.getRegisterInfo();
463 if (RI->needsStackRealignment(MF)) {
464 Align MaxAlignment = MFI.getMaxAlign();
465
466 const RISCVInstrInfo *TII = STI.getInstrInfo();
467 if (isInt<12>(-(int)MaxAlignment.value())) {
468 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
469 .addReg(SPReg)
470 .addImm(-(int)MaxAlignment.value());
471 } else {
472 unsigned ShiftAmount = Log2(MaxAlignment);
473 Register VR =
474 MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
475 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)
476 .addReg(SPReg)
477 .addImm(ShiftAmount);
478 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)
479 .addReg(VR)
480 .addImm(ShiftAmount);
481 }
482 // FP will be used to restore the frame in the epilogue, so we need
483 // another base register BP to record SP after re-alignment. SP will
484 // track the current stack after allocating variable sized objects.
485 if (hasBP(MF)) {
486 // move BP, SP
487 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg)
488 .addReg(SPReg)
489 .addImm(0);
490 }
491 }
492 }
493 }
494
emitEpilogue(MachineFunction & MF,MachineBasicBlock & MBB) const495 void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
496 MachineBasicBlock &MBB) const {
497 const RISCVRegisterInfo *RI = STI.getRegisterInfo();
498 MachineFrameInfo &MFI = MF.getFrameInfo();
499 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
500 Register FPReg = getFPReg(STI);
501 Register SPReg = getSPReg(STI);
502
503 // Get the insert location for the epilogue. If there were no terminators in
504 // the block, get the last instruction.
505 MachineBasicBlock::iterator MBBI = MBB.end();
506 DebugLoc DL;
507 if (!MBB.empty()) {
508 MBBI = MBB.getFirstTerminator();
509 if (MBBI == MBB.end())
510 MBBI = MBB.getLastNonDebugInstr();
511 DL = MBBI->getDebugLoc();
512
513 // If this is not a terminator, the actual insert location should be after the
514 // last instruction.
515 if (!MBBI->isTerminator())
516 MBBI = std::next(MBBI);
517
518 // If callee-saved registers are saved via libcall, place stack adjustment
519 // before this call.
520 while (MBBI != MBB.begin() &&
521 std::prev(MBBI)->getFlag(MachineInstr::FrameDestroy))
522 --MBBI;
523 }
524
525 const auto &CSI = getNonLibcallCSI(MFI.getCalleeSavedInfo());
526
527 // Skip to before the restores of callee-saved registers
528 // FIXME: assumes exactly one instruction is used to restore each
529 // callee-saved register.
530 auto LastFrameDestroy = MBBI;
531 if (!CSI.empty())
532 LastFrameDestroy = std::prev(MBBI, CSI.size());
533
534 uint64_t StackSize = MFI.getStackSize();
535 uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize();
536 uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
537
538 // Restore the stack pointer using the value of the frame pointer. Only
539 // necessary if the stack pointer was modified, meaning the stack size is
540 // unknown.
541 if (RI->needsStackRealignment(MF) || MFI.hasVarSizedObjects()) {
542 assert(hasFP(MF) && "frame pointer should not have been eliminated");
543 adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset,
544 MachineInstr::FrameDestroy);
545 }
546
547 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
548 if (FirstSPAdjustAmount) {
549 uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
550 assert(SecondSPAdjustAmount > 0 &&
551 "SecondSPAdjustAmount should be greater than zero");
552
553 adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount,
554 MachineInstr::FrameDestroy);
555 }
556
557 if (FirstSPAdjustAmount)
558 StackSize = FirstSPAdjustAmount;
559
560 // Deallocate stack
561 adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
562
563 // Emit epilogue for shadow call stack.
564 emitSCSEpilogue(MF, MBB, MBBI, DL);
565 }
566
567 StackOffset
getFrameIndexReference(const MachineFunction & MF,int FI,Register & FrameReg) const568 RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
569 Register &FrameReg) const {
570 const MachineFrameInfo &MFI = MF.getFrameInfo();
571 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
572 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
573
574 // Callee-saved registers should be referenced relative to the stack
575 // pointer (positive offset), otherwise use the frame pointer (negative
576 // offset).
577 const auto &CSI = getNonLibcallCSI(MFI.getCalleeSavedInfo());
578 int MinCSFI = 0;
579 int MaxCSFI = -1;
580
581 int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea() +
582 MFI.getOffsetAdjustment();
583
584 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
585
586 if (CSI.size()) {
587 MinCSFI = CSI[0].getFrameIdx();
588 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
589 }
590
591 if (FI >= MinCSFI && FI <= MaxCSFI) {
592 FrameReg = RISCV::X2;
593
594 if (FirstSPAdjustAmount)
595 Offset += FirstSPAdjustAmount;
596 else
597 Offset += MFI.getStackSize();
598 } else if (RI->needsStackRealignment(MF) && !MFI.isFixedObjectIndex(FI)) {
599 // If the stack was realigned, the frame pointer is set in order to allow
600 // SP to be restored, so we need another base register to record the stack
601 // after realignment.
602 if (hasBP(MF))
603 FrameReg = RISCVABI::getBPReg();
604 else
605 FrameReg = RISCV::X2;
606 Offset += MFI.getStackSize();
607 if (FI < 0)
608 Offset += RVFI->getLibCallStackSize();
609 } else {
610 FrameReg = RI->getFrameRegister(MF);
611 if (hasFP(MF)) {
612 Offset += RVFI->getVarArgsSaveSize();
613 if (FI >= 0)
614 Offset -= RVFI->getLibCallStackSize();
615 } else {
616 Offset += MFI.getStackSize();
617 if (FI < 0)
618 Offset += RVFI->getLibCallStackSize();
619 }
620 }
621 return StackOffset::getFixed(Offset);
622 }
623
determineCalleeSaves(MachineFunction & MF,BitVector & SavedRegs,RegScavenger * RS) const624 void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
625 BitVector &SavedRegs,
626 RegScavenger *RS) const {
627 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
628 // Unconditionally spill RA and FP only if the function uses a frame
629 // pointer.
630 if (hasFP(MF)) {
631 SavedRegs.set(RISCV::X1);
632 SavedRegs.set(RISCV::X8);
633 }
634 // Mark BP as used if function has dedicated base pointer.
635 if (hasBP(MF))
636 SavedRegs.set(RISCVABI::getBPReg());
637
638 // If interrupt is enabled and there are calls in the handler,
639 // unconditionally save all Caller-saved registers and
640 // all FP registers, regardless whether they are used.
641 MachineFrameInfo &MFI = MF.getFrameInfo();
642
643 if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) {
644
645 static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */
646 RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */
647 RISCV::X10, RISCV::X11, /* a0-a1, a2-a7 */
648 RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17,
649 RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 /* t3-t6 */
650 };
651
652 for (unsigned i = 0; CSRegs[i]; ++i)
653 SavedRegs.set(CSRegs[i]);
654
655 if (MF.getSubtarget<RISCVSubtarget>().hasStdExtD() ||
656 MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) {
657
658 // If interrupt is enabled, this list contains all FP registers.
659 const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs();
660
661 for (unsigned i = 0; Regs[i]; ++i)
662 if (RISCV::FPR32RegClass.contains(Regs[i]) ||
663 RISCV::FPR64RegClass.contains(Regs[i]))
664 SavedRegs.set(Regs[i]);
665 }
666 }
667 }
668
processFunctionBeforeFrameFinalized(MachineFunction & MF,RegScavenger * RS) const669 void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
670 MachineFunction &MF, RegScavenger *RS) const {
671 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
672 MachineFrameInfo &MFI = MF.getFrameInfo();
673 const TargetRegisterClass *RC = &RISCV::GPRRegClass;
674 // estimateStackSize has been observed to under-estimate the final stack
675 // size, so give ourselves wiggle-room by checking for stack size
676 // representable an 11-bit signed field rather than 12-bits.
677 // FIXME: It may be possible to craft a function with a small stack that
678 // still needs an emergency spill slot for branch relaxation. This case
679 // would currently be missed.
680 if (!isInt<11>(MFI.estimateStackSize(MF))) {
681 int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
682 RegInfo->getSpillAlign(*RC), false);
683 RS->addScavengingFrameIndex(RegScavFI);
684 }
685 }
686
687 // Not preserve stack space within prologue for outgoing variables when the
688 // function contains variable size objects and let eliminateCallFramePseudoInstr
689 // preserve stack space for it.
hasReservedCallFrame(const MachineFunction & MF) const690 bool RISCVFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
691 return !MF.getFrameInfo().hasVarSizedObjects();
692 }
693
694 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions.
eliminateCallFramePseudoInstr(MachineFunction & MF,MachineBasicBlock & MBB,MachineBasicBlock::iterator MI) const695 MachineBasicBlock::iterator RISCVFrameLowering::eliminateCallFramePseudoInstr(
696 MachineFunction &MF, MachineBasicBlock &MBB,
697 MachineBasicBlock::iterator MI) const {
698 Register SPReg = RISCV::X2;
699 DebugLoc DL = MI->getDebugLoc();
700
701 if (!hasReservedCallFrame(MF)) {
702 // If space has not been reserved for a call frame, ADJCALLSTACKDOWN and
703 // ADJCALLSTACKUP must be converted to instructions manipulating the stack
704 // pointer. This is necessary when there is a variable length stack
705 // allocation (e.g. alloca), which means it's not possible to allocate
706 // space for outgoing arguments from within the function prologue.
707 int64_t Amount = MI->getOperand(0).getImm();
708
709 if (Amount != 0) {
710 // Ensure the stack remains aligned after adjustment.
711 Amount = alignSPAdjust(Amount);
712
713 if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)
714 Amount = -Amount;
715
716 adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags);
717 }
718 }
719
720 return MBB.erase(MI);
721 }
722
723 // We would like to split the SP adjustment to reduce prologue/epilogue
724 // as following instructions. In this way, the offset of the callee saved
725 // register could fit in a single store.
726 // add sp,sp,-2032
727 // sw ra,2028(sp)
728 // sw s0,2024(sp)
729 // sw s1,2020(sp)
730 // sw s3,2012(sp)
731 // sw s4,2008(sp)
732 // add sp,sp,-64
733 uint64_t
getFirstSPAdjustAmount(const MachineFunction & MF) const734 RISCVFrameLowering::getFirstSPAdjustAmount(const MachineFunction &MF) const {
735 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
736 const MachineFrameInfo &MFI = MF.getFrameInfo();
737 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
738 uint64_t StackSize = MFI.getStackSize();
739
740 // Disable SplitSPAdjust if save-restore libcall used. The callee saved
741 // registers will be pushed by the save-restore libcalls, so we don't have to
742 // split the SP adjustment in this case.
743 if (RVFI->getLibCallStackSize())
744 return 0;
745
746 // Return the FirstSPAdjustAmount if the StackSize can not fit in signed
747 // 12-bit and there exists a callee saved register need to be pushed.
748 if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
749 // FirstSPAdjustAmount is choosed as (2048 - StackAlign)
750 // because 2048 will cause sp = sp + 2048 in epilogue split into
751 // multi-instructions. The offset smaller than 2048 can fit in signle
752 // load/store instruction and we have to stick with the stack alignment.
753 // 2048 is 16-byte alignment. The stack alignment for RV32 and RV64 is 16,
754 // for RV32E is 4. So (2048 - StackAlign) will satisfy the stack alignment.
755 return 2048 - getStackAlign().value();
756 }
757 return 0;
758 }
759
spillCalleeSavedRegisters(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,ArrayRef<CalleeSavedInfo> CSI,const TargetRegisterInfo * TRI) const760 bool RISCVFrameLowering::spillCalleeSavedRegisters(
761 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
762 ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
763 if (CSI.empty())
764 return true;
765
766 MachineFunction *MF = MBB.getParent();
767 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
768 DebugLoc DL;
769 if (MI != MBB.end() && !MI->isDebugInstr())
770 DL = MI->getDebugLoc();
771
772 const char *SpillLibCall = getSpillLibCallName(*MF, CSI);
773 if (SpillLibCall) {
774 // Add spill libcall via non-callee-saved register t0.
775 BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5)
776 .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL)
777 .setMIFlag(MachineInstr::FrameSetup);
778
779 // Add registers spilled in libcall as liveins.
780 for (auto &CS : CSI)
781 MBB.addLiveIn(CS.getReg());
782 }
783
784 // Manually spill values not spilled by libcall.
785 const auto &NonLibcallCSI = getNonLibcallCSI(CSI);
786 for (auto &CS : NonLibcallCSI) {
787 // Insert the spill to the stack frame.
788 Register Reg = CS.getReg();
789 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
790 TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);
791 }
792
793 return true;
794 }
795
restoreCalleeSavedRegisters(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,MutableArrayRef<CalleeSavedInfo> CSI,const TargetRegisterInfo * TRI) const796 bool RISCVFrameLowering::restoreCalleeSavedRegisters(
797 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
798 MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
799 if (CSI.empty())
800 return true;
801
802 MachineFunction *MF = MBB.getParent();
803 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
804 DebugLoc DL;
805 if (MI != MBB.end() && !MI->isDebugInstr())
806 DL = MI->getDebugLoc();
807
808 // Manually restore values not restored by libcall. Insert in reverse order.
809 // loadRegFromStackSlot can insert multiple instructions.
810 const auto &NonLibcallCSI = getNonLibcallCSI(CSI);
811 for (auto &CS : reverse(NonLibcallCSI)) {
812 Register Reg = CS.getReg();
813 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
814 TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI);
815 assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");
816 }
817
818 const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI);
819 if (RestoreLibCall) {
820 // Add restore libcall via tail call.
821 MachineBasicBlock::iterator NewMI =
822 BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL))
823 .addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL)
824 .setMIFlag(MachineInstr::FrameDestroy);
825
826 // Remove trailing returns, since the terminator is now a tail call to the
827 // restore function.
828 if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) {
829 NewMI->copyImplicitOps(*MF, *MI);
830 MI->eraseFromParent();
831 }
832 }
833
834 return true;
835 }
836
canUseAsPrologue(const MachineBasicBlock & MBB) const837 bool RISCVFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const {
838 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
839 const MachineFunction *MF = MBB.getParent();
840 const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
841
842 if (!RVFI->useSaveRestoreLibCalls(*MF))
843 return true;
844
845 // Inserting a call to a __riscv_save libcall requires the use of the register
846 // t0 (X5) to hold the return address. Therefore if this register is already
847 // used we can't insert the call.
848
849 RegScavenger RS;
850 RS.enterBasicBlock(*TmpMBB);
851 return !RS.isRegUsed(RISCV::X5);
852 }
853
canUseAsEpilogue(const MachineBasicBlock & MBB) const854 bool RISCVFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
855 const MachineFunction *MF = MBB.getParent();
856 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
857 const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
858
859 if (!RVFI->useSaveRestoreLibCalls(*MF))
860 return true;
861
862 // Using the __riscv_restore libcalls to restore CSRs requires a tail call.
863 // This means if we still need to continue executing code within this function
864 // the restore cannot take place in this basic block.
865
866 if (MBB.succ_size() > 1)
867 return false;
868
869 MachineBasicBlock *SuccMBB =
870 MBB.succ_empty() ? TmpMBB->getFallThrough() : *MBB.succ_begin();
871
872 // Doing a tail call should be safe if there are no successors, because either
873 // we have a returning block or the end of the block is unreachable, so the
874 // restore will be eliminated regardless.
875 if (!SuccMBB)
876 return true;
877
878 // The successor can only contain a return, since we would effectively be
879 // replacing the successor with our own tail return at the end of our block.
880 return SuccMBB->isReturnBlock() && SuccMBB->size() == 1;
881 }
882