1 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
15 
16 #include "RISCVFrameLowering.h"
17 #include "RISCVISelLowering.h"
18 #include "RISCVInstrInfo.h"
19 #include "Utils/RISCVBaseInfo.h"
20 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
23 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
24 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/Target/TargetMachine.h"
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "RISCVGenSubtargetInfo.inc"
31 
32 namespace llvm {
33 class StringRef;
34 
35 class RISCVSubtarget : public RISCVGenSubtargetInfo {
36   virtual void anchor();
37   bool HasStdExtM = false;
38   bool HasStdExtA = false;
39   bool HasStdExtF = false;
40   bool HasStdExtD = false;
41   bool HasStdExtC = false;
42   bool HasStdExtB = false;
43   bool HasStdExtZbb = false;
44   bool HasStdExtZbc = false;
45   bool HasStdExtZbe = false;
46   bool HasStdExtZbf = false;
47   bool HasStdExtZbm = false;
48   bool HasStdExtZbp = false;
49   bool HasStdExtZbr = false;
50   bool HasStdExtZbs = false;
51   bool HasStdExtZbt = false;
52   bool HasStdExtZbproposedc = false;
53   bool HasStdExtV = false;
54   bool HasStdExtZvlsseg = false;
55   bool HasStdExtZvamo = false;
56   bool HasRV64 = false;
57   bool IsRV32E = false;
58   bool EnableLinkerRelax = false;
59   bool EnableRVCHintInstrs = true;
60   bool EnableSaveRestore = false;
61   unsigned XLen = 32;
62   MVT XLenVT = MVT::i32;
63   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
64   BitVector UserReservedRegister;
65   RISCVFrameLowering FrameLowering;
66   RISCVInstrInfo InstrInfo;
67   RISCVRegisterInfo RegInfo;
68   RISCVTargetLowering TLInfo;
69   SelectionDAGTargetInfo TSInfo;
70 
71   /// Initializes using the passed in CPU and feature strings so that we can
72   /// use initializer lists for subtarget initialization.
73   RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
74                                                   StringRef CPU,
75                                                   StringRef TuneCPU,
76                                                   StringRef FS,
77                                                   StringRef ABIName);
78 
79 public:
80   // Initializes the data members to match that of the specified triple.
81   RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
82                  StringRef FS, StringRef ABIName, const TargetMachine &TM);
83 
84   // Parses features string setting specified subtarget options. The
85   // definition of this function is auto-generated by tblgen.
86   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
87 
getFrameLowering()88   const RISCVFrameLowering *getFrameLowering() const override {
89     return &FrameLowering;
90   }
getInstrInfo()91   const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
getRegisterInfo()92   const RISCVRegisterInfo *getRegisterInfo() const override {
93     return &RegInfo;
94   }
getTargetLowering()95   const RISCVTargetLowering *getTargetLowering() const override {
96     return &TLInfo;
97   }
getSelectionDAGInfo()98   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
99     return &TSInfo;
100   }
enableMachineScheduler()101   bool enableMachineScheduler() const override { return true; }
hasStdExtM()102   bool hasStdExtM() const { return HasStdExtM; }
hasStdExtA()103   bool hasStdExtA() const { return HasStdExtA; }
hasStdExtF()104   bool hasStdExtF() const { return HasStdExtF; }
hasStdExtD()105   bool hasStdExtD() const { return HasStdExtD; }
hasStdExtC()106   bool hasStdExtC() const { return HasStdExtC; }
hasStdExtB()107   bool hasStdExtB() const { return HasStdExtB; }
hasStdExtZbb()108   bool hasStdExtZbb() const { return HasStdExtZbb; }
hasStdExtZbc()109   bool hasStdExtZbc() const { return HasStdExtZbc; }
hasStdExtZbe()110   bool hasStdExtZbe() const { return HasStdExtZbe; }
hasStdExtZbf()111   bool hasStdExtZbf() const { return HasStdExtZbf; }
hasStdExtZbm()112   bool hasStdExtZbm() const { return HasStdExtZbm; }
hasStdExtZbp()113   bool hasStdExtZbp() const { return HasStdExtZbp; }
hasStdExtZbr()114   bool hasStdExtZbr() const { return HasStdExtZbr; }
hasStdExtZbs()115   bool hasStdExtZbs() const { return HasStdExtZbs; }
hasStdExtZbt()116   bool hasStdExtZbt() const { return HasStdExtZbt; }
hasStdExtZbproposedc()117   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
hasStdExtV()118   bool hasStdExtV() const { return HasStdExtV; }
hasStdExtZvlsseg()119   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
hasStdExtZvamo()120   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
is64Bit()121   bool is64Bit() const { return HasRV64; }
isRV32E()122   bool isRV32E() const { return IsRV32E; }
enableLinkerRelax()123   bool enableLinkerRelax() const { return EnableLinkerRelax; }
enableRVCHintInstrs()124   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
enableSaveRestore()125   bool enableSaveRestore() const { return EnableSaveRestore; }
getXLenVT()126   MVT getXLenVT() const { return XLenVT; }
getXLen()127   unsigned getXLen() const { return XLen; }
getTargetABI()128   RISCVABI::ABI getTargetABI() const { return TargetABI; }
isRegisterReservedByUser(Register i)129   bool isRegisterReservedByUser(Register i) const {
130     assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
131     return UserReservedRegister[i];
132   }
133 
134 protected:
135   // GlobalISel related APIs.
136   std::unique_ptr<CallLowering> CallLoweringInfo;
137   std::unique_ptr<InstructionSelector> InstSelector;
138   std::unique_ptr<LegalizerInfo> Legalizer;
139   std::unique_ptr<RegisterBankInfo> RegBankInfo;
140 
141 public:
142   const CallLowering *getCallLowering() const override;
143   InstructionSelector *getInstructionSelector() const override;
144   const LegalizerInfo *getLegalizerInfo() const override;
145   const RegisterBankInfo *getRegBankInfo() const override;
146 };
147 } // End llvm namespace
148 
149 #endif
150