1 use crate::cdsl::cpu_modes::CpuMode;
2 use crate::cdsl::instructions::{InstructionGroupBuilder, InstructionPredicateMap};
3 use crate::cdsl::isa::TargetIsa;
4 use crate::cdsl::recipes::Recipes;
5 use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
6 use crate::cdsl::settings::{SettingGroup, SettingGroupBuilder};
7
8 use crate::shared::Definitions as SharedDefinitions;
9
define_settings(_shared: &SettingGroup) -> SettingGroup10 fn define_settings(_shared: &SettingGroup) -> SettingGroup {
11 let setting = SettingGroupBuilder::new("arm32");
12 setting.build()
13 }
14
define_regs() -> IsaRegs15 fn define_regs() -> IsaRegs {
16 let mut regs = IsaRegsBuilder::new();
17
18 let builder = RegBankBuilder::new("FloatRegs", "s")
19 .units(64)
20 .track_pressure(true);
21 let float_regs = regs.add_bank(builder);
22
23 let builder = RegBankBuilder::new("IntRegs", "r")
24 .units(16)
25 .track_pressure(true);
26 let int_regs = regs.add_bank(builder);
27
28 let builder = RegBankBuilder::new("FlagRegs", "")
29 .units(1)
30 .names(vec!["nzcv"])
31 .track_pressure(false);
32 let flag_reg = regs.add_bank(builder);
33
34 let builder = RegClassBuilder::new_toplevel("S", float_regs).count(32);
35 regs.add_class(builder);
36
37 let builder = RegClassBuilder::new_toplevel("D", float_regs).width(2);
38 regs.add_class(builder);
39
40 let builder = RegClassBuilder::new_toplevel("Q", float_regs).width(4);
41 regs.add_class(builder);
42
43 let builder = RegClassBuilder::new_toplevel("GPR", int_regs);
44 regs.add_class(builder);
45
46 let builder = RegClassBuilder::new_toplevel("FLAG", flag_reg);
47 regs.add_class(builder);
48
49 regs.build()
50 }
51
define(shared_defs: &mut SharedDefinitions) -> TargetIsa52 pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
53 let settings = define_settings(&shared_defs.settings);
54 let regs = define_regs();
55
56 let inst_group = InstructionGroupBuilder::new(
57 "arm32",
58 "arm32 specific instruction set",
59 &mut shared_defs.all_instructions,
60 &shared_defs.format_registry,
61 )
62 .build();
63
64 // CPU modes for 32-bit ARM and Thumb2.
65 let mut a32 = CpuMode::new("A32");
66 let mut t32 = CpuMode::new("T32");
67
68 // TODO refine these.
69 let narrow_flags = shared_defs.transform_groups.by_name("narrow_flags");
70 a32.legalize_default(narrow_flags);
71 t32.legalize_default(narrow_flags);
72
73 let cpu_modes = vec![a32, t32];
74
75 // TODO implement arm32 recipes.
76 let recipes = Recipes::new();
77
78 // TODO implement arm32 encodings and predicates.
79 let encodings_predicates = InstructionPredicateMap::new();
80
81 TargetIsa::new(
82 "arm32",
83 inst_group,
84 settings,
85 regs,
86 recipes,
87 cpu_modes,
88 encodings_predicates,
89 )
90 }
91