1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #ifndef V8_ARM_CONSTANTS_ARM_H_
6 #define V8_ARM_CONSTANTS_ARM_H_
7
8 #include <stdint.h>
9
10 #include "src/base/logging.h"
11 #include "src/base/macros.h"
12 #include "src/boxed-float.h"
13 #include "src/globals.h"
14
15 // ARM EABI is required.
16 #if defined(__arm__) && !defined(__ARM_EABI__)
17 #error ARM EABI support is required.
18 #endif
19
20 namespace v8 {
21 namespace internal {
22
23 // Constant pool marker.
24 // Use UDF, the permanently undefined instruction.
25 const int kConstantPoolMarkerMask = 0xfff000f0;
26 const int kConstantPoolMarker = 0xe7f000f0;
27 const int kConstantPoolLengthMaxMask = 0xffff;
EncodeConstantPoolLength(int length)28 inline int EncodeConstantPoolLength(int length) {
29 DCHECK((length & kConstantPoolLengthMaxMask) == length);
30 return ((length & 0xfff0) << 4) | (length & 0xf);
31 }
DecodeConstantPoolLength(int instr)32 inline int DecodeConstantPoolLength(int instr) {
33 DCHECK_EQ(instr & kConstantPoolMarkerMask, kConstantPoolMarker);
34 return ((instr >> 4) & 0xfff0) | (instr & 0xf);
35 }
36
37 // Number of registers in normal ARM mode.
38 const int kNumRegisters = 16;
39
40 // VFP support.
41 const int kNumVFPSingleRegisters = 32;
42 const int kNumVFPDoubleRegisters = 32;
43 const int kNumVFPRegisters = kNumVFPSingleRegisters + kNumVFPDoubleRegisters;
44
45 // PC is register 15.
46 const int kPCRegister = 15;
47 const int kNoRegister = -1;
48
49 // Used in embedded constant pool builder - max reach in bits for
50 // various load instructions (unsigned)
51 const int kLdrMaxReachBits = 12;
52 const int kVldrMaxReachBits = 10;
53
54 // -----------------------------------------------------------------------------
55 // Conditions.
56
57 // Defines constants and accessor classes to assemble, disassemble and
58 // simulate ARM instructions.
59 //
60 // Section references in the code refer to the "ARM Architecture Reference
61 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf)
62 //
63 // Constants for specific fields are defined in their respective named enums.
64 // General constants are in an anonymous enum in class Instr.
65
66 // Values for the condition field as defined in section A3.2
67 enum Condition {
68 kNoCondition = -1,
69
70 eq = 0 << 28, // Z set Equal.
71 ne = 1 << 28, // Z clear Not equal.
72 cs = 2 << 28, // C set Unsigned higher or same.
73 cc = 3 << 28, // C clear Unsigned lower.
74 mi = 4 << 28, // N set Negative.
75 pl = 5 << 28, // N clear Positive or zero.
76 vs = 6 << 28, // V set Overflow.
77 vc = 7 << 28, // V clear No overflow.
78 hi = 8 << 28, // C set, Z clear Unsigned higher.
79 ls = 9 << 28, // C clear or Z set Unsigned lower or same.
80 ge = 10 << 28, // N == V Greater or equal.
81 lt = 11 << 28, // N != V Less than.
82 gt = 12 << 28, // Z clear, N == V Greater than.
83 le = 13 << 28, // Z set or N != V Less then or equal
84 al = 14 << 28, // Always.
85
86 kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1).
87 kNumberOfConditions = 16,
88
89 // Aliases.
90 hs = cs, // C set Unsigned higher or same.
91 lo = cc // C clear Unsigned lower.
92 };
93
94
NegateCondition(Condition cond)95 inline Condition NegateCondition(Condition cond) {
96 DCHECK(cond != al);
97 return static_cast<Condition>(cond ^ ne);
98 }
99
100
101 // Commute a condition such that {a cond b == b cond' a}.
CommuteCondition(Condition cond)102 inline Condition CommuteCondition(Condition cond) {
103 switch (cond) {
104 case lo:
105 return hi;
106 case hi:
107 return lo;
108 case hs:
109 return ls;
110 case ls:
111 return hs;
112 case lt:
113 return gt;
114 case gt:
115 return lt;
116 case ge:
117 return le;
118 case le:
119 return ge;
120 default:
121 return cond;
122 }
123 }
124
125
126 // -----------------------------------------------------------------------------
127 // Instructions encoding.
128
129 // Instr is merely used by the Assembler to distinguish 32bit integers
130 // representing instructions from usual 32 bit values.
131 // Instruction objects are pointers to 32bit values, and provide methods to
132 // access the various ISA fields.
133 typedef int32_t Instr;
134
135
136 // Opcodes for Data-processing instructions (instructions with a type 0 and 1)
137 // as defined in section A3.4
138 enum Opcode {
139 AND = 0 << 21, // Logical AND.
140 EOR = 1 << 21, // Logical Exclusive OR.
141 SUB = 2 << 21, // Subtract.
142 RSB = 3 << 21, // Reverse Subtract.
143 ADD = 4 << 21, // Add.
144 ADC = 5 << 21, // Add with Carry.
145 SBC = 6 << 21, // Subtract with Carry.
146 RSC = 7 << 21, // Reverse Subtract with Carry.
147 TST = 8 << 21, // Test.
148 TEQ = 9 << 21, // Test Equivalence.
149 CMP = 10 << 21, // Compare.
150 CMN = 11 << 21, // Compare Negated.
151 ORR = 12 << 21, // Logical (inclusive) OR.
152 MOV = 13 << 21, // Move.
153 BIC = 14 << 21, // Bit Clear.
154 MVN = 15 << 21 // Move Not.
155 };
156
157
158 // The bits for bit 7-4 for some type 0 miscellaneous instructions.
159 enum MiscInstructionsBits74 {
160 // With bits 22-21 01.
161 BX = 1 << 4,
162 BXJ = 2 << 4,
163 BLX = 3 << 4,
164 BKPT = 7 << 4,
165
166 // With bits 22-21 11.
167 CLZ = 1 << 4
168 };
169
170
171 // Instruction encoding bits and masks.
172 enum {
173 H = 1 << 5, // Halfword (or byte).
174 S6 = 1 << 6, // Signed (or unsigned).
175 L = 1 << 20, // Load (or store).
176 S = 1 << 20, // Set condition code (or leave unchanged).
177 W = 1 << 21, // Writeback base register (or leave unchanged).
178 A = 1 << 21, // Accumulate in multiply instruction (or not).
179 B = 1 << 22, // Unsigned byte (or word).
180 N = 1 << 22, // Long (or short).
181 U = 1 << 23, // Positive (or negative) offset/index.
182 P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing).
183 I = 1 << 25, // Immediate shifter operand (or not).
184 B0 = 1 << 0,
185 B4 = 1 << 4,
186 B5 = 1 << 5,
187 B6 = 1 << 6,
188 B7 = 1 << 7,
189 B8 = 1 << 8,
190 B9 = 1 << 9,
191 B10 = 1 << 10,
192 B12 = 1 << 12,
193 B16 = 1 << 16,
194 B17 = 1 << 17,
195 B18 = 1 << 18,
196 B19 = 1 << 19,
197 B20 = 1 << 20,
198 B21 = 1 << 21,
199 B22 = 1 << 22,
200 B23 = 1 << 23,
201 B24 = 1 << 24,
202 B25 = 1 << 25,
203 B26 = 1 << 26,
204 B27 = 1 << 27,
205 B28 = 1 << 28,
206
207 // Instruction bit masks.
208 kCondMask = 15 << 28,
209 kALUMask = 0x6f << 21,
210 kRdMask = 15 << 12, // In str instruction.
211 kCoprocessorMask = 15 << 8,
212 kOpCodeMask = 15 << 21, // In data-processing instructions.
213 kImm24Mask = (1 << 24) - 1,
214 kImm16Mask = (1 << 16) - 1,
215 kImm8Mask = (1 << 8) - 1,
216 kOff12Mask = (1 << 12) - 1,
217 kOff8Mask = (1 << 8) - 1
218 };
219
220 enum BarrierOption {
221 OSHLD = 0x1,
222 OSHST = 0x2,
223 OSH = 0x3,
224 NSHLD = 0x5,
225 NSHST = 0x6,
226 NSH = 0x7,
227 ISHLD = 0x9,
228 ISHST = 0xa,
229 ISH = 0xb,
230 LD = 0xd,
231 ST = 0xe,
232 SY = 0xf,
233 };
234
235
236 // -----------------------------------------------------------------------------
237 // Addressing modes and instruction variants.
238
239 // Condition code updating mode.
240 enum SBit {
241 SetCC = 1 << 20, // Set condition code.
242 LeaveCC = 0 << 20 // Leave condition code unchanged.
243 };
244
245
246 // Status register selection.
247 enum SRegister {
248 CPSR = 0 << 22,
249 SPSR = 1 << 22
250 };
251
252
253 // Shifter types for Data-processing operands as defined in section A5.1.2.
254 enum ShiftOp {
255 LSL = 0 << 5, // Logical shift left.
256 LSR = 1 << 5, // Logical shift right.
257 ASR = 2 << 5, // Arithmetic shift right.
258 ROR = 3 << 5, // Rotate right.
259
260 // RRX is encoded as ROR with shift_imm == 0.
261 // Use a special code to make the distinction. The RRX ShiftOp is only used
262 // as an argument, and will never actually be encoded. The Assembler will
263 // detect it and emit the correct ROR shift operand with shift_imm == 0.
264 RRX = -1,
265 kNumberOfShifts = 4
266 };
267
268
269 // Status register fields.
270 enum SRegisterField {
271 CPSR_c = CPSR | 1 << 16,
272 CPSR_x = CPSR | 1 << 17,
273 CPSR_s = CPSR | 1 << 18,
274 CPSR_f = CPSR | 1 << 19,
275 SPSR_c = SPSR | 1 << 16,
276 SPSR_x = SPSR | 1 << 17,
277 SPSR_s = SPSR | 1 << 18,
278 SPSR_f = SPSR | 1 << 19
279 };
280
281 // Status register field mask (or'ed SRegisterField enum values).
282 typedef uint32_t SRegisterFieldMask;
283
284
285 // Memory operand addressing mode.
286 enum AddrMode {
287 // Bit encoding P U W.
288 Offset = (8|4|0) << 21, // Offset (without writeback to base).
289 PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback.
290 PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback.
291 NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base).
292 NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback.
293 NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback.
294 };
295
296
297 // Load/store multiple addressing mode.
298 enum BlockAddrMode {
299 // Bit encoding P U W .
300 da = (0|0|0) << 21, // Decrement after.
301 ia = (0|4|0) << 21, // Increment after.
302 db = (8|0|0) << 21, // Decrement before.
303 ib = (8|4|0) << 21, // Increment before.
304 da_w = (0|0|1) << 21, // Decrement after with writeback to base.
305 ia_w = (0|4|1) << 21, // Increment after with writeback to base.
306 db_w = (8|0|1) << 21, // Decrement before with writeback to base.
307 ib_w = (8|4|1) << 21, // Increment before with writeback to base.
308
309 // Alias modes for comparison when writeback does not matter.
310 da_x = (0|0|0) << 21, // Decrement after.
311 ia_x = (0|4|0) << 21, // Increment after.
312 db_x = (8|0|0) << 21, // Decrement before.
313 ib_x = (8|4|0) << 21, // Increment before.
314
315 kBlockAddrModeMask = (8|4|1) << 21
316 };
317
318
319 // Coprocessor load/store operand size.
320 enum LFlag {
321 Long = 1 << 22, // Long load/store coprocessor.
322 Short = 0 << 22 // Short load/store coprocessor.
323 };
324
325 // Neon sizes.
326 enum NeonSize { Neon8 = 0x0, Neon16 = 0x1, Neon32 = 0x2, Neon64 = 0x3 };
327
328 // NEON data type
329 enum NeonDataType {
330 NeonS8 = 0,
331 NeonS16 = 1,
332 NeonS32 = 2,
333 // Gap to make it easier to extract U and size.
334 NeonU8 = 4,
335 NeonU16 = 5,
336 NeonU32 = 6
337 };
338
NeonU(NeonDataType dt)339 inline int NeonU(NeonDataType dt) { return static_cast<int>(dt) >> 2; }
NeonSz(NeonDataType dt)340 inline int NeonSz(NeonDataType dt) { return static_cast<int>(dt) & 0x3; }
341
342 // Convert sizes to data types (U bit is clear).
NeonSizeToDataType(NeonSize size)343 inline NeonDataType NeonSizeToDataType(NeonSize size) {
344 DCHECK_NE(Neon64, size);
345 return static_cast<NeonDataType>(size);
346 }
347
NeonDataTypeToSize(NeonDataType dt)348 inline NeonSize NeonDataTypeToSize(NeonDataType dt) {
349 return static_cast<NeonSize>(NeonSz(dt));
350 }
351
352 enum NeonListType {
353 nlt_1 = 0x7,
354 nlt_2 = 0xA,
355 nlt_3 = 0x6,
356 nlt_4 = 0x2
357 };
358
359 // -----------------------------------------------------------------------------
360 // Supervisor Call (svc) specific support.
361
362 // Special Software Interrupt codes when used in the presence of the ARM
363 // simulator.
364 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for
365 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature.
366 enum SoftwareInterruptCodes {
367 // transition to C code
368 kCallRtRedirected = 0x10,
369 // break point
370 kBreakpoint = 0x20,
371 // stop
372 kStopCode = 1 << 23
373 };
374 const uint32_t kStopCodeMask = kStopCode - 1;
375 const uint32_t kMaxStopCode = kStopCode - 1;
376 const int32_t kDefaultStopCode = -1;
377
378
379 // Type of VFP register. Determines register encoding.
380 enum VFPRegPrecision {
381 kSinglePrecision = 0,
382 kDoublePrecision = 1,
383 kSimd128Precision = 2
384 };
385
386 // VFP FPSCR constants.
387 enum VFPConversionMode {
388 kFPSCRRounding = 0,
389 kDefaultRoundToZero = 1
390 };
391
392 // This mask does not include the "inexact" or "input denormal" cumulative
393 // exceptions flags, because we usually don't want to check for it.
394 const uint32_t kVFPExceptionMask = 0xf;
395 const uint32_t kVFPInvalidOpExceptionBit = 1 << 0;
396 const uint32_t kVFPOverflowExceptionBit = 1 << 2;
397 const uint32_t kVFPUnderflowExceptionBit = 1 << 3;
398 const uint32_t kVFPInexactExceptionBit = 1 << 4;
399 const uint32_t kVFPFlushToZeroMask = 1 << 24;
400 const uint32_t kVFPDefaultNaNModeControlBit = 1 << 25;
401
402 const uint32_t kVFPNConditionFlagBit = 1 << 31;
403 const uint32_t kVFPZConditionFlagBit = 1 << 30;
404 const uint32_t kVFPCConditionFlagBit = 1 << 29;
405 const uint32_t kVFPVConditionFlagBit = 1 << 28;
406
407
408 // VFP rounding modes. See ARM DDI 0406B Page A2-29.
409 enum VFPRoundingMode {
410 RN = 0 << 22, // Round to Nearest.
411 RP = 1 << 22, // Round towards Plus Infinity.
412 RM = 2 << 22, // Round towards Minus Infinity.
413 RZ = 3 << 22, // Round towards zero.
414
415 // Aliases.
416 kRoundToNearest = RN,
417 kRoundToPlusInf = RP,
418 kRoundToMinusInf = RM,
419 kRoundToZero = RZ
420 };
421
422 const uint32_t kVFPRoundingModeMask = 3 << 22;
423
424 enum CheckForInexactConversion {
425 kCheckForInexactConversion,
426 kDontCheckForInexactConversion
427 };
428
429 // -----------------------------------------------------------------------------
430 // Hints.
431
432 // Branch hints are not used on the ARM. They are defined so that they can
433 // appear in shared function signatures, but will be ignored in ARM
434 // implementations.
435 enum Hint { no_hint };
436
437 // Hints are not used on the arm. Negating is trivial.
NegateHint(Hint ignored)438 inline Hint NegateHint(Hint ignored) { return no_hint; }
439
440
441 // -----------------------------------------------------------------------------
442 // Instruction abstraction.
443
444 // The class Instruction enables access to individual fields defined in the ARM
445 // architecture instruction set encoding as described in figure A3-1.
446 // Note that the Assembler uses typedef int32_t Instr.
447 //
448 // Example: Test whether the instruction at ptr does set the condition code
449 // bits.
450 //
451 // bool InstructionSetsConditionCodes(byte* ptr) {
452 // Instruction* instr = Instruction::At(ptr);
453 // int type = instr->TypeValue();
454 // return ((type == 0) || (type == 1)) && instr->HasS();
455 // }
456 //
457 class Instruction {
458 public:
459 enum {
460 kInstrSize = 4,
461 kInstrSizeLog2 = 2,
462 kPCReadOffset = 8
463 };
464
465 // Helper macro to define static accessors.
466 // We use the cast to char* trick to bypass the strict anti-aliasing rules.
467 #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \
468 static inline return_type Name(Instr instr) { \
469 char* temp = reinterpret_cast<char*>(&instr); \
470 return reinterpret_cast<Instruction*>(temp)->Name(); \
471 }
472
473 #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name)
474
475 // Get the raw instruction bits.
InstructionBits()476 inline Instr InstructionBits() const {
477 return *reinterpret_cast<const Instr*>(this);
478 }
479
480 // Set the raw instruction bits to value.
SetInstructionBits(Instr value)481 inline void SetInstructionBits(Instr value) {
482 *reinterpret_cast<Instr*>(this) = value;
483 }
484
485 // Extract a single bit from the instruction bits and return it as bit 0 in
486 // the result.
Bit(int nr)487 inline int Bit(int nr) const {
488 return (InstructionBits() >> nr) & 1;
489 }
490
491 // Extract a bit field <hi:lo> from the instruction bits and return it in the
492 // least-significant bits of the result.
Bits(int hi,int lo)493 inline int Bits(int hi, int lo) const {
494 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1);
495 }
496
497 // Read a bit field <hi:lo>, leaving its position unchanged in the result.
BitField(int hi,int lo)498 inline int BitField(int hi, int lo) const {
499 return InstructionBits() & (((2 << (hi - lo)) - 1) << lo);
500 }
501
502 // Static support.
503
504 // Extract a single bit from the instruction bits and return it as bit 0 in
505 // the result.
Bit(Instr instr,int nr)506 static inline int Bit(Instr instr, int nr) {
507 return (instr >> nr) & 1;
508 }
509
510 // Extract a bit field <hi:lo> from the instruction bits and return it in the
511 // least-significant bits of the result.
Bits(Instr instr,int hi,int lo)512 static inline int Bits(Instr instr, int hi, int lo) {
513 return (instr >> lo) & ((2 << (hi - lo)) - 1);
514 }
515
516 // Read a bit field <hi:lo>, leaving its position unchanged in the result.
BitField(Instr instr,int hi,int lo)517 static inline int BitField(Instr instr, int hi, int lo) {
518 return instr & (((2 << (hi - lo)) - 1) << lo);
519 }
520
521 // Accessors for the different named fields used in the ARM encoding.
522 // The naming of these accessor corresponds to figure A3-1.
523 //
524 // Two kind of accessors are declared:
525 // - <Name>Field() will return the raw field, i.e. the field's bits at their
526 // original place in the instruction encoding.
527 // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as
528 // 0xC0810002 ConditionField(instr) will return 0xC0000000.
529 // - <Name>Value() will return the field value, shifted back to bit 0.
530 // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as
531 // 0xC0810002 ConditionField(instr) will return 0xC.
532
533
534 // Generally applicable fields
ConditionValue()535 inline int ConditionValue() const { return Bits(31, 28); }
ConditionField()536 inline Condition ConditionField() const {
537 return static_cast<Condition>(BitField(31, 28));
538 }
539 DECLARE_STATIC_TYPED_ACCESSOR(int, ConditionValue);
540 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField);
541
TypeValue()542 inline int TypeValue() const { return Bits(27, 25); }
SpecialValue()543 inline int SpecialValue() const { return Bits(27, 23); }
544
RnValue()545 inline int RnValue() const { return Bits(19, 16); }
546 DECLARE_STATIC_ACCESSOR(RnValue);
RdValue()547 inline int RdValue() const { return Bits(15, 12); }
548 DECLARE_STATIC_ACCESSOR(RdValue);
549
CoprocessorValue()550 inline int CoprocessorValue() const { return Bits(11, 8); }
551 // Support for VFP.
552 // Vn(19-16) | Vd(15-12) | Vm(3-0)
VnValue()553 inline int VnValue() const { return Bits(19, 16); }
VmValue()554 inline int VmValue() const { return Bits(3, 0); }
VdValue()555 inline int VdValue() const { return Bits(15, 12); }
NValue()556 inline int NValue() const { return Bit(7); }
MValue()557 inline int MValue() const { return Bit(5); }
DValue()558 inline int DValue() const { return Bit(22); }
RtValue()559 inline int RtValue() const { return Bits(15, 12); }
PValue()560 inline int PValue() const { return Bit(24); }
UValue()561 inline int UValue() const { return Bit(23); }
Opc1Value()562 inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); }
Opc2Value()563 inline int Opc2Value() const { return Bits(19, 16); }
Opc3Value()564 inline int Opc3Value() const { return Bits(7, 6); }
SzValue()565 inline int SzValue() const { return Bit(8); }
VLValue()566 inline int VLValue() const { return Bit(20); }
VCValue()567 inline int VCValue() const { return Bit(8); }
VAValue()568 inline int VAValue() const { return Bits(23, 21); }
VBValue()569 inline int VBValue() const { return Bits(6, 5); }
VFPNRegValue(VFPRegPrecision pre)570 inline int VFPNRegValue(VFPRegPrecision pre) {
571 return VFPGlueRegValue(pre, 16, 7);
572 }
VFPMRegValue(VFPRegPrecision pre)573 inline int VFPMRegValue(VFPRegPrecision pre) {
574 return VFPGlueRegValue(pre, 0, 5);
575 }
VFPDRegValue(VFPRegPrecision pre)576 inline int VFPDRegValue(VFPRegPrecision pre) {
577 return VFPGlueRegValue(pre, 12, 22);
578 }
579
580 // Fields used in Data processing instructions
OpcodeValue()581 inline int OpcodeValue() const {
582 return static_cast<Opcode>(Bits(24, 21));
583 }
OpcodeField()584 inline Opcode OpcodeField() const {
585 return static_cast<Opcode>(BitField(24, 21));
586 }
SValue()587 inline int SValue() const { return Bit(20); }
588 // with register
RmValue()589 inline int RmValue() const { return Bits(3, 0); }
590 DECLARE_STATIC_ACCESSOR(RmValue);
ShiftValue()591 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); }
ShiftField()592 inline ShiftOp ShiftField() const {
593 return static_cast<ShiftOp>(BitField(6, 5));
594 }
RegShiftValue()595 inline int RegShiftValue() const { return Bit(4); }
RsValue()596 inline int RsValue() const { return Bits(11, 8); }
ShiftAmountValue()597 inline int ShiftAmountValue() const { return Bits(11, 7); }
598 // with immediate
RotateValue()599 inline int RotateValue() const { return Bits(11, 8); }
600 DECLARE_STATIC_ACCESSOR(RotateValue);
Immed8Value()601 inline int Immed8Value() const { return Bits(7, 0); }
602 DECLARE_STATIC_ACCESSOR(Immed8Value);
Immed4Value()603 inline int Immed4Value() const { return Bits(19, 16); }
ImmedMovwMovtValue()604 inline int ImmedMovwMovtValue() const {
605 return Immed4Value() << 12 | Offset12Value(); }
606 DECLARE_STATIC_ACCESSOR(ImmedMovwMovtValue);
607
608 // Fields used in Load/Store instructions
PUValue()609 inline int PUValue() const { return Bits(24, 23); }
PUField()610 inline int PUField() const { return BitField(24, 23); }
BValue()611 inline int BValue() const { return Bit(22); }
WValue()612 inline int WValue() const { return Bit(21); }
LValue()613 inline int LValue() const { return Bit(20); }
614 // with register uses same fields as Data processing instructions above
615 // with immediate
Offset12Value()616 inline int Offset12Value() const { return Bits(11, 0); }
617 // multiple
RlistValue()618 inline int RlistValue() const { return Bits(15, 0); }
619 // extra loads and stores
SignValue()620 inline int SignValue() const { return Bit(6); }
HValue()621 inline int HValue() const { return Bit(5); }
ImmedHValue()622 inline int ImmedHValue() const { return Bits(11, 8); }
ImmedLValue()623 inline int ImmedLValue() const { return Bits(3, 0); }
624
625 // Fields used in Branch instructions
LinkValue()626 inline int LinkValue() const { return Bit(24); }
SImmed24Value()627 inline int SImmed24Value() const { return ((InstructionBits() << 8) >> 8); }
628
629 // Fields used in Software interrupt instructions
SvcValue()630 inline SoftwareInterruptCodes SvcValue() const {
631 return static_cast<SoftwareInterruptCodes>(Bits(23, 0));
632 }
633
634 // Test for special encodings of type 0 instructions (extra loads and stores,
635 // as well as multiplications).
IsSpecialType0()636 inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); }
637
638 // Test for miscellaneous instructions encodings of type 0 instructions.
IsMiscType0()639 inline bool IsMiscType0() const { return (Bit(24) == 1)
640 && (Bit(23) == 0)
641 && (Bit(20) == 0)
642 && ((Bit(7) == 0)); }
643
644 // Test for nop-like instructions which fall under type 1.
IsNopLikeType1()645 inline bool IsNopLikeType1() const { return Bits(24, 8) == 0x120F0; }
646
647 // Test for a stop instruction.
IsStop()648 inline bool IsStop() const {
649 return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode);
650 }
651
652 // Special accessors that test for existence of a value.
HasS()653 inline bool HasS() const { return SValue() == 1; }
HasB()654 inline bool HasB() const { return BValue() == 1; }
HasW()655 inline bool HasW() const { return WValue() == 1; }
HasL()656 inline bool HasL() const { return LValue() == 1; }
HasU()657 inline bool HasU() const { return UValue() == 1; }
HasSign()658 inline bool HasSign() const { return SignValue() == 1; }
HasH()659 inline bool HasH() const { return HValue() == 1; }
HasLink()660 inline bool HasLink() const { return LinkValue() == 1; }
661
662 // Decode the double immediate from a vmov instruction.
663 Float64 DoubleImmedVmov() const;
664
665 // Instructions are read of out a code stream. The only way to get a
666 // reference to an instruction is to convert a pointer. There is no way
667 // to allocate or create instances of class Instruction.
668 // Use the At(pc) function to create references to Instruction.
At(Address pc)669 static Instruction* At(Address pc) {
670 return reinterpret_cast<Instruction*>(pc);
671 }
672
673
674 private:
675 // Join split register codes, depending on register precision.
676 // four_bit is the position of the least-significant bit of the four
677 // bit specifier. one_bit is the position of the additional single bit
678 // specifier.
VFPGlueRegValue(VFPRegPrecision pre,int four_bit,int one_bit)679 inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) {
680 if (pre == kSinglePrecision) {
681 return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit);
682 } else {
683 int reg_num = (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit);
684 if (pre == kDoublePrecision) {
685 return reg_num;
686 }
687 DCHECK_EQ(kSimd128Precision, pre);
688 DCHECK_EQ(reg_num & 1, 0);
689 return reg_num / 2;
690 }
691 }
692
693 // We need to prevent the creation of instances of class Instruction.
694 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
695 };
696
697
698 // Helper functions for converting between register numbers and names.
699 class Registers {
700 public:
701 // Return the name of the register.
702 static const char* Name(int reg);
703
704 // Lookup the register number for the name provided.
705 static int Number(const char* name);
706
707 struct RegisterAlias {
708 int reg;
709 const char* name;
710 };
711
712 private:
713 static const char* names_[kNumRegisters];
714 static const RegisterAlias aliases_[];
715 };
716
717 // Helper functions for converting between VFP register numbers and names.
718 class VFPRegisters {
719 public:
720 // Return the name of the register.
721 static const char* Name(int reg, bool is_double);
722
723 // Lookup the register number for the name provided.
724 // Set flag pointed by is_double to true if register
725 // is double-precision.
726 static int Number(const char* name, bool* is_double);
727
728 private:
729 static const char* names_[kNumVFPRegisters];
730 };
731
732
733 } // namespace internal
734 } // namespace v8
735
736 #endif // V8_ARM_CONSTANTS_ARM_H_
737