1 /*
2 * Copyright © 2009 Red Hat, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Dave Airlie <airlied@redhat.com>
25 *
26 */
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include <errno.h>
32 #include <sys/ioctl.h>
33 #include <sys/param.h>
34 #include <sys/linker.h>
35 /* Driver data structures */
36 #include "radeon.h"
37 #include "radeon_bo_helper.h"
38 #include "radeon_drm_queue.h"
39 #include "radeon_glamor.h"
40 #include "radeon_reg.h"
41 #include "radeon_probe.h"
42 #include "micmap.h"
43 #include "mipointrst.h"
44
45 #include "radeon_version.h"
46 #include "shadow.h"
47 #include <xf86Priv.h>
48
49 #include "atipciids.h"
50
51 #if HAVE_PRESENT_H
52 #include <present.h>
53 #endif
54
55 /* DPMS */
56 #ifdef HAVE_XEXTPROTO_71
57 #include <X11/extensions/dpmsconst.h>
58 #else
59 #define DPMS_SERVER
60 #include <X11/extensions/dpms.h>
61 #endif
62
63 #include <X11/extensions/damageproto.h>
64
65 #include "radeon_chipinfo_gen.h"
66
67 #include "radeon_bo_gem.h"
68 #include "radeon_cs_gem.h"
69 #include "radeon_vbo.h"
70
71 static DevScreenPrivateKeyRec radeon_client_private_key;
72 DevScreenPrivateKeyRec radeon_device_private_key;
73
74 extern SymTabRec RADEONChipsets[];
75 static Bool radeon_setup_kernel_mem(ScreenPtr pScreen);
76
77 const OptionInfoRec RADEONOptions_KMS[] = {
78 { OPTION_ACCEL, "Accel", OPTV_BOOLEAN, {0}, FALSE },
79 { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE },
80 { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE },
81 { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE },
82 { OPTION_COLOR_TILING_2D,"ColorTiling2D", OPTV_BOOLEAN, {0}, FALSE },
83 { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE },
84 { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE },
85 #ifdef USE_GLAMOR
86 { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE },
87 { OPTION_SHADOW_PRIMARY, "ShadowPrimary", OPTV_BOOLEAN, {0}, FALSE },
88 #endif
89 { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE },
90 { OPTION_EXA_PIXMAPS, "EXAPixmaps", OPTV_BOOLEAN, {0}, FALSE },
91 { OPTION_ZAPHOD_HEADS, "ZaphodHeads", OPTV_STRING, {0}, FALSE },
92 { OPTION_SWAPBUFFERS_WAIT,"SwapbuffersWait", OPTV_BOOLEAN, {0}, FALSE },
93 { OPTION_DELETE_DP12, "DeleteUnusedDP12Displays", OPTV_BOOLEAN, {0}, FALSE},
94 { OPTION_DRI3, "DRI3", OPTV_BOOLEAN, {0}, FALSE },
95 { OPTION_DRI, "DRI", OPTV_INTEGER, {0}, FALSE },
96 { OPTION_TEAR_FREE, "TearFree", OPTV_BOOLEAN, {0}, FALSE },
97 { -1, NULL, OPTV_NONE, {0}, FALSE }
98 };
99
RADEONOptionsWeak(void)100 const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions_KMS; }
101
radeon_cs_flush_indirect(ScrnInfoPtr pScrn)102 void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
103 {
104 RADEONInfoPtr info = RADEONPTR(pScrn);
105 struct radeon_accel_state *accel_state;
106 int ret;
107
108 info->gpu_flushed++;
109
110 #ifdef USE_GLAMOR
111 if (info->use_glamor) {
112 glamor_block_handler(pScrn->pScreen);
113 return;
114 }
115 #endif
116
117 if (!info->cs->cdw)
118 return;
119
120 accel_state = info->accel_state;
121
122 /* release the current VBO so we don't block on mapping it later */
123 if (info->accel_state->vbo.vb_offset && info->accel_state->vbo.vb_bo) {
124 radeon_vbo_put(pScrn, &info->accel_state->vbo);
125 info->accel_state->vbo.vb_start_op = -1;
126 }
127
128 /* release the current VBO so we don't block on mapping it later */
129 if (info->accel_state->cbuf.vb_bo) {
130 radeon_vbo_put(pScrn, &info->accel_state->cbuf);
131 info->accel_state->cbuf.vb_start_op = -1;
132 }
133
134 radeon_cs_emit(info->cs);
135 radeon_cs_erase(info->cs);
136
137 if (accel_state->use_vbos)
138 radeon_vbo_flush_bos(pScrn);
139
140 ret = radeon_cs_space_check_with_bo(info->cs,
141 accel_state->vbo.vb_bo,
142 RADEON_GEM_DOMAIN_GTT, 0);
143 if (ret)
144 ErrorF("space check failed in flush\n");
145
146 if (info->reemit_current2d && info->state_2d.op)
147 info->reemit_current2d(pScrn, info->state_2d.op);
148
149 if (info->dri2.enabled) {
150 info->accel_state->XInited3D = FALSE;
151 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
152 }
153
154 }
155
radeon_ddx_cs_start(ScrnInfoPtr pScrn,int n,const char * file,const char * func,int line)156 void radeon_ddx_cs_start(ScrnInfoPtr pScrn,
157 int n, const char *file,
158 const char *func, int line)
159 {
160 RADEONInfoPtr info = RADEONPTR(pScrn);
161
162 if (info->cs->cdw + n > info->cs->ndw) {
163 radeon_cs_flush_indirect(pScrn);
164
165 }
166 radeon_cs_begin(info->cs, n, file, func, line);
167 }
168
169
170 extern _X_EXPORT int gRADEONEntityIndex;
171
getRADEONEntityIndex(void)172 static int getRADEONEntityIndex(void)
173 {
174 return gRADEONEntityIndex;
175 }
176
177
RADEONEntPriv(ScrnInfoPtr pScrn)178 RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn)
179 {
180 DevUnion *pPriv;
181 RADEONInfoPtr info = RADEONPTR(pScrn);
182 pPriv = xf86GetEntityPrivate(info->pEnt->index,
183 getRADEONEntityIndex());
184 return pPriv->ptr;
185 }
186
187 /* Allocate our private RADEONInfoRec */
RADEONGetRec(ScrnInfoPtr pScrn)188 static Bool RADEONGetRec(ScrnInfoPtr pScrn)
189 {
190 if (pScrn->driverPrivate) return TRUE;
191
192 pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1);
193 return TRUE;
194 }
195
196 /* Free our private RADEONInfoRec */
RADEONFreeRec(ScrnInfoPtr pScrn)197 static void RADEONFreeRec(ScrnInfoPtr pScrn)
198 {
199 DevUnion *pPriv;
200 RADEONEntPtr pRADEONEnt;
201 RADEONInfoPtr info;
202 EntityInfoPtr pEnt;
203
204 if (!pScrn)
205 return;
206
207 pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]);
208 pPriv = xf86GetEntityPrivate(pEnt->index, gRADEONEntityIndex);
209 pRADEONEnt = pPriv->ptr;
210
211 info = RADEONPTR(pScrn);
212 if (info) {
213 if (info->fbcon_pixmap)
214 pScrn->pScreen->DestroyPixmap(info->fbcon_pixmap);
215
216 if (info->accel_state) {
217 free(info->accel_state);
218 info->accel_state = NULL;
219 }
220
221 #ifdef USE_GLAMOR
222 if (info->gbm)
223 gbm_device_destroy(info->gbm);
224 #endif
225
226 pRADEONEnt->scrn[info->instance_id] = NULL;
227 pRADEONEnt->num_scrns--;
228 free(pScrn->driverPrivate);
229 pScrn->driverPrivate = NULL;
230 }
231
232 if (pRADEONEnt->fd > 0) {
233 DevUnion *pPriv;
234 RADEONEntPtr pRADEONEnt;
235 pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
236 getRADEONEntityIndex());
237
238 pRADEONEnt = pPriv->ptr;
239 pRADEONEnt->fd_ref--;
240 if (!pRADEONEnt->fd_ref) {
241 #ifdef XF86_PDEV_SERVER_FD
242 if (!(pRADEONEnt->platform_dev &&
243 pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD))
244 #endif
245 drmClose(pRADEONEnt->fd);
246 free(pPriv->ptr);
247 pPriv->ptr = NULL;
248 }
249 }
250
251 free(pEnt);
252 }
253
254 static void *
radeonShadowWindow(ScreenPtr screen,CARD32 row,CARD32 offset,int mode,CARD32 * size,void * closure)255 radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode,
256 CARD32 *size, void *closure)
257 {
258 ScrnInfoPtr pScrn = xf86ScreenToScrn(screen);
259 RADEONInfoPtr info = RADEONPTR(pScrn);
260 int stride;
261
262 stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8;
263 *size = stride;
264
265 return ((uint8_t *)info->front_buffer->bo.radeon->ptr + row * stride + offset);
266 }
267
268 static void
radeonUpdatePacked(ScreenPtr pScreen,shadowBufPtr pBuf)269 radeonUpdatePacked(ScreenPtr pScreen, shadowBufPtr pBuf)
270 {
271 shadowUpdatePacked(pScreen, pBuf);
272 }
273
274 static Bool
callback_needs_flush(RADEONInfoPtr info,struct radeon_client_priv * client_priv)275 callback_needs_flush(RADEONInfoPtr info, struct radeon_client_priv *client_priv)
276 {
277 return (int)(client_priv->needs_flush - info->gpu_flushed) > 0;
278 }
279
280 static void
radeon_event_callback(CallbackListPtr * list,pointer user_data,pointer call_data)281 radeon_event_callback(CallbackListPtr *list,
282 pointer user_data, pointer call_data)
283 {
284 EventInfoRec *eventinfo = call_data;
285 ScrnInfoPtr pScrn = user_data;
286 ScreenPtr pScreen = pScrn->pScreen;
287 struct radeon_client_priv *client_priv =
288 dixLookupScreenPrivate(&eventinfo->client->devPrivates,
289 &radeon_client_private_key, pScreen);
290 struct radeon_client_priv *server_priv =
291 dixLookupScreenPrivate(&serverClient->devPrivates,
292 &radeon_client_private_key, pScreen);
293 RADEONInfoPtr info = RADEONPTR(pScrn);
294 int i;
295
296 if (callback_needs_flush(info, client_priv) ||
297 callback_needs_flush(info, server_priv))
298 return;
299
300 /* Don't let gpu_flushed get too far ahead of needs_flush, in order
301 * to prevent false positives in callback_needs_flush()
302 */
303 client_priv->needs_flush = info->gpu_flushed;
304 server_priv->needs_flush = info->gpu_flushed;
305
306 for (i = 0; i < eventinfo->count; i++) {
307 if (eventinfo->events[i].u.u.type == info->callback_event_type) {
308 client_priv->needs_flush++;
309 server_priv->needs_flush++;
310 return;
311 }
312 }
313 }
314
315 static void
radeon_flush_callback(CallbackListPtr * list,pointer user_data,pointer call_data)316 radeon_flush_callback(CallbackListPtr *list,
317 pointer user_data, pointer call_data)
318 {
319 ScrnInfoPtr pScrn = user_data;
320 ScreenPtr pScreen = pScrn->pScreen;
321 ClientPtr client = call_data ? call_data : serverClient;
322 struct radeon_client_priv *client_priv =
323 dixLookupScreenPrivate(&client->devPrivates,
324 &radeon_client_private_key, pScreen);
325 RADEONInfoPtr info = RADEONPTR(pScrn);
326
327 if (pScrn->vtSema && callback_needs_flush(info, client_priv))
328 radeon_cs_flush_indirect(pScrn);
329 }
330
RADEONCreateScreenResources_KMS(ScreenPtr pScreen)331 static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen)
332 {
333 ExtensionEntry *damage_ext;
334 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
335 RADEONInfoPtr info = RADEONPTR(pScrn);
336 PixmapPtr pixmap;
337
338 pScreen->CreateScreenResources = info->CreateScreenResources;
339 if (!(*pScreen->CreateScreenResources)(pScreen))
340 return FALSE;
341 pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS;
342
343 /* Set the RandR primary output if Xorg hasn't */
344 if (dixPrivateKeyRegistered(rrPrivKey)) {
345 rrScrPrivPtr rrScrPriv = rrGetScrPriv(pScreen);
346
347 if (!pScreen->isGPU && !rrScrPriv->primaryOutput) {
348 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
349
350 rrScrPriv->primaryOutput = xf86_config->output[0]->randr_output;
351 RROutputChanged(rrScrPriv->primaryOutput, FALSE);
352 rrScrPriv->layoutChanged = TRUE;
353 }
354
355 drmmode_uevent_init(pScrn, &info->drmmode);
356 }
357
358 if (!drmmode_set_desired_modes(pScrn, &info->drmmode, pScreen->isGPU))
359 return FALSE;
360
361 if (info->r600_shadow_fb) {
362 pixmap = pScreen->GetScreenPixmap(pScreen);
363
364 if (!shadowAdd(pScreen, pixmap, radeonUpdatePacked,
365 radeonShadowWindow, 0, NULL))
366 return FALSE;
367 }
368
369 if (info->dri2.enabled || info->use_glamor) {
370 if (info->front_buffer) {
371 PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
372 if (!radeon_set_pixmap_bo(pPix, info->front_buffer))
373 return FALSE;
374
375 if (info->surf_man && !info->use_glamor)
376 *radeon_get_pixmap_surface(pPix) = info->front_surface;
377 }
378 }
379
380 if (info->use_glamor)
381 radeon_glamor_create_screen_resources(pScreen);
382
383 info->callback_event_type = -1;
384 if (!pScreen->isGPU && (damage_ext = CheckExtension("DAMAGE"))) {
385 info->callback_event_type = damage_ext->eventBase + XDamageNotify;
386
387 if (!AddCallback(&FlushCallback, radeon_flush_callback, pScrn))
388 return FALSE;
389
390 if (!AddCallback(&EventCallback, radeon_event_callback, pScrn)) {
391 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn);
392 return FALSE;
393 }
394
395 if (!dixRegisterScreenPrivateKey(&radeon_client_private_key, pScreen,
396 PRIVATE_CLIENT, sizeof(struct radeon_client_priv))) {
397 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn);
398 DeleteCallback(&EventCallback, radeon_event_callback, pScrn);
399 return FALSE;
400 }
401 }
402
403 return TRUE;
404 }
405
406 static Bool
radeon_scanout_extents_intersect(xf86CrtcPtr xf86_crtc,BoxPtr extents)407 radeon_scanout_extents_intersect(xf86CrtcPtr xf86_crtc, BoxPtr extents)
408 {
409 if (xf86_crtc->scrn->is_gpu) {
410 extents->x1 -= xf86_crtc->x;
411 extents->y1 -= xf86_crtc->y;
412 extents->x2 -= xf86_crtc->x;
413 extents->y2 -= xf86_crtc->y;
414 } else {
415 extents->x1 -= xf86_crtc->filter_width >> 1;
416 extents->x2 += xf86_crtc->filter_width >> 1;
417 extents->y1 -= xf86_crtc->filter_height >> 1;
418 extents->y2 += xf86_crtc->filter_height >> 1;
419 pixman_f_transform_bounds(&xf86_crtc->f_framebuffer_to_crtc, extents);
420 }
421
422 extents->x1 = max(extents->x1, 0);
423 extents->y1 = max(extents->y1, 0);
424 extents->x2 = min(extents->x2, xf86_crtc->mode.HDisplay);
425 extents->y2 = min(extents->y2, xf86_crtc->mode.VDisplay);
426
427 return (extents->x1 < extents->x2 && extents->y1 < extents->y2);
428 }
429
430 static RegionPtr
transform_region(RegionPtr region,struct pict_f_transform * transform,int w,int h)431 transform_region(RegionPtr region, struct pict_f_transform *transform,
432 int w, int h)
433 {
434 BoxPtr boxes = RegionRects(region);
435 int nboxes = RegionNumRects(region);
436 xRectanglePtr rects = malloc(nboxes * sizeof(*rects));
437 RegionPtr transformed;
438 int nrects = 0;
439 BoxRec box;
440 int i;
441
442 for (i = 0; i < nboxes; i++) {
443 box.x1 = boxes[i].x1;
444 box.x2 = boxes[i].x2;
445 box.y1 = boxes[i].y1;
446 box.y2 = boxes[i].y2;
447 pixman_f_transform_bounds(transform, &box);
448
449 box.x1 = max(box.x1, 0);
450 box.y1 = max(box.y1, 0);
451 box.x2 = min(box.x2, w);
452 box.y2 = min(box.y2, h);
453 if (box.x1 >= box.x2 || box.y1 >= box.y2)
454 continue;
455
456 rects[nrects].x = box.x1;
457 rects[nrects].y = box.y1;
458 rects[nrects].width = box.x2 - box.x1;
459 rects[nrects].height = box.y2 - box.y1;
460 nrects++;
461 }
462
463 transformed = RegionFromRects(nrects, rects, CT_UNSORTED);
464 free(rects);
465 return transformed;
466 }
467
468 static void
radeon_sync_scanout_pixmaps(xf86CrtcPtr xf86_crtc,RegionPtr new_region,int scanout_id)469 radeon_sync_scanout_pixmaps(xf86CrtcPtr xf86_crtc, RegionPtr new_region,
470 int scanout_id)
471 {
472 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
473 DrawablePtr dst = &drmmode_crtc->scanout[scanout_id].pixmap->drawable;
474 DrawablePtr src = &drmmode_crtc->scanout[scanout_id ^ 1].pixmap->drawable;
475 RegionPtr last_region = &drmmode_crtc->scanout_last_region;
476 ScrnInfoPtr scrn = xf86_crtc->scrn;
477 ScreenPtr pScreen = scrn->pScreen;
478 RADEONInfoPtr info = RADEONPTR(scrn);
479 RegionRec remaining;
480 RegionPtr sync_region = NULL;
481 BoxRec extents;
482 Bool force;
483 GCPtr gc;
484
485 if (RegionNil(last_region))
486 return;
487
488 RegionNull(&remaining);
489 RegionSubtract(&remaining, last_region, new_region);
490 if (RegionNil(&remaining))
491 goto uninit;
492
493 extents = *RegionExtents(&remaining);
494 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents))
495 goto uninit;
496
497 if (xf86_crtc->driverIsPerformingTransform) {
498 sync_region = transform_region(&remaining,
499 &xf86_crtc->f_framebuffer_to_crtc,
500 dst->width, dst->height);
501 } else {
502 sync_region = RegionDuplicate(&remaining);
503 RegionTranslate(sync_region, -xf86_crtc->x, -xf86_crtc->y);
504 }
505
506 force = info->accel_state->force;
507 info->accel_state->force = TRUE;
508
509 gc = GetScratchGC(dst->depth, pScreen);
510 if (gc) {
511 gc->funcs->ChangeClip(gc, CT_REGION, sync_region, 0);
512 ValidateGC(dst, gc);
513 sync_region = NULL;
514 gc->ops->CopyArea(src, dst, gc, 0, 0, dst->width, dst->height, 0, 0);
515 FreeScratchGC(gc);
516 }
517
518 info->accel_state->force = force;
519
520 uninit:
521 if (sync_region)
522 RegionDestroy(sync_region);
523 RegionUninit(&remaining);
524 }
525
526 static void
radeon_scanout_flip_abort(xf86CrtcPtr crtc,void * event_data)527 radeon_scanout_flip_abort(xf86CrtcPtr crtc, void *event_data)
528 {
529 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn);
530 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
531 struct drmmode_fb *fb = event_data;
532
533 drmmode_crtc->scanout_update_pending = 0;
534
535 if (drmmode_crtc->flip_pending == fb) {
536 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending,
537 NULL);
538 }
539 }
540
541 static void
radeon_scanout_flip_handler(xf86CrtcPtr crtc,uint32_t msc,uint64_t usec,void * event_data)542 radeon_scanout_flip_handler(xf86CrtcPtr crtc, uint32_t msc, uint64_t usec,
543 void *event_data)
544 {
545 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn);
546 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
547 struct drmmode_fb *fb = event_data;
548
549 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, fb);
550 radeon_scanout_flip_abort(crtc, event_data);
551 }
552
553
554 static RegionPtr
dirty_region(PixmapDirtyUpdatePtr dirty)555 dirty_region(PixmapDirtyUpdatePtr dirty)
556 {
557 RegionPtr damageregion = DamageRegion(dirty->damage);
558 RegionPtr dstregion;
559
560 #ifdef HAS_DIRTYTRACKING_ROTATION
561 if (dirty->rotation != RR_Rotate_0) {
562 dstregion = transform_region(damageregion,
563 &dirty->f_inverse,
564 dirty->slave_dst->drawable.width,
565 dirty->slave_dst->drawable.height);
566 } else
567 #endif
568 {
569 RegionRec pixregion;
570
571 dstregion = RegionDuplicate(damageregion);
572 RegionTranslate(dstregion, -dirty->x, -dirty->y);
573 PixmapRegionInit(&pixregion, dirty->slave_dst);
574 RegionIntersect(dstregion, dstregion, &pixregion);
575 RegionUninit(&pixregion);
576 }
577
578 return dstregion;
579 }
580
581 static void
redisplay_dirty(PixmapDirtyUpdatePtr dirty,RegionPtr region)582 redisplay_dirty(PixmapDirtyUpdatePtr dirty, RegionPtr region)
583 {
584 ScrnInfoPtr src_scrn =
585 xf86ScreenToScrn(radeon_dirty_src_drawable(dirty)->pScreen);
586
587 if (RegionNil(region))
588 goto out;
589
590 if (dirty->slave_dst->master_pixmap)
591 DamageRegionAppend(&dirty->slave_dst->drawable, region);
592
593 #ifdef HAS_DIRTYTRACKING_ROTATION
594 PixmapSyncDirtyHelper(dirty);
595 #else
596 PixmapSyncDirtyHelper(dirty, region);
597 #endif
598
599 radeon_cs_flush_indirect(src_scrn);
600 if (dirty->slave_dst->master_pixmap)
601 DamageRegionProcessPending(&dirty->slave_dst->drawable);
602
603 out:
604 DamageEmpty(dirty->damage);
605 }
606
607 static void
radeon_prime_scanout_update_abort(xf86CrtcPtr crtc,void * event_data)608 radeon_prime_scanout_update_abort(xf86CrtcPtr crtc, void *event_data)
609 {
610 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
611
612 drmmode_crtc->scanout_update_pending = 0;
613 }
614
615 void
radeon_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty)616 radeon_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty)
617 {
618 ScreenPtr master_screen = radeon_dirty_master(dirty);
619 PixmapDirtyUpdatePtr ent;
620 RegionPtr region;
621
622 xorg_list_for_each_entry(ent, &master_screen->pixmap_dirty_list, ent) {
623 if (!radeon_dirty_src_equals(dirty, ent->slave_dst))
624 continue;
625
626 region = dirty_region(ent);
627 redisplay_dirty(ent, region);
628 RegionDestroy(region);
629 }
630 }
631
632
633 #if HAS_SYNC_SHARED_PIXMAP
634
635 static Bool
master_has_sync_shared_pixmap(ScrnInfoPtr scrn,PixmapDirtyUpdatePtr dirty)636 master_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty)
637 {
638 ScreenPtr master_screen = radeon_dirty_master(dirty);
639
640 return !!master_screen->SyncSharedPixmap;
641 }
642
643 static Bool
slave_has_sync_shared_pixmap(ScrnInfoPtr scrn,PixmapDirtyUpdatePtr dirty)644 slave_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty)
645 {
646 ScreenPtr slave_screen = dirty->slave_dst->drawable.pScreen;
647
648 return !!slave_screen->SyncSharedPixmap;
649 }
650
651 static void
call_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty)652 call_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty)
653 {
654 ScreenPtr master_screen = radeon_dirty_master(dirty);
655
656 master_screen->SyncSharedPixmap(dirty);
657 }
658
659 #else /* !HAS_SYNC_SHARED_PIXMAP */
660
661 static Bool
master_has_sync_shared_pixmap(ScrnInfoPtr scrn,PixmapDirtyUpdatePtr dirty)662 master_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty)
663 {
664 ScrnInfoPtr master_scrn = xf86ScreenToScrn(radeon_dirty_master(dirty));
665
666 return master_scrn->driverName == scrn->driverName;
667 }
668
669 static Bool
slave_has_sync_shared_pixmap(ScrnInfoPtr scrn,PixmapDirtyUpdatePtr dirty)670 slave_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty)
671 {
672 ScrnInfoPtr slave_scrn = xf86ScreenToScrn(dirty->slave_dst->drawable.pScreen);
673
674 return slave_scrn->driverName == scrn->driverName;
675 }
676
677 static void
call_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty)678 call_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty)
679 {
680 radeon_sync_shared_pixmap(dirty);
681 }
682
683 #endif /* HAS_SYNC_SHARED_PIXMAPS */
684
685
686 static xf86CrtcPtr
radeon_prime_dirty_to_crtc(PixmapDirtyUpdatePtr dirty)687 radeon_prime_dirty_to_crtc(PixmapDirtyUpdatePtr dirty)
688 {
689 ScreenPtr screen = dirty->slave_dst->drawable.pScreen;
690 ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
691 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn);
692 int c;
693
694 /* Find the CRTC which is scanning out from this slave pixmap */
695 for (c = 0; c < xf86_config->num_crtc; c++) {
696 xf86CrtcPtr xf86_crtc = xf86_config->crtc[c];
697 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
698
699 if (radeon_dirty_src_equals(dirty, drmmode_crtc->prime_scanout_pixmap))
700 return xf86_crtc;
701 }
702
703 return NULL;
704 }
705
706 static Bool
radeon_prime_scanout_do_update(xf86CrtcPtr crtc,unsigned scanout_id)707 radeon_prime_scanout_do_update(xf86CrtcPtr crtc, unsigned scanout_id)
708 {
709 ScrnInfoPtr scrn = crtc->scrn;
710 ScreenPtr screen = scrn->pScreen;
711 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
712 PixmapDirtyUpdatePtr dirty;
713 Bool ret = FALSE;
714
715 xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list, ent) {
716 if (radeon_dirty_src_equals(dirty, drmmode_crtc->prime_scanout_pixmap)) {
717 RegionPtr region;
718
719 if (master_has_sync_shared_pixmap(scrn, dirty))
720 call_sync_shared_pixmap(dirty);
721
722 region = dirty_region(dirty);
723 if (RegionNil(region))
724 goto destroy;
725
726 if (drmmode_crtc->tear_free) {
727 RegionTranslate(region, crtc->x, crtc->y);
728 radeon_sync_scanout_pixmaps(crtc, region, scanout_id);
729 radeon_cs_flush_indirect(scrn);
730 RegionCopy(&drmmode_crtc->scanout_last_region, region);
731 RegionTranslate(region, -crtc->x, -crtc->y);
732 dirty->slave_dst = drmmode_crtc->scanout[scanout_id].pixmap;
733 }
734
735 redisplay_dirty(dirty, region);
736 ret = TRUE;
737 destroy:
738 RegionDestroy(region);
739 break;
740 }
741 }
742
743 return ret;
744 }
745
746 static void
radeon_prime_scanout_update_handler(xf86CrtcPtr crtc,uint32_t frame,uint64_t usec,void * event_data)747 radeon_prime_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, uint64_t usec,
748 void *event_data)
749 {
750 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
751
752 radeon_prime_scanout_do_update(crtc, 0);
753 drmmode_crtc->scanout_update_pending = 0;
754 }
755
756 static void
radeon_prime_scanout_update(PixmapDirtyUpdatePtr dirty)757 radeon_prime_scanout_update(PixmapDirtyUpdatePtr dirty)
758 {
759 ScreenPtr screen = dirty->slave_dst->drawable.pScreen;
760 ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
761 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
762 xf86CrtcPtr xf86_crtc = radeon_prime_dirty_to_crtc(dirty);
763 drmmode_crtc_private_ptr drmmode_crtc;
764 uintptr_t drm_queue_seq;
765
766 if (!xf86_crtc || !xf86_crtc->enabled)
767 return;
768
769 drmmode_crtc = xf86_crtc->driver_private;
770 if (drmmode_crtc->scanout_update_pending ||
771 !drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap ||
772 drmmode_crtc->dpms_mode != DPMSModeOn)
773 return;
774
775 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc,
776 RADEON_DRM_QUEUE_CLIENT_DEFAULT,
777 RADEON_DRM_QUEUE_ID_DEFAULT, NULL,
778 radeon_prime_scanout_update_handler,
779 radeon_prime_scanout_update_abort,
780 FALSE);
781 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) {
782 xf86DrvMsg(scrn->scrnIndex, X_WARNING,
783 "radeon_drm_queue_alloc failed for PRIME update\n");
784 radeon_prime_scanout_update_handler(xf86_crtc, 0, 0, NULL);
785 return;
786 }
787
788 drmmode_crtc->scanout_update_pending = drm_queue_seq;
789
790 if (!drmmode_wait_vblank(xf86_crtc, DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT,
791 1, drm_queue_seq, NULL, NULL)) {
792 if (!(drmmode_crtc->scanout_status & DRMMODE_SCANOUT_VBLANK_FAILED)) {
793 xf86DrvMsg(scrn->scrnIndex, X_WARNING,
794 "drmmode_wait_vblank failed for PRIME update: %s\n",
795 strerror(errno));
796 drmmode_crtc->scanout_status |= DRMMODE_SCANOUT_VBLANK_FAILED;
797 }
798
799 drmmode_crtc->drmmode->event_context.vblank_handler(pRADEONEnt->fd,
800 0, 0, 0,
801 (void*)drm_queue_seq);
802 drmmode_crtc->wait_flip_nesting_level++;
803 radeon_drm_queue_handle_deferred(xf86_crtc);
804 return;
805 }
806
807 if (drmmode_crtc->scanout_status ==
808 (DRMMODE_SCANOUT_FLIP_FAILED | DRMMODE_SCANOUT_VBLANK_FAILED)) {
809 /* The page flip and vblank ioctls failed before, but the vblank
810 * ioctl is working again, so we can try re-enabling TearFree
811 */
812 xf86_crtc->funcs->set_mode_major(xf86_crtc, &xf86_crtc->mode,
813 xf86_crtc->rotation,
814 xf86_crtc->x, xf86_crtc->y);
815 }
816
817 drmmode_crtc->scanout_status &= ~DRMMODE_SCANOUT_VBLANK_FAILED;
818 }
819
820 static void
radeon_prime_scanout_flip(PixmapDirtyUpdatePtr ent)821 radeon_prime_scanout_flip(PixmapDirtyUpdatePtr ent)
822 {
823 ScreenPtr screen = ent->slave_dst->drawable.pScreen;
824 ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
825 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
826 xf86CrtcPtr crtc = radeon_prime_dirty_to_crtc(ent);
827 drmmode_crtc_private_ptr drmmode_crtc;
828 uintptr_t drm_queue_seq;
829 unsigned scanout_id;
830 struct drmmode_fb *fb;
831
832 if (!crtc || !crtc->enabled)
833 return;
834
835 drmmode_crtc = crtc->driver_private;
836 scanout_id = drmmode_crtc->scanout_id ^ 1;
837 if (drmmode_crtc->scanout_update_pending ||
838 !drmmode_crtc->scanout[scanout_id].pixmap ||
839 drmmode_crtc->dpms_mode != DPMSModeOn)
840 return;
841
842 if (!radeon_prime_scanout_do_update(crtc, scanout_id))
843 return;
844
845 fb = radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap);
846 if (!fb) {
847 xf86DrvMsg(scrn->scrnIndex, X_WARNING,
848 "Failed to get FB for PRIME flip.\n");
849 return;
850 }
851
852 drm_queue_seq = radeon_drm_queue_alloc(crtc,
853 RADEON_DRM_QUEUE_CLIENT_DEFAULT,
854 RADEON_DRM_QUEUE_ID_DEFAULT, fb,
855 radeon_scanout_flip_handler,
856 radeon_scanout_flip_abort, TRUE);
857 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) {
858 xf86DrvMsg(scrn->scrnIndex, X_WARNING,
859 "Allocating DRM event queue entry failed for PRIME flip.\n");
860 return;
861 }
862
863 if (drmmode_page_flip_target_relative(pRADEONEnt, drmmode_crtc,
864 fb->handle, 0, drm_queue_seq, 1)
865 != 0) {
866 if (!(drmmode_crtc->scanout_status & DRMMODE_SCANOUT_FLIP_FAILED)) {
867 xf86DrvMsg(scrn->scrnIndex, X_WARNING,
868 "flip queue failed in %s: %s, TearFree inactive\n",
869 __func__, strerror(errno));
870 drmmode_crtc->scanout_status |= DRMMODE_SCANOUT_FLIP_FAILED;
871 }
872
873 radeon_drm_abort_entry(drm_queue_seq);
874 return;
875 }
876
877 if (drmmode_crtc->scanout_status & DRMMODE_SCANOUT_FLIP_FAILED) {
878 xf86DrvMsg(scrn->scrnIndex, X_INFO, "TearFree active again\n");
879 drmmode_crtc->scanout_status &= ~DRMMODE_SCANOUT_FLIP_FAILED;
880 }
881
882 drmmode_crtc->scanout_id = scanout_id;
883 drmmode_crtc->scanout_update_pending = drm_queue_seq;
884 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, fb);
885 }
886
887 static void
radeon_dirty_update(ScrnInfoPtr scrn)888 radeon_dirty_update(ScrnInfoPtr scrn)
889 {
890 ScreenPtr screen = scrn->pScreen;
891 PixmapDirtyUpdatePtr ent;
892 RegionPtr region;
893
894 xorg_list_for_each_entry(ent, &screen->pixmap_dirty_list, ent) {
895 if (screen->isGPU) {
896 PixmapDirtyUpdatePtr region_ent = ent;
897
898 if (master_has_sync_shared_pixmap(scrn, ent)) {
899 ScreenPtr master_screen = radeon_dirty_master(ent);
900
901 xorg_list_for_each_entry(region_ent, &master_screen->pixmap_dirty_list, ent) {
902 if (radeon_dirty_src_equals(ent, region_ent->slave_dst))
903 break;
904 }
905 }
906
907 region = dirty_region(region_ent);
908
909 if (RegionNotEmpty(region)) {
910 xf86CrtcPtr crtc = radeon_prime_dirty_to_crtc(ent);
911 drmmode_crtc_private_ptr drmmode_crtc = NULL;
912
913 if (crtc)
914 drmmode_crtc = crtc->driver_private;
915
916 if (drmmode_crtc && drmmode_crtc->tear_free)
917 radeon_prime_scanout_flip(ent);
918 else
919 radeon_prime_scanout_update(ent);
920 } else {
921 DamageEmpty(region_ent->damage);
922 }
923
924 RegionDestroy(region);
925 } else {
926 if (slave_has_sync_shared_pixmap(scrn, ent))
927 continue;
928
929 region = dirty_region(ent);
930 redisplay_dirty(ent, region);
931 RegionDestroy(region);
932 }
933 }
934 }
935
936
937 Bool
radeon_scanout_do_update(xf86CrtcPtr xf86_crtc,int scanout_id,PixmapPtr src_pix,BoxRec extents)938 radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int scanout_id,
939 PixmapPtr src_pix, BoxRec extents)
940 {
941 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
942 RegionRec region = { .extents = extents, .data = NULL };
943 ScrnInfoPtr scrn = xf86_crtc->scrn;
944 ScreenPtr pScreen = scrn->pScreen;
945 RADEONInfoPtr info = RADEONPTR(scrn);
946 DrawablePtr pDraw;
947 Bool force;
948
949 if (!xf86_crtc->enabled ||
950 !drmmode_crtc->scanout[scanout_id].pixmap ||
951 extents.x1 >= extents.x2 || extents.y1 >= extents.y2)
952 return FALSE;
953
954 pDraw = &drmmode_crtc->scanout[scanout_id].pixmap->drawable;
955 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents))
956 return FALSE;
957
958 if (drmmode_crtc->tear_free) {
959 radeon_sync_scanout_pixmaps(xf86_crtc, ®ion, scanout_id);
960 RegionCopy(&drmmode_crtc->scanout_last_region, ®ion);
961 }
962
963 force = info->accel_state->force;
964 info->accel_state->force = TRUE;
965
966 if (xf86_crtc->driverIsPerformingTransform) {
967 SourceValidateProcPtr SourceValidate = pScreen->SourceValidate;
968 PictFormatPtr format = PictureWindowFormat(pScreen->root);
969 int error;
970 PicturePtr src, dst;
971
972 src = CreatePicture(None, &src_pix->drawable, format, 0L, NULL,
973 serverClient, &error);
974 if (!src) {
975 ErrorF("Failed to create source picture for transformed scanout "
976 "update\n");
977 goto out;
978 }
979
980 dst = CreatePicture(None, pDraw, format, 0L, NULL, serverClient, &error);
981 if (!dst) {
982 ErrorF("Failed to create destination picture for transformed scanout "
983 "update\n");
984 goto free_src;
985 }
986
987 error = SetPictureTransform(src, &xf86_crtc->crtc_to_framebuffer);
988 if (error) {
989 ErrorF("SetPictureTransform failed for transformed scanout "
990 "update\n");
991 goto free_dst;
992 }
993
994 if (xf86_crtc->filter)
995 SetPicturePictFilter(src, xf86_crtc->filter, xf86_crtc->params,
996 xf86_crtc->nparams);
997
998 pScreen->SourceValidate = NULL;
999 CompositePicture(PictOpSrc,
1000 src, NULL, dst,
1001 extents.x1, extents.y1, 0, 0, extents.x1,
1002 extents.y1, extents.x2 - extents.x1,
1003 extents.y2 - extents.y1);
1004 pScreen->SourceValidate = SourceValidate;
1005
1006 free_dst:
1007 FreePicture(dst, None);
1008 free_src:
1009 FreePicture(src, None);
1010 } else
1011 out:
1012 {
1013 GCPtr gc = GetScratchGC(pDraw->depth, pScreen);
1014
1015 ValidateGC(pDraw, gc);
1016 (*gc->ops->CopyArea)(&src_pix->drawable, pDraw, gc,
1017 xf86_crtc->x + extents.x1, xf86_crtc->y + extents.y1,
1018 extents.x2 - extents.x1, extents.y2 - extents.y1,
1019 extents.x1, extents.y1);
1020 FreeScratchGC(gc);
1021 }
1022
1023 info->accel_state->force = force;
1024
1025 return TRUE;
1026 }
1027
1028 static void
radeon_scanout_update_abort(xf86CrtcPtr crtc,void * event_data)1029 radeon_scanout_update_abort(xf86CrtcPtr crtc, void *event_data)
1030 {
1031 drmmode_crtc_private_ptr drmmode_crtc = event_data;
1032
1033 drmmode_crtc->scanout_update_pending = 0;
1034 }
1035
1036 static void
radeon_scanout_update_handler(xf86CrtcPtr crtc,uint32_t frame,uint64_t usec,void * event_data)1037 radeon_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, uint64_t usec,
1038 void *event_data)
1039 {
1040 drmmode_crtc_private_ptr drmmode_crtc = event_data;
1041 ScreenPtr screen = crtc->scrn->pScreen;
1042 RegionPtr region = DamageRegion(drmmode_crtc->scanout_damage);
1043
1044 if (crtc->enabled &&
1045 !drmmode_crtc->flip_pending &&
1046 drmmode_crtc->dpms_mode == DPMSModeOn) {
1047 if (radeon_scanout_do_update(crtc, drmmode_crtc->scanout_id,
1048 screen->GetWindowPixmap(screen->root),
1049 region->extents)) {
1050 radeon_cs_flush_indirect(crtc->scrn);
1051 RegionEmpty(region);
1052 }
1053 }
1054
1055 radeon_scanout_update_abort(crtc, event_data);
1056 }
1057
1058 static void
radeon_scanout_update(xf86CrtcPtr xf86_crtc)1059 radeon_scanout_update(xf86CrtcPtr xf86_crtc)
1060 {
1061 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
1062 ScrnInfoPtr scrn = xf86_crtc->scrn;
1063 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
1064 uintptr_t drm_queue_seq;
1065 DamagePtr pDamage;
1066 RegionPtr pRegion;
1067 BoxRec extents;
1068
1069 if (!xf86_crtc->enabled ||
1070 drmmode_crtc->scanout_update_pending ||
1071 drmmode_crtc->flip_pending ||
1072 drmmode_crtc->dpms_mode != DPMSModeOn)
1073 return;
1074
1075 pDamage = drmmode_crtc->scanout_damage;
1076 if (!pDamage)
1077 return;
1078
1079 pRegion = DamageRegion(pDamage);
1080 if (!RegionNotEmpty(pRegion))
1081 return;
1082
1083 extents = *RegionExtents(pRegion);
1084 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents)) {
1085 RegionEmpty(pRegion);
1086 return;
1087 }
1088
1089 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc,
1090 RADEON_DRM_QUEUE_CLIENT_DEFAULT,
1091 RADEON_DRM_QUEUE_ID_DEFAULT,
1092 drmmode_crtc,
1093 radeon_scanout_update_handler,
1094 radeon_scanout_update_abort,
1095 FALSE);
1096 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) {
1097 xf86DrvMsg(scrn->scrnIndex, X_WARNING,
1098 "radeon_drm_queue_alloc failed for scanout update\n");
1099 radeon_scanout_update_handler(xf86_crtc, 0, 0, drmmode_crtc);
1100 return;
1101 }
1102
1103 drmmode_crtc->scanout_update_pending = drm_queue_seq;
1104
1105 if (!drmmode_wait_vblank(xf86_crtc, DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT,
1106 1, drm_queue_seq, NULL, NULL)) {
1107 if (!(drmmode_crtc->scanout_status & DRMMODE_SCANOUT_VBLANK_FAILED)) {
1108 xf86DrvMsg(scrn->scrnIndex, X_WARNING,
1109 "drmmode_wait_vblank failed for scanout update: %s\n",
1110 strerror(errno));
1111 drmmode_crtc->scanout_status |= DRMMODE_SCANOUT_VBLANK_FAILED;
1112 }
1113
1114 drmmode_crtc->drmmode->event_context.vblank_handler(pRADEONEnt->fd,
1115 0, 0, 0,
1116 (void*)drm_queue_seq);
1117 drmmode_crtc->wait_flip_nesting_level++;
1118 radeon_drm_queue_handle_deferred(xf86_crtc);
1119 return;
1120 }
1121
1122 if (drmmode_crtc->scanout_status ==
1123 (DRMMODE_SCANOUT_FLIP_FAILED | DRMMODE_SCANOUT_VBLANK_FAILED)) {
1124 /* The page flip and vblank ioctls failed before, but the vblank
1125 * ioctl is working again, so we can try re-enabling TearFree
1126 */
1127 xf86_crtc->funcs->set_mode_major(xf86_crtc, &xf86_crtc->mode,
1128 xf86_crtc->rotation,
1129 xf86_crtc->x, xf86_crtc->y);
1130 }
1131
1132 drmmode_crtc->scanout_status &= ~DRMMODE_SCANOUT_VBLANK_FAILED;
1133 }
1134
1135 static void
radeon_scanout_flip(ScreenPtr pScreen,RADEONInfoPtr info,xf86CrtcPtr xf86_crtc)1136 radeon_scanout_flip(ScreenPtr pScreen, RADEONInfoPtr info,
1137 xf86CrtcPtr xf86_crtc)
1138 {
1139 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
1140 RegionPtr region = DamageRegion(drmmode_crtc->scanout_damage);
1141 ScrnInfoPtr scrn = xf86_crtc->scrn;
1142 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
1143 uintptr_t drm_queue_seq;
1144 unsigned scanout_id;
1145 struct drmmode_fb *fb;
1146
1147 if (drmmode_crtc->scanout_update_pending ||
1148 drmmode_crtc->flip_pending ||
1149 drmmode_crtc->dpms_mode != DPMSModeOn)
1150 return;
1151
1152 scanout_id = drmmode_crtc->scanout_id ^ 1;
1153 if (!radeon_scanout_do_update(xf86_crtc, scanout_id,
1154 pScreen->GetWindowPixmap(pScreen->root),
1155 region->extents))
1156 return;
1157
1158 radeon_cs_flush_indirect(scrn);
1159 RegionEmpty(region);
1160
1161 fb = radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap);
1162 if (!fb) {
1163 xf86DrvMsg(scrn->scrnIndex, X_WARNING,
1164 "Failed to get FB for scanout flip.\n");
1165 return;
1166 }
1167
1168 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc,
1169 RADEON_DRM_QUEUE_CLIENT_DEFAULT,
1170 RADEON_DRM_QUEUE_ID_DEFAULT, fb,
1171 radeon_scanout_flip_handler,
1172 radeon_scanout_flip_abort, TRUE);
1173 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) {
1174 xf86DrvMsg(scrn->scrnIndex, X_WARNING,
1175 "Allocating DRM event queue entry failed.\n");
1176 return;
1177 }
1178
1179 if (drmmode_page_flip_target_relative(pRADEONEnt, drmmode_crtc,
1180 fb->handle, 0, drm_queue_seq, 1)
1181 != 0) {
1182 if (!(drmmode_crtc->scanout_status & DRMMODE_SCANOUT_FLIP_FAILED)) {
1183 xf86DrvMsg(scrn->scrnIndex, X_WARNING,
1184 "flip queue failed in %s: %s, TearFree inactive\n",
1185 __func__, strerror(errno));
1186 drmmode_crtc->scanout_status |= DRMMODE_SCANOUT_FLIP_FAILED;
1187 }
1188
1189 radeon_drm_abort_entry(drm_queue_seq);
1190 RegionCopy(DamageRegion(drmmode_crtc->scanout_damage),
1191 &drmmode_crtc->scanout_last_region);
1192 RegionEmpty(&drmmode_crtc->scanout_last_region);
1193 radeon_scanout_update(xf86_crtc);
1194 drmmode_crtc_scanout_destroy(drmmode_crtc->drmmode,
1195 &drmmode_crtc->scanout[scanout_id]);
1196 drmmode_crtc->tear_free = FALSE;
1197 return;
1198 }
1199
1200 if (drmmode_crtc->scanout_status & DRMMODE_SCANOUT_FLIP_FAILED) {
1201 xf86DrvMsg(scrn->scrnIndex, X_INFO, "TearFree active again\n");
1202 drmmode_crtc->scanout_status &= ~DRMMODE_SCANOUT_FLIP_FAILED;
1203 }
1204
1205 drmmode_crtc->scanout_id = scanout_id;
1206 drmmode_crtc->scanout_update_pending = drm_queue_seq;
1207 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, fb);
1208 }
1209
RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS_DECL)1210 static void RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS_DECL)
1211 {
1212 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
1213 RADEONInfoPtr info = RADEONPTR(pScrn);
1214 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1215 int c;
1216
1217 pScreen->BlockHandler = info->BlockHandler;
1218 (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS);
1219 pScreen->BlockHandler = RADEONBlockHandler_KMS;
1220
1221 if (!xf86ScreenToScrn(radeon_master_screen(pScreen))->vtSema)
1222 return;
1223
1224 if (!pScreen->isGPU)
1225 {
1226 for (c = 0; c < xf86_config->num_crtc; c++) {
1227 xf86CrtcPtr crtc = xf86_config->crtc[c];
1228 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
1229
1230 if (drmmode_crtc->rotate.pixmap)
1231 continue;
1232
1233 if (drmmode_crtc->tear_free)
1234 radeon_scanout_flip(pScreen, info, crtc);
1235 else if (drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap)
1236 radeon_scanout_update(crtc);
1237 }
1238 }
1239
1240 radeon_cs_flush_indirect(pScrn);
1241
1242 radeon_dirty_update(pScrn);
1243 }
1244
RADEONIsFastFBWorking(ScrnInfoPtr pScrn)1245 static Bool RADEONIsFastFBWorking(ScrnInfoPtr pScrn)
1246 {
1247 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
1248 struct drm_radeon_info ginfo;
1249 int r;
1250 uint32_t tmp = 0;
1251
1252 memset(&ginfo, 0, sizeof(ginfo));
1253 ginfo.request = RADEON_INFO_FASTFB_WORKING;
1254 ginfo.value = (uintptr_t)&tmp;
1255 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
1256 if (r) {
1257 return FALSE;
1258 }
1259 if (tmp == 1)
1260 return TRUE;
1261 return FALSE;
1262 }
1263
RADEONIsFusionGARTWorking(ScrnInfoPtr pScrn)1264 static Bool RADEONIsFusionGARTWorking(ScrnInfoPtr pScrn)
1265 {
1266 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
1267 struct drm_radeon_info ginfo;
1268 int r;
1269 uint32_t tmp;
1270
1271 memset(&ginfo, 0, sizeof(ginfo));
1272 ginfo.request = RADEON_INFO_FUSION_GART_WORKING;
1273 ginfo.value = (uintptr_t)&tmp;
1274 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
1275 if (r) {
1276 return FALSE;
1277 }
1278 if (tmp == 1)
1279 return TRUE;
1280 return FALSE;
1281 }
1282
RADEONIsAccelWorking(ScrnInfoPtr pScrn)1283 static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn)
1284 {
1285 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
1286 RADEONInfoPtr info = RADEONPTR(pScrn);
1287 struct drm_radeon_info ginfo;
1288 int r;
1289 uint32_t tmp;
1290
1291 memset(&ginfo, 0, sizeof(ginfo));
1292 if (info->dri2.pKernelDRMVersion->version_minor >= 5)
1293 ginfo.request = RADEON_INFO_ACCEL_WORKING2;
1294 else
1295 ginfo.request = RADEON_INFO_ACCEL_WORKING;
1296 ginfo.value = (uintptr_t)&tmp;
1297 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
1298 if (r) {
1299 /* If kernel is too old before 2.6.32 than assume accel is working */
1300 if (r == -EINVAL) {
1301 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Kernel too old missing accel "
1302 "information, assuming accel is working\n");
1303 return TRUE;
1304 }
1305 return FALSE;
1306 }
1307 if (info->ChipFamily == CHIP_FAMILY_HAWAII) {
1308 if (tmp == 2 || tmp == 3)
1309 return TRUE;
1310 } else if (tmp) {
1311 return TRUE;
1312 }
1313 return FALSE;
1314 }
1315
1316 /* This is called by RADEONPreInit to set up the default visual */
RADEONPreInitVisual(ScrnInfoPtr pScrn)1317 static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn)
1318 {
1319 RADEONInfoPtr info = RADEONPTR(pScrn);
1320
1321 if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb))
1322 return FALSE;
1323
1324 switch (pScrn->depth) {
1325 case 8:
1326 case 15:
1327 case 16:
1328 case 24:
1329 case 30:
1330 break;
1331
1332 default:
1333 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1334 "Given depth (%d) is not supported by %s driver\n",
1335 pScrn->depth, RADEON_DRIVER_NAME);
1336 return FALSE;
1337 }
1338
1339 xf86PrintDepthBpp(pScrn);
1340
1341 info->pix24bpp = xf86GetBppFromDepth(pScrn,
1342 pScrn->depth);
1343 info->pixel_bytes = pScrn->bitsPerPixel / 8;
1344
1345 if (info->pix24bpp == 24) {
1346 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1347 "Radeon does NOT support 24bpp\n");
1348 return FALSE;
1349 }
1350
1351 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1352 "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n",
1353 pScrn->depth,
1354 info->pixel_bytes,
1355 info->pixel_bytes > 1 ? "s" : "",
1356 info->pix24bpp);
1357
1358 if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE;
1359
1360 if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) {
1361 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1362 "Default visual (%s) is not supported at depth %d\n",
1363 xf86GetVisualName(pScrn->defaultVisual), pScrn->depth);
1364 return FALSE;
1365 }
1366 return TRUE;
1367 }
1368
1369 /* This is called by RADEONPreInit to handle all color weight issues */
RADEONPreInitWeight(ScrnInfoPtr pScrn)1370 static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn)
1371 {
1372 RADEONInfoPtr info = RADEONPTR(pScrn);
1373
1374 /* Save flag for 6 bit DAC to use for
1375 setting CRTC registers. Otherwise use
1376 an 8 bit DAC, even if xf86SetWeight sets
1377 pScrn->rgbBits to some value other than
1378 8. */
1379 info->dac6bits = FALSE;
1380
1381 if (pScrn->depth > 8) {
1382 rgb defaultWeight = { 0, 0, 0 };
1383
1384 if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE;
1385 } else {
1386 pScrn->rgbBits = 8;
1387 }
1388
1389 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1390 "Using %d bits per RGB (%d bit DAC)\n",
1391 pScrn->rgbBits, info->dac6bits ? 6 : 8);
1392
1393 return TRUE;
1394 }
1395
RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)1396 static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
1397 {
1398 RADEONInfoPtr info = RADEONPTR(pScrn);
1399
1400 if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) {
1401 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n");
1402 return FALSE;
1403 }
1404
1405 /* Check whether direct mapping is used for fast fb access*/
1406 if (RADEONIsFastFBWorking(pScrn)) {
1407 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct mapping of fb aperture is enabled for fast fb access.\n");
1408 info->is_fast_fb = TRUE;
1409 }
1410
1411 if (!xf86ReturnOptValBool(info->Options, OPTION_ACCEL, TRUE) ||
1412 (!RADEONIsAccelWorking(pScrn))) {
1413 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1414 "GPU accel disabled or not working, using shadowfb for KMS\n");
1415 shadowfb:
1416 if (!xf86LoadSubModule(pScrn, "shadow"))
1417 return FALSE;
1418
1419 info->r600_shadow_fb = TRUE;
1420 return TRUE;
1421 }
1422
1423 #ifdef DRI2
1424 info->dri2.available = !!xf86LoadSubModule(pScrn, "dri2");
1425 #endif
1426
1427 if (radeon_glamor_pre_init(pScrn))
1428 return TRUE;
1429
1430 if (info->ChipFamily >= CHIP_FAMILY_TAHITI) {
1431 goto shadowfb;
1432 } else if (info->ChipFamily == CHIP_FAMILY_PALM) {
1433 info->accel_state->allowHWDFS = RADEONIsFusionGARTWorking(pScrn);
1434 } else
1435 info->accel_state->allowHWDFS = TRUE;
1436
1437 if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
1438 (info->ChipFamily == CHIP_FAMILY_RS200) ||
1439 (info->ChipFamily == CHIP_FAMILY_RS300) ||
1440 (info->ChipFamily == CHIP_FAMILY_RS400) ||
1441 (info->ChipFamily == CHIP_FAMILY_RS480) ||
1442 (info->ChipFamily == CHIP_FAMILY_RS600) ||
1443 (info->ChipFamily == CHIP_FAMILY_RS690) ||
1444 (info->ChipFamily == CHIP_FAMILY_RS740))
1445 info->accel_state->has_tcl = FALSE;
1446 else {
1447 info->accel_state->has_tcl = TRUE;
1448 }
1449
1450 {
1451 int errmaj = 0, errmin = 0;
1452 info->exaReq.majorversion = EXA_VERSION_MAJOR;
1453 info->exaReq.minorversion = EXA_VERSION_MINOR;
1454 if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL,
1455 &info->exaReq, &errmaj, &errmin)) {
1456 LoaderErrorMsg(NULL, "exa", errmaj, errmin);
1457 return FALSE;
1458 }
1459 }
1460
1461 return TRUE;
1462 }
1463
RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn)1464 static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn)
1465 {
1466 RADEONInfoPtr info = RADEONPTR(pScrn);
1467 int i;
1468
1469 info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo);
1470 pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset);
1471 if (!pScrn->chipset) {
1472 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1473 "ChipID 0x%04x is not recognized\n", info->Chipset);
1474 return FALSE;
1475 }
1476
1477 if (info->Chipset < 0) {
1478 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1479 "Chipset \"%s\" is not recognized\n", pScrn->chipset);
1480 return FALSE;
1481 }
1482 xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
1483 "Chipset: \"%s\" (ChipID = 0x%04x)\n",
1484 pScrn->chipset,
1485 info->Chipset);
1486
1487 for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) {
1488 if (info->Chipset == RADEONCards[i].pci_device_id) {
1489 RADEONCardInfo *card = &RADEONCards[i];
1490 info->ChipFamily = card->chip_family;
1491 break;
1492 }
1493 }
1494
1495 #ifdef RENDER
1496 info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL,
1497 info->Chipset != PCI_CHIP_RN50_515E &&
1498 info->Chipset != PCI_CHIP_RN50_5969);
1499 #endif
1500 return TRUE;
1501 }
1502
radeon_get_drm_master_fd(ScrnInfoPtr pScrn)1503 static int radeon_get_drm_master_fd(ScrnInfoPtr pScrn)
1504 {
1505 RADEONInfoPtr info = RADEONPTR(pScrn);
1506 #ifdef XF86_PDEV_SERVER_FD
1507 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
1508 #endif
1509 struct pci_device *dev = info->PciInfo;
1510 char *busid;
1511 int fd;
1512
1513 #ifdef XF86_PDEV_SERVER_FD
1514 if (pRADEONEnt->platform_dev) {
1515 fd = xf86_get_platform_device_int_attrib(pRADEONEnt->platform_dev,
1516 ODEV_ATTRIB_FD, -1);
1517 if (fd != -1)
1518 return fd;
1519 }
1520 #endif
1521
1522 XNFasprintf(&busid, "pci:%04x:%02x:%02x.%d",
1523 dev->domain, dev->bus, dev->dev, dev->func);
1524
1525 fd = kldload("radeon");
1526 if (fd == -1 && errno != EEXIST) {
1527 fd = kldload("radeonkms");
1528 if (fd == -1 && errno != EEXIST) {
1529 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1530 "[drm] Failed to load kernel module for %s: %s\n",
1531 busid, strerror(errno));
1532 free(busid);
1533 return fd;
1534 }
1535 }
1536
1537 fd = drmOpen(NULL, busid);
1538 if (fd == -1)
1539 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1540 "[drm] Failed to open DRM device for %s: %s\n",
1541 busid, strerror(errno));
1542
1543 free(busid);
1544 return fd;
1545 }
1546
radeon_open_drm_master(ScrnInfoPtr pScrn)1547 static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
1548 {
1549 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
1550 drmSetVersion sv;
1551 int err;
1552
1553 if (pRADEONEnt->fd) {
1554 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1555 " reusing fd for second head\n");
1556 pRADEONEnt->fd_ref++;
1557 return TRUE;
1558 }
1559
1560 pRADEONEnt->fd = radeon_get_drm_master_fd(pScrn);
1561 if (pRADEONEnt->fd == -1)
1562 return FALSE;
1563
1564 /* Check that what we opened was a master or a master-capable FD,
1565 * by setting the version of the interface we'll use to talk to it.
1566 * (see DRIOpenDRMMaster() in DRI1)
1567 */
1568 sv.drm_di_major = 1;
1569 sv.drm_di_minor = 1;
1570 sv.drm_dd_major = -1;
1571 sv.drm_dd_minor = -1;
1572 err = drmSetInterfaceVersion(pRADEONEnt->fd, &sv);
1573 if (err != 0) {
1574 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1575 "[drm] failed to set drm interface version.\n");
1576 drmClose(pRADEONEnt->fd);
1577 pRADEONEnt->fd = -1;
1578
1579 return FALSE;
1580 }
1581
1582 pRADEONEnt->fd_ref = 1;
1583 return TRUE;
1584 }
1585
r600_get_tile_config(ScrnInfoPtr pScrn)1586 static Bool r600_get_tile_config(ScrnInfoPtr pScrn)
1587 {
1588 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
1589 RADEONInfoPtr info = RADEONPTR(pScrn);
1590 struct drm_radeon_info ginfo;
1591 int r;
1592 uint32_t tmp;
1593
1594 if (info->ChipFamily < CHIP_FAMILY_R600)
1595 return FALSE;
1596
1597 memset(&ginfo, 0, sizeof(ginfo));
1598 ginfo.request = RADEON_INFO_TILING_CONFIG;
1599 ginfo.value = (uintptr_t)&tmp;
1600 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
1601 if (r)
1602 return FALSE;
1603
1604 info->tile_config = tmp;
1605 info->r7xx_bank_op = 0;
1606 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
1607 if (info->dri2.pKernelDRMVersion->version_minor >= 7) {
1608 switch (info->tile_config & 0xf) {
1609 case 0:
1610 info->num_channels = 1;
1611 break;
1612 case 1:
1613 info->num_channels = 2;
1614 break;
1615 case 2:
1616 info->num_channels = 4;
1617 break;
1618 case 3:
1619 info->num_channels = 8;
1620 break;
1621 default:
1622 return FALSE;
1623 }
1624
1625 switch((info->tile_config & 0xf0) >> 4) {
1626 case 0:
1627 info->num_banks = 4;
1628 break;
1629 case 1:
1630 info->num_banks = 8;
1631 break;
1632 case 2:
1633 info->num_banks = 16;
1634 break;
1635 default:
1636 return FALSE;
1637 }
1638
1639 switch ((info->tile_config & 0xf00) >> 8) {
1640 case 0:
1641 info->group_bytes = 256;
1642 break;
1643 case 1:
1644 info->group_bytes = 512;
1645 break;
1646 default:
1647 return FALSE;
1648 }
1649 } else
1650 return FALSE;
1651 } else {
1652 switch((info->tile_config & 0xe) >> 1) {
1653 case 0:
1654 info->num_channels = 1;
1655 break;
1656 case 1:
1657 info->num_channels = 2;
1658 break;
1659 case 2:
1660 info->num_channels = 4;
1661 break;
1662 case 3:
1663 info->num_channels = 8;
1664 break;
1665 default:
1666 return FALSE;
1667 }
1668 switch((info->tile_config & 0x30) >> 4) {
1669 case 0:
1670 info->num_banks = 4;
1671 break;
1672 case 1:
1673 info->num_banks = 8;
1674 break;
1675 default:
1676 return FALSE;
1677 }
1678 switch((info->tile_config & 0xc0) >> 6) {
1679 case 0:
1680 info->group_bytes = 256;
1681 break;
1682 case 1:
1683 info->group_bytes = 512;
1684 break;
1685 default:
1686 return FALSE;
1687 }
1688 }
1689
1690 info->have_tiling_info = TRUE;
1691 return TRUE;
1692 }
1693
RADEONSetupCapabilities(ScrnInfoPtr pScrn)1694 static void RADEONSetupCapabilities(ScrnInfoPtr pScrn)
1695 {
1696 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
1697 RADEONInfoPtr info = RADEONPTR(pScrn);
1698 uint64_t value;
1699 int ret;
1700
1701 pScrn->capabilities = 0;
1702
1703 /* PRIME offloading requires acceleration */
1704 if (info->r600_shadow_fb)
1705 return;
1706
1707 ret = drmGetCap(pRADEONEnt->fd, DRM_CAP_PRIME, &value);
1708 if (ret == 0) {
1709 if (value & DRM_PRIME_CAP_EXPORT)
1710 pScrn->capabilities |= RR_Capability_SourceOutput | RR_Capability_SourceOffload;
1711 if (value & DRM_PRIME_CAP_IMPORT) {
1712 pScrn->capabilities |= RR_Capability_SinkOffload;
1713 if (info->drmmode.count_crtcs)
1714 pScrn->capabilities |= RR_Capability_SinkOutput;
1715 }
1716 }
1717 }
1718
1719 /* When the root window is created, initialize the screen contents from
1720 * console if -background none was specified on the command line
1721 */
RADEONCreateWindow_oneshot(WindowPtr pWin)1722 static Bool RADEONCreateWindow_oneshot(WindowPtr pWin)
1723 {
1724 ScreenPtr pScreen = pWin->drawable.pScreen;
1725 ScrnInfoPtr pScrn;
1726 RADEONInfoPtr info;
1727 Bool ret;
1728
1729 if (pWin != pScreen->root)
1730 ErrorF("%s called for non-root window %p\n", __func__, pWin);
1731
1732 pScrn = xf86ScreenToScrn(pScreen);
1733 info = RADEONPTR(pScrn);
1734 pScreen->CreateWindow = info->CreateWindow;
1735 ret = pScreen->CreateWindow(pWin);
1736
1737 if (ret)
1738 drmmode_copy_fb(pScrn, &info->drmmode);
1739
1740 return ret;
1741 }
1742
1743 /* When the root window is mapped, set the initial modes */
RADEONWindowExposures_oneshot(WindowPtr pWin,RegionPtr pRegion,RegionPtr pBSRegion)1744 void RADEONWindowExposures_oneshot(WindowPtr pWin, RegionPtr pRegion
1745 #if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,16,99,901,0)
1746 , RegionPtr pBSRegion
1747 #endif
1748 )
1749 {
1750 ScreenPtr pScreen = pWin->drawable.pScreen;
1751 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
1752 RADEONInfoPtr info = RADEONPTR(pScrn);
1753
1754 if (pWin != pScreen->root)
1755 ErrorF("%s called for non-root window %p\n", __func__, pWin);
1756
1757 pScreen->WindowExposures = info->WindowExposures;
1758 #if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,16,99,901,0)
1759 pScreen->WindowExposures(pWin, pRegion, pBSRegion);
1760 #else
1761 pScreen->WindowExposures(pWin, pRegion);
1762 #endif
1763
1764 radeon_finish(pScrn, info->front_buffer);
1765 drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE);
1766 }
1767
RADEONPreInit_KMS(ScrnInfoPtr pScrn,int flags)1768 Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
1769 {
1770 RADEONInfoPtr info;
1771 RADEONEntPtr pRADEONEnt;
1772 MessageType from;
1773 Gamma zeros = { 0.0, 0.0, 0.0 };
1774 uint32_t tiling = 0;
1775 int cpp;
1776
1777 if (flags & PROBE_DETECT)
1778 return TRUE;
1779
1780 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1781 "RADEONPreInit_KMS\n");
1782 if (pScrn->numEntities != 1) return FALSE;
1783
1784 pRADEONEnt = xf86GetEntityPrivate(pScrn->entityList[0],
1785 getRADEONEntityIndex())->ptr;
1786 if (pRADEONEnt->num_scrns == ARRAY_SIZE(pRADEONEnt->scrn)) {
1787 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1788 "Only up to %u Zaphod instances supported\n",
1789 (unsigned)ARRAY_SIZE(pRADEONEnt->scrn));
1790 return FALSE;
1791 }
1792
1793 if (!RADEONGetRec(pScrn)) return FALSE;
1794
1795 info = RADEONPTR(pScrn);
1796
1797 info->instance_id = pRADEONEnt->num_scrns++;
1798 pRADEONEnt->scrn[info->instance_id] = pScrn;
1799
1800 info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]);
1801 if (info->pEnt->location.type != BUS_PCI
1802 #ifdef XSERVER_PLATFORM_BUS
1803 && info->pEnt->location.type != BUS_PLATFORM
1804 #endif
1805 )
1806 return FALSE;
1807
1808 if (xf86IsEntityShared(pScrn->entityList[0]) &&
1809 info->instance_id == 0) {
1810 xf86SetPrimInitDone(pScrn->entityList[0]);
1811 }
1812
1813 info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
1814 pScrn->monitor = pScrn->confScreen->monitor;
1815
1816 if (!RADEONPreInitVisual(pScrn))
1817 return FALSE;
1818
1819 xf86CollectOptions(pScrn, NULL);
1820 if (!(info->Options = malloc(sizeof(RADEONOptions_KMS))))
1821 return FALSE;
1822
1823 memcpy(info->Options, RADEONOptions_KMS, sizeof(RADEONOptions_KMS));
1824 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
1825
1826 if (!RADEONPreInitWeight(pScrn))
1827 return FALSE;
1828
1829 if (!RADEONPreInitChipType_KMS(pScrn))
1830 return FALSE;
1831
1832 if (radeon_open_drm_master(pScrn) == FALSE) {
1833 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
1834 return FALSE;
1835 }
1836
1837 info->dri2.available = FALSE;
1838 info->dri2.enabled = FALSE;
1839 info->dri2.pKernelDRMVersion = drmGetVersion(pRADEONEnt->fd);
1840 if (!info->dri2.pKernelDRMVersion) {
1841 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1842 "RADEONDRIGetVersion failed to get the DRM version\n");
1843 return FALSE;
1844 }
1845
1846 /* Get ScreenInit function */
1847 if (!xf86LoadSubModule(pScrn, "fb"))
1848 return FALSE;
1849
1850 if (!RADEONPreInitAccel_KMS(pScrn))
1851 return FALSE;
1852
1853 /* Depth 30 only supported since Linux 3.16 / kms driver minor version 39 */
1854 if (pScrn->depth == 30 && info->dri2.pKernelDRMVersion->version_minor < 39) {
1855 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
1856 "Depth 30 is not supported. Kernel too old. Needs Linux 3.16+\n");
1857 return FALSE;
1858 }
1859
1860 radeon_drm_queue_init(pScrn);
1861
1862 info->allowColorTiling2D = FALSE;
1863
1864 /* don't enable tiling if accel is not enabled */
1865 if (!info->r600_shadow_fb) {
1866 Bool colorTilingDefault =
1867 info->ChipFamily >= CHIP_FAMILY_R300 &&
1868 /* this check could be removed sometime after a big mesa release
1869 * with proper bit, in the meantime you need to set tiling option in
1870 * xorg configuration files
1871 */
1872 info->ChipFamily <= CHIP_FAMILY_MULLINS &&
1873 !info->is_fast_fb;
1874
1875 /* 2D color tiling */
1876 if (info->ChipFamily >= CHIP_FAMILY_R600) {
1877 info->allowColorTiling2D = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING_2D,
1878 info->ChipFamily <= CHIP_FAMILY_MULLINS);
1879 }
1880
1881 if (info->ChipFamily >= CHIP_FAMILY_R600) {
1882 /* set default group bytes, overridden by kernel info below */
1883 info->group_bytes = 256;
1884 info->have_tiling_info = FALSE;
1885 if (info->dri2.pKernelDRMVersion->version_minor >= 6) {
1886 if (r600_get_tile_config(pScrn)) {
1887 info->allowColorTiling = xf86ReturnOptValBool(info->Options,
1888 OPTION_COLOR_TILING, colorTilingDefault);
1889 if (!info->use_glamor) {
1890 /* need working DFS for tiling */
1891 if (info->ChipFamily == CHIP_FAMILY_PALM &&
1892 !info->accel_state->allowHWDFS)
1893 info->allowColorTiling = FALSE;
1894 }
1895 } else
1896 info->allowColorTiling = FALSE;
1897 } else
1898 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1899 "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or newer\n");
1900 } else
1901 info->allowColorTiling = xf86ReturnOptValBool(info->Options,
1902 OPTION_COLOR_TILING, colorTilingDefault);
1903 } else
1904 info->allowColorTiling = FALSE;
1905
1906 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1907 "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis");
1908 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1909 "KMS Color Tiling 2D: %sabled\n", info->allowColorTiling2D ? "en" : "dis");
1910
1911 #if USE_GLAMOR
1912 if (info->use_glamor) {
1913 info->shadow_primary = xf86ReturnOptValBool(info->Options,
1914 OPTION_SHADOW_PRIMARY, FALSE);
1915
1916 if (info->shadow_primary)
1917 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ShadowPrimary enabled\n");
1918 }
1919 #endif
1920
1921 if (!info->r600_shadow_fb) {
1922 from = X_DEFAULT;
1923
1924 info->tear_free = 2;
1925 if (xf86GetOptValBool(info->Options, OPTION_TEAR_FREE,
1926 &info->tear_free))
1927 from = X_CONFIG;
1928 xf86DrvMsg(pScrn->scrnIndex, from, "TearFree property default: %s\n",
1929 info->tear_free == 2 ? "auto" : (info->tear_free ? "on" : "off"));
1930 }
1931
1932 if (!pScrn->is_gpu) {
1933 if (info->dri2.pKernelDRMVersion->version_minor >= 8) {
1934 info->allowPageFlip = xf86ReturnOptValBool(info->Options,
1935 OPTION_PAGE_FLIP, TRUE);
1936
1937 if (info->shadow_primary) {
1938 xf86DrvMsg(pScrn->scrnIndex,
1939 info->allowPageFlip ? X_WARNING : X_DEFAULT,
1940 "KMS Pageflipping: disabled%s\n",
1941 info->allowPageFlip ?
1942 " because of ShadowPrimary" : "");
1943 info->allowPageFlip = FALSE;
1944 } else {
1945 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1946 "KMS Pageflipping: %sabled\n",
1947 info->allowPageFlip ? "en" : "dis");
1948 }
1949 }
1950
1951 if (!info->use_glamor) {
1952 info->swapBuffersWait =
1953 xf86ReturnOptValBool(info->Options, OPTION_SWAPBUFFERS_WAIT, TRUE);
1954 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
1955 "SwapBuffers wait for vsync: %sabled\n",
1956 info->swapBuffersWait ? "en" : "dis");
1957 }
1958 }
1959
1960 if (xf86ReturnOptValBool(info->Options, OPTION_DELETE_DP12, FALSE)) {
1961 info->drmmode.delete_dp_12_displays = TRUE;
1962 }
1963
1964 if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) {
1965 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
1966 return FALSE;
1967 }
1968
1969 RADEONSetupCapabilities(pScrn);
1970
1971 if (info->drmmode.count_crtcs == 1)
1972 pRADEONEnt->HasCRTC2 = FALSE;
1973 else
1974 pRADEONEnt->HasCRTC2 = TRUE;
1975
1976
1977 /* fix up cloning on rn50 cards
1978 * since they only have one crtc sometimes the xserver doesn't assign
1979 * a crtc to one of the outputs even though both outputs have common modes
1980 * which results in only one monitor being enabled. Assign a crtc here so
1981 * that both outputs light up.
1982 */
1983 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
1984 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1985 int i;
1986
1987 for (i = 0; i < xf86_config->num_output; i++) {
1988 xf86OutputPtr output = xf86_config->output[i];
1989
1990 /* XXX: double check crtc mode */
1991 if (output->probed_modes && !output->crtc)
1992 output->crtc = xf86_config->crtc[0];
1993 }
1994 }
1995
1996 /* set cursor size */
1997 if (info->ChipFamily >= CHIP_FAMILY_BONAIRE) {
1998 info->cursor_w = CURSOR_WIDTH_CIK;
1999 info->cursor_h = CURSOR_HEIGHT_CIK;
2000 } else {
2001 info->cursor_w = CURSOR_WIDTH;
2002 info->cursor_h = CURSOR_HEIGHT;
2003 }
2004
2005 {
2006 struct drm_radeon_gem_info mminfo;
2007
2008 if (!drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
2009 {
2010 info->vram_size = mminfo.vram_visible;
2011 info->gart_size = mminfo.gart_size;
2012 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2013 "mem size init: gart size :%llx vram size: s:%llx visible:%llx\n",
2014 (unsigned long long)mminfo.gart_size,
2015 (unsigned long long)mminfo.vram_size,
2016 (unsigned long long)mminfo.vram_visible);
2017 }
2018 }
2019
2020 if (!info->use_glamor) {
2021 info->exa_pixmaps = xf86ReturnOptValBool(info->Options,
2022 OPTION_EXA_PIXMAPS,
2023 (info->vram_size > (32 * 1024 * 1024) &&
2024 info->RenderAccel &&
2025 !info->is_fast_fb));
2026 if (info->exa_pixmaps)
2027 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2028 "EXA: Driver will allow EXA pixmaps in VRAM\n");
2029 else
2030 xf86DrvMsg(pScrn->scrnIndex, X_INFO,
2031 "EXA: Driver will not allow EXA pixmaps in VRAM\n");
2032 }
2033
2034 /* no tiled scanout on r6xx+ yet */
2035 if (info->allowColorTiling) {
2036 if (info->ChipFamily >= CHIP_FAMILY_R600)
2037 tiling |= RADEON_TILING_MICRO;
2038 else
2039 tiling |= RADEON_TILING_MACRO;
2040 }
2041 cpp = pScrn->bitsPerPixel / 8;
2042 pScrn->displayWidth =
2043 RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling));
2044
2045 /* Set display resolution */
2046 xf86SetDpi(pScrn, 0, 0);
2047
2048 if (!xf86SetGamma(pScrn, zeros)) return FALSE;
2049
2050 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
2051 if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE;
2052 }
2053
2054 if (!pScrn->modes
2055 #ifdef XSERVER_PLATFORM_BUS
2056 && !pScrn->is_gpu
2057 #endif
2058 ) {
2059 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n");
2060 return FALSE;
2061 }
2062
2063 return TRUE;
2064 }
2065
RADEONCursorInit_KMS(ScreenPtr pScreen)2066 static Bool RADEONCursorInit_KMS(ScreenPtr pScreen)
2067 {
2068 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
2069 RADEONInfoPtr info = RADEONPTR(pScrn);
2070
2071 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
2072 "Initializing Cursor\n");
2073
2074 /* Set Silken Mouse */
2075 xf86SetSilkenMouse(pScreen);
2076
2077 /* Cursor setup */
2078 miDCInitialize(pScreen, xf86GetPointerScreenFuncs());
2079
2080 if (info->allowPageFlip) {
2081 miPointerScreenPtr PointPriv =
2082 dixLookupPrivate(&pScreen->devPrivates, miPointerScreenKey);
2083
2084 if (!dixRegisterScreenPrivateKey(&radeon_device_private_key, pScreen,
2085 PRIVATE_DEVICE,
2086 sizeof(struct radeon_device_priv))) {
2087 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "dixRegisterScreenPrivateKey failed\n");
2088 return FALSE;
2089 }
2090
2091 info->SpriteFuncs = PointPriv->spriteFuncs;
2092 PointPriv->spriteFuncs = &drmmode_sprite_funcs;
2093 }
2094
2095 if (xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE))
2096 return TRUE;
2097
2098 if (!xf86_cursors_init(pScreen, info->cursor_w, info->cursor_h,
2099 HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
2100 HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
2101 HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 |
2102 HARDWARE_CURSOR_UPDATE_UNHIDDEN |
2103 HARDWARE_CURSOR_ARGB)) {
2104 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "xf86_cursors_init failed\n");
2105 return FALSE;
2106 }
2107
2108 return TRUE;
2109 }
2110
2111 void
RADEONBlank(ScrnInfoPtr pScrn)2112 RADEONBlank(ScrnInfoPtr pScrn)
2113 {
2114 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
2115 xf86OutputPtr output;
2116 xf86CrtcPtr crtc;
2117 int o, c;
2118
2119 for (c = 0; c < xf86_config->num_crtc; c++) {
2120 crtc = xf86_config->crtc[c];
2121 for (o = 0; o < xf86_config->num_output; o++) {
2122 output = xf86_config->output[o];
2123 if (output->crtc != crtc)
2124 continue;
2125
2126 output->funcs->dpms(output, DPMSModeOff);
2127 }
2128 crtc->funcs->dpms(crtc, DPMSModeOff);
2129 }
2130 }
2131
2132 void
RADEONUnblank(ScrnInfoPtr pScrn)2133 RADEONUnblank(ScrnInfoPtr pScrn)
2134 {
2135 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
2136 xf86OutputPtr output;
2137 xf86CrtcPtr crtc;
2138 int o, c;
2139 for (c = 0; c < xf86_config->num_crtc; c++) {
2140 crtc = xf86_config->crtc[c];
2141 if(!crtc->enabled)
2142 continue;
2143 crtc->funcs->dpms(crtc, DPMSModeOn);
2144 for (o = 0; o < xf86_config->num_output; o++) {
2145 output = xf86_config->output[o];
2146 if (output->crtc != crtc)
2147 continue;
2148 output->funcs->dpms(output, DPMSModeOn);
2149 }
2150 }
2151 }
2152
2153
RADEONSaveScreen_KMS(ScreenPtr pScreen,int mode)2154 static Bool RADEONSaveScreen_KMS(ScreenPtr pScreen, int mode)
2155 {
2156 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
2157 Bool unblank;
2158
2159 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
2160 "RADEONSaveScreen(%d)\n", mode);
2161
2162 unblank = xf86IsUnblank(mode);
2163 if (unblank) SetTimeSinceLastInputEvent();
2164
2165 if (pScrn && pScrn->vtSema) {
2166 if (unblank)
2167 RADEONUnblank(pScrn);
2168 else
2169 RADEONBlank(pScrn);
2170 }
2171 return TRUE;
2172 }
2173
radeon_set_drm_master(ScrnInfoPtr pScrn)2174 static Bool radeon_set_drm_master(ScrnInfoPtr pScrn)
2175 {
2176 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
2177 int err;
2178
2179 #ifdef XF86_PDEV_SERVER_FD
2180 if (pRADEONEnt->platform_dev &&
2181 (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD))
2182 return TRUE;
2183 #endif
2184
2185 err = drmSetMaster(pRADEONEnt->fd);
2186 if (err)
2187 ErrorF("Unable to retrieve master\n");
2188
2189 return err == 0;
2190 }
2191
radeon_drop_drm_master(ScrnInfoPtr pScrn)2192 static void radeon_drop_drm_master(ScrnInfoPtr pScrn)
2193 {
2194 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
2195
2196 #ifdef XF86_PDEV_SERVER_FD
2197 if (pRADEONEnt->platform_dev &&
2198 (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD))
2199 return;
2200 #endif
2201
2202 drmDropMaster(pRADEONEnt->fd);
2203 }
2204
2205 /* Called at the end of each server generation. Restore the original
2206 * text mode, unmap video memory, and unwrap and call the saved
2207 * CloseScreen function.
2208 */
RADEONCloseScreen_KMS(ScreenPtr pScreen)2209 static Bool RADEONCloseScreen_KMS(ScreenPtr pScreen)
2210 {
2211 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
2212 RADEONInfoPtr info = RADEONPTR(pScrn);
2213 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
2214
2215 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
2216 "RADEONCloseScreen\n");
2217
2218 /* Clear mask of assigned crtc's in this generation */
2219 pRADEONEnt->assigned_crtcs = 0;
2220
2221 drmmode_uevent_fini(pScrn, &info->drmmode);
2222 radeon_drm_queue_close(pScrn);
2223 radeon_cs_flush_indirect(pScrn);
2224
2225 if (info->callback_event_type != -1) {
2226 DeleteCallback(&EventCallback, radeon_event_callback, pScrn);
2227 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn);
2228 }
2229
2230 if (info->accel_state->exa) {
2231 exaDriverFini(pScreen);
2232 free(info->accel_state->exa);
2233 info->accel_state->exa = NULL;
2234 }
2235
2236 radeon_sync_close(pScreen);
2237
2238 if (info->accel_state->use_vbos)
2239 radeon_vbo_free_lists(pScrn);
2240
2241 radeon_drop_drm_master(pScrn);
2242
2243 drmmode_fini(pScrn, &info->drmmode);
2244 if (info->dri2.enabled)
2245 radeon_dri2_close_screen(pScreen);
2246
2247 radeon_glamor_fini(pScreen);
2248
2249 pScrn->vtSema = FALSE;
2250 xf86ClearPrimInitDone(info->pEnt->index);
2251
2252 if (info->allowPageFlip) {
2253 miPointerScreenPtr PointPriv =
2254 dixLookupPrivate(&pScreen->devPrivates, miPointerScreenKey);
2255
2256 if (PointPriv->spriteFuncs == &drmmode_sprite_funcs)
2257 PointPriv->spriteFuncs = info->SpriteFuncs;
2258 }
2259
2260 pScreen->BlockHandler = info->BlockHandler;
2261 pScreen->CloseScreen = info->CloseScreen;
2262 return pScreen->CloseScreen(pScreen);
2263 }
2264
2265
RADEONFreeScreen_KMS(ScrnInfoPtr pScrn)2266 void RADEONFreeScreen_KMS(ScrnInfoPtr pScrn)
2267 {
2268 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
2269 "RADEONFreeScreen\n");
2270
2271 RADEONFreeRec(pScrn);
2272 }
2273
RADEONScreenInit_KMS(ScreenPtr pScreen,int argc,char ** argv)2274 Bool RADEONScreenInit_KMS(ScreenPtr pScreen, int argc, char **argv)
2275 {
2276 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
2277 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
2278 RADEONInfoPtr info = RADEONPTR(pScrn);
2279 int subPixelOrder = SubPixelUnknown;
2280 MessageType from;
2281 Bool value;
2282 int driLevel;
2283 const char *s;
2284 void *front_ptr;
2285
2286 pScrn->fbOffset = 0;
2287
2288 miClearVisualTypes();
2289 if (!miSetVisualTypes(pScrn->depth,
2290 miGetDefaultVisualMask(pScrn->depth),
2291 pScrn->rgbBits,
2292 pScrn->defaultVisual)) return FALSE;
2293 miSetPixmapDepths ();
2294
2295 if (!radeon_set_drm_master(pScrn))
2296 return FALSE;
2297
2298 info->directRenderingEnabled = FALSE;
2299 if (info->r600_shadow_fb == FALSE)
2300 info->directRenderingEnabled = radeon_dri2_screen_init(pScreen);
2301
2302 if (info->ChipFamily >= CHIP_FAMILY_R600) {
2303 info->surf_man = radeon_surface_manager_new(pRADEONEnt->fd);
2304
2305 if (!info->surf_man) {
2306 xf86DrvMsg(pScreen->myNum, X_ERROR,
2307 "Failed to initialize surface manager\n");
2308 return FALSE;
2309 }
2310 }
2311
2312 if (!info->bufmgr)
2313 info->bufmgr = radeon_bo_manager_gem_ctor(pRADEONEnt->fd);
2314 if (!info->bufmgr) {
2315 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2316 "failed to initialise GEM buffer manager");
2317 return FALSE;
2318 }
2319 drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr);
2320
2321 if (!info->csm)
2322 info->csm = radeon_cs_manager_gem_ctor(pRADEONEnt->fd);
2323 if (!info->csm) {
2324 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2325 "failed to initialise command submission manager");
2326 return FALSE;
2327 }
2328
2329 if (!info->cs)
2330 info->cs = radeon_cs_create(info->csm, RADEON_BUFFER_SIZE/4);
2331 if (!info->cs) {
2332 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2333 "failed to initialise command submission buffer");
2334 return FALSE;
2335 }
2336
2337 radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_GTT, info->gart_size);
2338 radeon_cs_space_set_flush(info->cs, (void(*)(void *))radeon_cs_flush_indirect, pScrn);
2339
2340 if (!radeon_setup_kernel_mem(pScreen)) {
2341 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "radeon_setup_kernel_mem failed\n");
2342 return FALSE;
2343 }
2344
2345 if (!(info->front_buffer->flags & RADEON_BO_FLAGS_GBM))
2346 front_ptr = info->front_buffer->bo.radeon->ptr;
2347 else
2348 front_ptr = NULL;
2349
2350 if (info->r600_shadow_fb) {
2351 info->fb_shadow = calloc(1,
2352 pScrn->displayWidth * pScrn->virtualY *
2353 ((pScrn->bitsPerPixel + 7) >> 3));
2354 if (!info->fb_shadow) {
2355 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2356 "Failed to allocate shadow framebuffer\n");
2357 return FALSE;
2358 } else {
2359 if (!fbScreenInit(pScreen, info->fb_shadow,
2360 pScrn->virtualX, pScrn->virtualY,
2361 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
2362 pScrn->bitsPerPixel))
2363 return FALSE;
2364 }
2365 }
2366
2367 if (info->r600_shadow_fb == FALSE) {
2368 /* Init fb layer */
2369 if (!fbScreenInit(pScreen, front_ptr,
2370 pScrn->virtualX, pScrn->virtualY,
2371 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
2372 pScrn->bitsPerPixel))
2373 return FALSE;
2374 }
2375
2376 xf86SetBlackWhitePixels(pScreen);
2377
2378 if (pScrn->bitsPerPixel > 8) {
2379 VisualPtr visual;
2380
2381 visual = pScreen->visuals + pScreen->numVisuals;
2382 while (--visual >= pScreen->visuals) {
2383 if ((visual->class | DynamicClass) == DirectColor) {
2384 visual->offsetRed = pScrn->offset.red;
2385 visual->offsetGreen = pScrn->offset.green;
2386 visual->offsetBlue = pScrn->offset.blue;
2387 visual->redMask = pScrn->mask.red;
2388 visual->greenMask = pScrn->mask.green;
2389 visual->blueMask = pScrn->mask.blue;
2390 }
2391 }
2392 }
2393
2394 /* Must be after RGB order fixed */
2395 fbPictureInit (pScreen, 0, 0);
2396
2397 #ifdef RENDER
2398 if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) {
2399 if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB;
2400 else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR;
2401 else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone;
2402 PictureSetSubpixelOrder (pScreen, subPixelOrder);
2403 }
2404 #endif
2405
2406 if (!pScreen->isGPU) {
2407 if (xorgGetVersion() >= XORG_VERSION_NUMERIC(1,18,3,0,0))
2408 value = info->use_glamor;
2409 else
2410 value = FALSE;
2411 from = X_DEFAULT;
2412
2413 if (!info->r600_shadow_fb) {
2414 if (xf86GetOptValBool(info->Options, OPTION_DRI3, &value))
2415 from = X_CONFIG;
2416
2417 if (xf86GetOptValInteger(info->Options, OPTION_DRI, &driLevel) &&
2418 (driLevel == 2 || driLevel == 3)) {
2419 from = X_CONFIG;
2420 value = driLevel == 3;
2421 }
2422 }
2423
2424 if (value) {
2425 value = radeon_sync_init(pScreen) &&
2426 radeon_present_screen_init(pScreen) &&
2427 radeon_dri3_screen_init(pScreen);
2428
2429 if (!value)
2430 from = X_WARNING;
2431 }
2432
2433 xf86DrvMsg(pScrn->scrnIndex, from, "DRI3 %sabled\n", value ? "en" : "dis");
2434 }
2435
2436 pScrn->vtSema = TRUE;
2437 xf86SetBackingStore(pScreen);
2438
2439 if (info->directRenderingEnabled) {
2440 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
2441 } else {
2442 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
2443 "Direct rendering disabled\n");
2444 }
2445
2446 if (info->r600_shadow_fb) {
2447 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n");
2448 info->accelOn = FALSE;
2449 } else {
2450 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
2451 "Initializing Acceleration\n");
2452 if (RADEONAccelInit(pScreen)) {
2453 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration enabled\n");
2454 info->accelOn = TRUE;
2455 } else {
2456 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2457 "Acceleration initialization failed\n");
2458 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n");
2459 info->accelOn = FALSE;
2460 }
2461 }
2462
2463 /* Init DPMS */
2464 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
2465 "Initializing DPMS\n");
2466 xf86DPMSInit(pScreen, xf86DPMSSet, 0);
2467
2468 if (!RADEONCursorInit_KMS(pScreen))
2469 return FALSE;
2470
2471 /* DGA setup */
2472 #ifdef XFreeXDGA
2473 /* DGA is dangerous on kms as the base and framebuffer location may change:
2474 * http://lists.freedesktop.org/archives/xorg-devel/2009-September/002113.html
2475 */
2476 /* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */
2477 #endif
2478 if (info->r600_shadow_fb == FALSE && !pScreen->isGPU) {
2479 /* Init Xv */
2480 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
2481 "Initializing Xv\n");
2482 RADEONInitVideo(pScreen);
2483 }
2484
2485 if (info->r600_shadow_fb == TRUE) {
2486 if (!shadowSetup(pScreen)) {
2487 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
2488 "Shadowfb initialization failed\n");
2489 return FALSE;
2490 }
2491 }
2492 pScrn->pScreen = pScreen;
2493
2494 if (!pScreen->isGPU) {
2495 if (serverGeneration == 1 && bgNoneRoot && info->accelOn) {
2496 info->CreateWindow = pScreen->CreateWindow;
2497 pScreen->CreateWindow = RADEONCreateWindow_oneshot;
2498 }
2499 info->WindowExposures = pScreen->WindowExposures;
2500 pScreen->WindowExposures = RADEONWindowExposures_oneshot;
2501 }
2502
2503 /* Provide SaveScreen & wrap BlockHandler and CloseScreen */
2504 /* Wrap CloseScreen */
2505 info->CloseScreen = pScreen->CloseScreen;
2506 pScreen->CloseScreen = RADEONCloseScreen_KMS;
2507 pScreen->SaveScreen = RADEONSaveScreen_KMS;
2508 info->BlockHandler = pScreen->BlockHandler;
2509 pScreen->BlockHandler = RADEONBlockHandler_KMS;
2510
2511 info->CreateScreenResources = pScreen->CreateScreenResources;
2512 pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS;
2513
2514 pScreen->StartPixmapTracking = PixmapStartDirtyTracking;
2515 pScreen->StopPixmapTracking = PixmapStopDirtyTracking;
2516 #if HAS_SYNC_SHARED_PIXMAP
2517 pScreen->SyncSharedPixmap = radeon_sync_shared_pixmap;
2518 #endif
2519
2520 if (!xf86CrtcScreenInit (pScreen))
2521 return FALSE;
2522
2523 /* Wrap pointer motion to flip touch screen around */
2524 // info->PointerMoved = pScrn->PointerMoved;
2525 // pScrn->PointerMoved = RADEONPointerMoved;
2526
2527 if (!drmmode_setup_colormap(pScreen, pScrn))
2528 return FALSE;
2529
2530 /* Note unused options */
2531 if (serverGeneration == 1)
2532 xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
2533
2534 drmmode_init(pScrn, &info->drmmode);
2535
2536 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
2537 "RADEONScreenInit finished\n");
2538
2539 info->accel_state->XInited3D = FALSE;
2540 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
2541
2542 return TRUE;
2543 }
2544
RADEONEnterVT_KMS(ScrnInfoPtr pScrn)2545 Bool RADEONEnterVT_KMS(ScrnInfoPtr pScrn)
2546 {
2547 RADEONInfoPtr info = RADEONPTR(pScrn);
2548
2549 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
2550 "RADEONEnterVT_KMS\n");
2551
2552 radeon_set_drm_master(pScrn);
2553
2554 if (info->r600_shadow_fb) {
2555 int base_align = drmmode_get_base_align(pScrn, info->pixel_bytes, 0);
2556 struct radeon_bo *front_bo = radeon_bo_open(info->bufmgr, 0,
2557 pScrn->displayWidth *
2558 info->pixel_bytes *
2559 pScrn->virtualY,
2560 base_align,
2561 RADEON_GEM_DOMAIN_VRAM, 0);
2562
2563 if (front_bo) {
2564 if (radeon_bo_map(front_bo, 1) == 0) {
2565 memset(front_bo->ptr, 0, front_bo->size);
2566 radeon_bo_unref(info->front_buffer->bo.radeon);
2567 info->front_buffer->bo.radeon = front_bo;
2568 } else {
2569 radeon_bo_unref(front_bo);
2570 front_bo = NULL;
2571 }
2572 }
2573
2574 if (!front_bo) {
2575 xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
2576 "Failed to allocate new scanout BO after VT switch, "
2577 "other DRM masters may see screen contents\n");
2578 }
2579 }
2580
2581 info->accel_state->XInited3D = FALSE;
2582 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
2583
2584 pScrn->vtSema = TRUE;
2585
2586 if (!drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE))
2587 return FALSE;
2588
2589 return TRUE;
2590 }
2591
2592 static
cleanup_black_fb(OsTimerPtr timer,CARD32 now,pointer data)2593 CARD32 cleanup_black_fb(OsTimerPtr timer, CARD32 now, pointer data)
2594 {
2595 ScreenPtr screen = data;
2596 ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
2597 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
2598 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn);
2599 int c;
2600
2601 if (xf86ScreenToScrn(radeon_master_screen(screen))->vtSema)
2602 return 0;
2603
2604 /* Unreference the all-black FB created by RADEONLeaveVT_KMS. After
2605 * this, there should be no FB left created by this driver.
2606 */
2607 for (c = 0; c < xf86_config->num_crtc; c++) {
2608 drmmode_crtc_private_ptr drmmode_crtc =
2609 xf86_config->crtc[c]->driver_private;
2610
2611 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, NULL);
2612 }
2613
2614 TimerFree(timer);
2615 return 0;
2616 }
2617
2618 static void
pixmap_unref_fb(PixmapPtr pixmap)2619 pixmap_unref_fb(PixmapPtr pixmap)
2620 {
2621 ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen);
2622 struct drmmode_fb **fb_ptr = radeon_pixmap_get_fb_ptr(pixmap);
2623 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
2624
2625 if (fb_ptr)
2626 drmmode_fb_reference(pRADEONEnt->fd, fb_ptr, NULL);
2627 }
2628
2629 static void
client_pixmap_unref_fb(void * value,XID id,void * pScreen)2630 client_pixmap_unref_fb(void *value, XID id, void *pScreen)
2631 {
2632 PixmapPtr pixmap = value;
2633
2634 if (pixmap->drawable.pScreen == pScreen)
2635 pixmap_unref_fb(pixmap);
2636 }
2637
RADEONLeaveVT_KMS(ScrnInfoPtr pScrn)2638 void RADEONLeaveVT_KMS(ScrnInfoPtr pScrn)
2639 {
2640 RADEONInfoPtr info = RADEONPTR(pScrn);
2641 ScreenPtr pScreen = pScrn->pScreen;
2642
2643 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
2644 "RADEONLeaveVT_KMS\n");
2645
2646 if (!info->r600_shadow_fb) {
2647 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
2648 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
2649 struct drmmode_scanout black_scanout = { .pixmap = NULL, .bo = NULL };
2650 xf86CrtcPtr crtc;
2651 drmmode_crtc_private_ptr drmmode_crtc;
2652 unsigned w = 0, h = 0;
2653 int i;
2654
2655 /* If we're called from CloseScreen, trying to clear the black
2656 * scanout BO will likely crash and burn
2657 */
2658 if (!pScreen->GCperDepth[0])
2659 goto hide_cursors;
2660
2661 /* Compute maximum scanout dimensions of active CRTCs */
2662 for (i = 0; i < xf86_config->num_crtc; i++) {
2663 crtc = xf86_config->crtc[i];
2664 drmmode_crtc = crtc->driver_private;
2665
2666 if (!drmmode_crtc->fb)
2667 continue;
2668
2669 w = max(w, crtc->mode.HDisplay);
2670 h = max(h, crtc->mode.VDisplay);
2671 }
2672
2673 /* Make all active CRTCs scan out from an all-black framebuffer */
2674 if (w > 0 && h > 0) {
2675 if (drmmode_crtc_scanout_create(crtc, &black_scanout, w, h)) {
2676 struct drmmode_fb *black_fb =
2677 radeon_pixmap_get_fb(black_scanout.pixmap);
2678
2679 radeon_pixmap_clear(black_scanout.pixmap);
2680 radeon_finish(pScrn, black_scanout.bo);
2681
2682 for (i = 0; i < xf86_config->num_crtc; i++) {
2683 crtc = xf86_config->crtc[i];
2684 drmmode_crtc = crtc->driver_private;
2685
2686 if (drmmode_crtc->fb) {
2687 if (black_fb) {
2688 drmmode_set_mode(crtc, black_fb, &crtc->mode, 0, 0);
2689 } else {
2690 drmModeSetCrtc(pRADEONEnt->fd,
2691 drmmode_crtc->mode_crtc->crtc_id, 0,
2692 0, 0, NULL, 0, NULL);
2693 drmmode_fb_reference(pRADEONEnt->fd,
2694 &drmmode_crtc->fb, NULL);
2695 }
2696
2697 if (pScrn->is_gpu) {
2698 if (drmmode_crtc->scanout[0].pixmap)
2699 pixmap_unref_fb(drmmode_crtc->scanout[0].pixmap);
2700 if (drmmode_crtc->scanout[1].pixmap)
2701 pixmap_unref_fb(drmmode_crtc->scanout[1].pixmap);
2702 } else {
2703 drmmode_crtc_scanout_free(crtc);
2704 }
2705 }
2706 }
2707 }
2708 }
2709
2710 xf86RotateFreeShadow(pScrn);
2711 drmmode_crtc_scanout_destroy(&info->drmmode, &black_scanout);
2712
2713 /* Unreference FBs of all pixmaps. After this, the only FB remaining
2714 * should be the all-black one being scanned out by active CRTCs
2715 */
2716 for (i = 0; i < currentMaxClients; i++) {
2717 if (i > 0 &&
2718 (!clients[i] || clients[i]->clientState != ClientStateRunning))
2719 continue;
2720
2721 FindClientResourcesByType(clients[i], RT_PIXMAP,
2722 client_pixmap_unref_fb, pScreen);
2723 }
2724
2725 pixmap_unref_fb(pScreen->GetScreenPixmap(pScreen));
2726 } else {
2727 memset(info->front_buffer->bo.radeon->ptr, 0,
2728 pScrn->displayWidth * info->pixel_bytes * pScrn->virtualY);
2729 }
2730
2731 if (pScreen->GCperDepth[0])
2732 TimerSet(NULL, 0, 1000, cleanup_black_fb, pScreen);
2733
2734 hide_cursors:
2735 xf86_hide_cursors (pScrn);
2736
2737 radeon_drop_drm_master(pScrn);
2738
2739 info->accel_state->XInited3D = FALSE;
2740 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
2741
2742 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
2743 "Ok, leaving now...\n");
2744 }
2745
2746
RADEONSwitchMode_KMS(ScrnInfoPtr pScrn,DisplayModePtr mode)2747 Bool RADEONSwitchMode_KMS(ScrnInfoPtr pScrn, DisplayModePtr mode)
2748 {
2749 Bool ret;
2750 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0);
2751 return ret;
2752
2753 }
2754
RADEONAdjustFrame_KMS(ScrnInfoPtr pScrn,int x,int y)2755 void RADEONAdjustFrame_KMS(ScrnInfoPtr pScrn, int x, int y)
2756 {
2757 RADEONInfoPtr info = RADEONPTR(pScrn);
2758 drmmode_adjust_frame(pScrn, &info->drmmode, x, y);
2759 return;
2760 }
2761
radeon_setup_kernel_mem(ScreenPtr pScreen)2762 static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
2763 {
2764 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
2765 RADEONInfoPtr info = RADEONPTR(pScrn);
2766 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
2767 int cpp = info->pixel_bytes;
2768 int pitch;
2769 uint32_t tiling_flags = 0;
2770
2771 if (info->accel_state->exa) {
2772 xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n");
2773 return FALSE;
2774 }
2775 if (!info->use_glamor && info->r600_shadow_fb == FALSE) {
2776 info->accel_state->exa = exaDriverAlloc();
2777 if (!info->accel_state->exa) {
2778 xf86DrvMsg(pScreen->myNum, X_ERROR, "exaDriverAlloc failed\n");
2779 return FALSE;
2780 }
2781 }
2782
2783 {
2784 int cursor_size;
2785 int c, i;
2786
2787 cursor_size = info->cursor_w * info->cursor_h * 4;
2788 cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE);
2789 for (c = 0; c < xf86_config->num_crtc; c++) {
2790 drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[c]->driver_private;
2791
2792 for (i = 0; i < 2; i++) {
2793 if (!drmmode_crtc->cursor_bo[i]) {
2794 drmmode_crtc->cursor_bo[i] =
2795 radeon_bo_open(info->bufmgr, 0, cursor_size, 0,
2796 RADEON_GEM_DOMAIN_VRAM, 0);
2797
2798 if (!(drmmode_crtc->cursor_bo[i])) {
2799 ErrorF("Failed to allocate cursor buffer memory\n");
2800 return FALSE;
2801 }
2802
2803 if (radeon_bo_map(drmmode_crtc->cursor_bo[i], 1))
2804 ErrorF("Failed to map cursor buffer memory\n");
2805 }
2806 }
2807 }
2808 }
2809
2810 if (!info->front_buffer) {
2811 int usage = CREATE_PIXMAP_USAGE_BACKING_PIXMAP;
2812
2813 if (info->allowColorTiling && !info->shadow_primary) {
2814 if (info->ChipFamily < CHIP_FAMILY_R600 || info->allowColorTiling2D)
2815 usage |= RADEON_CREATE_PIXMAP_TILING_MACRO;
2816 else
2817 usage |= RADEON_CREATE_PIXMAP_TILING_MICRO;
2818 }
2819
2820 info->front_buffer = radeon_alloc_pixmap_bo(pScrn, pScrn->virtualX,
2821 pScrn->virtualY,
2822 pScrn->depth,
2823 usage,
2824 pScrn->bitsPerPixel,
2825 &pitch,
2826 &info->front_surface,
2827 &tiling_flags);
2828
2829 if (info->r600_shadow_fb == TRUE) {
2830 if (radeon_bo_map(info->front_buffer->bo.radeon, 1)) {
2831 ErrorF("Failed to map cursor buffer memory\n");
2832 }
2833 }
2834
2835 if (!info->use_glamor) {
2836 #if X_BYTE_ORDER == X_BIG_ENDIAN
2837 switch (cpp) {
2838 case 4:
2839 tiling_flags |= RADEON_TILING_SWAP_32BIT;
2840 break;
2841 case 2:
2842 tiling_flags |= RADEON_TILING_SWAP_16BIT;
2843 break;
2844 }
2845 if (info->ChipFamily < CHIP_FAMILY_R600 &&
2846 info->r600_shadow_fb && tiling_flags)
2847 tiling_flags |= RADEON_TILING_SURFACE;
2848 #endif
2849 if (tiling_flags)
2850 radeon_bo_set_tiling(info->front_buffer->bo.radeon, tiling_flags, pitch);
2851 }
2852
2853 pScrn->displayWidth = pitch / cpp;
2854 }
2855
2856 pitch = pScrn->displayWidth * cpp;
2857 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n",
2858 pitch * pScrn->virtualY / 1024);
2859 radeon_kms_update_vram_limit(pScrn, pitch * pScrn->virtualY);
2860 return TRUE;
2861 }
2862
radeon_kms_update_vram_limit(ScrnInfoPtr pScrn,uint32_t new_fb_size)2863 void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size)
2864 {
2865 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
2866 RADEONInfoPtr info = RADEONPTR(pScrn);
2867 uint64_t remain_size_bytes;
2868 int c;
2869
2870 for (c = 0; c < xf86_config->num_crtc; c++) {
2871 drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[c]->driver_private;
2872
2873 if (drmmode_crtc->cursor_bo[0])
2874 new_fb_size += (64 * 4 * 64);
2875 }
2876
2877 remain_size_bytes = info->vram_size - new_fb_size;
2878 remain_size_bytes = (remain_size_bytes / 10) * 9;
2879 if (remain_size_bytes > 0xffffffff)
2880 remain_size_bytes = 0xffffffff;
2881 radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM,
2882 (uint32_t)remain_size_bytes);
2883
2884 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %uK\n",
2885 (uint32_t)remain_size_bytes / 1024);
2886 }
2887
2888 /* Used to disallow modes that are not supported by the hardware */
RADEONValidMode(ScrnInfoPtr pScrn,DisplayModePtr mode,Bool verbose,int flag)2889 ModeStatus RADEONValidMode(ScrnInfoPtr pScrn, DisplayModePtr mode,
2890 Bool verbose, int flag)
2891 {
2892 RADEONInfoPtr info = RADEONPTR(pScrn);
2893 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
2894
2895 /*
2896 * RN50 has effective maximum mode bandwidth of about 300MiB/s.
2897 * XXX should really do this for all chips by properly computing
2898 * memory bandwidth and an overhead factor.
2899 */
2900 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
2901 if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300)
2902 return MODE_BANDWIDTH;
2903 }
2904 /* There are problems with double scan mode at high clocks
2905 * They're likely related PLL and display buffer settings.
2906 * Disable these modes for now.
2907 */
2908 if (mode->Flags & V_DBLSCAN) {
2909 if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768))
2910 return MODE_CLOCK_RANGE;
2911 }
2912 return MODE_OK;
2913 }
2914