1*a9fa9459Szrj@c Copyright (C) 2009-2016 Free Software Foundation, Inc. 2*a9fa9459Szrj@c Contributed by ARM Ltd. 3*a9fa9459Szrj@c This is part of the GAS manual. 4*a9fa9459Szrj@c For copying conditions, see the file as.texinfo. 5*a9fa9459Szrj@c man end 6*a9fa9459Szrj 7*a9fa9459Szrj@ifset GENERIC 8*a9fa9459Szrj@page 9*a9fa9459Szrj@node AArch64-Dependent 10*a9fa9459Szrj@chapter AArch64 Dependent Features 11*a9fa9459Szrj@end ifset 12*a9fa9459Szrj 13*a9fa9459Szrj@ifclear GENERIC 14*a9fa9459Szrj@node Machine Dependencies 15*a9fa9459Szrj@chapter AArch64 Dependent Features 16*a9fa9459Szrj@end ifclear 17*a9fa9459Szrj 18*a9fa9459Szrj@cindex AArch64 support 19*a9fa9459Szrj@menu 20*a9fa9459Szrj* AArch64 Options:: Options 21*a9fa9459Szrj* AArch64 Extensions:: Extensions 22*a9fa9459Szrj* AArch64 Syntax:: Syntax 23*a9fa9459Szrj* AArch64 Floating Point:: Floating Point 24*a9fa9459Szrj* AArch64 Directives:: AArch64 Machine Directives 25*a9fa9459Szrj* AArch64 Opcodes:: Opcodes 26*a9fa9459Szrj* AArch64 Mapping Symbols:: Mapping Symbols 27*a9fa9459Szrj@end menu 28*a9fa9459Szrj 29*a9fa9459Szrj@node AArch64 Options 30*a9fa9459Szrj@section Options 31*a9fa9459Szrj@cindex AArch64 options (none) 32*a9fa9459Szrj@cindex options for AArch64 (none) 33*a9fa9459Szrj 34*a9fa9459Szrj@c man begin OPTIONS 35*a9fa9459Szrj@table @gcctabopt 36*a9fa9459Szrj 37*a9fa9459Szrj@cindex @option{-EB} command line option, AArch64 38*a9fa9459Szrj@item -EB 39*a9fa9459SzrjThis option specifies that the output generated by the assembler should 40*a9fa9459Szrjbe marked as being encoded for a big-endian processor. 41*a9fa9459Szrj 42*a9fa9459Szrj@cindex @option{-EL} command line option, AArch64 43*a9fa9459Szrj@item -EL 44*a9fa9459SzrjThis option specifies that the output generated by the assembler should 45*a9fa9459Szrjbe marked as being encoded for a little-endian processor. 46*a9fa9459Szrj 47*a9fa9459Szrj@cindex @option{-mabi=} command line option, AArch64 48*a9fa9459Szrj@item -mabi=@var{abi} 49*a9fa9459SzrjSpecify which ABI the source code uses. The recognized arguments 50*a9fa9459Szrjare: @code{ilp32} and @code{lp64}, which decides the generated object 51*a9fa9459Szrjfile in ELF32 and ELF64 format respectively. The default is @code{lp64}. 52*a9fa9459Szrj 53*a9fa9459Szrj@cindex @option{-mcpu=} command line option, AArch64 54*a9fa9459Szrj@item -mcpu=@var{processor}[+@var{extension}@dots{}] 55*a9fa9459SzrjThis option specifies the target processor. The assembler will issue an error 56*a9fa9459Szrjmessage if an attempt is made to assemble an instruction which will not execute 57*a9fa9459Szrjon the target processor. The following processor names are recognized: 58*a9fa9459Szrj@code{cortex-a35}, 59*a9fa9459Szrj@code{cortex-a53}, 60*a9fa9459Szrj@code{cortex-a57}, 61*a9fa9459Szrj@code{cortex-a72}, 62*a9fa9459Szrj@code{cortex-a73}, 63*a9fa9459Szrj@code{exynos-m1}, 64*a9fa9459Szrj@code{qdf24xx}, 65*a9fa9459Szrj@code{thunderx}, 66*a9fa9459Szrj@code{vulcan}, 67*a9fa9459Szrj@code{xgene1} 68*a9fa9459Szrjand 69*a9fa9459Szrj@code{xgene2}. 70*a9fa9459SzrjThe special name @code{all} may be used to allow the assembler to accept 71*a9fa9459Szrjinstructions valid for any supported processor, including all optional 72*a9fa9459Szrjextensions. 73*a9fa9459Szrj 74*a9fa9459SzrjIn addition to the basic instruction set, the assembler can be told to 75*a9fa9459Szrjaccept, or restrict, various extension mnemonics that extend the 76*a9fa9459Szrjprocessor. @xref{AArch64 Extensions}. 77*a9fa9459Szrj 78*a9fa9459SzrjIf some implementations of a particular processor can have an 79*a9fa9459Szrjextension, then then those extensions are automatically enabled. 80*a9fa9459SzrjConsequently, you will not normally have to specify any additional 81*a9fa9459Szrjextensions. 82*a9fa9459Szrj 83*a9fa9459Szrj@cindex @option{-march=} command line option, AArch64 84*a9fa9459Szrj@item -march=@var{architecture}[+@var{extension}@dots{}] 85*a9fa9459SzrjThis option specifies the target architecture. The assembler will 86*a9fa9459Szrjissue an error message if an attempt is made to assemble an 87*a9fa9459Szrjinstruction which will not execute on the target architecture. The 88*a9fa9459Szrjfollowing architecture names are recognized: @code{armv8-a}, 89*a9fa9459Szrj@code{armv8.1-a} and @code{armv8.2-a}. 90*a9fa9459Szrj 91*a9fa9459SzrjIf both @option{-mcpu} and @option{-march} are specified, the 92*a9fa9459Szrjassembler will use the setting for @option{-mcpu}. If neither are 93*a9fa9459Szrjspecified, the assembler will default to @option{-mcpu=all}. 94*a9fa9459Szrj 95*a9fa9459SzrjThe architecture option can be extended with the same instruction set 96*a9fa9459Szrjextension options as the @option{-mcpu} option. Unlike 97*a9fa9459Szrj@option{-mcpu}, extensions are not always enabled by default, 98*a9fa9459Szrj@xref{AArch64 Extensions}. 99*a9fa9459Szrj 100*a9fa9459Szrj@cindex @code{-mverbose-error} command line option, AArch64 101*a9fa9459Szrj@item -mverbose-error 102*a9fa9459SzrjThis option enables verbose error messages for AArch64 gas. This option 103*a9fa9459Szrjis enabled by default. 104*a9fa9459Szrj 105*a9fa9459Szrj@cindex @code{-mno-verbose-error} command line option, AArch64 106*a9fa9459Szrj@item -mno-verbose-error 107*a9fa9459SzrjThis option disables verbose error messages in AArch64 gas. 108*a9fa9459Szrj 109*a9fa9459Szrj@end table 110*a9fa9459Szrj@c man end 111*a9fa9459Szrj 112*a9fa9459Szrj@node AArch64 Extensions 113*a9fa9459Szrj@section Architecture Extensions 114*a9fa9459Szrj 115*a9fa9459SzrjThe table below lists the permitted architecture extensions that are 116*a9fa9459Szrjsupported by the assembler and the conditions under which they are 117*a9fa9459Szrjautomatically enabled. 118*a9fa9459Szrj 119*a9fa9459SzrjMultiple extensions may be specified, separated by a @code{+}. 120*a9fa9459SzrjExtension mnemonics may also be removed from those the assembler 121*a9fa9459Szrjaccepts. This is done by prepending @code{no} to the option that adds 122*a9fa9459Szrjthe extension. Extensions that are removed must be listed after all 123*a9fa9459Szrjextensions that have been added. 124*a9fa9459Szrj 125*a9fa9459SzrjEnabling an extension that requires other extensions will 126*a9fa9459Szrjautomatically cause those extensions to be enabled. Similarly, 127*a9fa9459Szrjdisabling an extension that is required by other extensions will 128*a9fa9459Szrjautomatically cause those extensions to be disabled. 129*a9fa9459Szrj 130*a9fa9459Szrj@multitable @columnfractions .12 .17 .17 .54 131*a9fa9459Szrj@headitem Extension @tab Minimum Architecture @tab Enabled by default 132*a9fa9459Szrj @tab Description 133*a9fa9459Szrj@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later 134*a9fa9459Szrj @tab Enable CRC instructions. 135*a9fa9459Szrj@item @code{crypto} @tab ARMv8-A @tab No 136*a9fa9459Szrj @tab Enable cryptographic extensions. This implies @code{fp} and @code{simd}. 137*a9fa9459Szrj@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later 138*a9fa9459Szrj @tab Enable floating-point extensions. 139*a9fa9459Szrj@item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later 140*a9fa9459Szrj @tab Enable ARMv8.2 16-bit floating-point support. This implies 141*a9fa9459Szrj @code{fp}. 142*a9fa9459Szrj@item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later 143*a9fa9459Szrj @tab Enable Limited Ordering Regions extensions. 144*a9fa9459Szrj@item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later 145*a9fa9459Szrj @tab Enable Large System extensions. 146*a9fa9459Szrj@item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later 147*a9fa9459Szrj @tab Enable Privileged Access Never support. 148*a9fa9459Szrj@item @code{profile} @tab ARMv8.2-A @tab No 149*a9fa9459Szrj @tab Enable statistical profiling extensions. 150*a9fa9459Szrj@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later 151*a9fa9459Szrj @tab Enable the Reliability, Availability and Serviceability 152*a9fa9459Szrj extension. 153*a9fa9459Szrj@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later 154*a9fa9459Szrj @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}. 155*a9fa9459Szrj@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later 156*a9fa9459Szrj @tab Enable Advanced SIMD extensions. This implies @code{fp}. 157*a9fa9459Szrj@end multitable 158*a9fa9459Szrj 159*a9fa9459Szrj@node AArch64 Syntax 160*a9fa9459Szrj@section Syntax 161*a9fa9459Szrj@menu 162*a9fa9459Szrj* AArch64-Chars:: Special Characters 163*a9fa9459Szrj* AArch64-Regs:: Register Names 164*a9fa9459Szrj* AArch64-Relocations:: Relocations 165*a9fa9459Szrj@end menu 166*a9fa9459Szrj 167*a9fa9459Szrj@node AArch64-Chars 168*a9fa9459Szrj@subsection Special Characters 169*a9fa9459Szrj 170*a9fa9459Szrj@cindex line comment character, AArch64 171*a9fa9459Szrj@cindex AArch64 line comment character 172*a9fa9459SzrjThe presence of a @samp{//} on a line indicates the start of a comment 173*a9fa9459Szrjthat extends to the end of the current line. If a @samp{#} appears as 174*a9fa9459Szrjthe first character of a line, the whole line is treated as a comment. 175*a9fa9459Szrj 176*a9fa9459Szrj@cindex line separator, AArch64 177*a9fa9459Szrj@cindex statement separator, AArch64 178*a9fa9459Szrj@cindex AArch64 line separator 179*a9fa9459SzrjThe @samp{;} character can be used instead of a newline to separate 180*a9fa9459Szrjstatements. 181*a9fa9459Szrj 182*a9fa9459Szrj@cindex immediate character, AArch64 183*a9fa9459Szrj@cindex AArch64 immediate character 184*a9fa9459SzrjThe @samp{#} can be optionally used to indicate immediate operands. 185*a9fa9459Szrj 186*a9fa9459Szrj@node AArch64-Regs 187*a9fa9459Szrj@subsection Register Names 188*a9fa9459Szrj 189*a9fa9459Szrj@cindex AArch64 register names 190*a9fa9459Szrj@cindex register names, AArch64 191*a9fa9459SzrjPlease refer to the section @samp{4.4 Register Names} of 192*a9fa9459Szrj@samp{ARMv8 Instruction Set Overview}, which is available at 193*a9fa9459Szrj@uref{http://infocenter.arm.com}. 194*a9fa9459Szrj 195*a9fa9459Szrj@node AArch64-Relocations 196*a9fa9459Szrj@subsection Relocations 197*a9fa9459Szrj 198*a9fa9459Szrj@cindex relocations, AArch64 199*a9fa9459Szrj@cindex AArch64 relocations 200*a9fa9459Szrj@cindex MOVN, MOVZ and MOVK group relocations, AArch64 201*a9fa9459SzrjRelocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated 202*a9fa9459Szrjby prefixing the label with @samp{#:abs_g2:} etc. 203*a9fa9459SzrjFor example to load the 48-bit absolute address of @var{foo} into x0: 204*a9fa9459Szrj 205*a9fa9459Szrj@smallexample 206*a9fa9459Szrj movz x0, #:abs_g2:foo // bits 32-47, overflow check 207*a9fa9459Szrj movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check 208*a9fa9459Szrj movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check 209*a9fa9459Szrj@end smallexample 210*a9fa9459Szrj 211*a9fa9459Szrj@cindex ADRP, ADD, LDR/STR group relocations, AArch64 212*a9fa9459SzrjRelocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR} 213*a9fa9459Szrjinstructions can be generated by prefixing the label with 214*a9fa9459Szrj@samp{:pg_hi21:} and @samp{#:lo12:} respectively. 215*a9fa9459Szrj 216*a9fa9459SzrjFor example to use 33-bit (+/-4GB) pc-relative addressing to 217*a9fa9459Szrjload the address of @var{foo} into x0: 218*a9fa9459Szrj 219*a9fa9459Szrj@smallexample 220*a9fa9459Szrj adrp x0, :pg_hi21:foo 221*a9fa9459Szrj add x0, x0, #:lo12:foo 222*a9fa9459Szrj@end smallexample 223*a9fa9459Szrj 224*a9fa9459SzrjOr to load the value of @var{foo} into x0: 225*a9fa9459Szrj 226*a9fa9459Szrj@smallexample 227*a9fa9459Szrj adrp x0, :pg_hi21:foo 228*a9fa9459Szrj ldr x0, [x0, #:lo12:foo] 229*a9fa9459Szrj@end smallexample 230*a9fa9459Szrj 231*a9fa9459SzrjNote that @samp{:pg_hi21:} is optional. 232*a9fa9459Szrj 233*a9fa9459Szrj@smallexample 234*a9fa9459Szrj adrp x0, foo 235*a9fa9459Szrj@end smallexample 236*a9fa9459Szrj 237*a9fa9459Szrjis equivalent to 238*a9fa9459Szrj 239*a9fa9459Szrj@smallexample 240*a9fa9459Szrj adrp x0, :pg_hi21:foo 241*a9fa9459Szrj@end smallexample 242*a9fa9459Szrj 243*a9fa9459Szrj@node AArch64 Floating Point 244*a9fa9459Szrj@section Floating Point 245*a9fa9459Szrj 246*a9fa9459Szrj@cindex floating point, AArch64 (@sc{ieee}) 247*a9fa9459Szrj@cindex AArch64 floating point (@sc{ieee}) 248*a9fa9459SzrjThe AArch64 architecture uses @sc{ieee} floating-point numbers. 249*a9fa9459Szrj 250*a9fa9459Szrj@node AArch64 Directives 251*a9fa9459Szrj@section AArch64 Machine Directives 252*a9fa9459Szrj 253*a9fa9459Szrj@cindex machine directives, AArch64 254*a9fa9459Szrj@cindex AArch64 machine directives 255*a9fa9459Szrj@table @code 256*a9fa9459Szrj 257*a9fa9459Szrj@c AAAAAAAAAAAAAAAAAAAAAAAAA 258*a9fa9459Szrj 259*a9fa9459Szrj@cindex @code{.arch} directive, AArch64 260*a9fa9459Szrj@item .arch @var{name} 261*a9fa9459SzrjSelect the target architecture. Valid values for @var{name} are the same as 262*a9fa9459Szrjfor the @option{-march} commandline option. 263*a9fa9459Szrj 264*a9fa9459SzrjSpecifying @code{.arch} clears any previously selected architecture 265*a9fa9459Szrjextensions. 266*a9fa9459Szrj 267*a9fa9459Szrj@cindex @code{.arch_extension} directive, AArch64 268*a9fa9459Szrj@item .arch_extension @var{name} 269*a9fa9459SzrjAdd or remove an architecture extension to the target architecture. Valid 270*a9fa9459Szrjvalues for @var{name} are the same as those accepted as architectural 271*a9fa9459Szrjextensions by the @option{-mcpu} commandline option. 272*a9fa9459Szrj 273*a9fa9459Szrj@code{.arch_extension} may be used multiple times to add or remove extensions 274*a9fa9459Szrjincrementally to the architecture being compiled for. 275*a9fa9459Szrj 276*a9fa9459Szrj@c BBBBBBBBBBBBBBBBBBBBBBBBBB 277*a9fa9459Szrj 278*a9fa9459Szrj@cindex @code{.bss} directive, AArch64 279*a9fa9459Szrj@item .bss 280*a9fa9459SzrjThis directive switches to the @code{.bss} section. 281*a9fa9459Szrj 282*a9fa9459Szrj@c CCCCCCCCCCCCCCCCCCCCCCCCCC 283*a9fa9459Szrj 284*a9fa9459Szrj@cindex @code{.cpu} directive, AArch64 285*a9fa9459Szrj@item .cpu @var{name} 286*a9fa9459SzrjSet the target processor. Valid values for @var{name} are the same as 287*a9fa9459Szrjthose accepted by the @option{-mcpu=} command line option. 288*a9fa9459Szrj 289*a9fa9459Szrj@c DDDDDDDDDDDDDDDDDDDDDDDDDD 290*a9fa9459Szrj 291*a9fa9459Szrj@cindex @code{.dword} directive, AArch64 292*a9fa9459Szrj@item .dword @var{expressions} 293*a9fa9459SzrjThe @code{.dword} directive produces 64 bit values. 294*a9fa9459Szrj 295*a9fa9459Szrj@c EEEEEEEEEEEEEEEEEEEEEEEEEE 296*a9fa9459Szrj 297*a9fa9459Szrj@cindex @code{.even} directive, AArch64 298*a9fa9459Szrj@item .even 299*a9fa9459SzrjThe @code{.even} directive aligns the output on the next even byte 300*a9fa9459Szrjboundary. 301*a9fa9459Szrj 302*a9fa9459Szrj@c FFFFFFFFFFFFFFFFFFFFFFFFFF 303*a9fa9459Szrj@c GGGGGGGGGGGGGGGGGGGGGGGGGG 304*a9fa9459Szrj@c HHHHHHHHHHHHHHHHHHHHHHHHHH 305*a9fa9459Szrj@c IIIIIIIIIIIIIIIIIIIIIIIIII 306*a9fa9459Szrj 307*a9fa9459Szrj@cindex @code{.inst} directive, AArch64 308*a9fa9459Szrj@item .inst @var{expressions} 309*a9fa9459SzrjInserts the expressions into the output as if they were instructions, 310*a9fa9459Szrjrather than data. 311*a9fa9459Szrj 312*a9fa9459Szrj@c JJJJJJJJJJJJJJJJJJJJJJJJJJ 313*a9fa9459Szrj@c KKKKKKKKKKKKKKKKKKKKKKKKKK 314*a9fa9459Szrj@c LLLLLLLLLLLLLLLLLLLLLLLLLL 315*a9fa9459Szrj 316*a9fa9459Szrj@cindex @code{.ltorg} directive, AArch64 317*a9fa9459Szrj@item .ltorg 318*a9fa9459SzrjThis directive causes the current contents of the literal pool to be 319*a9fa9459Szrjdumped into the current section (which is assumed to be the .text 320*a9fa9459Szrjsection) at the current location (aligned to a word boundary). 321*a9fa9459SzrjGAS maintains a separate literal pool for each section and each 322*a9fa9459Szrjsub-section. The @code{.ltorg} directive will only affect the literal 323*a9fa9459Szrjpool of the current section and sub-section. At the end of assembly 324*a9fa9459Szrjall remaining, un-empty literal pools will automatically be dumped. 325*a9fa9459Szrj 326*a9fa9459SzrjNote - older versions of GAS would dump the current literal 327*a9fa9459Szrjpool any time a section change occurred. This is no longer done, since 328*a9fa9459Szrjit prevents accurate control of the placement of literal pools. 329*a9fa9459Szrj 330*a9fa9459Szrj@c MMMMMMMMMMMMMMMMMMMMMMMMMM 331*a9fa9459Szrj 332*a9fa9459Szrj@c NNNNNNNNNNNNNNNNNNNNNNNNNN 333*a9fa9459Szrj@c OOOOOOOOOOOOOOOOOOOOOOOOOO 334*a9fa9459Szrj 335*a9fa9459Szrj@c PPPPPPPPPPPPPPPPPPPPPPPPPP 336*a9fa9459Szrj 337*a9fa9459Szrj@cindex @code{.pool} directive, AArch64 338*a9fa9459Szrj@item .pool 339*a9fa9459SzrjThis is a synonym for .ltorg. 340*a9fa9459Szrj 341*a9fa9459Szrj@c QQQQQQQQQQQQQQQQQQQQQQQQQQ 342*a9fa9459Szrj@c RRRRRRRRRRRRRRRRRRRRRRRRRR 343*a9fa9459Szrj 344*a9fa9459Szrj@cindex @code{.req} directive, AArch64 345*a9fa9459Szrj@item @var{name} .req @var{register name} 346*a9fa9459SzrjThis creates an alias for @var{register name} called @var{name}. For 347*a9fa9459Szrjexample: 348*a9fa9459Szrj 349*a9fa9459Szrj@smallexample 350*a9fa9459Szrj foo .req w0 351*a9fa9459Szrj@end smallexample 352*a9fa9459Szrj 353*a9fa9459Szrj@c SSSSSSSSSSSSSSSSSSSSSSSSSS 354*a9fa9459Szrj 355*a9fa9459Szrj@c TTTTTTTTTTTTTTTTTTTTTTTTTT 356*a9fa9459Szrj 357*a9fa9459Szrj@cindex @code{.tlsdescadd} directive, AArch64 358*a9fa9459Szrj@item @code{.tlsdescadd} 359*a9fa9459SzrjEmits a TLSDESC_ADD reloc on the next instruction. 360*a9fa9459Szrj 361*a9fa9459Szrj@cindex @code{.tlsdesccall} directive, AArch64 362*a9fa9459Szrj@item @code{.tlsdesccall} 363*a9fa9459SzrjEmits a TLSDESC_CALL reloc on the next instruction. 364*a9fa9459Szrj 365*a9fa9459Szrj@cindex @code{.tlsdescldr} directive, AArch64 366*a9fa9459Szrj@item @code{.tlsdescldr} 367*a9fa9459SzrjEmits a TLSDESC_LDR reloc on the next instruction. 368*a9fa9459Szrj 369*a9fa9459Szrj@c UUUUUUUUUUUUUUUUUUUUUUUUUU 370*a9fa9459Szrj 371*a9fa9459Szrj@cindex @code{.unreq} directive, AArch64 372*a9fa9459Szrj@item .unreq @var{alias-name} 373*a9fa9459SzrjThis undefines a register alias which was previously defined using the 374*a9fa9459Szrj@code{req} directive. For example: 375*a9fa9459Szrj 376*a9fa9459Szrj@smallexample 377*a9fa9459Szrj foo .req w0 378*a9fa9459Szrj .unreq foo 379*a9fa9459Szrj@end smallexample 380*a9fa9459Szrj 381*a9fa9459SzrjAn error occurs if the name is undefined. Note - this pseudo op can 382*a9fa9459Szrjbe used to delete builtin in register name aliases (eg 'w0'). This 383*a9fa9459Szrjshould only be done if it is really necessary. 384*a9fa9459Szrj 385*a9fa9459Szrj@c VVVVVVVVVVVVVVVVVVVVVVVVVV 386*a9fa9459Szrj 387*a9fa9459Szrj@c WWWWWWWWWWWWWWWWWWWWWWWWWW 388*a9fa9459Szrj@c XXXXXXXXXXXXXXXXXXXXXXXXXX 389*a9fa9459Szrj 390*a9fa9459Szrj@cindex @code{.xword} directive, AArch64 391*a9fa9459Szrj@item .xword @var{expressions} 392*a9fa9459SzrjThe @code{.xword} directive produces 64 bit values. This is the same 393*a9fa9459Szrjas the @code{.dword} directive. 394*a9fa9459Szrj 395*a9fa9459Szrj@c YYYYYYYYYYYYYYYYYYYYYYYYYY 396*a9fa9459Szrj@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ 397*a9fa9459Szrj 398*a9fa9459Szrj@end table 399*a9fa9459Szrj 400*a9fa9459Szrj@node AArch64 Opcodes 401*a9fa9459Szrj@section Opcodes 402*a9fa9459Szrj 403*a9fa9459Szrj@cindex AArch64 opcodes 404*a9fa9459Szrj@cindex opcodes for AArch64 405*a9fa9459SzrjGAS implements all the standard AArch64 opcodes. It also 406*a9fa9459Szrjimplements several pseudo opcodes, including several synthetic load 407*a9fa9459Szrjinstructions. 408*a9fa9459Szrj 409*a9fa9459Szrj@table @code 410*a9fa9459Szrj 411*a9fa9459Szrj@cindex @code{LDR reg,=<expr>} pseudo op, AArch64 412*a9fa9459Szrj@item LDR = 413*a9fa9459Szrj@smallexample 414*a9fa9459Szrj ldr <register> , =<expression> 415*a9fa9459Szrj@end smallexample 416*a9fa9459Szrj 417*a9fa9459SzrjThe constant expression will be placed into the nearest literal pool (if it not 418*a9fa9459Szrjalready there) and a PC-relative LDR instruction will be generated. 419*a9fa9459Szrj 420*a9fa9459Szrj@end table 421*a9fa9459Szrj 422*a9fa9459SzrjFor more information on the AArch64 instruction set and assembly language 423*a9fa9459Szrjnotation, see @samp{ARMv8 Instruction Set Overview} available at 424*a9fa9459Szrj@uref{http://infocenter.arm.com}. 425*a9fa9459Szrj 426*a9fa9459Szrj 427*a9fa9459Szrj@node AArch64 Mapping Symbols 428*a9fa9459Szrj@section Mapping Symbols 429*a9fa9459Szrj 430*a9fa9459SzrjThe AArch64 ELF specification requires that special symbols be inserted 431*a9fa9459Szrjinto object files to mark certain features: 432*a9fa9459Szrj 433*a9fa9459Szrj@table @code 434*a9fa9459Szrj 435*a9fa9459Szrj@cindex @code{$x} 436*a9fa9459Szrj@item $x 437*a9fa9459SzrjAt the start of a region of code containing AArch64 instructions. 438*a9fa9459Szrj 439*a9fa9459Szrj@cindex @code{$d} 440*a9fa9459Szrj@item $d 441*a9fa9459SzrjAt the start of a region of data. 442*a9fa9459Szrj 443*a9fa9459Szrj@end table 444