1 /* Definitions of target machine for GCC for IA-32. 2 Copyright (C) 1988-2018 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 Under Section 7 of GPL version 3, you are granted additional 17 permissions described in the GCC Runtime Library Exception, version 18 3.1, as published by the Free Software Foundation. 19 20 You should have received a copy of the GNU General Public License and 21 a copy of the GCC Runtime Library Exception along with this program; 22 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 23 <http://www.gnu.org/licenses/>. */ 24 25 /* The purpose of this file is to define the characteristics of the i386, 26 independent of assembler syntax or operating system. 27 28 Three other files build on this one to describe a specific assembler syntax: 29 bsd386.h, att386.h, and sun386.h. 30 31 The actual tm.h file for a particular system should include 32 this file, and then the file for the appropriate assembler syntax. 33 34 Many macros that specify assembler syntax are omitted entirely from 35 this file because they really belong in the files for particular 36 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 37 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 38 that start with ASM_ or end in ASM_OP. */ 39 40 /* Redefines for option macros. */ 41 42 #define TARGET_64BIT TARGET_ISA_64BIT 43 #define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x) 44 #define TARGET_MMX TARGET_ISA_MMX 45 #define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x) 46 #define TARGET_3DNOW TARGET_ISA_3DNOW 47 #define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x) 48 #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A 49 #define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x) 50 #define TARGET_SSE TARGET_ISA_SSE 51 #define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x) 52 #define TARGET_SSE2 TARGET_ISA_SSE2 53 #define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x) 54 #define TARGET_SSE3 TARGET_ISA_SSE3 55 #define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x) 56 #define TARGET_SSSE3 TARGET_ISA_SSSE3 57 #define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x) 58 #define TARGET_SSE4_1 TARGET_ISA_SSE4_1 59 #define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x) 60 #define TARGET_SSE4_2 TARGET_ISA_SSE4_2 61 #define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x) 62 #define TARGET_AVX TARGET_ISA_AVX 63 #define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x) 64 #define TARGET_AVX2 TARGET_ISA_AVX2 65 #define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x) 66 #define TARGET_AVX512F TARGET_ISA_AVX512F 67 #define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x) 68 #define TARGET_AVX512PF TARGET_ISA_AVX512PF 69 #define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x) 70 #define TARGET_AVX512ER TARGET_ISA_AVX512ER 71 #define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x) 72 #define TARGET_AVX512CD TARGET_ISA_AVX512CD 73 #define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x) 74 #define TARGET_AVX512DQ TARGET_ISA_AVX512DQ 75 #define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x) 76 #define TARGET_AVX512BW TARGET_ISA_AVX512BW 77 #define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x) 78 #define TARGET_AVX512VL TARGET_ISA_AVX512VL 79 #define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x) 80 #define TARGET_AVX512VBMI TARGET_ISA_AVX512VBMI 81 #define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x) 82 #define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA 83 #define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x) 84 #define TARGET_AVX5124FMAPS TARGET_ISA_AVX5124FMAPS 85 #define TARGET_AVX5124FMAPS_P(x) TARGET_ISA_AVX5124FMAPS_P(x) 86 #define TARGET_AVX5124VNNIW TARGET_ISA_AVX5124VNNIW 87 #define TARGET_AVX5124VNNIW_P(x) TARGET_ISA_AVX5124VNNIW_P(x) 88 #define TARGET_AVX512VBMI2 TARGET_ISA_AVX512VBMI2 89 #define TARGET_AVX512VBMI2_P(x) TARGET_ISA_AVX512VBMI2_P(x) 90 #define TARGET_AVX512VPOPCNTDQ TARGET_ISA_AVX512VPOPCNTDQ 91 #define TARGET_AVX512VPOPCNTDQ_P(x) TARGET_ISA_AVX512VPOPCNTDQ_P(x) 92 #define TARGET_AVX512VNNI TARGET_ISA_AVX512VNNI 93 #define TARGET_AVX512VNNI_P(x) TARGET_ISA_AVX512VNNI_P(x) 94 #define TARGET_AVX512BITALG TARGET_ISA_AVX512BITALG 95 #define TARGET_AVX512BITALG_P(x) TARGET_ISA_AVX512BITALG_P(x) 96 #define TARGET_FMA TARGET_ISA_FMA 97 #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) 98 #define TARGET_SSE4A TARGET_ISA_SSE4A 99 #define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x) 100 #define TARGET_FMA4 TARGET_ISA_FMA4 101 #define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x) 102 #define TARGET_XOP TARGET_ISA_XOP 103 #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x) 104 #define TARGET_LWP TARGET_ISA_LWP 105 #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) 106 #define TARGET_ABM TARGET_ISA_ABM 107 #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) 108 #define TARGET_PCONFIG TARGET_ISA_PCONFIG 109 #define TARGET_PCONFIG_P(x) TARGET_ISA_PCONFIG_P(x) 110 #define TARGET_WBNOINVD TARGET_ISA_WBNOINVD 111 #define TARGET_WBNOINVD_P(x) TARGET_ISA_WBNOINVD_P(x) 112 #define TARGET_SGX TARGET_ISA_SGX 113 #define TARGET_SGX_P(x) TARGET_ISA_SGX_P(x) 114 #define TARGET_RDPID TARGET_ISA_RDPID 115 #define TARGET_RDPID_P(x) TARGET_ISA_RDPID_P(x) 116 #define TARGET_GFNI TARGET_ISA_GFNI 117 #define TARGET_GFNI_P(x) TARGET_ISA_GFNI_P(x) 118 #define TARGET_VAES TARGET_ISA_VAES 119 #define TARGET_VAES_P(x) TARGET_ISA_VAES_P(x) 120 #define TARGET_VPCLMULQDQ TARGET_ISA_VPCLMULQDQ 121 #define TARGET_VPCLMULQDQ_P(x) TARGET_ISA_VPCLMULQDQ_P(x) 122 #define TARGET_BMI TARGET_ISA_BMI 123 #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) 124 #define TARGET_BMI2 TARGET_ISA_BMI2 125 #define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x) 126 #define TARGET_LZCNT TARGET_ISA_LZCNT 127 #define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x) 128 #define TARGET_TBM TARGET_ISA_TBM 129 #define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x) 130 #define TARGET_POPCNT TARGET_ISA_POPCNT 131 #define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x) 132 #define TARGET_SAHF TARGET_ISA_SAHF 133 #define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x) 134 #define TARGET_MOVBE TARGET_ISA_MOVBE 135 #define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x) 136 #define TARGET_CRC32 TARGET_ISA_CRC32 137 #define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x) 138 #define TARGET_AES TARGET_ISA_AES 139 #define TARGET_AES_P(x) TARGET_ISA_AES_P(x) 140 #define TARGET_SHA TARGET_ISA_SHA 141 #define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x) 142 #define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT 143 #define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x) 144 #define TARGET_CLZERO TARGET_ISA_CLZERO 145 #define TARGET_CLZERO_P(x) TARGET_ISA_CLZERO_P(x) 146 #define TARGET_XSAVEC TARGET_ISA_XSAVEC 147 #define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x) 148 #define TARGET_XSAVES TARGET_ISA_XSAVES 149 #define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x) 150 #define TARGET_PCLMUL TARGET_ISA_PCLMUL 151 #define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x) 152 #define TARGET_CMPXCHG16B TARGET_ISA_CX16 153 #define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x) 154 #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE 155 #define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x) 156 #define TARGET_RDRND TARGET_ISA_RDRND 157 #define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x) 158 #define TARGET_F16C TARGET_ISA_F16C 159 #define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x) 160 #define TARGET_RTM TARGET_ISA_RTM 161 #define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x) 162 #define TARGET_HLE TARGET_ISA_HLE 163 #define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x) 164 #define TARGET_RDSEED TARGET_ISA_RDSEED 165 #define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x) 166 #define TARGET_PRFCHW TARGET_ISA_PRFCHW 167 #define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x) 168 #define TARGET_ADX TARGET_ISA_ADX 169 #define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x) 170 #define TARGET_FXSR TARGET_ISA_FXSR 171 #define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x) 172 #define TARGET_XSAVE TARGET_ISA_XSAVE 173 #define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x) 174 #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT 175 #define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x) 176 #define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1 177 #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) 178 #define TARGET_MPX TARGET_ISA_MPX 179 #define TARGET_MPX_P(x) TARGET_ISA_MPX_P(x) 180 #define TARGET_CLWB TARGET_ISA_CLWB 181 #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) 182 #define TARGET_MWAITX TARGET_ISA_MWAITX 183 #define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x) 184 #define TARGET_PKU TARGET_ISA_PKU 185 #define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x) 186 #define TARGET_SHSTK TARGET_ISA_SHSTK 187 #define TARGET_SHSTK_P(x) TARGET_ISA_SHSTK_P(x) 188 #define TARGET_MOVDIRI TARGET_ISA_MOVDIRI 189 #define TARGET_MOVDIRI_P(x) TARGET_ISA_MOVDIRI_P(x) 190 #define TARGET_MOVDIR64B TARGET_ISA_MOVDIR64B 191 #define TARGET_MOVDIR64B_P(x) TARGET_ISA_MOVDIR64B_P(x) 192 193 #define TARGET_LP64 TARGET_ABI_64 194 #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) 195 #define TARGET_X32 TARGET_ABI_X32 196 #define TARGET_X32_P(x) TARGET_ABI_X32_P(x) 197 #define TARGET_16BIT TARGET_CODE16 198 #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) 199 200 #include "config/vxworks-dummy.h" 201 202 #include "config/i386/i386-opts.h" 203 204 #define MAX_STRINGOP_ALGS 4 205 206 /* Specify what algorithm to use for stringops on known size. 207 When size is unknown, the UNKNOWN_SIZE alg is used. When size is 208 known at compile time or estimated via feedback, the SIZE array 209 is walked in order until MAX is greater then the estimate (or -1 210 means infinity). Corresponding ALG is used then. 211 When NOALIGN is true the code guaranting the alignment of the memory 212 block is skipped. 213 214 For example initializer: 215 {{256, loop}, {-1, rep_prefix_4_byte}} 216 will use loop for blocks smaller or equal to 256 bytes, rep prefix will 217 be used otherwise. */ 218 struct stringop_algs 219 { 220 const enum stringop_alg unknown_size; 221 const struct stringop_strategy { 222 const int max; 223 const enum stringop_alg alg; 224 int noalign; 225 } size [MAX_STRINGOP_ALGS]; 226 }; 227 228 /* Define the specific costs for a given cpu */ 229 230 struct processor_costs { 231 const int add; /* cost of an add instruction */ 232 const int lea; /* cost of a lea instruction */ 233 const int shift_var; /* variable shift costs */ 234 const int shift_const; /* constant shift costs */ 235 const int mult_init[5]; /* cost of starting a multiply 236 in QImode, HImode, SImode, DImode, TImode*/ 237 const int mult_bit; /* cost of multiply per each bit set */ 238 const int divide[5]; /* cost of a divide/mod 239 in QImode, HImode, SImode, DImode, TImode*/ 240 int movsx; /* The cost of movsx operation. */ 241 int movzx; /* The cost of movzx operation. */ 242 const int large_insn; /* insns larger than this cost more */ 243 const int move_ratio; /* The threshold of number of scalar 244 memory-to-memory move insns. */ 245 const int movzbl_load; /* cost of loading using movzbl */ 246 const int int_load[3]; /* cost of loading integer registers 247 in QImode, HImode and SImode relative 248 to reg-reg move (2). */ 249 const int int_store[3]; /* cost of storing integer register 250 in QImode, HImode and SImode */ 251 const int fp_move; /* cost of reg,reg fld/fst */ 252 const int fp_load[3]; /* cost of loading FP register 253 in SFmode, DFmode and XFmode */ 254 const int fp_store[3]; /* cost of storing FP register 255 in SFmode, DFmode and XFmode */ 256 const int mmx_move; /* cost of moving MMX register. */ 257 const int mmx_load[2]; /* cost of loading MMX register 258 in SImode and DImode */ 259 const int mmx_store[2]; /* cost of storing MMX register 260 in SImode and DImode */ 261 const int xmm_move, ymm_move, /* cost of moving XMM and YMM register. */ 262 zmm_move; 263 const int sse_load[5]; /* cost of loading SSE register 264 in 32bit, 64bit, 128bit, 256bit and 512bit */ 265 const int sse_unaligned_load[5];/* cost of unaligned load. */ 266 const int sse_store[5]; /* cost of storing SSE register 267 in SImode, DImode and TImode. */ 268 const int sse_unaligned_store[5];/* cost of unaligned store. */ 269 const int mmxsse_to_integer; /* cost of moving mmxsse register to 270 integer. */ 271 const int ssemmx_to_integer; /* cost of moving integer to mmxsse register. */ 272 const int gather_static, gather_per_elt; /* Cost of gather load is computed 273 as static + per_item * nelts. */ 274 const int scatter_static, scatter_per_elt; /* Cost of gather store is 275 computed as static + per_item * nelts. */ 276 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 277 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 278 const int prefetch_block; /* bytes moved to cache for prefetch. */ 279 const int simultaneous_prefetches; /* number of parallel prefetch 280 operations. */ 281 const int branch_cost; /* Default value for BRANCH_COST. */ 282 const int fadd; /* cost of FADD and FSUB instructions. */ 283 const int fmul; /* cost of FMUL instruction. */ 284 const int fdiv; /* cost of FDIV instruction. */ 285 const int fabs; /* cost of FABS instruction. */ 286 const int fchs; /* cost of FCHS instruction. */ 287 const int fsqrt; /* cost of FSQRT instruction. */ 288 /* Specify what algorithm 289 to use for stringops on unknown size. */ 290 const int sse_op; /* cost of cheap SSE instruction. */ 291 const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */ 292 const int mulss; /* cost of MULSS instructions. */ 293 const int mulsd; /* cost of MULSD instructions. */ 294 const int fmass; /* cost of FMASS instructions. */ 295 const int fmasd; /* cost of FMASD instructions. */ 296 const int divss; /* cost of DIVSS instructions. */ 297 const int divsd; /* cost of DIVSD instructions. */ 298 const int sqrtss; /* cost of SQRTSS instructions. */ 299 const int sqrtsd; /* cost of SQRTSD instructions. */ 300 const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp; 301 /* Specify reassociation width for integer, 302 fp, vector integer and vector fp 303 operations. Generally should correspond 304 to number of instructions executed in 305 parallel. See also 306 ix86_reassociation_width. */ 307 struct stringop_algs *memcpy, *memset; 308 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer 309 cost model. */ 310 const int cond_not_taken_branch_cost;/* Cost of not taken branch for 311 vectorizer cost model. */ 312 }; 313 314 extern const struct processor_costs *ix86_cost; 315 extern const struct processor_costs ix86_size_cost; 316 317 #define ix86_cur_cost() \ 318 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) 319 320 /* Macros used in the machine description to test the flags. */ 321 322 /* configure can arrange to change it. */ 323 324 #ifndef TARGET_CPU_DEFAULT 325 #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC 326 #endif 327 328 #ifndef TARGET_FPMATH_DEFAULT 329 #define TARGET_FPMATH_DEFAULT \ 330 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 331 #endif 332 333 #ifndef TARGET_FPMATH_DEFAULT_P 334 #define TARGET_FPMATH_DEFAULT_P(x) \ 335 (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387) 336 #endif 337 338 /* If the i387 is disabled or -miamcu is used , then do not return 339 values in it. */ 340 #define TARGET_FLOAT_RETURNS_IN_80387 \ 341 (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU) 342 #define TARGET_FLOAT_RETURNS_IN_80387_P(x) \ 343 (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x)) 344 345 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 346 compile-time constant. */ 347 #ifdef IN_LIBGCC2 348 #undef TARGET_64BIT 349 #ifdef __x86_64__ 350 #define TARGET_64BIT 1 351 #else 352 #define TARGET_64BIT 0 353 #endif 354 #else 355 #ifndef TARGET_BI_ARCH 356 #undef TARGET_64BIT 357 #undef TARGET_64BIT_P 358 #if TARGET_64BIT_DEFAULT 359 #define TARGET_64BIT 1 360 #define TARGET_64BIT_P(x) 1 361 #else 362 #define TARGET_64BIT 0 363 #define TARGET_64BIT_P(x) 0 364 #endif 365 #endif 366 #endif 367 368 #define HAS_LONG_COND_BRANCH 1 369 #define HAS_LONG_UNCOND_BRANCH 1 370 371 #define TARGET_386 (ix86_tune == PROCESSOR_I386) 372 #define TARGET_486 (ix86_tune == PROCESSOR_I486) 373 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 374 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 375 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) 376 #define TARGET_K6 (ix86_tune == PROCESSOR_K6) 377 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 378 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 379 #define TARGET_K8 (ix86_tune == PROCESSOR_K8) 380 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 381 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 382 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) 383 #define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM) 384 #define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE) 385 #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) 386 #define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL) 387 #define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT) 388 #define TARGET_KNL (ix86_tune == PROCESSOR_KNL) 389 #define TARGET_KNM (ix86_tune == PROCESSOR_KNM) 390 #define TARGET_SKYLAKE (ix86_tune == PROCESSOR_SKYLAKE) 391 #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512) 392 #define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE) 393 #define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT) 394 #define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER) 395 #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) 396 #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) 397 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) 398 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) 399 #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) 400 #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) 401 #define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4) 402 #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) 403 #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) 404 #define TARGET_ZNVER1 (ix86_tune == PROCESSOR_ZNVER1) 405 406 /* Feature tests against the various tunings. */ 407 enum ix86_tune_indices { 408 #undef DEF_TUNE 409 #define DEF_TUNE(tune, name, selector) tune, 410 #include "x86-tune.def" 411 #undef DEF_TUNE 412 X86_TUNE_LAST 413 }; 414 415 extern unsigned char ix86_tune_features[X86_TUNE_LAST]; 416 417 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] 418 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] 419 #define TARGET_ZERO_EXTEND_WITH_AND \ 420 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] 421 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] 422 #define TARGET_BRANCH_PREDICTION_HINTS \ 423 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] 424 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] 425 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] 426 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] 427 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] 428 #define TARGET_PARTIAL_FLAG_REG_STALL \ 429 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] 430 #define TARGET_LCP_STALL \ 431 ix86_tune_features[X86_TUNE_LCP_STALL] 432 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] 433 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] 434 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] 435 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] 436 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] 437 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] 438 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] 439 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] 440 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] 441 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] 442 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] 443 #define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \ 444 ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES] 445 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] 446 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] 447 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] 448 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] 449 #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] 450 #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] 451 #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] 452 #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] 453 #define TARGET_INTEGER_DFMODE_MOVES \ 454 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] 455 #define TARGET_PARTIAL_REG_DEPENDENCY \ 456 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] 457 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 458 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] 459 #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ 460 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] 461 #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ 462 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] 463 #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ 464 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] 465 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] 466 #define TARGET_SSE_TYPELESS_STORES \ 467 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] 468 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] 469 #define TARGET_MEMORY_MISMATCH_STALL \ 470 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] 471 #define TARGET_PROLOGUE_USING_MOVE \ 472 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] 473 #define TARGET_EPILOGUE_USING_MOVE \ 474 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] 475 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] 476 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] 477 #define TARGET_INTER_UNIT_MOVES_TO_VEC \ 478 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC] 479 #define TARGET_INTER_UNIT_MOVES_FROM_VEC \ 480 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC] 481 #define TARGET_INTER_UNIT_CONVERSIONS \ 482 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] 483 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] 484 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] 485 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] 486 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] 487 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] 488 #define TARGET_PAD_SHORT_FUNCTION \ 489 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] 490 #define TARGET_EXT_80387_CONSTANTS \ 491 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] 492 #define TARGET_AVOID_VECTOR_DECODE \ 493 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] 494 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ 495 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] 496 #define TARGET_SLOW_IMUL_IMM32_MEM \ 497 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] 498 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] 499 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] 500 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] 501 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] 502 #define TARGET_USE_VECTOR_FP_CONVERTS \ 503 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] 504 #define TARGET_USE_VECTOR_CONVERTS \ 505 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] 506 #define TARGET_SLOW_PSHUFB \ 507 ix86_tune_features[X86_TUNE_SLOW_PSHUFB] 508 #define TARGET_AVOID_4BYTE_PREFIXES \ 509 ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES] 510 #define TARGET_USE_GATHER \ 511 ix86_tune_features[X86_TUNE_USE_GATHER] 512 #define TARGET_FUSE_CMP_AND_BRANCH_32 \ 513 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] 514 #define TARGET_FUSE_CMP_AND_BRANCH_64 \ 515 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64] 516 #define TARGET_FUSE_CMP_AND_BRANCH \ 517 (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \ 518 : TARGET_FUSE_CMP_AND_BRANCH_32) 519 #define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \ 520 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS] 521 #define TARGET_FUSE_ALU_AND_BRANCH \ 522 ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH] 523 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] 524 #define TARGET_AVOID_LEA_FOR_ADDR \ 525 ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR] 526 #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ 527 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] 528 #define TARGET_AVX128_OPTIMAL \ 529 ix86_tune_features[X86_TUNE_AVX128_OPTIMAL] 530 #define TARGET_GENERAL_REGS_SSE_SPILL \ 531 ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] 532 #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ 533 ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] 534 #define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \ 535 ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS] 536 #define TARGET_ADJUST_UNROLL \ 537 ix86_tune_features[X86_TUNE_ADJUST_UNROLL] 538 #define TARGET_AVOID_FALSE_DEP_FOR_BMI \ 539 ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] 540 #define TARGET_ONE_IF_CONV_INSN \ 541 ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN] 542 #define TARGET_EMIT_VZEROUPPER \ 543 ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER] 544 545 /* Feature tests against the various architecture variations. */ 546 enum ix86_arch_indices { 547 X86_ARCH_CMOV, 548 X86_ARCH_CMPXCHG, 549 X86_ARCH_CMPXCHG8B, 550 X86_ARCH_XADD, 551 X86_ARCH_BSWAP, 552 553 X86_ARCH_LAST 554 }; 555 556 extern unsigned char ix86_arch_features[X86_ARCH_LAST]; 557 558 #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] 559 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] 560 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] 561 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] 562 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] 563 564 /* For sane SSE instruction set generation we need fcomi instruction. 565 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic 566 expands to a sequence that includes conditional move. */ 567 #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) 568 569 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 570 571 extern unsigned char x86_prefetch_sse; 572 #define TARGET_PREFETCH_SSE x86_prefetch_sse 573 574 #define ASSEMBLER_DIALECT (ix86_asm_dialect) 575 576 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 577 #define TARGET_MIX_SSE_I387 \ 578 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) 579 580 #define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE) 581 #define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE) 582 #define TARGET_HARD_XF_REGS (TARGET_80387) 583 584 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 585 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 586 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 587 #define TARGET_SUN_TLS 0 588 589 #ifndef TARGET_64BIT_DEFAULT 590 #define TARGET_64BIT_DEFAULT 0 591 #endif 592 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 593 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 594 #endif 595 596 #define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL) 597 #define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS) 598 599 /* Fence to use after loop using storent. */ 600 601 extern tree x86_mfence; 602 #define FENCE_FOLLOWING_MOVNT x86_mfence 603 604 /* Once GDB has been enhanced to deal with functions without frame 605 pointers, we can change this to allow for elimination of 606 the frame pointer in leaf functions. */ 607 #define TARGET_DEFAULT 0 608 609 /* Extra bits to force. */ 610 #define TARGET_SUBTARGET_DEFAULT 0 611 #define TARGET_SUBTARGET_ISA_DEFAULT 0 612 613 /* Extra bits to force on w/ 32-bit mode. */ 614 #define TARGET_SUBTARGET32_DEFAULT 0 615 #define TARGET_SUBTARGET32_ISA_DEFAULT 0 616 617 /* Extra bits to force on w/ 64-bit mode. */ 618 #define TARGET_SUBTARGET64_DEFAULT 0 619 #define TARGET_SUBTARGET64_ISA_DEFAULT 0 620 621 /* Replace MACH-O, ifdefs by in-line tests, where possible. 622 (a) Macros defined in config/i386/darwin.h */ 623 #define TARGET_MACHO 0 624 #define TARGET_MACHO_BRANCH_ISLANDS 0 625 #define MACHOPIC_ATT_STUB 0 626 /* (b) Macros defined in config/darwin.h */ 627 #define MACHO_DYNAMIC_NO_PIC_P 0 628 #define MACHOPIC_INDIRECT 0 629 #define MACHOPIC_PURE 0 630 631 /* For the RDOS */ 632 #define TARGET_RDOS 0 633 634 /* For the Windows 64-bit ABI. */ 635 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 636 637 /* For the Windows 32-bit ABI. */ 638 #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 639 640 /* This is re-defined by cygming.h. */ 641 #define TARGET_SEH 0 642 643 /* The default abi used by target. */ 644 #define DEFAULT_ABI SYSV_ABI 645 646 /* The default TLS segment register used by target. */ 647 #define DEFAULT_TLS_SEG_REG \ 648 (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS) 649 650 /* Subtargets may reset this to 1 in order to enable 96-bit long double 651 with the rounding mode forced to 53 bits. */ 652 #define TARGET_96_ROUND_53_LONG_DOUBLE 0 653 654 /* -march=native handling only makes sense with compiler running on 655 an x86 or x86_64 chip. If changing this condition, also change 656 the condition in driver-i386.c. */ 657 #if defined(__i386__) || defined(__x86_64__) 658 /* In driver-i386.c. */ 659 extern const char *host_detect_local_cpu (int argc, const char **argv); 660 #define EXTRA_SPEC_FUNCTIONS \ 661 { "local_cpu_detect", host_detect_local_cpu }, 662 #define HAVE_LOCAL_CPU_DETECT 663 #endif 664 665 #if TARGET_64BIT_DEFAULT 666 #define OPT_ARCH64 "!m32" 667 #define OPT_ARCH32 "m32" 668 #else 669 #define OPT_ARCH64 "m64|mx32" 670 #define OPT_ARCH32 "m64|mx32:;" 671 #endif 672 673 /* Support for configure-time defaults of some command line options. 674 The order here is important so that -march doesn't squash the 675 tune or cpu values. */ 676 #define OPTION_DEFAULT_SPECS \ 677 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 678 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 679 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 680 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 681 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 682 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 683 {"arch", "%{!march=*:-march=%(VALUE)}"}, \ 684 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ 685 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, 686 687 /* Specs for the compiler proper */ 688 689 #ifndef CC1_CPU_SPEC 690 #define CC1_CPU_SPEC_1 "" 691 692 #ifndef HAVE_LOCAL_CPU_DETECT 693 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 694 #else 695 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 696 "%{march=native:%>march=native %:local_cpu_detect(arch) \ 697 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ 698 %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" 699 #endif 700 #endif 701 702 /* Target CPU builtins. */ 703 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () 704 705 /* Target Pragmas. */ 706 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () 707 708 #ifndef CC1_SPEC 709 #define CC1_SPEC "%(cc1_cpu) " 710 #endif 711 712 /* This macro defines names of additional specifications to put in the 713 specs that can be used in various specifications like CC1_SPEC. Its 714 definition is an initializer with a subgrouping for each command option. 715 716 Each subgrouping contains a string constant, that defines the 717 specification name, and a string constant that used by the GCC driver 718 program. 719 720 Do not define this macro if it does not need to do anything. */ 721 722 #ifndef SUBTARGET_EXTRA_SPECS 723 #define SUBTARGET_EXTRA_SPECS 724 #endif 725 726 #define EXTRA_SPECS \ 727 { "cc1_cpu", CC1_CPU_SPEC }, \ 728 SUBTARGET_EXTRA_SPECS 729 730 731 /* Whether to allow x87 floating-point arithmetic on MODE (one of 732 SFmode, DFmode and XFmode) in the current excess precision 733 configuration. */ 734 #define X87_ENABLE_ARITH(MODE) \ 735 (flag_unsafe_math_optimizations \ 736 || flag_excess_precision == EXCESS_PRECISION_FAST \ 737 || (MODE) == XFmode) 738 739 /* Likewise, whether to allow direct conversions from integer mode 740 IMODE (HImode, SImode or DImode) to MODE. */ 741 #define X87_ENABLE_FLOAT(MODE, IMODE) \ 742 (flag_unsafe_math_optimizations \ 743 || flag_excess_precision == EXCESS_PRECISION_FAST \ 744 || (MODE) == XFmode \ 745 || ((MODE) == DFmode && (IMODE) == SImode) \ 746 || (IMODE) == HImode) 747 748 /* target machine storage layout */ 749 750 #define SHORT_TYPE_SIZE 16 751 #define INT_TYPE_SIZE 32 752 #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 753 #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 754 #define LONG_LONG_TYPE_SIZE 64 755 #define FLOAT_TYPE_SIZE 32 756 #define DOUBLE_TYPE_SIZE 64 757 #define LONG_DOUBLE_TYPE_SIZE \ 758 (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80)) 759 760 #define WIDEST_HARDWARE_FP_SIZE 80 761 762 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 763 #define MAX_BITS_PER_WORD 64 764 #else 765 #define MAX_BITS_PER_WORD 32 766 #endif 767 768 /* Define this if most significant byte of a word is the lowest numbered. */ 769 /* That is true on the 80386. */ 770 771 #define BITS_BIG_ENDIAN 0 772 773 /* Define this if most significant byte of a word is the lowest numbered. */ 774 /* That is not true on the 80386. */ 775 #define BYTES_BIG_ENDIAN 0 776 777 /* Define this if most significant word of a multiword number is the lowest 778 numbered. */ 779 /* Not true for 80386 */ 780 #define WORDS_BIG_ENDIAN 0 781 782 /* Width of a word, in units (bytes). */ 783 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 784 785 #ifndef IN_LIBGCC2 786 #define MIN_UNITS_PER_WORD 4 787 #endif 788 789 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 790 #define PARM_BOUNDARY BITS_PER_WORD 791 792 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 793 #define STACK_BOUNDARY (TARGET_64BIT_MS_ABI ? 128 : BITS_PER_WORD) 794 795 /* Stack boundary of the main function guaranteed by OS. */ 796 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) 797 798 /* Minimum stack boundary. */ 799 #define MIN_STACK_BOUNDARY BITS_PER_WORD 800 801 /* Boundary (in *bits*) on which the stack pointer prefers to be 802 aligned; the compiler cannot rely on having this alignment. */ 803 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 804 805 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for 806 both 32bit and 64bit, to support codes that need 128 bit stack 807 alignment for SSE instructions, but can't realign the stack. */ 808 #define PREFERRED_STACK_BOUNDARY_DEFAULT \ 809 (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128) 810 811 /* 1 if -mstackrealign should be turned on by default. It will 812 generate an alternate prologue and epilogue that realigns the 813 runtime stack if nessary. This supports mixing codes that keep a 814 4-byte aligned stack, as specified by i386 psABI, with codes that 815 need a 16-byte aligned stack, as required by SSE instructions. */ 816 #define STACK_REALIGN_DEFAULT 0 817 818 /* Boundary (in *bits*) on which the incoming stack is aligned. */ 819 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary 820 821 /* According to Windows x64 software convention, the maximum stack allocatable 822 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of 823 instructions allowed to adjust the stack pointer in the epilog, forcing the 824 use of frame pointer for frames larger than 2 GB. This theorical limit 825 is reduced by 256, an over-estimated upper bound for the stack use by the 826 prologue. 827 We define only one threshold for both the prolog and the epilog. When the 828 frame size is larger than this threshold, we allocate the area to save SSE 829 regs, then save them, and then allocate the remaining. There is no SEH 830 unwind info for this later allocation. */ 831 #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) 832 833 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is 834 mandatory for the 64-bit ABI, and may or may not be true for other 835 operating systems. */ 836 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT 837 838 /* Minimum allocation boundary for the code of a function. */ 839 #define FUNCTION_BOUNDARY 8 840 841 /* C++ stores the virtual bit in the lowest bit of function pointers. */ 842 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 843 844 /* Minimum size in bits of the largest boundary to which any 845 and all fundamental data types supported by the hardware 846 might need to be aligned. No data type wants to be aligned 847 rounder than this. 848 849 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 850 and Pentium Pro XFmode values at 128 bit boundaries. 851 852 When increasing the maximum, also update 853 TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */ 854 855 #define BIGGEST_ALIGNMENT \ 856 (TARGET_IAMCU ? 32 : (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128))) 857 858 /* Maximum stack alignment. */ 859 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT 860 861 /* Alignment value for attribute ((aligned)). It is a constant since 862 it is the part of the ABI. We shouldn't change it with -mavx. */ 863 #define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128) 864 865 /* Decide whether a variable of mode MODE should be 128 bit aligned. */ 866 #define ALIGN_MODE_128(MODE) \ 867 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 868 869 /* The published ABIs say that doubles should be aligned on word 870 boundaries, so lower the alignment for structure fields unless 871 -malign-double is set. */ 872 873 /* ??? Blah -- this macro is used directly by libobjc. Since it 874 supports no vector modes, cut out the complexity and fall back 875 on BIGGEST_FIELD_ALIGNMENT. */ 876 #ifdef IN_TARGET_LIBS 877 #ifdef __x86_64__ 878 #define BIGGEST_FIELD_ALIGNMENT 128 879 #else 880 #define BIGGEST_FIELD_ALIGNMENT 32 881 #endif 882 #else 883 #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ 884 x86_field_alignment ((TYPE), (COMPUTED)) 885 #endif 886 887 /* If defined, a C expression to compute the alignment for a static 888 variable. TYPE is the data type, and ALIGN is the alignment that 889 the object would ordinarily have. The value of this macro is used 890 instead of that alignment to align the object. 891 892 If this macro is not defined, then ALIGN is used. 893 894 One use of this macro is to increase alignment of medium-size 895 data to make it all fit in fewer cache lines. Another is to 896 cause character arrays to be word-aligned so that `strcpy' calls 897 that copy constants to character arrays can be done inline. */ 898 899 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 900 ix86_data_alignment ((TYPE), (ALIGN), true) 901 902 /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates 903 some alignment increase, instead of optimization only purposes. E.g. 904 AMD x86-64 psABI says that variables with array type larger than 15 bytes 905 must be aligned to 16 byte boundaries. 906 907 If this macro is not defined, then ALIGN is used. */ 908 909 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ 910 ix86_data_alignment ((TYPE), (ALIGN), false) 911 912 /* If defined, a C expression to compute the alignment for a local 913 variable. TYPE is the data type, and ALIGN is the alignment that 914 the object would ordinarily have. The value of this macro is used 915 instead of that alignment to align the object. 916 917 If this macro is not defined, then ALIGN is used. 918 919 One use of this macro is to increase alignment of medium-size 920 data to make it all fit in fewer cache lines. */ 921 922 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 923 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) 924 925 /* If defined, a C expression to compute the alignment for stack slot. 926 TYPE is the data type, MODE is the widest mode available, and ALIGN 927 is the alignment that the slot would ordinarily have. The value of 928 this macro is used instead of that alignment to align the slot. 929 930 If this macro is not defined, then ALIGN is used when TYPE is NULL, 931 Otherwise, LOCAL_ALIGNMENT will be used. 932 933 One use of this macro is to set alignment of stack slot to the 934 maximum alignment of all possible modes which the slot may have. */ 935 936 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ 937 ix86_local_alignment ((TYPE), (MODE), (ALIGN)) 938 939 /* If defined, a C expression to compute the alignment for a local 940 variable DECL. 941 942 If this macro is not defined, then 943 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. 944 945 One use of this macro is to increase alignment of medium-size 946 data to make it all fit in fewer cache lines. */ 947 948 #define LOCAL_DECL_ALIGNMENT(DECL) \ 949 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) 950 951 /* If defined, a C expression to compute the minimum required alignment 952 for dynamic stack realignment purposes for EXP (a TYPE or DECL), 953 MODE, assuming normal alignment ALIGN. 954 955 If this macro is not defined, then (ALIGN) will be used. */ 956 957 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ 958 ix86_minimum_alignment ((EXP), (MODE), (ALIGN)) 959 960 961 /* Set this nonzero if move instructions will actually fail to work 962 when given unaligned data. */ 963 #define STRICT_ALIGNMENT 0 964 965 /* If bit field type is int, don't let it cross an int, 966 and give entire struct the alignment of an int. */ 967 /* Required on the 386 since it doesn't have bit-field insns. */ 968 #define PCC_BITFIELD_TYPE_MATTERS 1 969 970 /* Standard register usage. */ 971 972 /* This processor has special stack-like registers. See reg-stack.c 973 for details. */ 974 975 #define STACK_REGS 976 977 #define IS_STACK_MODE(MODE) \ 978 (X87_FLOAT_MODE_P (MODE) \ 979 && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \ 980 || TARGET_MIX_SSE_I387)) 981 982 /* Number of actual hardware registers. 983 The hardware registers are assigned numbers for the compiler 984 from 0 to just below FIRST_PSEUDO_REGISTER. 985 All registers that the compiler knows about must be given numbers, 986 even those that are not normally considered general registers. 987 988 In the 80386 we give the 8 general purpose registers the numbers 0-7. 989 We number the floating point registers 8-15. 990 Note that registers 0-7 can be accessed as a short or int, 991 while only 0-3 may be used with byte `mov' instructions. 992 993 Reg 16 does not correspond to any hardware register, but instead 994 appears in the RTL as an argument pointer prior to reload, and is 995 eliminated during reloading in favor of either the stack or frame 996 pointer. */ 997 998 #define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG 999 1000 /* Number of hardware registers that go into the DWARF-2 unwind info. 1001 If not defined, equals FIRST_PSEUDO_REGISTER. */ 1002 1003 #define DWARF_FRAME_REGISTERS 17 1004 1005 /* 1 for registers that have pervasive standard uses 1006 and are not available for the register allocator. 1007 On the 80386, the stack pointer is such, as is the arg pointer. 1008 1009 REX registers are disabled for 32bit targets in 1010 TARGET_CONDITIONAL_REGISTER_USAGE. */ 1011 1012 #define FIXED_REGISTERS \ 1013 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 1014 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 1015 /*arg,flags,fpsr,fpcr,frame*/ \ 1016 1, 1, 1, 1, 1, \ 1017 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 1018 0, 0, 0, 0, 0, 0, 0, 0, \ 1019 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 1020 0, 0, 0, 0, 0, 0, 0, 0, \ 1021 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 1022 0, 0, 0, 0, 0, 0, 0, 0, \ 1023 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 1024 0, 0, 0, 0, 0, 0, 0, 0, \ 1025 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 1026 0, 0, 0, 0, 0, 0, 0, 0, \ 1027 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 1028 0, 0, 0, 0, 0, 0, 0, 0, \ 1029 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 1030 0, 0, 0, 0, 0, 0, 0, 0, \ 1031 /* b0, b1, b2, b3*/ \ 1032 0, 0, 0, 0 } 1033 1034 /* 1 for registers not available across function calls. 1035 These must include the FIXED_REGISTERS and also any 1036 registers that can be used without being saved. 1037 The latter must include the registers where values are returned 1038 and the register where structure-value addresses are passed. 1039 Aside from that, you can include as many other registers as you like. 1040 1041 Value is set to 1 if the register is call used unconditionally. 1042 Bit one is set if the register is call used on TARGET_32BIT ABI. 1043 Bit two is set if the register is call used on TARGET_64BIT ABI. 1044 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. 1045 1046 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ 1047 1048 #define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \ 1049 ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1)) 1050 1051 #define CALL_USED_REGISTERS \ 1052 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 1053 { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1054 /*arg,flags,fpsr,fpcr,frame*/ \ 1055 1, 1, 1, 1, 1, \ 1056 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 1057 1, 1, 1, 1, 1, 1, 6, 6, \ 1058 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 1059 1, 1, 1, 1, 1, 1, 1, 1, \ 1060 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 1061 1, 1, 1, 1, 2, 2, 2, 2, \ 1062 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 1063 6, 6, 6, 6, 6, 6, 6, 6, \ 1064 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 1065 6, 6, 6, 6, 6, 6, 6, 6, \ 1066 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 1067 6, 6, 6, 6, 6, 6, 6, 6, \ 1068 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 1069 1, 1, 1, 1, 1, 1, 1, 1, \ 1070 /* b0, b1, b2, b3*/ \ 1071 1, 1, 1, 1 } 1072 1073 /* Order in which to allocate registers. Each register must be 1074 listed once, even those in FIXED_REGISTERS. List frame pointer 1075 late and fixed registers last. Note that, in general, we prefer 1076 registers listed in CALL_USED_REGISTERS, keeping the others 1077 available for storage of persistent values. 1078 1079 The ADJUST_REG_ALLOC_ORDER actually overwrite the order, 1080 so this is just empty initializer for array. */ 1081 1082 #define REG_ALLOC_ORDER \ 1083 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 1084 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 1085 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 1086 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \ 1087 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, \ 1088 78, 79, 80 } 1089 1090 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order 1091 to be rearranged based on a particular function. When using sse math, 1092 we want to allocate SSE before x87 registers and vice versa. */ 1093 1094 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () 1095 1096 1097 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) 1098 1099 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 1100 (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \ 1101 && GENERAL_REGNO_P (REGNO) \ 1102 && ((MODE) == XFmode || (MODE) == XCmode)) 1103 1104 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 1105 1106 #define VALID_AVX256_REG_MODE(MODE) \ 1107 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1108 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ 1109 || (MODE) == V4DFmode) 1110 1111 #define VALID_AVX256_REG_OR_OI_MODE(MODE) \ 1112 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) 1113 1114 #define VALID_AVX512F_SCALAR_MODE(MODE) \ 1115 ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \ 1116 || (MODE) == SFmode) 1117 1118 #define VALID_AVX512F_REG_MODE(MODE) \ 1119 ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ 1120 || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ 1121 || (MODE) == V4TImode) 1122 1123 #define VALID_AVX512F_REG_OR_XI_MODE(MODE) \ 1124 (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode) 1125 1126 #define VALID_AVX512VL_128_REG_MODE(MODE) \ 1127 ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ 1128 || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \ 1129 || (MODE) == TFmode || (MODE) == V1TImode) 1130 1131 #define VALID_SSE2_REG_MODE(MODE) \ 1132 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1133 || (MODE) == V2DImode || (MODE) == DFmode) 1134 1135 #define VALID_SSE_REG_MODE(MODE) \ 1136 ((MODE) == V1TImode || (MODE) == TImode \ 1137 || (MODE) == V4SFmode || (MODE) == V4SImode \ 1138 || (MODE) == SFmode || (MODE) == TFmode) 1139 1140 #define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1141 ((MODE) == V2SFmode || (MODE) == SFmode) 1142 1143 #define VALID_MMX_REG_MODE(MODE) \ 1144 ((MODE == V1DImode) || (MODE) == DImode \ 1145 || (MODE) == V2SImode || (MODE) == SImode \ 1146 || (MODE) == V4HImode || (MODE) == V8QImode) 1147 1148 #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) 1149 1150 #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) 1151 1152 #define VALID_BND_REG_MODE(MODE) \ 1153 (TARGET_64BIT ? (MODE) == BND64mode : (MODE) == BND32mode) 1154 1155 #define VALID_DFP_MODE_P(MODE) \ 1156 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) 1157 1158 #define VALID_FP_MODE_P(MODE) \ 1159 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 1160 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 1161 1162 #define VALID_INT_MODE_P(MODE) \ 1163 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1164 || (MODE) == DImode \ 1165 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1166 || (MODE) == CDImode \ 1167 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 1168 || (MODE) == TFmode || (MODE) == TCmode))) 1169 1170 /* Return true for modes passed in SSE registers. */ 1171 #define SSE_REG_MODE_P(MODE) \ 1172 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ 1173 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1174 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1175 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1176 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ 1177 || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \ 1178 || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \ 1179 || (MODE) == V16SFmode) 1180 1181 #define X87_FLOAT_MODE_P(MODE) \ 1182 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) 1183 1184 #define SSE_FLOAT_MODE_P(MODE) \ 1185 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1186 1187 #define FMA4_VEC_FLOAT_MODE_P(MODE) \ 1188 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ 1189 || (MODE) == V8SFmode || (MODE) == V4DFmode)) 1190 1191 /* It is possible to write patterns to move flags; but until someone 1192 does it, */ 1193 #define AVOID_CCMODE_COPIES 1194 1195 /* Specify the modes required to caller save a given hard regno. 1196 We do this on i386 to prevent flags from being saved at all. 1197 1198 Kill any attempts to combine saving of modes. */ 1199 1200 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1201 (CC_REGNO_P (REGNO) ? VOIDmode \ 1202 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1203 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ 1204 : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \ 1205 && TARGET_PARTIAL_REG_STALL) \ 1206 || MASK_REGNO_P (REGNO)) ? SImode \ 1207 : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \ 1208 || MASK_REGNO_P (REGNO)) ? SImode \ 1209 : (MODE)) 1210 1211 /* Specify the registers used for certain standard purposes. 1212 The values of these macros are register numbers. */ 1213 1214 /* on the 386 the pc register is %eip, and is not usable as a general 1215 register. The ordinary mov instructions won't work */ 1216 /* #define PC_REGNUM */ 1217 1218 /* Base register for access to arguments of the function. */ 1219 #define ARG_POINTER_REGNUM ARGP_REG 1220 1221 /* Register to use for pushing function arguments. */ 1222 #define STACK_POINTER_REGNUM SP_REG 1223 1224 /* Base register for access to local variables of the function. */ 1225 #define FRAME_POINTER_REGNUM FRAME_REG 1226 #define HARD_FRAME_POINTER_REGNUM BP_REG 1227 1228 #define FIRST_INT_REG AX_REG 1229 #define LAST_INT_REG SP_REG 1230 1231 #define FIRST_QI_REG AX_REG 1232 #define LAST_QI_REG BX_REG 1233 1234 /* First & last stack-like regs */ 1235 #define FIRST_STACK_REG ST0_REG 1236 #define LAST_STACK_REG ST7_REG 1237 1238 #define FIRST_SSE_REG XMM0_REG 1239 #define LAST_SSE_REG XMM7_REG 1240 1241 #define FIRST_MMX_REG MM0_REG 1242 #define LAST_MMX_REG MM7_REG 1243 1244 #define FIRST_REX_INT_REG R8_REG 1245 #define LAST_REX_INT_REG R15_REG 1246 1247 #define FIRST_REX_SSE_REG XMM8_REG 1248 #define LAST_REX_SSE_REG XMM15_REG 1249 1250 #define FIRST_EXT_REX_SSE_REG XMM16_REG 1251 #define LAST_EXT_REX_SSE_REG XMM31_REG 1252 1253 #define FIRST_MASK_REG MASK0_REG 1254 #define LAST_MASK_REG MASK7_REG 1255 1256 #define FIRST_BND_REG BND0_REG 1257 #define LAST_BND_REG BND3_REG 1258 1259 /* Override this in other tm.h files to cope with various OS lossage 1260 requiring a frame pointer. */ 1261 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1262 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1263 #endif 1264 1265 /* Make sure we can access arbitrary call frames. */ 1266 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1267 1268 /* Register to hold the addressing base for position independent 1269 code access to data items. We don't use PIC pointer for 64bit 1270 mode. Define the regnum to dummy value to prevent gcc from 1271 pessimizing code dealing with EBX. 1272 1273 To avoid clobbering a call-saved register unnecessarily, we renumber 1274 the pic register when possible. The change is visible after the 1275 prologue has been emitted. */ 1276 1277 #define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG) 1278 1279 #define PIC_OFFSET_TABLE_REGNUM \ 1280 (ix86_use_pseudo_pic_reg () \ 1281 ? (pic_offset_table_rtx \ 1282 ? INVALID_REGNUM \ 1283 : REAL_PIC_OFFSET_TABLE_REGNUM) \ 1284 : INVALID_REGNUM) 1285 1286 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1287 1288 /* This is overridden by <cygwin.h>. */ 1289 #define MS_AGGREGATE_RETURN 0 1290 1291 #define KEEP_AGGREGATE_RETURN_POINTER 0 1292 1293 /* Define the classes of registers for register constraints in the 1294 machine description. Also define ranges of constants. 1295 1296 One of the classes must always be named ALL_REGS and include all hard regs. 1297 If there is more than one class, another class must be named NO_REGS 1298 and contain no registers. 1299 1300 The name GENERAL_REGS must be the name of a class (or an alias for 1301 another name such as ALL_REGS). This is the class of registers 1302 that is allowed by "g" or "r" in a register constraint. 1303 Also, registers outside this class are allocated only when 1304 instructions express preferences for them. 1305 1306 The classes must be numbered in nondecreasing order; that is, 1307 a larger-numbered class must never be contained completely 1308 in a smaller-numbered class. This is why CLOBBERED_REGS class 1309 is listed early, even though in 64-bit mode it contains more 1310 registers than just %eax, %ecx, %edx. 1311 1312 For any two classes, it is very desirable that there be another 1313 class that represents their union. 1314 1315 It might seem that class BREG is unnecessary, since no useful 386 1316 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1317 and the "b" register constraint is useful in asms for syscalls. 1318 1319 The flags, fpsr and fpcr registers are in no class. */ 1320 1321 enum reg_class 1322 { 1323 NO_REGS, 1324 AREG, DREG, CREG, BREG, SIREG, DIREG, 1325 AD_REGS, /* %eax/%edx for DImode */ 1326 CLOBBERED_REGS, /* call-clobbered integer registers */ 1327 Q_REGS, /* %eax %ebx %ecx %edx */ 1328 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1329 TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */ 1330 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1331 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1332 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp 1333 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ 1334 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1335 FLOAT_REGS, 1336 SSE_FIRST_REG, 1337 NO_REX_SSE_REGS, 1338 SSE_REGS, 1339 EVEX_SSE_REGS, 1340 BND_REGS, 1341 ALL_SSE_REGS, 1342 MMX_REGS, 1343 FP_TOP_SSE_REGS, 1344 FP_SECOND_SSE_REGS, 1345 FLOAT_SSE_REGS, 1346 FLOAT_INT_REGS, 1347 INT_SSE_REGS, 1348 FLOAT_INT_SSE_REGS, 1349 MASK_EVEX_REGS, 1350 MASK_REGS, 1351 MOD4_SSE_REGS, 1352 ALL_REGS, LIM_REG_CLASSES 1353 }; 1354 1355 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1356 1357 #define INTEGER_CLASS_P(CLASS) \ 1358 reg_class_subset_p ((CLASS), GENERAL_REGS) 1359 #define FLOAT_CLASS_P(CLASS) \ 1360 reg_class_subset_p ((CLASS), FLOAT_REGS) 1361 #define SSE_CLASS_P(CLASS) \ 1362 reg_class_subset_p ((CLASS), ALL_SSE_REGS) 1363 #define MMX_CLASS_P(CLASS) \ 1364 ((CLASS) == MMX_REGS) 1365 #define MASK_CLASS_P(CLASS) \ 1366 reg_class_subset_p ((CLASS), MASK_REGS) 1367 #define MAYBE_INTEGER_CLASS_P(CLASS) \ 1368 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1369 #define MAYBE_FLOAT_CLASS_P(CLASS) \ 1370 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1371 #define MAYBE_SSE_CLASS_P(CLASS) \ 1372 reg_classes_intersect_p ((CLASS), ALL_SSE_REGS) 1373 #define MAYBE_MMX_CLASS_P(CLASS) \ 1374 reg_classes_intersect_p ((CLASS), MMX_REGS) 1375 #define MAYBE_MASK_CLASS_P(CLASS) \ 1376 reg_classes_intersect_p ((CLASS), MASK_REGS) 1377 1378 #define Q_CLASS_P(CLASS) \ 1379 reg_class_subset_p ((CLASS), Q_REGS) 1380 1381 #define MAYBE_NON_Q_CLASS_P(CLASS) \ 1382 reg_classes_intersect_p ((CLASS), NON_Q_REGS) 1383 1384 /* Give names of register classes as strings for dump file. */ 1385 1386 #define REG_CLASS_NAMES \ 1387 { "NO_REGS", \ 1388 "AREG", "DREG", "CREG", "BREG", \ 1389 "SIREG", "DIREG", \ 1390 "AD_REGS", \ 1391 "CLOBBERED_REGS", \ 1392 "Q_REGS", "NON_Q_REGS", \ 1393 "TLS_GOTBASE_REGS", \ 1394 "INDEX_REGS", \ 1395 "LEGACY_REGS", \ 1396 "GENERAL_REGS", \ 1397 "FP_TOP_REG", "FP_SECOND_REG", \ 1398 "FLOAT_REGS", \ 1399 "SSE_FIRST_REG", \ 1400 "NO_REX_SSE_REGS", \ 1401 "SSE_REGS", \ 1402 "EVEX_SSE_REGS", \ 1403 "BND_REGS", \ 1404 "ALL_SSE_REGS", \ 1405 "MMX_REGS", \ 1406 "FP_TOP_SSE_REGS", \ 1407 "FP_SECOND_SSE_REGS", \ 1408 "FLOAT_SSE_REGS", \ 1409 "FLOAT_INT_REGS", \ 1410 "INT_SSE_REGS", \ 1411 "FLOAT_INT_SSE_REGS", \ 1412 "MASK_EVEX_REGS", \ 1413 "MASK_REGS", \ 1414 "MOD4_SSE_REGS", \ 1415 "ALL_REGS" } 1416 1417 /* Define which registers fit in which classes. This is an initializer 1418 for a vector of HARD_REG_SET of length N_REG_CLASSES. 1419 1420 Note that CLOBBERED_REGS are calculated by 1421 TARGET_CONDITIONAL_REGISTER_USAGE. */ 1422 1423 #define REG_CLASS_CONTENTS \ 1424 { { 0x00, 0x0, 0x0 }, \ 1425 { 0x01, 0x0, 0x0 }, /* AREG */ \ 1426 { 0x02, 0x0, 0x0 }, /* DREG */ \ 1427 { 0x04, 0x0, 0x0 }, /* CREG */ \ 1428 { 0x08, 0x0, 0x0 }, /* BREG */ \ 1429 { 0x10, 0x0, 0x0 }, /* SIREG */ \ 1430 { 0x20, 0x0, 0x0 }, /* DIREG */ \ 1431 { 0x03, 0x0, 0x0 }, /* AD_REGS */ \ 1432 { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \ 1433 { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ 1434 { 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \ 1435 { 0x7e, 0x1fe0, 0x0 }, /* TLS_GOTBASE_REGS */ \ 1436 { 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \ 1437 { 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ 1438 { 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \ 1439 { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ 1440 { 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ 1441 { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ 1442 { 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \ 1443 { 0x1fe00000, 0x000000, 0x0 }, /* NO_REX_SSE_REGS */ \ 1444 { 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \ 1445 { 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \ 1446 { 0x0, 0x0,0x1e000 }, /* BND_REGS */ \ 1447 { 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \ 1448 { 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \ 1449 { 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \ 1450 { 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \ 1451 { 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \ 1452 { 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \ 1453 { 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \ 1454 { 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \ 1455 { 0x0, 0x0, 0x1fc0 }, /* MASK_EVEX_REGS */ \ 1456 { 0x0, 0x0, 0x1fe0 }, /* MASK_REGS */ \ 1457 { 0x1fe00000,0xffffe000, 0x1f }, /* MOD4_SSE_REGS */ \ 1458 { 0xffffffff,0xffffffff,0x1ffff } \ 1459 } 1460 1461 /* The same information, inverted: 1462 Return the class number of the smallest class containing 1463 reg number REGNO. This could be a conditional expression 1464 or could index an array. */ 1465 1466 #define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)]) 1467 1468 /* When this hook returns true for MODE, the compiler allows 1469 registers explicitly used in the rtl to be used as spill registers 1470 but prevents the compiler from extending the lifetime of these 1471 registers. */ 1472 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 1473 1474 #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) 1475 #define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG) 1476 1477 #define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X))) 1478 #define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG)) 1479 1480 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1481 #define REX_INT_REGNO_P(N) \ 1482 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) 1483 1484 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1485 #define GENERAL_REGNO_P(N) \ 1486 (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N)) 1487 1488 #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) 1489 #define ANY_QI_REGNO_P(N) \ 1490 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) 1491 1492 #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) 1493 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) 1494 1495 #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) 1496 #define SSE_REGNO_P(N) \ 1497 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ 1498 || REX_SSE_REGNO_P (N) \ 1499 || EXT_REX_SSE_REGNO_P (N)) 1500 1501 #define REX_SSE_REGNO_P(N) \ 1502 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) 1503 1504 #define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X))) 1505 1506 #define EXT_REX_SSE_REGNO_P(N) \ 1507 IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG) 1508 1509 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1510 #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) 1511 1512 #define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) 1513 #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG) 1514 1515 #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) 1516 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) 1517 1518 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1519 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1520 1521 #define BND_REG_P(X) (REG_P (X) && BND_REGNO_P (REGNO (X))) 1522 #define BND_REGNO_P(N) IN_RANGE ((N), FIRST_BND_REG, LAST_BND_REG) 1523 1524 #define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X))) 1525 #define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \ 1526 || (N) == XMM4_REG \ 1527 || (N) == XMM8_REG \ 1528 || (N) == XMM12_REG \ 1529 || (N) == XMM16_REG \ 1530 || (N) == XMM20_REG \ 1531 || (N) == XMM24_REG \ 1532 || (N) == XMM28_REG) 1533 1534 /* First floating point reg */ 1535 #define FIRST_FLOAT_REG FIRST_STACK_REG 1536 #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG) 1537 1538 #define GET_SSE_REGNO(N) \ 1539 ((N) < 8 ? FIRST_SSE_REG + (N) \ 1540 : (N) < 16 ? FIRST_REX_SSE_REG + (N) - 8 \ 1541 : FIRST_EXT_REX_SSE_REG + (N) - 16) 1542 1543 /* The class value for index registers, and the one for base regs. */ 1544 1545 #define INDEX_REG_CLASS INDEX_REGS 1546 #define BASE_REG_CLASS GENERAL_REGS 1547 1548 /* Stack layout; function entry, exit and calling. */ 1549 1550 /* Define this if pushing a word on the stack 1551 makes the stack pointer a smaller address. */ 1552 #define STACK_GROWS_DOWNWARD 1 1553 1554 /* Define this to nonzero if the nominal address of the stack frame 1555 is at the high-address end of the local variables; 1556 that is, each additional local variable allocated 1557 goes at a more negative offset in the frame. */ 1558 #define FRAME_GROWS_DOWNWARD 1 1559 1560 #define PUSH_ROUNDING(BYTES) ix86_push_rounding (BYTES) 1561 1562 /* If defined, the maximum amount of space required for outgoing arguments 1563 will be computed and placed into the variable `crtl->outgoing_args_size'. 1564 No space will be pushed onto the stack for each call; instead, the 1565 function prologue should increase the stack frame size by this amount. 1566 1567 In 32bit mode enabling argument accumulation results in about 5% code size 1568 growth because move instructions are less compact than push. In 64bit 1569 mode the difference is less drastic but visible. 1570 1571 FIXME: Unlike earlier implementations, the size of unwind info seems to 1572 actually grow with accumulation. Is that because accumulated args 1573 unwind info became unnecesarily bloated? 1574 1575 With the 64-bit MS ABI, we can generate correct code with or without 1576 accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code 1577 generated without accumulated args is terrible. 1578 1579 If stack probes are required, the space used for large function 1580 arguments on the stack must also be probed, so enable 1581 -maccumulate-outgoing-args so this happens in the prologue. 1582 1583 We must use argument accumulation in interrupt function if stack 1584 may be realigned to avoid DRAP. */ 1585 1586 #define ACCUMULATE_OUTGOING_ARGS \ 1587 ((TARGET_ACCUMULATE_OUTGOING_ARGS \ 1588 && optimize_function_for_speed_p (cfun)) \ 1589 || (cfun->machine->func_type != TYPE_NORMAL \ 1590 && crtl->stack_realign_needed) \ 1591 || TARGET_STACK_PROBE \ 1592 || TARGET_64BIT_MS_ABI \ 1593 || (TARGET_MACHO && crtl->profile)) 1594 1595 /* If defined, a C expression whose value is nonzero when we want to use PUSH 1596 instructions to pass outgoing arguments. */ 1597 1598 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1599 1600 /* We want the stack and args grow in opposite directions, even if 1601 PUSH_ARGS is 0. */ 1602 #define PUSH_ARGS_REVERSED 1 1603 1604 /* Offset of first parameter from the argument pointer register value. */ 1605 #define FIRST_PARM_OFFSET(FNDECL) 0 1606 1607 /* Define this macro if functions should assume that stack space has been 1608 allocated for arguments even when their values are passed in registers. 1609 1610 The value of this macro is the size, in bytes, of the area reserved for 1611 arguments passed in registers for the function represented by FNDECL. 1612 1613 This space can be allocated by the caller, or be a part of the 1614 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1615 which. */ 1616 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) 1617 1618 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ 1619 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) 1620 1621 /* Define how to find the value returned by a library function 1622 assuming the value has mode MODE. */ 1623 1624 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) 1625 1626 /* Define the size of the result block used for communication between 1627 untyped_call and untyped_return. The block contains a DImode value 1628 followed by the block used by fnsave and frstor. */ 1629 1630 #define APPLY_RESULT_SIZE (8+108) 1631 1632 /* 1 if N is a possible register number for function argument passing. */ 1633 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1634 1635 /* Define a data type for recording info about an argument list 1636 during the scan of that argument list. This data type should 1637 hold all necessary information about the function itself 1638 and about the args processed so far, enough to enable macros 1639 such as FUNCTION_ARG to determine where the next arg should go. */ 1640 1641 typedef struct ix86_args { 1642 int words; /* # words passed so far */ 1643 int nregs; /* # registers available for passing */ 1644 int regno; /* next available register number */ 1645 int fastcall; /* fastcall or thiscall calling convention 1646 is used */ 1647 int sse_words; /* # sse words passed so far */ 1648 int sse_nregs; /* # sse registers available for passing */ 1649 int warn_avx512f; /* True when we want to warn 1650 about AVX512F ABI. */ 1651 int warn_avx; /* True when we want to warn about AVX ABI. */ 1652 int warn_sse; /* True when we want to warn about SSE ABI. */ 1653 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1654 int warn_empty; /* True when we want to warn about empty classes 1655 passing ABI change. */ 1656 int sse_regno; /* next available sse register number */ 1657 int mmx_words; /* # mmx words passed so far */ 1658 int mmx_nregs; /* # mmx registers available for passing */ 1659 int mmx_regno; /* next available mmx register number */ 1660 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1661 int caller; /* true if it is caller. */ 1662 int float_in_sse; /* Set to 1 or 2 for 32bit targets if 1663 SFmode/DFmode arguments should be passed 1664 in SSE registers. Otherwise 0. */ 1665 int bnd_regno; /* next available bnd register number */ 1666 int bnds_in_bt; /* number of bounds expected in BT. */ 1667 int force_bnd_pass; /* number of bounds expected for stdarg arg. */ 1668 int stdarg; /* Set to 1 if function is stdarg. */ 1669 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise 1670 MS_ABI for ms abi. */ 1671 tree decl; /* Callee decl. */ 1672 } CUMULATIVE_ARGS; 1673 1674 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1675 for a call to a function whose data type is FNTYPE. 1676 For a library call, FNTYPE is 0. */ 1677 1678 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1679 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ 1680 (N_NAMED_ARGS) != -1) 1681 1682 /* Output assembler code to FILE to increment profiler label # LABELNO 1683 for profiling a function entry. */ 1684 1685 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1686 x86_function_profiler ((FILE), (LABELNO)) 1687 1688 #define MCOUNT_NAME "_mcount" 1689 1690 #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" 1691 1692 #define PROFILE_COUNT_REGISTER "edx" 1693 1694 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1695 the stack pointer does not matter. The value is tested only in 1696 functions that have frame pointers. 1697 No definition is equivalent to always zero. */ 1698 /* Note on the 386 it might be more efficient not to define this since 1699 we have to restore it ourselves from the frame pointer, in order to 1700 use pop */ 1701 1702 #define EXIT_IGNORE_STACK 1 1703 1704 /* Define this macro as a C expression that is nonzero for registers 1705 used by the epilogue or the `return' pattern. */ 1706 1707 #define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO) 1708 1709 /* Output assembler code for a block containing the constant parts 1710 of a trampoline, leaving space for the variable parts. */ 1711 1712 /* On the 386, the trampoline contains two instructions: 1713 mov #STATIC,ecx 1714 jmp FUNCTION 1715 The trampoline is generated entirely at runtime. The operand of JMP 1716 is the address of FUNCTION relative to the instruction following the 1717 JMP (which is 5 bytes long). */ 1718 1719 /* Length in units of the trampoline for entering a nested function. */ 1720 1721 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 28 : 14) 1722 1723 /* Definitions for register eliminations. 1724 1725 This is an array of structures. Each structure initializes one pair 1726 of eliminable registers. The "from" register number is given first, 1727 followed by "to". Eliminations of the same "from" register are listed 1728 in order of preference. 1729 1730 There are two registers that can always be eliminated on the i386. 1731 The frame pointer and the arg pointer can be replaced by either the 1732 hard frame pointer or to the stack pointer, depending upon the 1733 circumstances. The hard frame pointer is not used before reload and 1734 so it is not eligible for elimination. */ 1735 1736 #define ELIMINABLE_REGS \ 1737 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1738 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1739 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1740 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1741 1742 /* Define the offset between two registers, one to be eliminated, and the other 1743 its replacement, at the start of a routine. */ 1744 1745 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1746 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1747 1748 /* Addressing modes, and classification of registers for them. */ 1749 1750 /* Macros to check register numbers against specific register classes. */ 1751 1752 /* These assume that REGNO is a hard or pseudo reg number. 1753 They give nonzero only if REGNO is a hard reg of the suitable class 1754 or a pseudo reg currently allocated to a suitable hard reg. 1755 Since they use reg_renumber, they are safe only once reg_renumber 1756 has been allocated, which happens in reginfo.c during register 1757 allocation. */ 1758 1759 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1760 ((REGNO) < STACK_POINTER_REGNUM \ 1761 || REX_INT_REGNO_P (REGNO) \ 1762 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ 1763 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1764 1765 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1766 (GENERAL_REGNO_P (REGNO) \ 1767 || (REGNO) == ARG_POINTER_REGNUM \ 1768 || (REGNO) == FRAME_POINTER_REGNUM \ 1769 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1770 1771 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1772 and check its validity for a certain class. 1773 We have two alternate definitions for each of them. 1774 The usual definition accepts all pseudo regs; the other rejects 1775 them unless they have been allocated suitable hard regs. 1776 The symbol REG_OK_STRICT causes the latter definition to be used. 1777 1778 Most source files want to accept pseudo regs in the hope that 1779 they will get allocated to the class that the insn wants them to be in. 1780 Source files for reload pass need to be strict. 1781 After reload, it makes no difference, since pseudo regs have 1782 been eliminated by then. */ 1783 1784 1785 /* Non strict versions, pseudos are ok. */ 1786 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1787 (REGNO (X) < STACK_POINTER_REGNUM \ 1788 || REX_INT_REGNO_P (REGNO (X)) \ 1789 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1790 1791 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1792 (GENERAL_REGNO_P (REGNO (X)) \ 1793 || REGNO (X) == ARG_POINTER_REGNUM \ 1794 || REGNO (X) == FRAME_POINTER_REGNUM \ 1795 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1796 1797 /* Strict versions, hard registers only */ 1798 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1799 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1800 1801 #ifndef REG_OK_STRICT 1802 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1803 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1804 1805 #else 1806 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1807 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1808 #endif 1809 1810 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression 1811 that is a valid memory address for an instruction. 1812 The MODE argument is the machine mode for the MEM expression 1813 that wants to use this address. 1814 1815 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, 1816 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1817 1818 See legitimize_pic_address in i386.c for details as to what 1819 constitutes a legitimate address when -fpic is used. */ 1820 1821 #define MAX_REGS_PER_ADDRESS 2 1822 1823 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1824 1825 /* If defined, a C expression to determine the base term of address X. 1826 This macro is used in only one place: `find_base_term' in alias.c. 1827 1828 It is always safe for this macro to not be defined. It exists so 1829 that alias analysis can understand machine-dependent addresses. 1830 1831 The typical use of this macro is to handle addresses containing 1832 a label_ref or symbol_ref within an UNSPEC. */ 1833 1834 #define FIND_BASE_TERM(X) ix86_find_base_term (X) 1835 1836 /* Nonzero if the constant value X is a legitimate general operand 1837 when generating PIC code. It is given that flag_pic is on and 1838 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1839 1840 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1841 1842 #define SYMBOLIC_CONST(X) \ 1843 (GET_CODE (X) == SYMBOL_REF \ 1844 || GET_CODE (X) == LABEL_REF \ 1845 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1846 1847 /* Max number of args passed in registers. If this is more than 3, we will 1848 have problems with ebx (register #4), since it is a caller save register and 1849 is also used as the pic register in ELF. So for now, don't allow more than 1850 3 registers to be passed in registers. */ 1851 1852 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ 1853 #define X86_64_REGPARM_MAX 6 1854 #define X86_64_MS_REGPARM_MAX 4 1855 1856 #define X86_32_REGPARM_MAX 3 1857 1858 #define REGPARM_MAX \ 1859 (TARGET_64BIT \ 1860 ? (TARGET_64BIT_MS_ABI \ 1861 ? X86_64_MS_REGPARM_MAX \ 1862 : X86_64_REGPARM_MAX) \ 1863 : X86_32_REGPARM_MAX) 1864 1865 #define X86_64_SSE_REGPARM_MAX 8 1866 #define X86_64_MS_SSE_REGPARM_MAX 4 1867 1868 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) 1869 1870 #define SSE_REGPARM_MAX \ 1871 (TARGET_64BIT \ 1872 ? (TARGET_64BIT_MS_ABI \ 1873 ? X86_64_MS_SSE_REGPARM_MAX \ 1874 : X86_64_SSE_REGPARM_MAX) \ 1875 : X86_32_SSE_REGPARM_MAX) 1876 1877 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1878 1879 /* Specify the machine mode that this machine uses 1880 for the index in the tablejump instruction. */ 1881 #define CASE_VECTOR_MODE \ 1882 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) 1883 1884 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1885 #define DEFAULT_SIGNED_CHAR 1 1886 1887 /* Max number of bytes we can move from memory to memory 1888 in one reasonably fast instruction. */ 1889 #define MOVE_MAX 16 1890 1891 /* MOVE_MAX_PIECES is the number of bytes at a time which we can 1892 move efficiently, as opposed to MOVE_MAX which is the maximum 1893 number of bytes we can move with a single instruction. 1894 1895 ??? We should use TImode in 32-bit mode and use OImode or XImode 1896 if they are available. But since by_pieces_ninsns determines the 1897 widest mode with MAX_FIXED_MODE_SIZE, we can only use TImode in 1898 64-bit mode. */ 1899 #define MOVE_MAX_PIECES \ 1900 ((TARGET_64BIT \ 1901 && TARGET_SSE2 \ 1902 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ 1903 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \ 1904 ? GET_MODE_SIZE (TImode) : UNITS_PER_WORD) 1905 1906 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1907 move-instruction pairs, we will do a movmem or libcall instead. 1908 Increasing the value will always make code faster, but eventually 1909 incurs high cost in increased code size. 1910 1911 If you don't define this, a reasonable default is used. */ 1912 1913 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) 1914 1915 /* If a clear memory operation would take CLEAR_RATIO or more simple 1916 move-instruction sequences, we will do a clrmem or libcall instead. */ 1917 1918 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) 1919 1920 /* Define if shifts truncate the shift count which implies one can 1921 omit a sign-extension or zero-extension of a shift count. 1922 1923 On i386, shifts do truncate the count. But bit test instructions 1924 take the modulo of the bit offset operand. */ 1925 1926 /* #define SHIFT_COUNT_TRUNCATED */ 1927 1928 /* A macro to update M and UNSIGNEDP when an object whose type is 1929 TYPE and which has the specified mode and signedness is to be 1930 stored in a register. This macro is only called when TYPE is a 1931 scalar type. 1932 1933 On i386 it is sometimes useful to promote HImode and QImode 1934 quantities to SImode. The choice depends on target type. */ 1935 1936 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1937 do { \ 1938 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1939 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1940 (MODE) = SImode; \ 1941 } while (0) 1942 1943 /* Specify the machine mode that pointers have. 1944 After generation of rtl, the compiler makes no further distinction 1945 between pointers and any other objects of this machine mode. */ 1946 #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) 1947 1948 /* Supply a definition of STACK_SAVEAREA_MODE for emit_stack_save. 1949 NONLOCAL needs space to save both shadow stack and stack pointers. 1950 1951 FIXME: We only need to save and restore stack pointer in ptr_mode. 1952 But expand_builtin_setjmp_setup and expand_builtin_longjmp use Pmode 1953 to save and restore stack pointer. See 1954 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84150 1955 */ 1956 #define STACK_SAVEAREA_MODE(LEVEL) \ 1957 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode) 1958 1959 /* Specify the machine mode that bounds have. */ 1960 #define BNDmode (ix86_pmode == PMODE_DI ? BND64mode : BND32mode) 1961 1962 /* A C expression whose value is zero if pointers that need to be extended 1963 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 1964 greater then zero if they are zero-extended and less then zero if the 1965 ptr_extend instruction should be used. */ 1966 1967 #define POINTERS_EXTEND_UNSIGNED 1 1968 1969 /* A function address in a call instruction 1970 is a byte address (for indexing purposes) 1971 so give the MEM rtx a byte's mode. */ 1972 #define FUNCTION_MODE QImode 1973 1974 1975 /* A C expression for the cost of a branch instruction. A value of 1 1976 is the default; other values are interpreted relative to that. */ 1977 1978 #define BRANCH_COST(speed_p, predictable_p) \ 1979 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) 1980 1981 /* An integer expression for the size in bits of the largest integer machine 1982 mode that should actually be used. We allow pairs of registers. */ 1983 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 1984 1985 /* Define this macro as a C expression which is nonzero if accessing 1986 less than a word of memory (i.e. a `char' or a `short') is no 1987 faster than accessing a word of memory, i.e., if such access 1988 require more than one instruction or if there is no difference in 1989 cost between byte and (aligned) word loads. 1990 1991 When this macro is not defined, the compiler will access a field by 1992 finding the smallest containing object; when it is defined, a 1993 fullword load will be used if alignment permits. Unless bytes 1994 accesses are faster than word accesses, using word accesses is 1995 preferable since it may eliminate subsequent memory access if 1996 subsequent accesses occur to other fields in the same word of the 1997 structure, but to different bytes. */ 1998 1999 #define SLOW_BYTE_ACCESS 0 2000 2001 /* Nonzero if access to memory by shorts is slow and undesirable. */ 2002 #define SLOW_SHORT_ACCESS 0 2003 2004 /* Define this macro if it is as good or better to call a constant 2005 function address than to call an address kept in a register. 2006 2007 Desirable on the 386 because a CALL with a constant address is 2008 faster than one with a register address. */ 2009 2010 #define NO_FUNCTION_CSE 1 2011 2012 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2013 return the mode to be used for the comparison. 2014 2015 For floating-point equality comparisons, CCFPEQmode should be used. 2016 VOIDmode should be used in all other cases. 2017 2018 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 2019 possible, to allow for more combinations. */ 2020 2021 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 2022 2023 /* Return nonzero if MODE implies a floating point inequality can be 2024 reversed. */ 2025 2026 #define REVERSIBLE_CC_MODE(MODE) 1 2027 2028 /* A C expression whose value is reversed condition code of the CODE for 2029 comparison done in CC_MODE mode. */ 2030 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 2031 2032 2033 /* Control the assembler format that we output, to the extent 2034 this does not vary between assemblers. */ 2035 2036 /* How to refer to registers in assembler output. 2037 This sequence is indexed by compiler's hard-register-number (see above). */ 2038 2039 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". 2040 For non floating point regs, the following are the HImode names. 2041 2042 For float regs, the stack top is sometimes referred to as "%st(0)" 2043 instead of just "%st". TARGET_PRINT_OPERAND handles this with the 2044 "y" code. */ 2045 2046 #define HI_REGISTER_NAMES \ 2047 {"ax","dx","cx","bx","si","di","bp","sp", \ 2048 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 2049 "argp", "flags", "fpsr", "fpcr", "frame", \ 2050 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2051 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ 2052 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2053 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \ 2054 "xmm16", "xmm17", "xmm18", "xmm19", \ 2055 "xmm20", "xmm21", "xmm22", "xmm23", \ 2056 "xmm24", "xmm25", "xmm26", "xmm27", \ 2057 "xmm28", "xmm29", "xmm30", "xmm31", \ 2058 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \ 2059 "bnd0", "bnd1", "bnd2", "bnd3" } 2060 2061 #define REGISTER_NAMES HI_REGISTER_NAMES 2062 2063 /* Table of additional register names to use in user input. */ 2064 2065 #define ADDITIONAL_REGISTER_NAMES \ 2066 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 2067 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 2068 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 2069 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 2070 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 2071 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 2072 { "ymm0", 21}, { "ymm1", 22}, { "ymm2", 23}, { "ymm3", 24}, \ 2073 { "ymm4", 25}, { "ymm5", 26}, { "ymm6", 27}, { "ymm7", 28}, \ 2074 { "ymm8", 45}, { "ymm9", 46}, { "ymm10", 47}, { "ymm11", 48}, \ 2075 { "ymm12", 49}, { "ymm13", 50}, { "ymm14", 51}, { "ymm15", 52}, \ 2076 { "ymm16", 53}, { "ymm17", 54}, { "ymm18", 55}, { "ymm19", 56}, \ 2077 { "ymm20", 57}, { "ymm21", 58}, { "ymm22", 59}, { "ymm23", 60}, \ 2078 { "ymm24", 61}, { "ymm25", 62}, { "ymm26", 63}, { "ymm27", 64}, \ 2079 { "ymm28", 65}, { "ymm29", 66}, { "ymm30", 67}, { "ymm31", 68}, \ 2080 { "zmm0", 21}, { "zmm1", 22}, { "zmm2", 23}, { "zmm3", 24}, \ 2081 { "zmm4", 25}, { "zmm5", 26}, { "zmm6", 27}, { "zmm7", 28}, \ 2082 { "zmm8", 45}, { "zmm9", 46}, { "zmm10", 47}, { "zmm11", 48}, \ 2083 { "zmm12", 49}, { "zmm13", 50}, { "zmm14", 51}, { "zmm15", 52}, \ 2084 { "zmm16", 53}, { "zmm17", 54}, { "zmm18", 55}, { "zmm19", 56}, \ 2085 { "zmm20", 57}, { "zmm21", 58}, { "zmm22", 59}, { "zmm23", 60}, \ 2086 { "zmm24", 61}, { "zmm25", 62}, { "zmm26", 63}, { "zmm27", 64}, \ 2087 { "zmm28", 65}, { "zmm29", 66}, { "zmm30", 67}, { "zmm31", 68} } 2088 2089 /* Note we are omitting these since currently I don't know how 2090 to get gcc to use these, since they want the same but different 2091 number as al, and ax. 2092 */ 2093 2094 #define QI_REGISTER_NAMES \ 2095 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 2096 2097 /* These parallel the array above, and can be used to access bits 8:15 2098 of regs 0 through 3. */ 2099 2100 #define QI_HIGH_REGISTER_NAMES \ 2101 {"ah", "dh", "ch", "bh", } 2102 2103 /* How to renumber registers for dbx and gdb. */ 2104 2105 #define DBX_REGISTER_NUMBER(N) \ 2106 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2107 2108 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2109 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2110 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2111 2112 /* Before the prologue, RA is at 0(%esp). */ 2113 #define INCOMING_RETURN_ADDR_RTX \ 2114 gen_rtx_MEM (Pmode, stack_pointer_rtx) 2115 2116 /* After the prologue, RA is at -4(AP) in the current frame. */ 2117 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2118 ((COUNT) == 0 \ 2119 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ 2120 -UNITS_PER_WORD)) \ 2121 : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD))) 2122 2123 /* PC is dbx register 8; let's use that column for RA. */ 2124 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2125 2126 /* Before the prologue, there are return address and error code for 2127 exception handler on the top of the frame. */ 2128 #define INCOMING_FRAME_SP_OFFSET \ 2129 (cfun->machine->func_type == TYPE_EXCEPTION \ 2130 ? 2 * UNITS_PER_WORD : UNITS_PER_WORD) 2131 2132 /* The value of INCOMING_FRAME_SP_OFFSET the assembler assumes in 2133 .cfi_startproc. */ 2134 #define DEFAULT_INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2135 2136 /* Describe how we implement __builtin_eh_return. */ 2137 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) 2138 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) 2139 2140 2141 /* Select a format to encode pointers in exception handling data. CODE 2142 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2143 true if the symbol may be affected by dynamic relocations. 2144 2145 ??? All x86 object file formats are capable of representing this. 2146 After all, the relocation needed is the same as for the call insn. 2147 Whether or not a particular assembler allows us to enter such, I 2148 guess we'll have to see. */ 2149 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2150 asm_preferred_eh_data_format ((CODE), (GLOBAL)) 2151 2152 /* These are a couple of extensions to the formats accepted 2153 by asm_fprintf: 2154 %z prints out opcode suffix for word-mode instruction 2155 %r prints out word-mode name for reg_names[arg] */ 2156 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 2157 case 'z': \ 2158 fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \ 2159 break; \ 2160 \ 2161 case 'r': \ 2162 { \ 2163 unsigned int regno = va_arg ((ARGS), int); \ 2164 if (LEGACY_INT_REGNO_P (regno)) \ 2165 fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \ 2166 fputs (reg_names[regno], (FILE)); \ 2167 break; \ 2168 } 2169 2170 /* This is how to output an insn to push a register on the stack. */ 2171 2172 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2173 asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO)) 2174 2175 /* This is how to output an insn to pop a register from the stack. */ 2176 2177 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2178 asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO)) 2179 2180 /* This is how to output an element of a case-vector that is absolute. */ 2181 2182 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2183 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2184 2185 /* This is how to output an element of a case-vector that is relative. */ 2186 2187 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2188 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2189 2190 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ 2191 2192 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ 2193 { \ 2194 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ 2195 (PTR) += TARGET_AVX ? 1 : 2; \ 2196 } 2197 2198 /* A C statement or statements which output an assembler instruction 2199 opcode to the stdio stream STREAM. The macro-operand PTR is a 2200 variable of type `char *' which points to the opcode name in 2201 its "internal" form--the form that is written in the machine 2202 description. */ 2203 2204 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 2205 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) 2206 2207 /* A C statement to output to the stdio stream FILE an assembler 2208 command to pad the location counter to a multiple of 1<<LOG 2209 bytes if it is within MAX_SKIP bytes. */ 2210 2211 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2212 #undef ASM_OUTPUT_MAX_SKIP_PAD 2213 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ 2214 if ((LOG) != 0) \ 2215 { \ 2216 if ((MAX_SKIP) == 0) \ 2217 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ 2218 else \ 2219 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ 2220 } 2221 #endif 2222 2223 /* Write the extra assembler code needed to declare a function 2224 properly. */ 2225 2226 #undef ASM_OUTPUT_FUNCTION_LABEL 2227 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ 2228 ix86_asm_output_function_label ((FILE), (NAME), (DECL)) 2229 2230 /* Under some conditions we need jump tables in the text section, 2231 because the assembler cannot handle label differences between 2232 sections. This is the case for x86_64 on Mach-O for example. */ 2233 2234 #define JUMP_TABLES_IN_TEXT_SECTION \ 2235 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ 2236 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) 2237 2238 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2239 and switch back. For x86 we do this only to save a few bytes that 2240 would otherwise be unused in the text section. */ 2241 #define CRT_MKSTR2(VAL) #VAL 2242 #define CRT_MKSTR(x) CRT_MKSTR2(x) 2243 2244 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2245 asm (SECTION_OP "\n\t" \ 2246 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ 2247 TEXT_SECTION_ASM_OP); 2248 2249 /* Default threshold for putting data in large sections 2250 with x86-64 medium memory model */ 2251 #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 2252 2253 /* Adjust the length of the insn with the length of BND prefix. */ 2254 2255 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 2256 do { \ 2257 if (NONDEBUG_INSN_P (INSN) && INSN_CODE (INSN) >= 0 \ 2258 && get_attr_maybe_prefix_bnd (INSN)) \ 2259 LENGTH += ix86_bnd_prefixed_insn_p (INSN); \ 2260 } while (0) 2261 2262 /* Which processor to tune code generation for. These must be in sync 2263 with processor_target_table in i386.c. */ 2264 2265 enum processor_type 2266 { 2267 PROCESSOR_GENERIC = 0, 2268 PROCESSOR_I386, /* 80386 */ 2269 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2270 PROCESSOR_PENTIUM, 2271 PROCESSOR_LAKEMONT, 2272 PROCESSOR_PENTIUMPRO, 2273 PROCESSOR_PENTIUM4, 2274 PROCESSOR_NOCONA, 2275 PROCESSOR_CORE2, 2276 PROCESSOR_NEHALEM, 2277 PROCESSOR_SANDYBRIDGE, 2278 PROCESSOR_HASWELL, 2279 PROCESSOR_BONNELL, 2280 PROCESSOR_SILVERMONT, 2281 PROCESSOR_KNL, 2282 PROCESSOR_KNM, 2283 PROCESSOR_SKYLAKE, 2284 PROCESSOR_SKYLAKE_AVX512, 2285 PROCESSOR_CANNONLAKE, 2286 PROCESSOR_ICELAKE_CLIENT, 2287 PROCESSOR_ICELAKE_SERVER, 2288 PROCESSOR_INTEL, 2289 PROCESSOR_GEODE, 2290 PROCESSOR_K6, 2291 PROCESSOR_ATHLON, 2292 PROCESSOR_K8, 2293 PROCESSOR_AMDFAM10, 2294 PROCESSOR_BDVER1, 2295 PROCESSOR_BDVER2, 2296 PROCESSOR_BDVER3, 2297 PROCESSOR_BDVER4, 2298 PROCESSOR_BTVER1, 2299 PROCESSOR_BTVER2, 2300 PROCESSOR_ZNVER1, 2301 PROCESSOR_max 2302 }; 2303 2304 extern enum processor_type ix86_tune; 2305 extern enum processor_type ix86_arch; 2306 2307 /* Size of the RED_ZONE area. */ 2308 #define RED_ZONE_SIZE 128 2309 /* Reserved area of the red zone for temporaries. */ 2310 #define RED_ZONE_RESERVE 8 2311 2312 extern unsigned int ix86_preferred_stack_boundary; 2313 extern unsigned int ix86_incoming_stack_boundary; 2314 2315 /* Smallest class containing REGNO. */ 2316 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2317 2318 enum ix86_fpcmp_strategy { 2319 IX86_FPCMP_SAHF, 2320 IX86_FPCMP_COMI, 2321 IX86_FPCMP_ARITH 2322 }; 2323 2324 /* To properly truncate FP values into integers, we need to set i387 control 2325 word. We can't emit proper mode switching code before reload, as spills 2326 generated by reload may truncate values incorrectly, but we still can avoid 2327 redundant computation of new control word by the mode switching pass. 2328 The fldcw instructions are still emitted redundantly, but this is probably 2329 not going to be noticeable problem, as most CPUs do have fast path for 2330 the sequence. 2331 2332 The machinery is to emit simple truncation instructions and split them 2333 before reload to instructions having USEs of two memory locations that 2334 are filled by this code to old and new control word. 2335 2336 Post-reload pass may be later used to eliminate the redundant fildcw if 2337 needed. */ 2338 2339 enum ix86_stack_slot 2340 { 2341 SLOT_TEMP = 0, 2342 SLOT_CW_STORED, 2343 SLOT_CW_TRUNC, 2344 SLOT_CW_FLOOR, 2345 SLOT_CW_CEIL, 2346 SLOT_CW_MASK_PM, 2347 SLOT_STV_TEMP, 2348 MAX_386_STACK_LOCALS 2349 }; 2350 2351 enum ix86_entity 2352 { 2353 X86_DIRFLAG = 0, 2354 AVX_U128, 2355 I387_TRUNC, 2356 I387_FLOOR, 2357 I387_CEIL, 2358 I387_MASK_PM, 2359 MAX_386_ENTITIES 2360 }; 2361 2362 enum x86_dirflag_state 2363 { 2364 X86_DIRFLAG_RESET, 2365 X86_DIRFLAG_ANY 2366 }; 2367 2368 enum avx_u128_state 2369 { 2370 AVX_U128_CLEAN, 2371 AVX_U128_DIRTY, 2372 AVX_U128_ANY 2373 }; 2374 2375 /* Define this macro if the port needs extra instructions inserted 2376 for mode switching in an optimizing compilation. */ 2377 2378 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2379 ix86_optimize_mode_switching[(ENTITY)] 2380 2381 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2382 initializer for an array of integers. Each initializer element N 2383 refers to an entity that needs mode switching, and specifies the 2384 number of different modes that might need to be set for this 2385 entity. The position of the initializer in the initializer - 2386 starting counting at zero - determines the integer that is used to 2387 refer to the mode-switched entity in question. */ 2388 2389 #define NUM_MODES_FOR_MODE_SWITCHING \ 2390 { X86_DIRFLAG_ANY, AVX_U128_ANY, \ 2391 I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2392 2393 2394 /* Avoid renaming of stack registers, as doing so in combination with 2395 scheduling just increases amount of live registers at time and in 2396 the turn amount of fxch instructions needed. 2397 2398 ??? Maybe Pentium chips benefits from renaming, someone can try.... 2399 2400 Don't rename evex to non-evex sse registers. */ 2401 2402 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 2403 (!STACK_REGNO_P (SRC) \ 2404 && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET)) 2405 2406 2407 #define FASTCALL_PREFIX '@' 2408 2409 #ifndef USED_FOR_TARGET 2410 /* Structure describing stack frame layout. 2411 Stack grows downward: 2412 2413 [arguments] 2414 <- ARG_POINTER 2415 saved pc 2416 2417 saved static chain if ix86_static_chain_on_stack 2418 2419 saved frame pointer if frame_pointer_needed 2420 <- HARD_FRAME_POINTER 2421 [saved regs] 2422 <- reg_save_offset 2423 [padding0] 2424 <- stack_realign_offset 2425 [saved SSE regs] 2426 OR 2427 [stub-saved registers for ms x64 --> sysv clobbers 2428 <- Start of out-of-line, stub-saved/restored regs 2429 (see libgcc/config/i386/(sav|res)ms64*.S) 2430 [XMM6-15] 2431 [RSI] 2432 [RDI] 2433 [?RBX] only if RBX is clobbered 2434 [?RBP] only if RBP and RBX are clobbered 2435 [?R12] only if R12 and all previous regs are clobbered 2436 [?R13] only if R13 and all previous regs are clobbered 2437 [?R14] only if R14 and all previous regs are clobbered 2438 [?R15] only if R15 and all previous regs are clobbered 2439 <- end of stub-saved/restored regs 2440 [padding1] 2441 ] 2442 <- sse_reg_save_offset 2443 [padding2] 2444 | <- FRAME_POINTER 2445 [va_arg registers] | 2446 | 2447 [frame] | 2448 | 2449 [padding2] | = to_allocate 2450 <- STACK_POINTER 2451 */ 2452 struct GTY(()) ix86_frame 2453 { 2454 int nsseregs; 2455 int nregs; 2456 int va_arg_size; 2457 int red_zone_size; 2458 int outgoing_arguments_size; 2459 2460 /* The offsets relative to ARG_POINTER. */ 2461 HOST_WIDE_INT frame_pointer_offset; 2462 HOST_WIDE_INT hard_frame_pointer_offset; 2463 HOST_WIDE_INT stack_pointer_offset; 2464 HOST_WIDE_INT hfp_save_offset; 2465 HOST_WIDE_INT reg_save_offset; 2466 HOST_WIDE_INT stack_realign_allocate; 2467 HOST_WIDE_INT stack_realign_offset; 2468 HOST_WIDE_INT sse_reg_save_offset; 2469 2470 /* When save_regs_using_mov is set, emit prologue using 2471 move instead of push instructions. */ 2472 bool save_regs_using_mov; 2473 }; 2474 2475 /* Machine specific frame tracking during prologue/epilogue generation. All 2476 values are positive, but since the x86 stack grows downward, are subtratced 2477 from the CFA to produce a valid address. */ 2478 2479 struct GTY(()) machine_frame_state 2480 { 2481 /* This pair tracks the currently active CFA as reg+offset. When reg 2482 is drap_reg, we don't bother trying to record here the real CFA when 2483 it might really be a DW_CFA_def_cfa_expression. */ 2484 rtx cfa_reg; 2485 HOST_WIDE_INT cfa_offset; 2486 2487 /* The current offset (canonically from the CFA) of ESP and EBP. 2488 When stack frame re-alignment is active, these may not be relative 2489 to the CFA. However, in all cases they are relative to the offsets 2490 of the saved registers stored in ix86_frame. */ 2491 HOST_WIDE_INT sp_offset; 2492 HOST_WIDE_INT fp_offset; 2493 2494 /* The size of the red-zone that may be assumed for the purposes of 2495 eliding register restore notes in the epilogue. This may be zero 2496 if no red-zone is in effect, or may be reduced from the real 2497 red-zone value by a maximum runtime stack re-alignment value. */ 2498 int red_zone_offset; 2499 2500 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid 2501 value within the frame. If false then the offset above should be 2502 ignored. Note that DRAP, if valid, *always* points to the CFA and 2503 thus has an offset of zero. */ 2504 BOOL_BITFIELD sp_valid : 1; 2505 BOOL_BITFIELD fp_valid : 1; 2506 BOOL_BITFIELD drap_valid : 1; 2507 2508 /* Indicate whether the local stack frame has been re-aligned. When 2509 set, the SP/FP offsets above are relative to the aligned frame 2510 and not the CFA. */ 2511 BOOL_BITFIELD realigned : 1; 2512 2513 /* Indicates whether the stack pointer has been re-aligned. When set, 2514 SP/FP continue to be relative to the CFA, but the stack pointer 2515 should only be used for offsets > sp_realigned_offset, while 2516 the frame pointer should be used for offsets <= sp_realigned_fp_last. 2517 The flags realigned and sp_realigned are mutually exclusive. */ 2518 BOOL_BITFIELD sp_realigned : 1; 2519 2520 /* If sp_realigned is set, this is the last valid offset from the CFA 2521 that can be used for access with the frame pointer. */ 2522 HOST_WIDE_INT sp_realigned_fp_last; 2523 2524 /* If sp_realigned is set, this is the offset from the CFA that the stack 2525 pointer was realigned, and may or may not be equal to sp_realigned_fp_last. 2526 Access via the stack pointer is only valid for offsets that are greater than 2527 this value. */ 2528 HOST_WIDE_INT sp_realigned_offset; 2529 }; 2530 2531 /* Private to winnt.c. */ 2532 struct seh_frame_state; 2533 2534 enum function_type 2535 { 2536 TYPE_UNKNOWN = 0, 2537 TYPE_NORMAL, 2538 /* The current function is an interrupt service routine with a 2539 pointer argument as specified by the "interrupt" attribute. */ 2540 TYPE_INTERRUPT, 2541 /* The current function is an interrupt service routine with a 2542 pointer argument and an integer argument as specified by the 2543 "interrupt" attribute. */ 2544 TYPE_EXCEPTION 2545 }; 2546 2547 struct GTY(()) machine_function { 2548 struct stack_local_entry *stack_locals; 2549 int varargs_gpr_size; 2550 int varargs_fpr_size; 2551 int optimize_mode_switching[MAX_386_ENTITIES]; 2552 2553 /* Cached initial frame layout for the current function. */ 2554 struct ix86_frame frame; 2555 2556 /* For -fsplit-stack support: A stack local which holds a pointer to 2557 the stack arguments for a function with a variable number of 2558 arguments. This is set at the start of the function and is used 2559 to initialize the overflow_arg_area field of the va_list 2560 structure. */ 2561 rtx split_stack_varargs_pointer; 2562 2563 /* This value is used for amd64 targets and specifies the current abi 2564 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ 2565 ENUM_BITFIELD(calling_abi) call_abi : 8; 2566 2567 /* Nonzero if the function accesses a previous frame. */ 2568 BOOL_BITFIELD accesses_prev_frame : 1; 2569 2570 /* Set by ix86_compute_frame_layout and used by prologue/epilogue 2571 expander to determine the style used. */ 2572 BOOL_BITFIELD use_fast_prologue_epilogue : 1; 2573 2574 /* Nonzero if the current function calls pc thunk and 2575 must not use the red zone. */ 2576 BOOL_BITFIELD pc_thunk_call_expanded : 1; 2577 2578 /* If true, the current function needs the default PIC register, not 2579 an alternate register (on x86) and must not use the red zone (on 2580 x86_64), even if it's a leaf function. We don't want the 2581 function to be regarded as non-leaf because TLS calls need not 2582 affect register allocation. This flag is set when a TLS call 2583 instruction is expanded within a function, and never reset, even 2584 if all such instructions are optimized away. Use the 2585 ix86_current_function_calls_tls_descriptor macro for a better 2586 approximation. */ 2587 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; 2588 2589 /* If true, the current function has a STATIC_CHAIN is placed on the 2590 stack below the return address. */ 2591 BOOL_BITFIELD static_chain_on_stack : 1; 2592 2593 /* If true, it is safe to not save/restore DRAP register. */ 2594 BOOL_BITFIELD no_drap_save_restore : 1; 2595 2596 /* Function type. */ 2597 ENUM_BITFIELD(function_type) func_type : 2; 2598 2599 /* How to generate indirec branch. */ 2600 ENUM_BITFIELD(indirect_branch) indirect_branch_type : 3; 2601 2602 /* If true, the current function has local indirect jumps, like 2603 "indirect_jump" or "tablejump". */ 2604 BOOL_BITFIELD has_local_indirect_jump : 1; 2605 2606 /* How to generate function return. */ 2607 ENUM_BITFIELD(indirect_branch) function_return_type : 3; 2608 2609 /* If true, the current function is a function specified with 2610 the "interrupt" or "no_caller_saved_registers" attribute. */ 2611 BOOL_BITFIELD no_caller_saved_registers : 1; 2612 2613 /* If true, there is register available for argument passing. This 2614 is used only in ix86_function_ok_for_sibcall by 32-bit to determine 2615 if there is scratch register available for indirect sibcall. In 2616 64-bit, rax, r10 and r11 are scratch registers which aren't used to 2617 pass arguments and can be used for indirect sibcall. */ 2618 BOOL_BITFIELD arg_reg_available : 1; 2619 2620 /* If true, we're out-of-lining reg save/restore for regs clobbered 2621 by 64-bit ms_abi functions calling a sysv_abi function. */ 2622 BOOL_BITFIELD call_ms2sysv : 1; 2623 2624 /* If true, the incoming 16-byte aligned stack has an offset (of 8) and 2625 needs padding prior to out-of-line stub save/restore area. */ 2626 BOOL_BITFIELD call_ms2sysv_pad_in : 1; 2627 2628 /* This is the number of extra registers saved by stub (valid range is 2629 0-6). Each additional register is only saved/restored by the stubs 2630 if all successive ones are. (Will always be zero when using a hard 2631 frame pointer.) */ 2632 unsigned int call_ms2sysv_extra_regs:3; 2633 2634 /* Nonzero if the function places outgoing arguments on stack. */ 2635 BOOL_BITFIELD outgoing_args_on_stack : 1; 2636 2637 /* If true, ENDBR is queued at function entrance. */ 2638 BOOL_BITFIELD endbr_queued_at_entrance : 1; 2639 2640 /* The largest alignment, in bytes, of stack slot actually used. */ 2641 unsigned int max_used_stack_alignment; 2642 2643 /* During prologue/epilogue generation, the current frame state. 2644 Otherwise, the frame state at the end of the prologue. */ 2645 struct machine_frame_state fs; 2646 2647 /* During SEH output, this is non-null. */ 2648 struct seh_frame_state * GTY((skip(""))) seh; 2649 }; 2650 #endif 2651 2652 #define ix86_stack_locals (cfun->machine->stack_locals) 2653 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) 2654 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) 2655 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2656 #define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded) 2657 #define ix86_tls_descriptor_calls_expanded_in_cfun \ 2658 (cfun->machine->tls_descriptor_call_expanded_p) 2659 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS 2660 calls are optimized away, we try to detect cases in which it was 2661 optimized away. Since such instructions (use (reg REG_SP)), we can 2662 verify whether there's any such instruction live by testing that 2663 REG_SP is live. */ 2664 #define ix86_current_function_calls_tls_descriptor \ 2665 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) 2666 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) 2667 #define ix86_red_zone_size (cfun->machine->frame.red_zone_size) 2668 2669 /* Control behavior of x86_file_start. */ 2670 #define X86_FILE_START_VERSION_DIRECTIVE false 2671 #define X86_FILE_START_FLTUSED false 2672 2673 /* Flag to mark data that is in the large address area. */ 2674 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2675 #define SYMBOL_REF_FAR_ADDR_P(X) \ 2676 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2677 2678 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to 2679 have defined always, to avoid ifdefing. */ 2680 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) 2681 #define SYMBOL_REF_DLLIMPORT_P(X) \ 2682 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) 2683 2684 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) 2685 #define SYMBOL_REF_DLLEXPORT_P(X) \ 2686 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) 2687 2688 #define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4) 2689 #define SYMBOL_REF_STUBVAR_P(X) \ 2690 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0) 2691 2692 extern void debug_ready_dispatch (void); 2693 extern void debug_dispatch_window (int); 2694 2695 /* The value at zero is only defined for the BMI instructions 2696 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ 2697 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2698 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 1 : 0) 2699 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2700 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 1 : 0) 2701 2702 2703 /* Flags returned by ix86_get_callcvt (). */ 2704 #define IX86_CALLCVT_CDECL 0x1 2705 #define IX86_CALLCVT_STDCALL 0x2 2706 #define IX86_CALLCVT_FASTCALL 0x4 2707 #define IX86_CALLCVT_THISCALL 0x8 2708 #define IX86_CALLCVT_REGPARM 0x10 2709 #define IX86_CALLCVT_SSEREGPARM 0x20 2710 2711 #define IX86_BASE_CALLCVT(FLAGS) \ 2712 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ 2713 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) 2714 2715 #define RECIP_MASK_NONE 0x00 2716 #define RECIP_MASK_DIV 0x01 2717 #define RECIP_MASK_SQRT 0x02 2718 #define RECIP_MASK_VEC_DIV 0x04 2719 #define RECIP_MASK_VEC_SQRT 0x08 2720 #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ 2721 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2722 #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2723 2724 #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) 2725 #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) 2726 #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) 2727 #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) 2728 2729 /* Use 128-bit AVX instructions in the auto-vectorizer. */ 2730 #define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128) 2731 /* Use 256-bit AVX instructions in the auto-vectorizer. */ 2732 #define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \ 2733 || prefer_vector_width_type == PVW_AVX256) 2734 2735 #define TARGET_INDIRECT_BRANCH_REGISTER \ 2736 (ix86_indirect_branch_register \ 2737 || cfun->machine->indirect_branch_type != indirect_branch_keep) 2738 2739 #define IX86_HLE_ACQUIRE (1 << 16) 2740 #define IX86_HLE_RELEASE (1 << 17) 2741 2742 /* For switching between functions with different target attributes. */ 2743 #define SWITCHABLE_TARGET 1 2744 2745 #define TARGET_SUPPORTS_WIDE_INT 1 2746 2747 /* 2748 Local variables: 2749 version-control: t 2750 End: 2751 */ 2752