1 /* Target-dependent code for AMD64. 2 3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 4 2011 Free Software Foundation, Inc. 5 6 Contributed by Jiri Smid, SuSE Labs. 7 8 This file is part of GDB. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 22 23 #include "defs.h" 24 #include "opcode/i386.h" 25 #include "dis-asm.h" 26 #include "arch-utils.h" 27 #include "block.h" 28 #include "dummy-frame.h" 29 #include "frame.h" 30 #include "frame-base.h" 31 #include "frame-unwind.h" 32 #include "inferior.h" 33 #include "gdbcmd.h" 34 #include "gdbcore.h" 35 #include "objfiles.h" 36 #include "regcache.h" 37 #include "regset.h" 38 #include "symfile.h" 39 #include "disasm.h" 40 #include "gdb_assert.h" 41 #include "exceptions.h" 42 #include "amd64-tdep.h" 43 #include "i387-tdep.h" 44 45 #include "features/i386/amd64.c" 46 #include "features/i386/amd64-avx.c" 47 48 /* Note that the AMD64 architecture was previously known as x86-64. 49 The latter is (forever) engraved into the canonical system name as 50 returned by config.guess, and used as the name for the AMD64 port 51 of GNU/Linux. The BSD's have renamed their ports to amd64; they 52 don't like to shout. For GDB we prefer the amd64_-prefix over the 53 x86_64_-prefix since it's so much easier to type. */ 54 55 /* Register information. */ 56 57 static const char *amd64_register_names[] = 58 { 59 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", 60 61 /* %r8 is indeed register number 8. */ 62 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 63 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs", 64 65 /* %st0 is register number 24. */ 66 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", 67 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop", 68 69 /* %xmm0 is register number 40. */ 70 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 71 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 72 "mxcsr", 73 }; 74 75 static const char *amd64_ymm_names[] = 76 { 77 "ymm0", "ymm1", "ymm2", "ymm3", 78 "ymm4", "ymm5", "ymm6", "ymm7", 79 "ymm8", "ymm9", "ymm10", "ymm11", 80 "ymm12", "ymm13", "ymm14", "ymm15" 81 }; 82 83 static const char *amd64_ymmh_names[] = 84 { 85 "ymm0h", "ymm1h", "ymm2h", "ymm3h", 86 "ymm4h", "ymm5h", "ymm6h", "ymm7h", 87 "ymm8h", "ymm9h", "ymm10h", "ymm11h", 88 "ymm12h", "ymm13h", "ymm14h", "ymm15h" 89 }; 90 91 /* The registers used to pass integer arguments during a function call. */ 92 static int amd64_dummy_call_integer_regs[] = 93 { 94 AMD64_RDI_REGNUM, /* %rdi */ 95 AMD64_RSI_REGNUM, /* %rsi */ 96 AMD64_RDX_REGNUM, /* %rdx */ 97 AMD64_RCX_REGNUM, /* %rcx */ 98 8, /* %r8 */ 99 9 /* %r9 */ 100 }; 101 102 /* DWARF Register Number Mapping as defined in the System V psABI, 103 section 3.6. */ 104 105 static int amd64_dwarf_regmap[] = 106 { 107 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ 108 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, 109 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, 110 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, 111 112 /* Frame Pointer Register RBP. */ 113 AMD64_RBP_REGNUM, 114 115 /* Stack Pointer Register RSP. */ 116 AMD64_RSP_REGNUM, 117 118 /* Extended Integer Registers 8 - 15. */ 119 8, 9, 10, 11, 12, 13, 14, 15, 120 121 /* Return Address RA. Mapped to RIP. */ 122 AMD64_RIP_REGNUM, 123 124 /* SSE Registers 0 - 7. */ 125 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 126 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 127 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 128 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 129 130 /* Extended SSE Registers 8 - 15. */ 131 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, 132 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, 133 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, 134 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, 135 136 /* Floating Point Registers 0-7. */ 137 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, 138 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, 139 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, 140 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, 141 142 /* Control and Status Flags Register. */ 143 AMD64_EFLAGS_REGNUM, 144 145 /* Selector Registers. */ 146 AMD64_ES_REGNUM, 147 AMD64_CS_REGNUM, 148 AMD64_SS_REGNUM, 149 AMD64_DS_REGNUM, 150 AMD64_FS_REGNUM, 151 AMD64_GS_REGNUM, 152 -1, 153 -1, 154 155 /* Segment Base Address Registers. */ 156 -1, 157 -1, 158 -1, 159 -1, 160 161 /* Special Selector Registers. */ 162 -1, 163 -1, 164 165 /* Floating Point Control Registers. */ 166 AMD64_MXCSR_REGNUM, 167 AMD64_FCTRL_REGNUM, 168 AMD64_FSTAT_REGNUM 169 }; 170 171 static const int amd64_dwarf_regmap_len = 172 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); 173 174 /* Convert DWARF register number REG to the appropriate register 175 number used by GDB. */ 176 177 static int 178 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) 179 { 180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 181 int ymm0_regnum = tdep->ymm0_regnum; 182 int regnum = -1; 183 184 if (reg >= 0 && reg < amd64_dwarf_regmap_len) 185 regnum = amd64_dwarf_regmap[reg]; 186 187 if (regnum == -1) 188 warning (_("Unmapped DWARF Register #%d encountered."), reg); 189 else if (ymm0_regnum >= 0 190 && i386_xmm_regnum_p (gdbarch, regnum)) 191 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep); 192 193 return regnum; 194 } 195 196 /* Map architectural register numbers to gdb register numbers. */ 197 198 static const int amd64_arch_regmap[16] = 199 { 200 AMD64_RAX_REGNUM, /* %rax */ 201 AMD64_RCX_REGNUM, /* %rcx */ 202 AMD64_RDX_REGNUM, /* %rdx */ 203 AMD64_RBX_REGNUM, /* %rbx */ 204 AMD64_RSP_REGNUM, /* %rsp */ 205 AMD64_RBP_REGNUM, /* %rbp */ 206 AMD64_RSI_REGNUM, /* %rsi */ 207 AMD64_RDI_REGNUM, /* %rdi */ 208 AMD64_R8_REGNUM, /* %r8 */ 209 AMD64_R9_REGNUM, /* %r9 */ 210 AMD64_R10_REGNUM, /* %r10 */ 211 AMD64_R11_REGNUM, /* %r11 */ 212 AMD64_R12_REGNUM, /* %r12 */ 213 AMD64_R13_REGNUM, /* %r13 */ 214 AMD64_R14_REGNUM, /* %r14 */ 215 AMD64_R15_REGNUM /* %r15 */ 216 }; 217 218 static const int amd64_arch_regmap_len = 219 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0])); 220 221 /* Convert architectural register number REG to the appropriate register 222 number used by GDB. */ 223 224 static int 225 amd64_arch_reg_to_regnum (int reg) 226 { 227 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len); 228 229 return amd64_arch_regmap[reg]; 230 } 231 232 /* Register names for byte pseudo-registers. */ 233 234 static const char *amd64_byte_names[] = 235 { 236 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl", 237 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l", 238 "ah", "bh", "ch", "dh" 239 }; 240 241 /* Number of lower byte registers. */ 242 #define AMD64_NUM_LOWER_BYTE_REGS 16 243 244 /* Register names for word pseudo-registers. */ 245 246 static const char *amd64_word_names[] = 247 { 248 "ax", "bx", "cx", "dx", "si", "di", "bp", "", 249 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" 250 }; 251 252 /* Register names for dword pseudo-registers. */ 253 254 static const char *amd64_dword_names[] = 255 { 256 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", 257 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" 258 }; 259 260 /* Return the name of register REGNUM. */ 261 262 static const char * 263 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) 264 { 265 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 266 if (i386_byte_regnum_p (gdbarch, regnum)) 267 return amd64_byte_names[regnum - tdep->al_regnum]; 268 else if (i386_ymm_regnum_p (gdbarch, regnum)) 269 return amd64_ymm_names[regnum - tdep->ymm0_regnum]; 270 else if (i386_word_regnum_p (gdbarch, regnum)) 271 return amd64_word_names[regnum - tdep->ax_regnum]; 272 else if (i386_dword_regnum_p (gdbarch, regnum)) 273 return amd64_dword_names[regnum - tdep->eax_regnum]; 274 else 275 return i386_pseudo_register_name (gdbarch, regnum); 276 } 277 278 static enum register_status 279 amd64_pseudo_register_read (struct gdbarch *gdbarch, 280 struct regcache *regcache, 281 int regnum, gdb_byte *buf) 282 { 283 gdb_byte raw_buf[MAX_REGISTER_SIZE]; 284 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 285 enum register_status status; 286 287 if (i386_byte_regnum_p (gdbarch, regnum)) 288 { 289 int gpnum = regnum - tdep->al_regnum; 290 291 /* Extract (always little endian). */ 292 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) 293 { 294 /* Special handling for AH, BH, CH, DH. */ 295 status = regcache_raw_read (regcache, 296 gpnum - AMD64_NUM_LOWER_BYTE_REGS, 297 raw_buf); 298 if (status == REG_VALID) 299 memcpy (buf, raw_buf + 1, 1); 300 } 301 else 302 { 303 status = regcache_raw_read (regcache, gpnum, raw_buf); 304 if (status == REG_VALID) 305 memcpy (buf, raw_buf, 1); 306 } 307 308 return status; 309 } 310 else if (i386_dword_regnum_p (gdbarch, regnum)) 311 { 312 int gpnum = regnum - tdep->eax_regnum; 313 /* Extract (always little endian). */ 314 status = regcache_raw_read (regcache, gpnum, raw_buf); 315 if (status == REG_VALID) 316 memcpy (buf, raw_buf, 4); 317 318 return status; 319 } 320 else 321 return i386_pseudo_register_read (gdbarch, regcache, regnum, buf); 322 } 323 324 static void 325 amd64_pseudo_register_write (struct gdbarch *gdbarch, 326 struct regcache *regcache, 327 int regnum, const gdb_byte *buf) 328 { 329 gdb_byte raw_buf[MAX_REGISTER_SIZE]; 330 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 331 332 if (i386_byte_regnum_p (gdbarch, regnum)) 333 { 334 int gpnum = regnum - tdep->al_regnum; 335 336 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) 337 { 338 /* Read ... AH, BH, CH, DH. */ 339 regcache_raw_read (regcache, 340 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); 341 /* ... Modify ... (always little endian). */ 342 memcpy (raw_buf + 1, buf, 1); 343 /* ... Write. */ 344 regcache_raw_write (regcache, 345 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); 346 } 347 else 348 { 349 /* Read ... */ 350 regcache_raw_read (regcache, gpnum, raw_buf); 351 /* ... Modify ... (always little endian). */ 352 memcpy (raw_buf, buf, 1); 353 /* ... Write. */ 354 regcache_raw_write (regcache, gpnum, raw_buf); 355 } 356 } 357 else if (i386_dword_regnum_p (gdbarch, regnum)) 358 { 359 int gpnum = regnum - tdep->eax_regnum; 360 361 /* Read ... */ 362 regcache_raw_read (regcache, gpnum, raw_buf); 363 /* ... Modify ... (always little endian). */ 364 memcpy (raw_buf, buf, 4); 365 /* ... Write. */ 366 regcache_raw_write (regcache, gpnum, raw_buf); 367 } 368 else 369 i386_pseudo_register_write (gdbarch, regcache, regnum, buf); 370 } 371 372 373 374 /* Return the union class of CLASS1 and CLASS2. See the psABI for 375 details. */ 376 377 static enum amd64_reg_class 378 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) 379 { 380 /* Rule (a): If both classes are equal, this is the resulting class. */ 381 if (class1 == class2) 382 return class1; 383 384 /* Rule (b): If one of the classes is NO_CLASS, the resulting class 385 is the other class. */ 386 if (class1 == AMD64_NO_CLASS) 387 return class2; 388 if (class2 == AMD64_NO_CLASS) 389 return class1; 390 391 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ 392 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) 393 return AMD64_MEMORY; 394 395 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ 396 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) 397 return AMD64_INTEGER; 398 399 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, 400 MEMORY is used as class. */ 401 if (class1 == AMD64_X87 || class1 == AMD64_X87UP 402 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 403 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) 404 return AMD64_MEMORY; 405 406 /* Rule (f): Otherwise class SSE is used. */ 407 return AMD64_SSE; 408 } 409 410 /* Return non-zero if TYPE is a non-POD structure or union type. */ 411 412 static int 413 amd64_non_pod_p (struct type *type) 414 { 415 /* ??? A class with a base class certainly isn't POD, but does this 416 catch all non-POD structure types? */ 417 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) 418 return 1; 419 420 return 0; 421 } 422 423 /* Classify TYPE according to the rules for aggregate (structures and 424 arrays) and union types, and store the result in CLASS. */ 425 426 static void 427 amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) 428 { 429 int len = TYPE_LENGTH (type); 430 431 /* 1. If the size of an object is larger than two eightbytes, or in 432 C++, is a non-POD structure or union type, or contains 433 unaligned fields, it has class memory. */ 434 if (len > 16 || amd64_non_pod_p (type)) 435 { 436 class[0] = class[1] = AMD64_MEMORY; 437 return; 438 } 439 440 /* 2. Both eightbytes get initialized to class NO_CLASS. */ 441 class[0] = class[1] = AMD64_NO_CLASS; 442 443 /* 3. Each field of an object is classified recursively so that 444 always two fields are considered. The resulting class is 445 calculated according to the classes of the fields in the 446 eightbyte: */ 447 448 if (TYPE_CODE (type) == TYPE_CODE_ARRAY) 449 { 450 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); 451 452 /* All fields in an array have the same type. */ 453 amd64_classify (subtype, class); 454 if (len > 8 && class[1] == AMD64_NO_CLASS) 455 class[1] = class[0]; 456 } 457 else 458 { 459 int i; 460 461 /* Structure or union. */ 462 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT 463 || TYPE_CODE (type) == TYPE_CODE_UNION); 464 465 for (i = 0; i < TYPE_NFIELDS (type); i++) 466 { 467 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); 468 int pos = TYPE_FIELD_BITPOS (type, i) / 64; 469 enum amd64_reg_class subclass[2]; 470 int bitsize = TYPE_FIELD_BITSIZE (type, i); 471 int endpos; 472 473 if (bitsize == 0) 474 bitsize = TYPE_LENGTH (subtype) * 8; 475 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64; 476 477 /* Ignore static fields. */ 478 if (field_is_static (&TYPE_FIELD (type, i))) 479 continue; 480 481 gdb_assert (pos == 0 || pos == 1); 482 483 amd64_classify (subtype, subclass); 484 class[pos] = amd64_merge_classes (class[pos], subclass[0]); 485 if (bitsize <= 64 && pos == 0 && endpos == 1) 486 /* This is a bit of an odd case: We have a field that would 487 normally fit in one of the two eightbytes, except that 488 it is placed in a way that this field straddles them. 489 This has been seen with a structure containing an array. 490 491 The ABI is a bit unclear in this case, but we assume that 492 this field's class (stored in subclass[0]) must also be merged 493 into class[1]. In other words, our field has a piece stored 494 in the second eight-byte, and thus its class applies to 495 the second eight-byte as well. 496 497 In the case where the field length exceeds 8 bytes, 498 it should not be necessary to merge the field class 499 into class[1]. As LEN > 8, subclass[1] is necessarily 500 different from AMD64_NO_CLASS. If subclass[1] is equal 501 to subclass[0], then the normal class[1]/subclass[1] 502 merging will take care of everything. For subclass[1] 503 to be different from subclass[0], I can only see the case 504 where we have a SSE/SSEUP or X87/X87UP pair, which both 505 use up all 16 bytes of the aggregate, and are already 506 handled just fine (because each portion sits on its own 507 8-byte). */ 508 class[1] = amd64_merge_classes (class[1], subclass[0]); 509 if (pos == 0) 510 class[1] = amd64_merge_classes (class[1], subclass[1]); 511 } 512 } 513 514 /* 4. Then a post merger cleanup is done: */ 515 516 /* Rule (a): If one of the classes is MEMORY, the whole argument is 517 passed in memory. */ 518 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY) 519 class[0] = class[1] = AMD64_MEMORY; 520 521 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to 522 SSE. */ 523 if (class[0] == AMD64_SSEUP) 524 class[0] = AMD64_SSE; 525 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE) 526 class[1] = AMD64_SSE; 527 } 528 529 /* Classify TYPE, and store the result in CLASS. */ 530 531 void 532 amd64_classify (struct type *type, enum amd64_reg_class class[2]) 533 { 534 enum type_code code = TYPE_CODE (type); 535 int len = TYPE_LENGTH (type); 536 537 class[0] = class[1] = AMD64_NO_CLASS; 538 539 /* Arguments of types (signed and unsigned) _Bool, char, short, int, 540 long, long long, and pointers are in the INTEGER class. Similarly, 541 range types, used by languages such as Ada, are also in the INTEGER 542 class. */ 543 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM 544 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE 545 || code == TYPE_CODE_CHAR 546 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) 547 && (len == 1 || len == 2 || len == 4 || len == 8)) 548 class[0] = AMD64_INTEGER; 549 550 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64 551 are in class SSE. */ 552 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT) 553 && (len == 4 || len == 8)) 554 /* FIXME: __m64 . */ 555 class[0] = AMD64_SSE; 556 557 /* Arguments of types __float128, _Decimal128 and __m128 are split into 558 two halves. The least significant ones belong to class SSE, the most 559 significant one to class SSEUP. */ 560 else if (code == TYPE_CODE_DECFLOAT && len == 16) 561 /* FIXME: __float128, __m128. */ 562 class[0] = AMD64_SSE, class[1] = AMD64_SSEUP; 563 564 /* The 64-bit mantissa of arguments of type long double belongs to 565 class X87, the 16-bit exponent plus 6 bytes of padding belongs to 566 class X87UP. */ 567 else if (code == TYPE_CODE_FLT && len == 16) 568 /* Class X87 and X87UP. */ 569 class[0] = AMD64_X87, class[1] = AMD64_X87UP; 570 571 /* Aggregates. */ 572 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT 573 || code == TYPE_CODE_UNION) 574 amd64_classify_aggregate (type, class); 575 } 576 577 static enum return_value_convention 578 amd64_return_value (struct gdbarch *gdbarch, struct type *func_type, 579 struct type *type, struct regcache *regcache, 580 gdb_byte *readbuf, const gdb_byte *writebuf) 581 { 582 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 583 enum amd64_reg_class class[2]; 584 int len = TYPE_LENGTH (type); 585 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; 586 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; 587 int integer_reg = 0; 588 int sse_reg = 0; 589 int i; 590 591 gdb_assert (!(readbuf && writebuf)); 592 gdb_assert (tdep->classify); 593 594 /* 1. Classify the return type with the classification algorithm. */ 595 tdep->classify (type, class); 596 597 /* 2. If the type has class MEMORY, then the caller provides space 598 for the return value and passes the address of this storage in 599 %rdi as if it were the first argument to the function. In effect, 600 this address becomes a hidden first argument. 601 602 On return %rax will contain the address that has been passed in 603 by the caller in %rdi. */ 604 if (class[0] == AMD64_MEMORY) 605 { 606 /* As indicated by the comment above, the ABI guarantees that we 607 can always find the return value just after the function has 608 returned. */ 609 610 if (readbuf) 611 { 612 ULONGEST addr; 613 614 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr); 615 read_memory (addr, readbuf, TYPE_LENGTH (type)); 616 } 617 618 return RETURN_VALUE_ABI_RETURNS_ADDRESS; 619 } 620 621 gdb_assert (class[1] != AMD64_MEMORY); 622 gdb_assert (len <= 16); 623 624 for (i = 0; len > 0; i++, len -= 8) 625 { 626 int regnum = -1; 627 int offset = 0; 628 629 switch (class[i]) 630 { 631 case AMD64_INTEGER: 632 /* 3. If the class is INTEGER, the next available register 633 of the sequence %rax, %rdx is used. */ 634 regnum = integer_regnum[integer_reg++]; 635 break; 636 637 case AMD64_SSE: 638 /* 4. If the class is SSE, the next available SSE register 639 of the sequence %xmm0, %xmm1 is used. */ 640 regnum = sse_regnum[sse_reg++]; 641 break; 642 643 case AMD64_SSEUP: 644 /* 5. If the class is SSEUP, the eightbyte is passed in the 645 upper half of the last used SSE register. */ 646 gdb_assert (sse_reg > 0); 647 regnum = sse_regnum[sse_reg - 1]; 648 offset = 8; 649 break; 650 651 case AMD64_X87: 652 /* 6. If the class is X87, the value is returned on the X87 653 stack in %st0 as 80-bit x87 number. */ 654 regnum = AMD64_ST0_REGNUM; 655 if (writebuf) 656 i387_return_value (gdbarch, regcache); 657 break; 658 659 case AMD64_X87UP: 660 /* 7. If the class is X87UP, the value is returned together 661 with the previous X87 value in %st0. */ 662 gdb_assert (i > 0 && class[0] == AMD64_X87); 663 regnum = AMD64_ST0_REGNUM; 664 offset = 8; 665 len = 2; 666 break; 667 668 case AMD64_NO_CLASS: 669 continue; 670 671 default: 672 gdb_assert (!"Unexpected register class."); 673 } 674 675 gdb_assert (regnum != -1); 676 677 if (readbuf) 678 regcache_raw_read_part (regcache, regnum, offset, min (len, 8), 679 readbuf + i * 8); 680 if (writebuf) 681 regcache_raw_write_part (regcache, regnum, offset, min (len, 8), 682 writebuf + i * 8); 683 } 684 685 return RETURN_VALUE_REGISTER_CONVENTION; 686 } 687 688 689 static CORE_ADDR 690 amd64_push_arguments (struct regcache *regcache, int nargs, 691 struct value **args, CORE_ADDR sp, int struct_return) 692 { 693 struct gdbarch *gdbarch = get_regcache_arch (regcache); 694 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 695 int *integer_regs = tdep->call_dummy_integer_regs; 696 int num_integer_regs = tdep->call_dummy_num_integer_regs; 697 698 static int sse_regnum[] = 699 { 700 /* %xmm0 ... %xmm7 */ 701 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 702 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 703 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 704 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 705 }; 706 struct value **stack_args = alloca (nargs * sizeof (struct value *)); 707 /* An array that mirrors the stack_args array. For all arguments 708 that are passed by MEMORY, if that argument's address also needs 709 to be stored in a register, the ARG_ADDR_REGNO array will contain 710 that register number (or a negative value otherwise). */ 711 int *arg_addr_regno = alloca (nargs * sizeof (int)); 712 int num_stack_args = 0; 713 int num_elements = 0; 714 int element = 0; 715 int integer_reg = 0; 716 int sse_reg = 0; 717 int i; 718 719 gdb_assert (tdep->classify); 720 721 /* Reserve a register for the "hidden" argument. */ 722 if (struct_return) 723 integer_reg++; 724 725 for (i = 0; i < nargs; i++) 726 { 727 struct type *type = value_type (args[i]); 728 int len = TYPE_LENGTH (type); 729 enum amd64_reg_class class[2]; 730 int needed_integer_regs = 0; 731 int needed_sse_regs = 0; 732 int j; 733 734 /* Classify argument. */ 735 tdep->classify (type, class); 736 737 /* Calculate the number of integer and SSE registers needed for 738 this argument. */ 739 for (j = 0; j < 2; j++) 740 { 741 if (class[j] == AMD64_INTEGER) 742 needed_integer_regs++; 743 else if (class[j] == AMD64_SSE) 744 needed_sse_regs++; 745 } 746 747 /* Check whether enough registers are available, and if the 748 argument should be passed in registers at all. */ 749 if (integer_reg + needed_integer_regs > num_integer_regs 750 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) 751 || (needed_integer_regs == 0 && needed_sse_regs == 0)) 752 { 753 /* The argument will be passed on the stack. */ 754 num_elements += ((len + 7) / 8); 755 stack_args[num_stack_args] = args[i]; 756 /* If this is an AMD64_MEMORY argument whose address must also 757 be passed in one of the integer registers, reserve that 758 register and associate this value to that register so that 759 we can store the argument address as soon as we know it. */ 760 if (class[0] == AMD64_MEMORY 761 && tdep->memory_args_by_pointer 762 && integer_reg < tdep->call_dummy_num_integer_regs) 763 arg_addr_regno[num_stack_args] = 764 tdep->call_dummy_integer_regs[integer_reg++]; 765 else 766 arg_addr_regno[num_stack_args] = -1; 767 num_stack_args++; 768 } 769 else 770 { 771 /* The argument will be passed in registers. */ 772 const gdb_byte *valbuf = value_contents (args[i]); 773 gdb_byte buf[8]; 774 775 gdb_assert (len <= 16); 776 777 for (j = 0; len > 0; j++, len -= 8) 778 { 779 int regnum = -1; 780 int offset = 0; 781 782 switch (class[j]) 783 { 784 case AMD64_INTEGER: 785 regnum = integer_regs[integer_reg++]; 786 break; 787 788 case AMD64_SSE: 789 regnum = sse_regnum[sse_reg++]; 790 break; 791 792 case AMD64_SSEUP: 793 gdb_assert (sse_reg > 0); 794 regnum = sse_regnum[sse_reg - 1]; 795 offset = 8; 796 break; 797 798 default: 799 gdb_assert (!"Unexpected register class."); 800 } 801 802 gdb_assert (regnum != -1); 803 memset (buf, 0, sizeof buf); 804 memcpy (buf, valbuf + j * 8, min (len, 8)); 805 regcache_raw_write_part (regcache, regnum, offset, 8, buf); 806 } 807 } 808 } 809 810 /* Allocate space for the arguments on the stack. */ 811 sp -= num_elements * 8; 812 813 /* The psABI says that "The end of the input argument area shall be 814 aligned on a 16 byte boundary." */ 815 sp &= ~0xf; 816 817 /* Write out the arguments to the stack. */ 818 for (i = 0; i < num_stack_args; i++) 819 { 820 struct type *type = value_type (stack_args[i]); 821 const gdb_byte *valbuf = value_contents (stack_args[i]); 822 int len = TYPE_LENGTH (type); 823 CORE_ADDR arg_addr = sp + element * 8; 824 825 write_memory (arg_addr, valbuf, len); 826 if (arg_addr_regno[i] >= 0) 827 { 828 /* We also need to store the address of that argument in 829 the given register. */ 830 gdb_byte buf[8]; 831 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 832 833 store_unsigned_integer (buf, 8, byte_order, arg_addr); 834 regcache_cooked_write (regcache, arg_addr_regno[i], buf); 835 } 836 element += ((len + 7) / 8); 837 } 838 839 /* The psABI says that "For calls that may call functions that use 840 varargs or stdargs (prototype-less calls or calls to functions 841 containing ellipsis (...) in the declaration) %al is used as 842 hidden argument to specify the number of SSE registers used. */ 843 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); 844 return sp; 845 } 846 847 static CORE_ADDR 848 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 849 struct regcache *regcache, CORE_ADDR bp_addr, 850 int nargs, struct value **args, CORE_ADDR sp, 851 int struct_return, CORE_ADDR struct_addr) 852 { 853 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 854 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 855 gdb_byte buf[8]; 856 857 /* Pass arguments. */ 858 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); 859 860 /* Pass "hidden" argument". */ 861 if (struct_return) 862 { 863 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 864 /* The "hidden" argument is passed throught the first argument 865 register. */ 866 const int arg_regnum = tdep->call_dummy_integer_regs[0]; 867 868 store_unsigned_integer (buf, 8, byte_order, struct_addr); 869 regcache_cooked_write (regcache, arg_regnum, buf); 870 } 871 872 /* Reserve some memory on the stack for the integer-parameter registers, 873 if required by the ABI. */ 874 if (tdep->integer_param_regs_saved_in_caller_frame) 875 sp -= tdep->call_dummy_num_integer_regs * 8; 876 877 /* Store return address. */ 878 sp -= 8; 879 store_unsigned_integer (buf, 8, byte_order, bp_addr); 880 write_memory (sp, buf, 8); 881 882 /* Finally, update the stack pointer... */ 883 store_unsigned_integer (buf, 8, byte_order, sp); 884 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); 885 886 /* ...and fake a frame pointer. */ 887 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); 888 889 return sp + 16; 890 } 891 892 /* Displaced instruction handling. */ 893 894 /* A partially decoded instruction. 895 This contains enough details for displaced stepping purposes. */ 896 897 struct amd64_insn 898 { 899 /* The number of opcode bytes. */ 900 int opcode_len; 901 /* The offset of the rex prefix or -1 if not present. */ 902 int rex_offset; 903 /* The offset to the first opcode byte. */ 904 int opcode_offset; 905 /* The offset to the modrm byte or -1 if not present. */ 906 int modrm_offset; 907 908 /* The raw instruction. */ 909 gdb_byte *raw_insn; 910 }; 911 912 struct displaced_step_closure 913 { 914 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */ 915 int tmp_used; 916 int tmp_regno; 917 ULONGEST tmp_save; 918 919 /* Details of the instruction. */ 920 struct amd64_insn insn_details; 921 922 /* Amount of space allocated to insn_buf. */ 923 int max_len; 924 925 /* The possibly modified insn. 926 This is a variable-length field. */ 927 gdb_byte insn_buf[1]; 928 }; 929 930 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with 931 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative, 932 at which point delete these in favor of libopcodes' versions). */ 933 934 static const unsigned char onebyte_has_modrm[256] = { 935 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 936 /* ------------------------------- */ 937 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ 938 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ 939 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ 940 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ 941 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ 942 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ 943 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ 944 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ 945 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ 946 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ 947 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ 948 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ 949 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ 950 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ 951 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ 952 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ 953 /* ------------------------------- */ 954 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 955 }; 956 957 static const unsigned char twobyte_has_modrm[256] = { 958 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 959 /* ------------------------------- */ 960 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ 961 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ 962 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ 963 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ 964 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ 965 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ 966 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ 967 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ 968 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ 969 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ 970 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ 971 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ 972 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ 973 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ 974 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ 975 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ 976 /* ------------------------------- */ 977 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 978 }; 979 980 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp); 981 982 static int 983 rex_prefix_p (gdb_byte pfx) 984 { 985 return REX_PREFIX_P (pfx); 986 } 987 988 /* Skip the legacy instruction prefixes in INSN. 989 We assume INSN is properly sentineled so we don't have to worry 990 about falling off the end of the buffer. */ 991 992 static gdb_byte * 993 amd64_skip_prefixes (gdb_byte *insn) 994 { 995 while (1) 996 { 997 switch (*insn) 998 { 999 case DATA_PREFIX_OPCODE: 1000 case ADDR_PREFIX_OPCODE: 1001 case CS_PREFIX_OPCODE: 1002 case DS_PREFIX_OPCODE: 1003 case ES_PREFIX_OPCODE: 1004 case FS_PREFIX_OPCODE: 1005 case GS_PREFIX_OPCODE: 1006 case SS_PREFIX_OPCODE: 1007 case LOCK_PREFIX_OPCODE: 1008 case REPE_PREFIX_OPCODE: 1009 case REPNE_PREFIX_OPCODE: 1010 ++insn; 1011 continue; 1012 default: 1013 break; 1014 } 1015 break; 1016 } 1017 1018 return insn; 1019 } 1020 1021 /* Return an integer register (other than RSP) that is unused as an input 1022 operand in INSN. 1023 In order to not require adding a rex prefix if the insn doesn't already 1024 have one, the result is restricted to RAX ... RDI, sans RSP. 1025 The register numbering of the result follows architecture ordering, 1026 e.g. RDI = 7. */ 1027 1028 static int 1029 amd64_get_unused_input_int_reg (const struct amd64_insn *details) 1030 { 1031 /* 1 bit for each reg */ 1032 int used_regs_mask = 0; 1033 1034 /* There can be at most 3 int regs used as inputs in an insn, and we have 1035 7 to choose from (RAX ... RDI, sans RSP). 1036 This allows us to take a conservative approach and keep things simple. 1037 E.g. By avoiding RAX, we don't have to specifically watch for opcodes 1038 that implicitly specify RAX. */ 1039 1040 /* Avoid RAX. */ 1041 used_regs_mask |= 1 << EAX_REG_NUM; 1042 /* Similarily avoid RDX, implicit operand in divides. */ 1043 used_regs_mask |= 1 << EDX_REG_NUM; 1044 /* Avoid RSP. */ 1045 used_regs_mask |= 1 << ESP_REG_NUM; 1046 1047 /* If the opcode is one byte long and there's no ModRM byte, 1048 assume the opcode specifies a register. */ 1049 if (details->opcode_len == 1 && details->modrm_offset == -1) 1050 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7); 1051 1052 /* Mark used regs in the modrm/sib bytes. */ 1053 if (details->modrm_offset != -1) 1054 { 1055 int modrm = details->raw_insn[details->modrm_offset]; 1056 int mod = MODRM_MOD_FIELD (modrm); 1057 int reg = MODRM_REG_FIELD (modrm); 1058 int rm = MODRM_RM_FIELD (modrm); 1059 int have_sib = mod != 3 && rm == 4; 1060 1061 /* Assume the reg field of the modrm byte specifies a register. */ 1062 used_regs_mask |= 1 << reg; 1063 1064 if (have_sib) 1065 { 1066 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]); 1067 int index = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]); 1068 used_regs_mask |= 1 << base; 1069 used_regs_mask |= 1 << index; 1070 } 1071 else 1072 { 1073 used_regs_mask |= 1 << rm; 1074 } 1075 } 1076 1077 gdb_assert (used_regs_mask < 256); 1078 gdb_assert (used_regs_mask != 255); 1079 1080 /* Finally, find a free reg. */ 1081 { 1082 int i; 1083 1084 for (i = 0; i < 8; ++i) 1085 { 1086 if (! (used_regs_mask & (1 << i))) 1087 return i; 1088 } 1089 1090 /* We shouldn't get here. */ 1091 internal_error (__FILE__, __LINE__, _("unable to find free reg")); 1092 } 1093 } 1094 1095 /* Extract the details of INSN that we need. */ 1096 1097 static void 1098 amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) 1099 { 1100 gdb_byte *start = insn; 1101 int need_modrm; 1102 1103 details->raw_insn = insn; 1104 1105 details->opcode_len = -1; 1106 details->rex_offset = -1; 1107 details->opcode_offset = -1; 1108 details->modrm_offset = -1; 1109 1110 /* Skip legacy instruction prefixes. */ 1111 insn = amd64_skip_prefixes (insn); 1112 1113 /* Skip REX instruction prefix. */ 1114 if (rex_prefix_p (*insn)) 1115 { 1116 details->rex_offset = insn - start; 1117 ++insn; 1118 } 1119 1120 details->opcode_offset = insn - start; 1121 1122 if (*insn == TWO_BYTE_OPCODE_ESCAPE) 1123 { 1124 /* Two or three-byte opcode. */ 1125 ++insn; 1126 need_modrm = twobyte_has_modrm[*insn]; 1127 1128 /* Check for three-byte opcode. */ 1129 switch (*insn) 1130 { 1131 case 0x24: 1132 case 0x25: 1133 case 0x38: 1134 case 0x3a: 1135 case 0x7a: 1136 case 0x7b: 1137 ++insn; 1138 details->opcode_len = 3; 1139 break; 1140 default: 1141 details->opcode_len = 2; 1142 break; 1143 } 1144 } 1145 else 1146 { 1147 /* One-byte opcode. */ 1148 need_modrm = onebyte_has_modrm[*insn]; 1149 details->opcode_len = 1; 1150 } 1151 1152 if (need_modrm) 1153 { 1154 ++insn; 1155 details->modrm_offset = insn - start; 1156 } 1157 } 1158 1159 /* Update %rip-relative addressing in INSN. 1160 1161 %rip-relative addressing only uses a 32-bit displacement. 1162 32 bits is not enough to be guaranteed to cover the distance between where 1163 the real instruction is and where its copy is. 1164 Convert the insn to use base+disp addressing. 1165 We set base = pc + insn_length so we can leave disp unchanged. */ 1166 1167 static void 1168 fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, 1169 CORE_ADDR from, CORE_ADDR to, struct regcache *regs) 1170 { 1171 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1172 const struct amd64_insn *insn_details = &dsc->insn_details; 1173 int modrm_offset = insn_details->modrm_offset; 1174 gdb_byte *insn = insn_details->raw_insn + modrm_offset; 1175 CORE_ADDR rip_base; 1176 int32_t disp; 1177 int insn_length; 1178 int arch_tmp_regno, tmp_regno; 1179 ULONGEST orig_value; 1180 1181 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */ 1182 ++insn; 1183 1184 /* Compute the rip-relative address. */ 1185 disp = extract_signed_integer (insn, sizeof (int32_t), byte_order); 1186 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf, 1187 dsc->max_len, from); 1188 rip_base = from + insn_length; 1189 1190 /* We need a register to hold the address. 1191 Pick one not used in the insn. 1192 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */ 1193 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details); 1194 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno); 1195 1196 /* REX.B should be unset as we were using rip-relative addressing, 1197 but ensure it's unset anyway, tmp_regno is not r8-r15. */ 1198 if (insn_details->rex_offset != -1) 1199 dsc->insn_buf[insn_details->rex_offset] &= ~REX_B; 1200 1201 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value); 1202 dsc->tmp_regno = tmp_regno; 1203 dsc->tmp_save = orig_value; 1204 dsc->tmp_used = 1; 1205 1206 /* Convert the ModRM field to be base+disp. */ 1207 dsc->insn_buf[modrm_offset] &= ~0xc7; 1208 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno; 1209 1210 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base); 1211 1212 if (debug_displaced) 1213 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n" 1214 "displaced: using temp reg %d, old value %s, new value %s\n", 1215 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save), 1216 paddress (gdbarch, rip_base)); 1217 } 1218 1219 static void 1220 fixup_displaced_copy (struct gdbarch *gdbarch, 1221 struct displaced_step_closure *dsc, 1222 CORE_ADDR from, CORE_ADDR to, struct regcache *regs) 1223 { 1224 const struct amd64_insn *details = &dsc->insn_details; 1225 1226 if (details->modrm_offset != -1) 1227 { 1228 gdb_byte modrm = details->raw_insn[details->modrm_offset]; 1229 1230 if ((modrm & 0xc7) == 0x05) 1231 { 1232 /* The insn uses rip-relative addressing. 1233 Deal with it. */ 1234 fixup_riprel (gdbarch, dsc, from, to, regs); 1235 } 1236 } 1237 } 1238 1239 struct displaced_step_closure * 1240 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, 1241 CORE_ADDR from, CORE_ADDR to, 1242 struct regcache *regs) 1243 { 1244 int len = gdbarch_max_insn_length (gdbarch); 1245 /* Extra space for sentinels so fixup_{riprel,displaced_copy don't have to 1246 continually watch for running off the end of the buffer. */ 1247 int fixup_sentinel_space = len; 1248 struct displaced_step_closure *dsc = 1249 xmalloc (sizeof (*dsc) + len + fixup_sentinel_space); 1250 gdb_byte *buf = &dsc->insn_buf[0]; 1251 struct amd64_insn *details = &dsc->insn_details; 1252 1253 dsc->tmp_used = 0; 1254 dsc->max_len = len + fixup_sentinel_space; 1255 1256 read_memory (from, buf, len); 1257 1258 /* Set up the sentinel space so we don't have to worry about running 1259 off the end of the buffer. An excessive number of leading prefixes 1260 could otherwise cause this. */ 1261 memset (buf + len, 0, fixup_sentinel_space); 1262 1263 amd64_get_insn_details (buf, details); 1264 1265 /* GDB may get control back after the insn after the syscall. 1266 Presumably this is a kernel bug. 1267 If this is a syscall, make sure there's a nop afterwards. */ 1268 { 1269 int syscall_length; 1270 1271 if (amd64_syscall_p (details, &syscall_length)) 1272 buf[details->opcode_offset + syscall_length] = NOP_OPCODE; 1273 } 1274 1275 /* Modify the insn to cope with the address where it will be executed from. 1276 In particular, handle any rip-relative addressing. */ 1277 fixup_displaced_copy (gdbarch, dsc, from, to, regs); 1278 1279 write_memory (to, buf, len); 1280 1281 if (debug_displaced) 1282 { 1283 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", 1284 paddress (gdbarch, from), paddress (gdbarch, to)); 1285 displaced_step_dump_bytes (gdb_stdlog, buf, len); 1286 } 1287 1288 return dsc; 1289 } 1290 1291 static int 1292 amd64_absolute_jmp_p (const struct amd64_insn *details) 1293 { 1294 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1295 1296 if (insn[0] == 0xff) 1297 { 1298 /* jump near, absolute indirect (/4) */ 1299 if ((insn[1] & 0x38) == 0x20) 1300 return 1; 1301 1302 /* jump far, absolute indirect (/5) */ 1303 if ((insn[1] & 0x38) == 0x28) 1304 return 1; 1305 } 1306 1307 return 0; 1308 } 1309 1310 static int 1311 amd64_absolute_call_p (const struct amd64_insn *details) 1312 { 1313 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1314 1315 if (insn[0] == 0xff) 1316 { 1317 /* Call near, absolute indirect (/2) */ 1318 if ((insn[1] & 0x38) == 0x10) 1319 return 1; 1320 1321 /* Call far, absolute indirect (/3) */ 1322 if ((insn[1] & 0x38) == 0x18) 1323 return 1; 1324 } 1325 1326 return 0; 1327 } 1328 1329 static int 1330 amd64_ret_p (const struct amd64_insn *details) 1331 { 1332 /* NOTE: gcc can emit "repz ; ret". */ 1333 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1334 1335 switch (insn[0]) 1336 { 1337 case 0xc2: /* ret near, pop N bytes */ 1338 case 0xc3: /* ret near */ 1339 case 0xca: /* ret far, pop N bytes */ 1340 case 0xcb: /* ret far */ 1341 case 0xcf: /* iret */ 1342 return 1; 1343 1344 default: 1345 return 0; 1346 } 1347 } 1348 1349 static int 1350 amd64_call_p (const struct amd64_insn *details) 1351 { 1352 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1353 1354 if (amd64_absolute_call_p (details)) 1355 return 1; 1356 1357 /* call near, relative */ 1358 if (insn[0] == 0xe8) 1359 return 1; 1360 1361 return 0; 1362 } 1363 1364 /* Return non-zero if INSN is a system call, and set *LENGTHP to its 1365 length in bytes. Otherwise, return zero. */ 1366 1367 static int 1368 amd64_syscall_p (const struct amd64_insn *details, int *lengthp) 1369 { 1370 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1371 1372 if (insn[0] == 0x0f && insn[1] == 0x05) 1373 { 1374 *lengthp = 2; 1375 return 1; 1376 } 1377 1378 return 0; 1379 } 1380 1381 /* Fix up the state of registers and memory after having single-stepped 1382 a displaced instruction. */ 1383 1384 void 1385 amd64_displaced_step_fixup (struct gdbarch *gdbarch, 1386 struct displaced_step_closure *dsc, 1387 CORE_ADDR from, CORE_ADDR to, 1388 struct regcache *regs) 1389 { 1390 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1391 /* The offset we applied to the instruction's address. */ 1392 ULONGEST insn_offset = to - from; 1393 gdb_byte *insn = dsc->insn_buf; 1394 const struct amd64_insn *insn_details = &dsc->insn_details; 1395 1396 if (debug_displaced) 1397 fprintf_unfiltered (gdb_stdlog, 1398 "displaced: fixup (%s, %s), " 1399 "insn = 0x%02x 0x%02x ...\n", 1400 paddress (gdbarch, from), paddress (gdbarch, to), 1401 insn[0], insn[1]); 1402 1403 /* If we used a tmp reg, restore it. */ 1404 1405 if (dsc->tmp_used) 1406 { 1407 if (debug_displaced) 1408 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n", 1409 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save)); 1410 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save); 1411 } 1412 1413 /* The list of issues to contend with here is taken from 1414 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28. 1415 Yay for Free Software! */ 1416 1417 /* Relocate the %rip back to the program's instruction stream, 1418 if necessary. */ 1419 1420 /* Except in the case of absolute or indirect jump or call 1421 instructions, or a return instruction, the new rip is relative to 1422 the displaced instruction; make it relative to the original insn. 1423 Well, signal handler returns don't need relocation either, but we use the 1424 value of %rip to recognize those; see below. */ 1425 if (! amd64_absolute_jmp_p (insn_details) 1426 && ! amd64_absolute_call_p (insn_details) 1427 && ! amd64_ret_p (insn_details)) 1428 { 1429 ULONGEST orig_rip; 1430 int insn_len; 1431 1432 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip); 1433 1434 /* A signal trampoline system call changes the %rip, resuming 1435 execution of the main program after the signal handler has 1436 returned. That makes them like 'return' instructions; we 1437 shouldn't relocate %rip. 1438 1439 But most system calls don't, and we do need to relocate %rip. 1440 1441 Our heuristic for distinguishing these cases: if stepping 1442 over the system call instruction left control directly after 1443 the instruction, the we relocate --- control almost certainly 1444 doesn't belong in the displaced copy. Otherwise, we assume 1445 the instruction has put control where it belongs, and leave 1446 it unrelocated. Goodness help us if there are PC-relative 1447 system calls. */ 1448 if (amd64_syscall_p (insn_details, &insn_len) 1449 && orig_rip != to + insn_len 1450 /* GDB can get control back after the insn after the syscall. 1451 Presumably this is a kernel bug. 1452 Fixup ensures its a nop, we add one to the length for it. */ 1453 && orig_rip != to + insn_len + 1) 1454 { 1455 if (debug_displaced) 1456 fprintf_unfiltered (gdb_stdlog, 1457 "displaced: syscall changed %%rip; " 1458 "not relocating\n"); 1459 } 1460 else 1461 { 1462 ULONGEST rip = orig_rip - insn_offset; 1463 1464 /* If we just stepped over a breakpoint insn, we don't backup 1465 the pc on purpose; this is to match behaviour without 1466 stepping. */ 1467 1468 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip); 1469 1470 if (debug_displaced) 1471 fprintf_unfiltered (gdb_stdlog, 1472 "displaced: " 1473 "relocated %%rip from %s to %s\n", 1474 paddress (gdbarch, orig_rip), 1475 paddress (gdbarch, rip)); 1476 } 1477 } 1478 1479 /* If the instruction was PUSHFL, then the TF bit will be set in the 1480 pushed value, and should be cleared. We'll leave this for later, 1481 since GDB already messes up the TF flag when stepping over a 1482 pushfl. */ 1483 1484 /* If the instruction was a call, the return address now atop the 1485 stack is the address following the copied instruction. We need 1486 to make it the address following the original instruction. */ 1487 if (amd64_call_p (insn_details)) 1488 { 1489 ULONGEST rsp; 1490 ULONGEST retaddr; 1491 const ULONGEST retaddr_len = 8; 1492 1493 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp); 1494 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order); 1495 retaddr = (retaddr - insn_offset) & 0xffffffffUL; 1496 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr); 1497 1498 if (debug_displaced) 1499 fprintf_unfiltered (gdb_stdlog, 1500 "displaced: relocated return addr at %s " 1501 "to %s\n", 1502 paddress (gdbarch, rsp), 1503 paddress (gdbarch, retaddr)); 1504 } 1505 } 1506 1507 /* If the instruction INSN uses RIP-relative addressing, return the 1508 offset into the raw INSN where the displacement to be adjusted is 1509 found. Returns 0 if the instruction doesn't use RIP-relative 1510 addressing. */ 1511 1512 static int 1513 rip_relative_offset (struct amd64_insn *insn) 1514 { 1515 if (insn->modrm_offset != -1) 1516 { 1517 gdb_byte modrm = insn->raw_insn[insn->modrm_offset]; 1518 1519 if ((modrm & 0xc7) == 0x05) 1520 { 1521 /* The displacement is found right after the ModRM byte. */ 1522 return insn->modrm_offset + 1; 1523 } 1524 } 1525 1526 return 0; 1527 } 1528 1529 static void 1530 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) 1531 { 1532 target_write_memory (*to, buf, len); 1533 *to += len; 1534 } 1535 1536 void 1537 amd64_relocate_instruction (struct gdbarch *gdbarch, 1538 CORE_ADDR *to, CORE_ADDR oldloc) 1539 { 1540 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1541 int len = gdbarch_max_insn_length (gdbarch); 1542 /* Extra space for sentinels. */ 1543 int fixup_sentinel_space = len; 1544 gdb_byte *buf = xmalloc (len + fixup_sentinel_space); 1545 struct amd64_insn insn_details; 1546 int offset = 0; 1547 LONGEST rel32, newrel; 1548 gdb_byte *insn; 1549 int insn_length; 1550 1551 read_memory (oldloc, buf, len); 1552 1553 /* Set up the sentinel space so we don't have to worry about running 1554 off the end of the buffer. An excessive number of leading prefixes 1555 could otherwise cause this. */ 1556 memset (buf + len, 0, fixup_sentinel_space); 1557 1558 insn = buf; 1559 amd64_get_insn_details (insn, &insn_details); 1560 1561 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc); 1562 1563 /* Skip legacy instruction prefixes. */ 1564 insn = amd64_skip_prefixes (insn); 1565 1566 /* Adjust calls with 32-bit relative addresses as push/jump, with 1567 the address pushed being the location where the original call in 1568 the user program would return to. */ 1569 if (insn[0] == 0xe8) 1570 { 1571 gdb_byte push_buf[16]; 1572 unsigned int ret_addr; 1573 1574 /* Where "ret" in the original code will return to. */ 1575 ret_addr = oldloc + insn_length; 1576 push_buf[0] = 0x68; /* pushq $... */ 1577 memcpy (&push_buf[1], &ret_addr, 4); 1578 /* Push the push. */ 1579 append_insns (to, 5, push_buf); 1580 1581 /* Convert the relative call to a relative jump. */ 1582 insn[0] = 0xe9; 1583 1584 /* Adjust the destination offset. */ 1585 rel32 = extract_signed_integer (insn + 1, 4, byte_order); 1586 newrel = (oldloc - *to) + rel32; 1587 store_signed_integer (insn + 1, 4, byte_order, newrel); 1588 1589 if (debug_displaced) 1590 fprintf_unfiltered (gdb_stdlog, 1591 "Adjusted insn rel32=%s at %s to" 1592 " rel32=%s at %s\n", 1593 hex_string (rel32), paddress (gdbarch, oldloc), 1594 hex_string (newrel), paddress (gdbarch, *to)); 1595 1596 /* Write the adjusted jump into its displaced location. */ 1597 append_insns (to, 5, insn); 1598 return; 1599 } 1600 1601 offset = rip_relative_offset (&insn_details); 1602 if (!offset) 1603 { 1604 /* Adjust jumps with 32-bit relative addresses. Calls are 1605 already handled above. */ 1606 if (insn[0] == 0xe9) 1607 offset = 1; 1608 /* Adjust conditional jumps. */ 1609 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) 1610 offset = 2; 1611 } 1612 1613 if (offset) 1614 { 1615 rel32 = extract_signed_integer (insn + offset, 4, byte_order); 1616 newrel = (oldloc - *to) + rel32; 1617 store_signed_integer (insn + offset, 4, byte_order, newrel); 1618 if (debug_displaced) 1619 fprintf_unfiltered (gdb_stdlog, 1620 "Adjusted insn rel32=%s at %s to" 1621 " rel32=%s at %s\n", 1622 hex_string (rel32), paddress (gdbarch, oldloc), 1623 hex_string (newrel), paddress (gdbarch, *to)); 1624 } 1625 1626 /* Write the adjusted instruction into its displaced location. */ 1627 append_insns (to, insn_length, buf); 1628 } 1629 1630 1631 /* The maximum number of saved registers. This should include %rip. */ 1632 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS 1633 1634 struct amd64_frame_cache 1635 { 1636 /* Base address. */ 1637 CORE_ADDR base; 1638 int base_p; 1639 CORE_ADDR sp_offset; 1640 CORE_ADDR pc; 1641 1642 /* Saved registers. */ 1643 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; 1644 CORE_ADDR saved_sp; 1645 int saved_sp_reg; 1646 1647 /* Do we have a frame? */ 1648 int frameless_p; 1649 }; 1650 1651 /* Initialize a frame cache. */ 1652 1653 static void 1654 amd64_init_frame_cache (struct amd64_frame_cache *cache) 1655 { 1656 int i; 1657 1658 /* Base address. */ 1659 cache->base = 0; 1660 cache->base_p = 0; 1661 cache->sp_offset = -8; 1662 cache->pc = 0; 1663 1664 /* Saved registers. We initialize these to -1 since zero is a valid 1665 offset (that's where %rbp is supposed to be stored). 1666 The values start out as being offsets, and are later converted to 1667 addresses (at which point -1 is interpreted as an address, still meaning 1668 "invalid"). */ 1669 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 1670 cache->saved_regs[i] = -1; 1671 cache->saved_sp = 0; 1672 cache->saved_sp_reg = -1; 1673 1674 /* Frameless until proven otherwise. */ 1675 cache->frameless_p = 1; 1676 } 1677 1678 /* Allocate and initialize a frame cache. */ 1679 1680 static struct amd64_frame_cache * 1681 amd64_alloc_frame_cache (void) 1682 { 1683 struct amd64_frame_cache *cache; 1684 1685 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); 1686 amd64_init_frame_cache (cache); 1687 return cache; 1688 } 1689 1690 /* GCC 4.4 and later, can put code in the prologue to realign the 1691 stack pointer. Check whether PC points to such code, and update 1692 CACHE accordingly. Return the first instruction after the code 1693 sequence or CURRENT_PC, whichever is smaller. If we don't 1694 recognize the code, return PC. */ 1695 1696 static CORE_ADDR 1697 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, 1698 struct amd64_frame_cache *cache) 1699 { 1700 /* There are 2 code sequences to re-align stack before the frame 1701 gets set up: 1702 1703 1. Use a caller-saved saved register: 1704 1705 leaq 8(%rsp), %reg 1706 andq $-XXX, %rsp 1707 pushq -8(%reg) 1708 1709 2. Use a callee-saved saved register: 1710 1711 pushq %reg 1712 leaq 16(%rsp), %reg 1713 andq $-XXX, %rsp 1714 pushq -8(%reg) 1715 1716 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: 1717 1718 0x48 0x83 0xe4 0xf0 andq $-16, %rsp 1719 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp 1720 */ 1721 1722 gdb_byte buf[18]; 1723 int reg, r; 1724 int offset, offset_and; 1725 1726 if (target_read_memory (pc, buf, sizeof buf)) 1727 return pc; 1728 1729 /* Check caller-saved saved register. The first instruction has 1730 to be "leaq 8(%rsp), %reg". */ 1731 if ((buf[0] & 0xfb) == 0x48 1732 && buf[1] == 0x8d 1733 && buf[3] == 0x24 1734 && buf[4] == 0x8) 1735 { 1736 /* MOD must be binary 10 and R/M must be binary 100. */ 1737 if ((buf[2] & 0xc7) != 0x44) 1738 return pc; 1739 1740 /* REG has register number. */ 1741 reg = (buf[2] >> 3) & 7; 1742 1743 /* Check the REX.R bit. */ 1744 if (buf[0] == 0x4c) 1745 reg += 8; 1746 1747 offset = 5; 1748 } 1749 else 1750 { 1751 /* Check callee-saved saved register. The first instruction 1752 has to be "pushq %reg". */ 1753 reg = 0; 1754 if ((buf[0] & 0xf8) == 0x50) 1755 offset = 0; 1756 else if ((buf[0] & 0xf6) == 0x40 1757 && (buf[1] & 0xf8) == 0x50) 1758 { 1759 /* Check the REX.B bit. */ 1760 if ((buf[0] & 1) != 0) 1761 reg = 8; 1762 1763 offset = 1; 1764 } 1765 else 1766 return pc; 1767 1768 /* Get register. */ 1769 reg += buf[offset] & 0x7; 1770 1771 offset++; 1772 1773 /* The next instruction has to be "leaq 16(%rsp), %reg". */ 1774 if ((buf[offset] & 0xfb) != 0x48 1775 || buf[offset + 1] != 0x8d 1776 || buf[offset + 3] != 0x24 1777 || buf[offset + 4] != 0x10) 1778 return pc; 1779 1780 /* MOD must be binary 10 and R/M must be binary 100. */ 1781 if ((buf[offset + 2] & 0xc7) != 0x44) 1782 return pc; 1783 1784 /* REG has register number. */ 1785 r = (buf[offset + 2] >> 3) & 7; 1786 1787 /* Check the REX.R bit. */ 1788 if (buf[offset] == 0x4c) 1789 r += 8; 1790 1791 /* Registers in pushq and leaq have to be the same. */ 1792 if (reg != r) 1793 return pc; 1794 1795 offset += 5; 1796 } 1797 1798 /* Rigister can't be %rsp nor %rbp. */ 1799 if (reg == 4 || reg == 5) 1800 return pc; 1801 1802 /* The next instruction has to be "andq $-XXX, %rsp". */ 1803 if (buf[offset] != 0x48 1804 || buf[offset + 2] != 0xe4 1805 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) 1806 return pc; 1807 1808 offset_and = offset; 1809 offset += buf[offset + 1] == 0x81 ? 7 : 4; 1810 1811 /* The next instruction has to be "pushq -8(%reg)". */ 1812 r = 0; 1813 if (buf[offset] == 0xff) 1814 offset++; 1815 else if ((buf[offset] & 0xf6) == 0x40 1816 && buf[offset + 1] == 0xff) 1817 { 1818 /* Check the REX.B bit. */ 1819 if ((buf[offset] & 0x1) != 0) 1820 r = 8; 1821 offset += 2; 1822 } 1823 else 1824 return pc; 1825 1826 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary 1827 01. */ 1828 if (buf[offset + 1] != 0xf8 1829 || (buf[offset] & 0xf8) != 0x70) 1830 return pc; 1831 1832 /* R/M has register. */ 1833 r += buf[offset] & 7; 1834 1835 /* Registers in leaq and pushq have to be the same. */ 1836 if (reg != r) 1837 return pc; 1838 1839 if (current_pc > pc + offset_and) 1840 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); 1841 1842 return min (pc + offset + 2, current_pc); 1843 } 1844 1845 /* Do a limited analysis of the prologue at PC and update CACHE 1846 accordingly. Bail out early if CURRENT_PC is reached. Return the 1847 address where the analysis stopped. 1848 1849 We will handle only functions beginning with: 1850 1851 pushq %rbp 0x55 1852 movq %rsp, %rbp 0x48 0x89 0xe5 1853 1854 Any function that doesn't start with this sequence will be assumed 1855 to have no prologue and thus no valid frame pointer in %rbp. */ 1856 1857 static CORE_ADDR 1858 amd64_analyze_prologue (struct gdbarch *gdbarch, 1859 CORE_ADDR pc, CORE_ADDR current_pc, 1860 struct amd64_frame_cache *cache) 1861 { 1862 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1863 static gdb_byte proto[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */ 1864 gdb_byte buf[3]; 1865 gdb_byte op; 1866 1867 if (current_pc <= pc) 1868 return current_pc; 1869 1870 pc = amd64_analyze_stack_align (pc, current_pc, cache); 1871 1872 op = read_memory_unsigned_integer (pc, 1, byte_order); 1873 1874 if (op == 0x55) /* pushq %rbp */ 1875 { 1876 /* Take into account that we've executed the `pushq %rbp' that 1877 starts this instruction sequence. */ 1878 cache->saved_regs[AMD64_RBP_REGNUM] = 0; 1879 cache->sp_offset += 8; 1880 1881 /* If that's all, return now. */ 1882 if (current_pc <= pc + 1) 1883 return current_pc; 1884 1885 /* Check for `movq %rsp, %rbp'. */ 1886 read_memory (pc + 1, buf, 3); 1887 if (memcmp (buf, proto, 3) != 0) 1888 return pc + 1; 1889 1890 /* OK, we actually have a frame. */ 1891 cache->frameless_p = 0; 1892 return pc + 4; 1893 } 1894 1895 return pc; 1896 } 1897 1898 /* Return PC of first real instruction. */ 1899 1900 static CORE_ADDR 1901 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1902 { 1903 struct amd64_frame_cache cache; 1904 CORE_ADDR pc; 1905 1906 amd64_init_frame_cache (&cache); 1907 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL, 1908 &cache); 1909 if (cache.frameless_p) 1910 return start_pc; 1911 1912 return pc; 1913 } 1914 1915 1916 /* Normal frames. */ 1917 1918 static void 1919 amd64_frame_cache_1 (struct frame_info *this_frame, 1920 struct amd64_frame_cache *cache) 1921 { 1922 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1923 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1924 gdb_byte buf[8]; 1925 int i; 1926 1927 cache->pc = get_frame_func (this_frame); 1928 if (cache->pc != 0) 1929 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), 1930 cache); 1931 1932 if (cache->frameless_p) 1933 { 1934 /* We didn't find a valid frame. If we're at the start of a 1935 function, or somewhere half-way its prologue, the function's 1936 frame probably hasn't been fully setup yet. Try to 1937 reconstruct the base address for the stack frame by looking 1938 at the stack pointer. For truly "frameless" functions this 1939 might work too. */ 1940 1941 if (cache->saved_sp_reg != -1) 1942 { 1943 /* Stack pointer has been saved. */ 1944 get_frame_register (this_frame, cache->saved_sp_reg, buf); 1945 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order); 1946 1947 /* We're halfway aligning the stack. */ 1948 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8; 1949 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8; 1950 1951 /* This will be added back below. */ 1952 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base; 1953 } 1954 else 1955 { 1956 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); 1957 cache->base = extract_unsigned_integer (buf, 8, byte_order) 1958 + cache->sp_offset; 1959 } 1960 } 1961 else 1962 { 1963 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf); 1964 cache->base = extract_unsigned_integer (buf, 8, byte_order); 1965 } 1966 1967 /* Now that we have the base address for the stack frame we can 1968 calculate the value of %rsp in the calling frame. */ 1969 cache->saved_sp = cache->base + 16; 1970 1971 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a 1972 frame we find it at the same offset from the reconstructed base 1973 address. If we're halfway aligning the stack, %rip is handled 1974 differently (see above). */ 1975 if (!cache->frameless_p || cache->saved_sp_reg == -1) 1976 cache->saved_regs[AMD64_RIP_REGNUM] = 8; 1977 1978 /* Adjust all the saved registers such that they contain addresses 1979 instead of offsets. */ 1980 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 1981 if (cache->saved_regs[i] != -1) 1982 cache->saved_regs[i] += cache->base; 1983 1984 cache->base_p = 1; 1985 } 1986 1987 static struct amd64_frame_cache * 1988 amd64_frame_cache (struct frame_info *this_frame, void **this_cache) 1989 { 1990 volatile struct gdb_exception ex; 1991 struct amd64_frame_cache *cache; 1992 1993 if (*this_cache) 1994 return *this_cache; 1995 1996 cache = amd64_alloc_frame_cache (); 1997 *this_cache = cache; 1998 1999 TRY_CATCH (ex, RETURN_MASK_ERROR) 2000 { 2001 amd64_frame_cache_1 (this_frame, cache); 2002 } 2003 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) 2004 throw_exception (ex); 2005 2006 return cache; 2007 } 2008 2009 static enum unwind_stop_reason 2010 amd64_frame_unwind_stop_reason (struct frame_info *this_frame, 2011 void **this_cache) 2012 { 2013 struct amd64_frame_cache *cache = 2014 amd64_frame_cache (this_frame, this_cache); 2015 2016 if (!cache->base_p) 2017 return UNWIND_UNAVAILABLE; 2018 2019 /* This marks the outermost frame. */ 2020 if (cache->base == 0) 2021 return UNWIND_OUTERMOST; 2022 2023 return UNWIND_NO_REASON; 2024 } 2025 2026 static void 2027 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache, 2028 struct frame_id *this_id) 2029 { 2030 struct amd64_frame_cache *cache = 2031 amd64_frame_cache (this_frame, this_cache); 2032 2033 if (!cache->base_p) 2034 return; 2035 2036 /* This marks the outermost frame. */ 2037 if (cache->base == 0) 2038 return; 2039 2040 (*this_id) = frame_id_build (cache->base + 16, cache->pc); 2041 } 2042 2043 static struct value * 2044 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache, 2045 int regnum) 2046 { 2047 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2048 struct amd64_frame_cache *cache = 2049 amd64_frame_cache (this_frame, this_cache); 2050 2051 gdb_assert (regnum >= 0); 2052 2053 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) 2054 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); 2055 2056 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) 2057 return frame_unwind_got_memory (this_frame, regnum, 2058 cache->saved_regs[regnum]); 2059 2060 return frame_unwind_got_register (this_frame, regnum, regnum); 2061 } 2062 2063 static const struct frame_unwind amd64_frame_unwind = 2064 { 2065 NORMAL_FRAME, 2066 amd64_frame_unwind_stop_reason, 2067 amd64_frame_this_id, 2068 amd64_frame_prev_register, 2069 NULL, 2070 default_frame_sniffer 2071 }; 2072 2073 2074 /* Signal trampolines. */ 2075 2076 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and 2077 64-bit variants. This would require using identical frame caches 2078 on both platforms. */ 2079 2080 static struct amd64_frame_cache * 2081 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) 2082 { 2083 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2084 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2085 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2086 volatile struct gdb_exception ex; 2087 struct amd64_frame_cache *cache; 2088 CORE_ADDR addr; 2089 gdb_byte buf[8]; 2090 int i; 2091 2092 if (*this_cache) 2093 return *this_cache; 2094 2095 cache = amd64_alloc_frame_cache (); 2096 2097 TRY_CATCH (ex, RETURN_MASK_ERROR) 2098 { 2099 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); 2100 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8; 2101 2102 addr = tdep->sigcontext_addr (this_frame); 2103 gdb_assert (tdep->sc_reg_offset); 2104 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); 2105 for (i = 0; i < tdep->sc_num_regs; i++) 2106 if (tdep->sc_reg_offset[i] != -1) 2107 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; 2108 2109 cache->base_p = 1; 2110 } 2111 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) 2112 throw_exception (ex); 2113 2114 *this_cache = cache; 2115 return cache; 2116 } 2117 2118 static enum unwind_stop_reason 2119 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, 2120 void **this_cache) 2121 { 2122 struct amd64_frame_cache *cache = 2123 amd64_sigtramp_frame_cache (this_frame, this_cache); 2124 2125 if (!cache->base_p) 2126 return UNWIND_UNAVAILABLE; 2127 2128 return UNWIND_NO_REASON; 2129 } 2130 2131 static void 2132 amd64_sigtramp_frame_this_id (struct frame_info *this_frame, 2133 void **this_cache, struct frame_id *this_id) 2134 { 2135 struct amd64_frame_cache *cache = 2136 amd64_sigtramp_frame_cache (this_frame, this_cache); 2137 2138 if (!cache->base_p) 2139 return; 2140 2141 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame)); 2142 } 2143 2144 static struct value * 2145 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame, 2146 void **this_cache, int regnum) 2147 { 2148 /* Make sure we've initialized the cache. */ 2149 amd64_sigtramp_frame_cache (this_frame, this_cache); 2150 2151 return amd64_frame_prev_register (this_frame, this_cache, regnum); 2152 } 2153 2154 static int 2155 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, 2156 struct frame_info *this_frame, 2157 void **this_cache) 2158 { 2159 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); 2160 2161 /* We shouldn't even bother if we don't have a sigcontext_addr 2162 handler. */ 2163 if (tdep->sigcontext_addr == NULL) 2164 return 0; 2165 2166 if (tdep->sigtramp_p != NULL) 2167 { 2168 if (tdep->sigtramp_p (this_frame)) 2169 return 1; 2170 } 2171 2172 if (tdep->sigtramp_start != 0) 2173 { 2174 CORE_ADDR pc = get_frame_pc (this_frame); 2175 2176 gdb_assert (tdep->sigtramp_end != 0); 2177 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) 2178 return 1; 2179 } 2180 2181 return 0; 2182 } 2183 2184 static const struct frame_unwind amd64_sigtramp_frame_unwind = 2185 { 2186 SIGTRAMP_FRAME, 2187 amd64_sigtramp_frame_unwind_stop_reason, 2188 amd64_sigtramp_frame_this_id, 2189 amd64_sigtramp_frame_prev_register, 2190 NULL, 2191 amd64_sigtramp_frame_sniffer 2192 }; 2193 2194 2195 static CORE_ADDR 2196 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache) 2197 { 2198 struct amd64_frame_cache *cache = 2199 amd64_frame_cache (this_frame, this_cache); 2200 2201 return cache->base; 2202 } 2203 2204 static const struct frame_base amd64_frame_base = 2205 { 2206 &amd64_frame_unwind, 2207 amd64_frame_base_address, 2208 amd64_frame_base_address, 2209 amd64_frame_base_address 2210 }; 2211 2212 /* Normal frames, but in a function epilogue. */ 2213 2214 /* The epilogue is defined here as the 'ret' instruction, which will 2215 follow any instruction such as 'leave' or 'pop %ebp' that destroys 2216 the function's stack frame. */ 2217 2218 static int 2219 amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) 2220 { 2221 gdb_byte insn; 2222 2223 if (target_read_memory (pc, &insn, 1)) 2224 return 0; /* Can't read memory at pc. */ 2225 2226 if (insn != 0xc3) /* 'ret' instruction. */ 2227 return 0; 2228 2229 return 1; 2230 } 2231 2232 static int 2233 amd64_epilogue_frame_sniffer (const struct frame_unwind *self, 2234 struct frame_info *this_frame, 2235 void **this_prologue_cache) 2236 { 2237 if (frame_relative_level (this_frame) == 0) 2238 return amd64_in_function_epilogue_p (get_frame_arch (this_frame), 2239 get_frame_pc (this_frame)); 2240 else 2241 return 0; 2242 } 2243 2244 static struct amd64_frame_cache * 2245 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) 2246 { 2247 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2248 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2249 volatile struct gdb_exception ex; 2250 struct amd64_frame_cache *cache; 2251 gdb_byte buf[8]; 2252 2253 if (*this_cache) 2254 return *this_cache; 2255 2256 cache = amd64_alloc_frame_cache (); 2257 *this_cache = cache; 2258 2259 TRY_CATCH (ex, RETURN_MASK_ERROR) 2260 { 2261 /* Cache base will be %esp plus cache->sp_offset (-8). */ 2262 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); 2263 cache->base = extract_unsigned_integer (buf, 8, 2264 byte_order) + cache->sp_offset; 2265 2266 /* Cache pc will be the frame func. */ 2267 cache->pc = get_frame_pc (this_frame); 2268 2269 /* The saved %esp will be at cache->base plus 16. */ 2270 cache->saved_sp = cache->base + 16; 2271 2272 /* The saved %eip will be at cache->base plus 8. */ 2273 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8; 2274 2275 cache->base_p = 1; 2276 } 2277 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) 2278 throw_exception (ex); 2279 2280 return cache; 2281 } 2282 2283 static enum unwind_stop_reason 2284 amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, 2285 void **this_cache) 2286 { 2287 struct amd64_frame_cache *cache 2288 = amd64_epilogue_frame_cache (this_frame, this_cache); 2289 2290 if (!cache->base_p) 2291 return UNWIND_UNAVAILABLE; 2292 2293 return UNWIND_NO_REASON; 2294 } 2295 2296 static void 2297 amd64_epilogue_frame_this_id (struct frame_info *this_frame, 2298 void **this_cache, 2299 struct frame_id *this_id) 2300 { 2301 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame, 2302 this_cache); 2303 2304 if (!cache->base_p) 2305 return; 2306 2307 (*this_id) = frame_id_build (cache->base + 8, cache->pc); 2308 } 2309 2310 static const struct frame_unwind amd64_epilogue_frame_unwind = 2311 { 2312 NORMAL_FRAME, 2313 amd64_epilogue_frame_unwind_stop_reason, 2314 amd64_epilogue_frame_this_id, 2315 amd64_frame_prev_register, 2316 NULL, 2317 amd64_epilogue_frame_sniffer 2318 }; 2319 2320 static struct frame_id 2321 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 2322 { 2323 CORE_ADDR fp; 2324 2325 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM); 2326 2327 return frame_id_build (fp + 16, get_frame_pc (this_frame)); 2328 } 2329 2330 /* 16 byte align the SP per frame requirements. */ 2331 2332 static CORE_ADDR 2333 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 2334 { 2335 return sp & -(CORE_ADDR)16; 2336 } 2337 2338 2339 /* Supply register REGNUM from the buffer specified by FPREGS and LEN 2340 in the floating-point register set REGSET to register cache 2341 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 2342 2343 static void 2344 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, 2345 int regnum, const void *fpregs, size_t len) 2346 { 2347 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 2348 2349 gdb_assert (len == tdep->sizeof_fpregset); 2350 amd64_supply_fxsave (regcache, regnum, fpregs); 2351 } 2352 2353 /* Collect register REGNUM from the register cache REGCACHE and store 2354 it in the buffer specified by FPREGS and LEN as described by the 2355 floating-point register set REGSET. If REGNUM is -1, do this for 2356 all registers in REGSET. */ 2357 2358 static void 2359 amd64_collect_fpregset (const struct regset *regset, 2360 const struct regcache *regcache, 2361 int regnum, void *fpregs, size_t len) 2362 { 2363 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 2364 2365 gdb_assert (len == tdep->sizeof_fpregset); 2366 amd64_collect_fxsave (regcache, regnum, fpregs); 2367 } 2368 2369 /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */ 2370 2371 static void 2372 amd64_supply_xstateregset (const struct regset *regset, 2373 struct regcache *regcache, int regnum, 2374 const void *xstateregs, size_t len) 2375 { 2376 amd64_supply_xsave (regcache, regnum, xstateregs); 2377 } 2378 2379 /* Similar to amd64_collect_fpregset, but use XSAVE extended state. */ 2380 2381 static void 2382 amd64_collect_xstateregset (const struct regset *regset, 2383 const struct regcache *regcache, 2384 int regnum, void *xstateregs, size_t len) 2385 { 2386 amd64_collect_xsave (regcache, regnum, xstateregs, 1); 2387 } 2388 2389 /* Return the appropriate register set for the core section identified 2390 by SECT_NAME and SECT_SIZE. */ 2391 2392 static const struct regset * 2393 amd64_regset_from_core_section (struct gdbarch *gdbarch, 2394 const char *sect_name, size_t sect_size) 2395 { 2396 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2397 2398 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) 2399 { 2400 if (tdep->fpregset == NULL) 2401 tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset, 2402 amd64_collect_fpregset); 2403 2404 return tdep->fpregset; 2405 } 2406 2407 if (strcmp (sect_name, ".reg-xstate") == 0) 2408 { 2409 if (tdep->xstateregset == NULL) 2410 tdep->xstateregset = regset_alloc (gdbarch, 2411 amd64_supply_xstateregset, 2412 amd64_collect_xstateregset); 2413 2414 return tdep->xstateregset; 2415 } 2416 2417 return i386_regset_from_core_section (gdbarch, sect_name, sect_size); 2418 } 2419 2420 2421 /* Figure out where the longjmp will land. Slurp the jmp_buf out of 2422 %rdi. We expect its value to be a pointer to the jmp_buf structure 2423 from which we extract the address that we will land at. This 2424 address is copied into PC. This routine returns non-zero on 2425 success. */ 2426 2427 static int 2428 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 2429 { 2430 gdb_byte buf[8]; 2431 CORE_ADDR jb_addr; 2432 struct gdbarch *gdbarch = get_frame_arch (frame); 2433 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; 2434 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr); 2435 2436 /* If JB_PC_OFFSET is -1, we have no way to find out where the 2437 longjmp will land. */ 2438 if (jb_pc_offset == -1) 2439 return 0; 2440 2441 get_frame_register (frame, AMD64_RDI_REGNUM, buf); 2442 jb_addr= extract_typed_address 2443 (buf, builtin_type (gdbarch)->builtin_data_ptr); 2444 if (target_read_memory (jb_addr + jb_pc_offset, buf, len)) 2445 return 0; 2446 2447 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); 2448 2449 return 1; 2450 } 2451 2452 static const int amd64_record_regmap[] = 2453 { 2454 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM, 2455 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, 2456 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM, 2457 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM, 2458 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM, 2459 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM 2460 }; 2461 2462 void 2463 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 2464 { 2465 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2466 const struct target_desc *tdesc = info.target_desc; 2467 2468 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its 2469 floating-point registers. */ 2470 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; 2471 2472 if (! tdesc_has_registers (tdesc)) 2473 tdesc = tdesc_amd64; 2474 tdep->tdesc = tdesc; 2475 2476 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS; 2477 tdep->register_names = amd64_register_names; 2478 2479 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL) 2480 { 2481 tdep->ymmh_register_names = amd64_ymmh_names; 2482 tdep->num_ymm_regs = 16; 2483 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM; 2484 } 2485 2486 tdep->num_byte_regs = 20; 2487 tdep->num_word_regs = 16; 2488 tdep->num_dword_regs = 16; 2489 /* Avoid wiring in the MMX registers for now. */ 2490 tdep->num_mmx_regs = 0; 2491 2492 set_gdbarch_pseudo_register_read (gdbarch, 2493 amd64_pseudo_register_read); 2494 set_gdbarch_pseudo_register_write (gdbarch, 2495 amd64_pseudo_register_write); 2496 2497 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name); 2498 2499 /* AMD64 has an FPU and 16 SSE registers. */ 2500 tdep->st0_regnum = AMD64_ST0_REGNUM; 2501 tdep->num_xmm_regs = 16; 2502 2503 /* This is what all the fuss is about. */ 2504 set_gdbarch_long_bit (gdbarch, 64); 2505 set_gdbarch_long_long_bit (gdbarch, 64); 2506 set_gdbarch_ptr_bit (gdbarch, 64); 2507 2508 /* In contrast to the i386, on AMD64 a `long double' actually takes 2509 up 128 bits, even though it's still based on the i387 extended 2510 floating-point format which has only 80 significant bits. */ 2511 set_gdbarch_long_double_bit (gdbarch, 128); 2512 2513 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); 2514 2515 /* Register numbers of various important registers. */ 2516 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ 2517 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ 2518 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ 2519 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ 2520 2521 /* The "default" register numbering scheme for AMD64 is referred to 2522 as the "DWARF Register Number Mapping" in the System V psABI. 2523 The preferred debugging format for all known AMD64 targets is 2524 actually DWARF2, and GCC doesn't seem to support DWARF (that is 2525 DWARF-1), but we provide the same mapping just in case. This 2526 mapping is also used for stabs, which GCC does support. */ 2527 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 2528 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 2529 2530 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to 2531 be in use on any of the supported AMD64 targets. */ 2532 2533 /* Call dummy code. */ 2534 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); 2535 set_gdbarch_frame_align (gdbarch, amd64_frame_align); 2536 set_gdbarch_frame_red_zone_size (gdbarch, 128); 2537 tdep->call_dummy_num_integer_regs = 2538 ARRAY_SIZE (amd64_dummy_call_integer_regs); 2539 tdep->call_dummy_integer_regs = amd64_dummy_call_integer_regs; 2540 tdep->classify = amd64_classify; 2541 2542 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p); 2543 set_gdbarch_register_to_value (gdbarch, i387_register_to_value); 2544 set_gdbarch_value_to_register (gdbarch, i387_value_to_register); 2545 2546 set_gdbarch_return_value (gdbarch, amd64_return_value); 2547 2548 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); 2549 2550 tdep->record_regmap = amd64_record_regmap; 2551 2552 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id); 2553 2554 /* Hook the function epilogue frame unwinder. This unwinder is 2555 appended to the list first, so that it supercedes the other 2556 unwinders in function epilogues. */ 2557 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind); 2558 2559 /* Hook the prologue-based frame unwinders. */ 2560 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind); 2561 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind); 2562 frame_base_set_default (gdbarch, &amd64_frame_base); 2563 2564 /* If we have a register mapping, enable the generic core file support. */ 2565 if (tdep->gregset_reg_offset) 2566 set_gdbarch_regset_from_core_section (gdbarch, 2567 amd64_regset_from_core_section); 2568 2569 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target); 2570 2571 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction); 2572 } 2573 2574 /* Provide a prototype to silence -Wmissing-prototypes. */ 2575 void _initialize_amd64_tdep (void); 2576 2577 void 2578 _initialize_amd64_tdep (void) 2579 { 2580 initialize_tdesc_amd64 (); 2581 initialize_tdesc_amd64_avx (); 2582 } 2583 2584 2585 /* The 64-bit FXSAVE format differs from the 32-bit format in the 2586 sense that the instruction pointer and data pointer are simply 2587 64-bit offsets into the code segment and the data segment instead 2588 of a selector offset pair. The functions below store the upper 32 2589 bits of these pointers (instead of just the 16-bits of the segment 2590 selector). */ 2591 2592 /* Fill register REGNUM in REGCACHE with the appropriate 2593 floating-point or SSE register value from *FXSAVE. If REGNUM is 2594 -1, do this for all registers. This function masks off any of the 2595 reserved bits in *FXSAVE. */ 2596 2597 void 2598 amd64_supply_fxsave (struct regcache *regcache, int regnum, 2599 const void *fxsave) 2600 { 2601 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2602 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2603 2604 i387_supply_fxsave (regcache, regnum, fxsave); 2605 2606 if (fxsave && gdbarch_ptr_bit (gdbarch) == 64) 2607 { 2608 const gdb_byte *regs = fxsave; 2609 2610 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 2611 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12); 2612 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 2613 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); 2614 } 2615 } 2616 2617 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */ 2618 2619 void 2620 amd64_supply_xsave (struct regcache *regcache, int regnum, 2621 const void *xsave) 2622 { 2623 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2624 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2625 2626 i387_supply_xsave (regcache, regnum, xsave); 2627 2628 if (xsave && gdbarch_ptr_bit (gdbarch) == 64) 2629 { 2630 const gdb_byte *regs = xsave; 2631 2632 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 2633 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), 2634 regs + 12); 2635 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 2636 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), 2637 regs + 20); 2638 } 2639 } 2640 2641 /* Fill register REGNUM (if it is a floating-point or SSE register) in 2642 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for 2643 all registers. This function doesn't touch any of the reserved 2644 bits in *FXSAVE. */ 2645 2646 void 2647 amd64_collect_fxsave (const struct regcache *regcache, int regnum, 2648 void *fxsave) 2649 { 2650 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2651 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2652 gdb_byte *regs = fxsave; 2653 2654 i387_collect_fxsave (regcache, regnum, fxsave); 2655 2656 if (gdbarch_ptr_bit (gdbarch) == 64) 2657 { 2658 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 2659 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12); 2660 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 2661 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); 2662 } 2663 } 2664 2665 /* Similar to amd64_collect_fxsave, but but use XSAVE extended state. */ 2666 2667 void 2668 amd64_collect_xsave (const struct regcache *regcache, int regnum, 2669 void *xsave, int gcore) 2670 { 2671 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2672 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2673 gdb_byte *regs = xsave; 2674 2675 i387_collect_xsave (regcache, regnum, xsave, gcore); 2676 2677 if (gdbarch_ptr_bit (gdbarch) == 64) 2678 { 2679 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 2680 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), 2681 regs + 12); 2682 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 2683 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), 2684 regs + 20); 2685 } 2686 } 2687