1 /* Native-dependent code for the i386. 2 3 Copyright (C) 2001, 2004, 2005, 2007, 2008, 2009, 2010, 2011 4 Free Software Foundation, Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #include "i386-nat.h" 22 #include "defs.h" 23 #include "breakpoint.h" 24 #include "command.h" 25 #include "gdbcmd.h" 26 #include "target.h" 27 #include "gdb_assert.h" 28 29 /* Support for hardware watchpoints and breakpoints using the i386 30 debug registers. 31 32 This provides several functions for inserting and removing 33 hardware-assisted breakpoints and watchpoints, testing if one or 34 more of the watchpoints triggered and at what address, checking 35 whether a given region can be watched, etc. 36 37 The functions below implement debug registers sharing by reference 38 counts, and allow to watch regions up to 16 bytes long. */ 39 40 struct i386_dr_low_type i386_dr_low; 41 42 43 /* Support for 8-byte wide hw watchpoints. */ 44 #define TARGET_HAS_DR_LEN_8 (i386_dr_low.debug_register_length == 8) 45 46 /* Debug registers' indices. */ 47 #define DR_NADDR 4 /* The number of debug address registers. */ 48 #define DR_STATUS 6 /* Index of debug status register (DR6). */ 49 #define DR_CONTROL 7 /* Index of debug control register (DR7). */ 50 51 /* DR7 Debug Control register fields. */ 52 53 /* How many bits to skip in DR7 to get to R/W and LEN fields. */ 54 #define DR_CONTROL_SHIFT 16 55 /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ 56 #define DR_CONTROL_SIZE 4 57 58 /* Watchpoint/breakpoint read/write fields in DR7. */ 59 #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ 60 #define DR_RW_WRITE (0x1) /* Break on data writes. */ 61 #define DR_RW_READ (0x3) /* Break on data reads or writes. */ 62 63 /* This is here for completeness. No platform supports this 64 functionality yet (as of March 2001). Note that the DE flag in the 65 CR4 register needs to be set to support this. */ 66 #ifndef DR_RW_IORW 67 #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ 68 #endif 69 70 /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift 71 is so we could OR this with the read/write field defined above. */ 72 #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ 73 #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ 74 #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ 75 #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ 76 77 /* Local and Global Enable flags in DR7. 78 79 When the Local Enable flag is set, the breakpoint/watchpoint is 80 enabled only for the current task; the processor automatically 81 clears this flag on every task switch. When the Global Enable flag 82 is set, the breakpoint/watchpoint is enabled for all tasks; the 83 processor never clears this flag. 84 85 Currently, all watchpoint are locally enabled. If you need to 86 enable them globally, read the comment which pertains to this in 87 i386_insert_aligned_watchpoint below. */ 88 #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ 89 #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ 90 #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ 91 92 /* Local and global exact breakpoint enable flags (a.k.a. slowdown 93 flags). These are only required on i386, to allow detection of the 94 exact instruction which caused a watchpoint to break; i486 and 95 later processors do that automatically. We set these flags for 96 backwards compatibility. */ 97 #define DR_LOCAL_SLOWDOWN (0x100) 98 #define DR_GLOBAL_SLOWDOWN (0x200) 99 100 /* Fields reserved by Intel. This includes the GD (General Detect 101 Enable) flag, which causes a debug exception to be generated when a 102 MOV instruction accesses one of the debug registers. 103 104 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ 105 #define DR_CONTROL_RESERVED (0xFC00) 106 107 /* Auxiliary helper macros. */ 108 109 /* A value that masks all fields in DR7 that are reserved by Intel. */ 110 #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) 111 112 /* The I'th debug register is vacant if its Local and Global Enable 113 bits are reset in the Debug Control register. */ 114 #define I386_DR_VACANT(i) \ 115 ((dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) 116 117 /* Locally enable the break/watchpoint in the I'th debug register. */ 118 #define I386_DR_LOCAL_ENABLE(i) \ 119 dr_control_mirror |= (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))) 120 121 /* Globally enable the break/watchpoint in the I'th debug register. */ 122 #define I386_DR_GLOBAL_ENABLE(i) \ 123 dr_control_mirror |= (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))) 124 125 /* Disable the break/watchpoint in the I'th debug register. */ 126 #define I386_DR_DISABLE(i) \ 127 dr_control_mirror &= ~(3 << (DR_ENABLE_SIZE * (i))) 128 129 /* Set in DR7 the RW and LEN fields for the I'th debug register. */ 130 #define I386_DR_SET_RW_LEN(i,rwlen) \ 131 do { \ 132 dr_control_mirror &= ~(0x0f << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \ 133 dr_control_mirror |= ((rwlen) << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \ 134 } while (0) 135 136 /* Get from DR7 the RW and LEN fields for the I'th debug register. */ 137 #define I386_DR_GET_RW_LEN(i) \ 138 ((dr_control_mirror >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) 139 140 /* Mask that this I'th watchpoint has triggered. */ 141 #define I386_DR_WATCH_MASK(i) (1 << (i)) 142 143 /* Did the watchpoint whose address is in the I'th register break? */ 144 #define I386_DR_WATCH_HIT(i) (dr_status_mirror & I386_DR_WATCH_MASK (i)) 145 146 /* A macro to loop over all debug registers. */ 147 #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) 148 149 /* Mirror the inferior's DRi registers. We keep the status and 150 control registers separated because they don't hold addresses. */ 151 static CORE_ADDR dr_mirror[DR_NADDR]; 152 static unsigned long dr_status_mirror, dr_control_mirror; 153 154 /* Reference counts for each debug register. */ 155 static int dr_ref_count[DR_NADDR]; 156 157 /* Whether or not to print the mirrored debug registers. */ 158 static int maint_show_dr; 159 160 /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ 161 typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; 162 163 /* Internal functions. */ 164 165 /* Return the value of a 4-bit field for DR7 suitable for watching a 166 region of LEN bytes for accesses of type TYPE. LEN is assumed to 167 have the value of 1, 2, or 4. */ 168 static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type); 169 170 /* Insert a watchpoint at address ADDR, which is assumed to be aligned 171 according to the length of the region to watch. LEN_RW_BITS is the 172 value of the bit-field from DR7 which describes the length and 173 access type of the region to be watched by this watchpoint. Return 174 0 on success, -1 on failure. */ 175 static int i386_insert_aligned_watchpoint (CORE_ADDR addr, 176 unsigned len_rw_bits); 177 178 /* Remove a watchpoint at address ADDR, which is assumed to be aligned 179 according to the length of the region to watch. LEN_RW_BITS is the 180 value of the bits from DR7 which describes the length and access 181 type of the region watched by this watchpoint. Return 0 on 182 success, -1 on failure. */ 183 static int i386_remove_aligned_watchpoint (CORE_ADDR addr, 184 unsigned len_rw_bits); 185 186 /* Insert or remove a (possibly non-aligned) watchpoint, or count the 187 number of debug registers required to watch a region at address 188 ADDR whose length is LEN for accesses of type TYPE. Return 0 on 189 successful insertion or removal, a positive number when queried 190 about the number of registers, or -1 on failure. If WHAT is not a 191 valid value, bombs through internal_error. */ 192 static int i386_handle_nonaligned_watchpoint (i386_wp_op_t what, 193 CORE_ADDR addr, int len, 194 enum target_hw_bp_type type); 195 196 /* Implementation. */ 197 198 /* Clear the reference counts and forget everything we knew about the 199 debug registers. */ 200 201 void 202 i386_cleanup_dregs (void) 203 { 204 int i; 205 206 ALL_DEBUG_REGISTERS(i) 207 { 208 dr_mirror[i] = 0; 209 dr_ref_count[i] = 0; 210 } 211 dr_control_mirror = 0; 212 dr_status_mirror = 0; 213 } 214 215 /* Print the values of the mirrored debug registers. This is called 216 when maint_show_dr is non-zero. To set that up, type "maint 217 show-debug-regs" at GDB's prompt. */ 218 219 static void 220 i386_show_dr (const char *func, CORE_ADDR addr, 221 int len, enum target_hw_bp_type type) 222 { 223 int addr_size = gdbarch_addr_bit (target_gdbarch) / 8; 224 int i; 225 226 puts_unfiltered (func); 227 if (addr || len) 228 printf_unfiltered (" (addr=%lx, len=%d, type=%s)", 229 /* This code is for ia32, so casting CORE_ADDR 230 to unsigned long should be okay. */ 231 (unsigned long)addr, len, 232 type == hw_write ? "data-write" 233 : (type == hw_read ? "data-read" 234 : (type == hw_access ? "data-read/write" 235 : (type == hw_execute ? "instruction-execute" 236 /* FIXME: if/when I/O read/write 237 watchpoints are supported, add them 238 here. */ 239 : "??unknown??")))); 240 puts_unfiltered (":\n"); 241 printf_unfiltered ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", 242 phex (dr_control_mirror, 8), phex (dr_status_mirror, 8)); 243 ALL_DEBUG_REGISTERS(i) 244 { 245 printf_unfiltered ("\ 246 \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", 247 i, phex (dr_mirror[i], addr_size), dr_ref_count[i], 248 i+1, phex (dr_mirror[i+1], addr_size), dr_ref_count[i+1]); 249 i++; 250 } 251 } 252 253 /* Return the value of a 4-bit field for DR7 suitable for watching a 254 region of LEN bytes for accesses of type TYPE. LEN is assumed to 255 have the value of 1, 2, or 4. */ 256 257 static unsigned 258 i386_length_and_rw_bits (int len, enum target_hw_bp_type type) 259 { 260 unsigned rw; 261 262 switch (type) 263 { 264 case hw_execute: 265 rw = DR_RW_EXECUTE; 266 break; 267 case hw_write: 268 rw = DR_RW_WRITE; 269 break; 270 case hw_read: 271 internal_error (__FILE__, __LINE__, 272 _("The i386 doesn't support " 273 "data-read watchpoints.\n")); 274 case hw_access: 275 rw = DR_RW_READ; 276 break; 277 #if 0 278 /* Not yet supported. */ 279 case hw_io_access: 280 rw = DR_RW_IORW; 281 break; 282 #endif 283 default: 284 internal_error (__FILE__, __LINE__, _("\ 285 Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), 286 (int) type); 287 } 288 289 switch (len) 290 { 291 case 1: 292 return (DR_LEN_1 | rw); 293 case 2: 294 return (DR_LEN_2 | rw); 295 case 4: 296 return (DR_LEN_4 | rw); 297 case 8: 298 if (TARGET_HAS_DR_LEN_8) 299 return (DR_LEN_8 | rw); 300 /* ELSE FALL THROUGH */ 301 default: 302 internal_error (__FILE__, __LINE__, _("\ 303 Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); 304 } 305 } 306 307 /* Insert a watchpoint at address ADDR, which is assumed to be aligned 308 according to the length of the region to watch. LEN_RW_BITS is the 309 value of the bits from DR7 which describes the length and access 310 type of the region to be watched by this watchpoint. Return 0 on 311 success, -1 on failure. */ 312 313 static int 314 i386_insert_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits) 315 { 316 int i; 317 318 if (!i386_dr_low.set_addr || !i386_dr_low.set_control) 319 return -1; 320 321 /* First, look for an occupied debug register with the same address 322 and the same RW and LEN definitions. If we find one, we can 323 reuse it for this watchpoint as well (and save a register). */ 324 ALL_DEBUG_REGISTERS(i) 325 { 326 if (!I386_DR_VACANT (i) 327 && dr_mirror[i] == addr 328 && I386_DR_GET_RW_LEN (i) == len_rw_bits) 329 { 330 dr_ref_count[i]++; 331 return 0; 332 } 333 } 334 335 /* Next, look for a vacant debug register. */ 336 ALL_DEBUG_REGISTERS(i) 337 { 338 if (I386_DR_VACANT (i)) 339 break; 340 } 341 342 /* No more debug registers! */ 343 if (i >= DR_NADDR) 344 return -1; 345 346 /* Now set up the register I to watch our region. */ 347 348 /* Record the info in our local mirrored array. */ 349 dr_mirror[i] = addr; 350 dr_ref_count[i] = 1; 351 I386_DR_SET_RW_LEN (i, len_rw_bits); 352 /* Note: we only enable the watchpoint locally, i.e. in the current 353 task. Currently, no i386 target allows or supports global 354 watchpoints; however, if any target would want that in the 355 future, GDB should probably provide a command to control whether 356 to enable watchpoints globally or locally, and the code below 357 should use global or local enable and slow-down flags as 358 appropriate. */ 359 I386_DR_LOCAL_ENABLE (i); 360 dr_control_mirror |= DR_LOCAL_SLOWDOWN; 361 dr_control_mirror &= I386_DR_CONTROL_MASK; 362 363 /* Finally, actually pass the info to the inferior. */ 364 i386_dr_low.set_addr (i, addr); 365 i386_dr_low.set_control (dr_control_mirror); 366 367 /* Only a sanity check for leftover bits (set possibly only by inferior). */ 368 if (i386_dr_low.unset_status) 369 i386_dr_low.unset_status (I386_DR_WATCH_MASK (i)); 370 371 return 0; 372 } 373 374 /* Remove a watchpoint at address ADDR, which is assumed to be aligned 375 according to the length of the region to watch. LEN_RW_BITS is the 376 value of the bits from DR7 which describes the length and access 377 type of the region watched by this watchpoint. Return 0 on 378 success, -1 on failure. */ 379 380 static int 381 i386_remove_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits) 382 { 383 int i, retval = -1; 384 385 ALL_DEBUG_REGISTERS(i) 386 { 387 if (!I386_DR_VACANT (i) 388 && dr_mirror[i] == addr 389 && I386_DR_GET_RW_LEN (i) == len_rw_bits) 390 { 391 if (--dr_ref_count[i] == 0) /* no longer in use? */ 392 { 393 /* Reset our mirror. */ 394 dr_mirror[i] = 0; 395 I386_DR_DISABLE (i); 396 /* Reset it in the inferior. */ 397 i386_dr_low.set_control (dr_control_mirror); 398 if (i386_dr_low.reset_addr) 399 i386_dr_low.reset_addr (i); 400 } 401 retval = 0; 402 } 403 } 404 405 return retval; 406 } 407 408 /* Insert or remove a (possibly non-aligned) watchpoint, or count the 409 number of debug registers required to watch a region at address 410 ADDR whose length is LEN for accesses of type TYPE. Return 0 on 411 successful insertion or removal, a positive number when queried 412 about the number of registers, or -1 on failure. If WHAT is not a 413 valid value, bombs through internal_error. */ 414 415 static int 416 i386_handle_nonaligned_watchpoint (i386_wp_op_t what, CORE_ADDR addr, int len, 417 enum target_hw_bp_type type) 418 { 419 int retval = 0, status = 0; 420 int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; 421 422 static int size_try_array[8][8] = 423 { 424 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ 425 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ 426 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ 427 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ 428 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ 429 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ 430 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ 431 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ 432 }; 433 434 while (len > 0) 435 { 436 int align = addr % max_wp_len; 437 /* Four (eight on AMD64) is the maximum length a debug register 438 can watch. */ 439 int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); 440 int size = size_try_array[try][align]; 441 442 if (what == WP_COUNT) 443 { 444 /* size_try_array[] is defined such that each iteration 445 through the loop is guaranteed to produce an address and a 446 size that can be watched with a single debug register. 447 Thus, for counting the registers required to watch a 448 region, we simply need to increment the count on each 449 iteration. */ 450 retval++; 451 } 452 else 453 { 454 unsigned len_rw = i386_length_and_rw_bits (size, type); 455 456 if (what == WP_INSERT) 457 status = i386_insert_aligned_watchpoint (addr, len_rw); 458 else if (what == WP_REMOVE) 459 status = i386_remove_aligned_watchpoint (addr, len_rw); 460 else 461 internal_error (__FILE__, __LINE__, _("\ 462 Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), 463 (int)what); 464 /* We keep the loop going even after a failure, because some 465 of the other aligned watchpoints might still succeed 466 (e.g. if they watch addresses that are already watched, 467 in which case we just increment the reference counts of 468 occupied debug registers). If we break out of the loop 469 too early, we could cause those addresses watched by 470 other watchpoints to be disabled when breakpoint.c reacts 471 to our failure to insert this watchpoint and tries to 472 remove it. */ 473 if (status) 474 retval = status; 475 } 476 477 addr += size; 478 len -= size; 479 } 480 481 return retval; 482 } 483 484 /* Insert a watchpoint to watch a memory region which starts at 485 address ADDR and whose length is LEN bytes. Watch memory accesses 486 of the type TYPE. Return 0 on success, -1 on failure. */ 487 488 static int 489 i386_insert_watchpoint (CORE_ADDR addr, int len, int type, 490 struct expression *cond) 491 { 492 int retval; 493 494 if (type == hw_read) 495 return 1; /* unsupported */ 496 497 if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) 498 || addr % len != 0) 499 retval = i386_handle_nonaligned_watchpoint (WP_INSERT, addr, len, type); 500 else 501 { 502 unsigned len_rw = i386_length_and_rw_bits (len, type); 503 504 retval = i386_insert_aligned_watchpoint (addr, len_rw); 505 } 506 507 if (maint_show_dr) 508 i386_show_dr ("insert_watchpoint", addr, len, type); 509 510 return retval; 511 } 512 513 /* Remove a watchpoint that watched the memory region which starts at 514 address ADDR, whose length is LEN bytes, and for accesses of the 515 type TYPE. Return 0 on success, -1 on failure. */ 516 static int 517 i386_remove_watchpoint (CORE_ADDR addr, int len, int type, 518 struct expression *cond) 519 { 520 int retval; 521 522 if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) 523 || addr % len != 0) 524 retval = i386_handle_nonaligned_watchpoint (WP_REMOVE, addr, len, type); 525 else 526 { 527 unsigned len_rw = i386_length_and_rw_bits (len, type); 528 529 retval = i386_remove_aligned_watchpoint (addr, len_rw); 530 } 531 532 if (maint_show_dr) 533 i386_show_dr ("remove_watchpoint", addr, len, type); 534 535 return retval; 536 } 537 538 /* Return non-zero if we can watch a memory region that starts at 539 address ADDR and whose length is LEN bytes. */ 540 541 static int 542 i386_region_ok_for_watchpoint (CORE_ADDR addr, int len) 543 { 544 int nregs; 545 546 /* Compute how many aligned watchpoints we would need to cover this 547 region. */ 548 nregs = i386_handle_nonaligned_watchpoint (WP_COUNT, addr, len, hw_write); 549 return nregs <= DR_NADDR ? 1 : 0; 550 } 551 552 /* If the inferior has some watchpoint that triggered, set the 553 address associated with that watchpoint and return non-zero. 554 Otherwise, return zero. */ 555 556 static int 557 i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) 558 { 559 CORE_ADDR addr = 0; 560 int i; 561 int rc = 0; 562 563 dr_status_mirror = i386_dr_low.get_status (); 564 565 ALL_DEBUG_REGISTERS(i) 566 { 567 if (I386_DR_WATCH_HIT (i) 568 /* This second condition makes sure DRi is set up for a data 569 watchpoint, not a hardware breakpoint. The reason is 570 that GDB doesn't call the target_stopped_data_address 571 method except for data watchpoints. In other words, I'm 572 being paranoiac. */ 573 && I386_DR_GET_RW_LEN (i) != 0 574 /* This third condition makes sure DRi is not vacant, this 575 avoids false positives in windows-nat.c. */ 576 && !I386_DR_VACANT (i)) 577 { 578 addr = dr_mirror[i]; 579 rc = 1; 580 if (maint_show_dr) 581 i386_show_dr ("watchpoint_hit", addr, -1, hw_write); 582 } 583 } 584 if (maint_show_dr && addr == 0) 585 i386_show_dr ("stopped_data_addr", 0, 0, hw_write); 586 587 if (rc) 588 *addr_p = addr; 589 return rc; 590 } 591 592 static int 593 i386_stopped_by_watchpoint (void) 594 { 595 CORE_ADDR addr = 0; 596 return i386_stopped_data_address (¤t_target, &addr); 597 } 598 599 /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. 600 Return 0 on success, EBUSY on failure. */ 601 static int 602 i386_insert_hw_breakpoint (struct gdbarch *gdbarch, 603 struct bp_target_info *bp_tgt) 604 { 605 unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); 606 CORE_ADDR addr = bp_tgt->placed_address; 607 int retval = i386_insert_aligned_watchpoint (addr, len_rw) ? EBUSY : 0; 608 609 if (maint_show_dr) 610 i386_show_dr ("insert_hwbp", addr, 1, hw_execute); 611 612 return retval; 613 } 614 615 /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. 616 Return 0 on success, -1 on failure. */ 617 618 static int 619 i386_remove_hw_breakpoint (struct gdbarch *gdbarch, 620 struct bp_target_info *bp_tgt) 621 { 622 unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); 623 CORE_ADDR addr = bp_tgt->placed_address; 624 int retval = i386_remove_aligned_watchpoint (addr, len_rw); 625 626 if (maint_show_dr) 627 i386_show_dr ("remove_hwbp", addr, 1, hw_execute); 628 629 return retval; 630 } 631 632 /* Returns the number of hardware watchpoints of type TYPE that we can 633 set. Value is positive if we can set CNT watchpoints, zero if 634 setting watchpoints of type TYPE is not supported, and negative if 635 CNT is more than the maximum number of watchpoints of type TYPE 636 that we can support. TYPE is one of bp_hardware_watchpoint, 637 bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. 638 CNT is the number of such watchpoints used so far (including this 639 one). OTHERTYPE is non-zero if other types of watchpoints are 640 currently enabled. 641 642 We always return 1 here because we don't have enough information 643 about possible overlap of addresses that they want to watch. As an 644 extreme example, consider the case where all the watchpoints watch 645 the same address and the same region length: then we can handle a 646 virtually unlimited number of watchpoints, due to debug register 647 sharing implemented via reference counts in i386-nat.c. */ 648 649 static int 650 i386_can_use_hw_breakpoint (int type, int cnt, int othertype) 651 { 652 return 1; 653 } 654 655 static void 656 add_show_debug_regs_command (void) 657 { 658 /* A maintenance command to enable printing the internal DRi mirror 659 variables. */ 660 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, 661 &maint_show_dr, _("\ 662 Set whether to show variables that mirror the x86 debug registers."), _("\ 663 Show whether to show variables that mirror the x86 debug registers."), _("\ 664 Use \"on\" to enable, \"off\" to disable.\n\ 665 If enabled, the debug registers values are shown when GDB inserts\n\ 666 or removes a hardware breakpoint or watchpoint, and when the inferior\n\ 667 triggers a breakpoint or watchpoint."), 668 NULL, 669 NULL, 670 &maintenance_set_cmdlist, 671 &maintenance_show_cmdlist); 672 } 673 674 /* There are only two global functions left. */ 675 676 void 677 i386_use_watchpoints (struct target_ops *t) 678 { 679 /* After a watchpoint trap, the PC points to the instruction after the 680 one that caused the trap. Therefore we don't need to step over it. 681 But we do need to reset the status register to avoid another trap. */ 682 t->to_have_continuable_watchpoint = 1; 683 684 t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint; 685 t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint; 686 t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint; 687 t->to_stopped_data_address = i386_stopped_data_address; 688 t->to_insert_watchpoint = i386_insert_watchpoint; 689 t->to_remove_watchpoint = i386_remove_watchpoint; 690 t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint; 691 t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint; 692 } 693 694 void 695 i386_set_debug_register_length (int len) 696 { 697 /* This function should be called only once for each native target. */ 698 gdb_assert (i386_dr_low.debug_register_length == 0); 699 gdb_assert (len == 4 || len == 8); 700 i386_dr_low.debug_register_length = len; 701 add_show_debug_regs_command (); 702 } 703