1 /* Intel 386 target-dependent stuff. 2 3 Copyright (C) 1988-2012 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "opcode/i386.h" 22 #include "arch-utils.h" 23 #include "command.h" 24 #include "dummy-frame.h" 25 #include "dwarf2-frame.h" 26 #include "doublest.h" 27 #include "frame.h" 28 #include "frame-base.h" 29 #include "frame-unwind.h" 30 #include "inferior.h" 31 #include "gdbcmd.h" 32 #include "gdbcore.h" 33 #include "gdbtypes.h" 34 #include "objfiles.h" 35 #include "osabi.h" 36 #include "regcache.h" 37 #include "reggroups.h" 38 #include "regset.h" 39 #include "symfile.h" 40 #include "symtab.h" 41 #include "target.h" 42 #include "value.h" 43 #include "dis-asm.h" 44 #include "disasm.h" 45 #include "remote.h" 46 #include "exceptions.h" 47 #include "gdb_assert.h" 48 #include "gdb_string.h" 49 50 #include "i386-tdep.h" 51 #include "i387-tdep.h" 52 #include "i386-xstate.h" 53 54 #include "record.h" 55 #include <stdint.h> 56 57 #include "features/i386/i386.c" 58 #include "features/i386/i386-avx.c" 59 #include "features/i386/i386-mmx.c" 60 61 #include "ax.h" 62 #include "ax-gdb.h" 63 64 /* Register names. */ 65 66 static const char *i386_register_names[] = 67 { 68 "eax", "ecx", "edx", "ebx", 69 "esp", "ebp", "esi", "edi", 70 "eip", "eflags", "cs", "ss", 71 "ds", "es", "fs", "gs", 72 "st0", "st1", "st2", "st3", 73 "st4", "st5", "st6", "st7", 74 "fctrl", "fstat", "ftag", "fiseg", 75 "fioff", "foseg", "fooff", "fop", 76 "xmm0", "xmm1", "xmm2", "xmm3", 77 "xmm4", "xmm5", "xmm6", "xmm7", 78 "mxcsr" 79 }; 80 81 static const char *i386_ymm_names[] = 82 { 83 "ymm0", "ymm1", "ymm2", "ymm3", 84 "ymm4", "ymm5", "ymm6", "ymm7", 85 }; 86 87 static const char *i386_ymmh_names[] = 88 { 89 "ymm0h", "ymm1h", "ymm2h", "ymm3h", 90 "ymm4h", "ymm5h", "ymm6h", "ymm7h", 91 }; 92 93 /* Register names for MMX pseudo-registers. */ 94 95 static const char *i386_mmx_names[] = 96 { 97 "mm0", "mm1", "mm2", "mm3", 98 "mm4", "mm5", "mm6", "mm7" 99 }; 100 101 /* Register names for byte pseudo-registers. */ 102 103 static const char *i386_byte_names[] = 104 { 105 "al", "cl", "dl", "bl", 106 "ah", "ch", "dh", "bh" 107 }; 108 109 /* Register names for word pseudo-registers. */ 110 111 static const char *i386_word_names[] = 112 { 113 "ax", "cx", "dx", "bx", 114 "", "bp", "si", "di" 115 }; 116 117 /* MMX register? */ 118 119 static int 120 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) 121 { 122 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 123 int mm0_regnum = tdep->mm0_regnum; 124 125 if (mm0_regnum < 0) 126 return 0; 127 128 regnum -= mm0_regnum; 129 return regnum >= 0 && regnum < tdep->num_mmx_regs; 130 } 131 132 /* Byte register? */ 133 134 int 135 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) 136 { 137 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 138 139 regnum -= tdep->al_regnum; 140 return regnum >= 0 && regnum < tdep->num_byte_regs; 141 } 142 143 /* Word register? */ 144 145 int 146 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) 147 { 148 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 149 150 regnum -= tdep->ax_regnum; 151 return regnum >= 0 && regnum < tdep->num_word_regs; 152 } 153 154 /* Dword register? */ 155 156 int 157 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) 158 { 159 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 160 int eax_regnum = tdep->eax_regnum; 161 162 if (eax_regnum < 0) 163 return 0; 164 165 regnum -= eax_regnum; 166 return regnum >= 0 && regnum < tdep->num_dword_regs; 167 } 168 169 static int 170 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) 171 { 172 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 173 int ymm0h_regnum = tdep->ymm0h_regnum; 174 175 if (ymm0h_regnum < 0) 176 return 0; 177 178 regnum -= ymm0h_regnum; 179 return regnum >= 0 && regnum < tdep->num_ymm_regs; 180 } 181 182 /* AVX register? */ 183 184 int 185 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) 186 { 187 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 188 int ymm0_regnum = tdep->ymm0_regnum; 189 190 if (ymm0_regnum < 0) 191 return 0; 192 193 regnum -= ymm0_regnum; 194 return regnum >= 0 && regnum < tdep->num_ymm_regs; 195 } 196 197 /* SSE register? */ 198 199 int 200 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) 201 { 202 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 203 int num_xmm_regs = I387_NUM_XMM_REGS (tdep); 204 205 if (num_xmm_regs == 0) 206 return 0; 207 208 regnum -= I387_XMM0_REGNUM (tdep); 209 return regnum >= 0 && regnum < num_xmm_regs; 210 } 211 212 static int 213 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) 214 { 215 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 216 217 if (I387_NUM_XMM_REGS (tdep) == 0) 218 return 0; 219 220 return (regnum == I387_MXCSR_REGNUM (tdep)); 221 } 222 223 /* FP register? */ 224 225 int 226 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) 227 { 228 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 229 230 if (I387_ST0_REGNUM (tdep) < 0) 231 return 0; 232 233 return (I387_ST0_REGNUM (tdep) <= regnum 234 && regnum < I387_FCTRL_REGNUM (tdep)); 235 } 236 237 int 238 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) 239 { 240 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 241 242 if (I387_ST0_REGNUM (tdep) < 0) 243 return 0; 244 245 return (I387_FCTRL_REGNUM (tdep) <= regnum 246 && regnum < I387_XMM0_REGNUM (tdep)); 247 } 248 249 /* Return the name of register REGNUM, or the empty string if it is 250 an anonymous register. */ 251 252 static const char * 253 i386_register_name (struct gdbarch *gdbarch, int regnum) 254 { 255 /* Hide the upper YMM registers. */ 256 if (i386_ymmh_regnum_p (gdbarch, regnum)) 257 return ""; 258 259 return tdesc_register_name (gdbarch, regnum); 260 } 261 262 /* Return the name of register REGNUM. */ 263 264 const char * 265 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) 266 { 267 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 268 if (i386_mmx_regnum_p (gdbarch, regnum)) 269 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; 270 else if (i386_ymm_regnum_p (gdbarch, regnum)) 271 return i386_ymm_names[regnum - tdep->ymm0_regnum]; 272 else if (i386_byte_regnum_p (gdbarch, regnum)) 273 return i386_byte_names[regnum - tdep->al_regnum]; 274 else if (i386_word_regnum_p (gdbarch, regnum)) 275 return i386_word_names[regnum - tdep->ax_regnum]; 276 277 internal_error (__FILE__, __LINE__, _("invalid regnum")); 278 } 279 280 /* Convert a dbx register number REG to the appropriate register 281 number used by GDB. */ 282 283 static int 284 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) 285 { 286 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 287 288 /* This implements what GCC calls the "default" register map 289 (dbx_register_map[]). */ 290 291 if (reg >= 0 && reg <= 7) 292 { 293 /* General-purpose registers. The debug info calls %ebp 294 register 4, and %esp register 5. */ 295 if (reg == 4) 296 return 5; 297 else if (reg == 5) 298 return 4; 299 else return reg; 300 } 301 else if (reg >= 12 && reg <= 19) 302 { 303 /* Floating-point registers. */ 304 return reg - 12 + I387_ST0_REGNUM (tdep); 305 } 306 else if (reg >= 21 && reg <= 28) 307 { 308 /* SSE registers. */ 309 int ymm0_regnum = tdep->ymm0_regnum; 310 311 if (ymm0_regnum >= 0 312 && i386_xmm_regnum_p (gdbarch, reg)) 313 return reg - 21 + ymm0_regnum; 314 else 315 return reg - 21 + I387_XMM0_REGNUM (tdep); 316 } 317 else if (reg >= 29 && reg <= 36) 318 { 319 /* MMX registers. */ 320 return reg - 29 + I387_MM0_REGNUM (tdep); 321 } 322 323 /* This will hopefully provoke a warning. */ 324 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); 325 } 326 327 /* Convert SVR4 register number REG to the appropriate register number 328 used by GDB. */ 329 330 static int 331 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) 332 { 333 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 334 335 /* This implements the GCC register map that tries to be compatible 336 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ 337 338 /* The SVR4 register numbering includes %eip and %eflags, and 339 numbers the floating point registers differently. */ 340 if (reg >= 0 && reg <= 9) 341 { 342 /* General-purpose registers. */ 343 return reg; 344 } 345 else if (reg >= 11 && reg <= 18) 346 { 347 /* Floating-point registers. */ 348 return reg - 11 + I387_ST0_REGNUM (tdep); 349 } 350 else if (reg >= 21 && reg <= 36) 351 { 352 /* The SSE and MMX registers have the same numbers as with dbx. */ 353 return i386_dbx_reg_to_regnum (gdbarch, reg); 354 } 355 356 switch (reg) 357 { 358 case 37: return I387_FCTRL_REGNUM (tdep); 359 case 38: return I387_FSTAT_REGNUM (tdep); 360 case 39: return I387_MXCSR_REGNUM (tdep); 361 case 40: return I386_ES_REGNUM; 362 case 41: return I386_CS_REGNUM; 363 case 42: return I386_SS_REGNUM; 364 case 43: return I386_DS_REGNUM; 365 case 44: return I386_FS_REGNUM; 366 case 45: return I386_GS_REGNUM; 367 } 368 369 /* This will hopefully provoke a warning. */ 370 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); 371 } 372 373 374 375 /* This is the variable that is set with "set disassembly-flavor", and 376 its legitimate values. */ 377 static const char att_flavor[] = "att"; 378 static const char intel_flavor[] = "intel"; 379 static const char *valid_flavors[] = 380 { 381 att_flavor, 382 intel_flavor, 383 NULL 384 }; 385 static const char *disassembly_flavor = att_flavor; 386 387 388 /* Use the program counter to determine the contents and size of a 389 breakpoint instruction. Return a pointer to a string of bytes that 390 encode a breakpoint instruction, store the length of the string in 391 *LEN and optionally adjust *PC to point to the correct memory 392 location for inserting the breakpoint. 393 394 On the i386 we have a single breakpoint that fits in a single byte 395 and can be inserted anywhere. 396 397 This function is 64-bit safe. */ 398 399 static const gdb_byte * 400 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) 401 { 402 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ 403 404 *len = sizeof (break_insn); 405 return break_insn; 406 } 407 408 /* Displaced instruction handling. */ 409 410 /* Skip the legacy instruction prefixes in INSN. 411 Not all prefixes are valid for any particular insn 412 but we needn't care, the insn will fault if it's invalid. 413 The result is a pointer to the first opcode byte, 414 or NULL if we run off the end of the buffer. */ 415 416 static gdb_byte * 417 i386_skip_prefixes (gdb_byte *insn, size_t max_len) 418 { 419 gdb_byte *end = insn + max_len; 420 421 while (insn < end) 422 { 423 switch (*insn) 424 { 425 case DATA_PREFIX_OPCODE: 426 case ADDR_PREFIX_OPCODE: 427 case CS_PREFIX_OPCODE: 428 case DS_PREFIX_OPCODE: 429 case ES_PREFIX_OPCODE: 430 case FS_PREFIX_OPCODE: 431 case GS_PREFIX_OPCODE: 432 case SS_PREFIX_OPCODE: 433 case LOCK_PREFIX_OPCODE: 434 case REPE_PREFIX_OPCODE: 435 case REPNE_PREFIX_OPCODE: 436 ++insn; 437 continue; 438 default: 439 return insn; 440 } 441 } 442 443 return NULL; 444 } 445 446 static int 447 i386_absolute_jmp_p (const gdb_byte *insn) 448 { 449 /* jmp far (absolute address in operand). */ 450 if (insn[0] == 0xea) 451 return 1; 452 453 if (insn[0] == 0xff) 454 { 455 /* jump near, absolute indirect (/4). */ 456 if ((insn[1] & 0x38) == 0x20) 457 return 1; 458 459 /* jump far, absolute indirect (/5). */ 460 if ((insn[1] & 0x38) == 0x28) 461 return 1; 462 } 463 464 return 0; 465 } 466 467 static int 468 i386_absolute_call_p (const gdb_byte *insn) 469 { 470 /* call far, absolute. */ 471 if (insn[0] == 0x9a) 472 return 1; 473 474 if (insn[0] == 0xff) 475 { 476 /* Call near, absolute indirect (/2). */ 477 if ((insn[1] & 0x38) == 0x10) 478 return 1; 479 480 /* Call far, absolute indirect (/3). */ 481 if ((insn[1] & 0x38) == 0x18) 482 return 1; 483 } 484 485 return 0; 486 } 487 488 static int 489 i386_ret_p (const gdb_byte *insn) 490 { 491 switch (insn[0]) 492 { 493 case 0xc2: /* ret near, pop N bytes. */ 494 case 0xc3: /* ret near */ 495 case 0xca: /* ret far, pop N bytes. */ 496 case 0xcb: /* ret far */ 497 case 0xcf: /* iret */ 498 return 1; 499 500 default: 501 return 0; 502 } 503 } 504 505 static int 506 i386_call_p (const gdb_byte *insn) 507 { 508 if (i386_absolute_call_p (insn)) 509 return 1; 510 511 /* call near, relative. */ 512 if (insn[0] == 0xe8) 513 return 1; 514 515 return 0; 516 } 517 518 /* Return non-zero if INSN is a system call, and set *LENGTHP to its 519 length in bytes. Otherwise, return zero. */ 520 521 static int 522 i386_syscall_p (const gdb_byte *insn, int *lengthp) 523 { 524 if (insn[0] == 0xcd) 525 { 526 *lengthp = 2; 527 return 1; 528 } 529 530 return 0; 531 } 532 533 /* Some kernels may run one past a syscall insn, so we have to cope. 534 Otherwise this is just simple_displaced_step_copy_insn. */ 535 536 struct displaced_step_closure * 537 i386_displaced_step_copy_insn (struct gdbarch *gdbarch, 538 CORE_ADDR from, CORE_ADDR to, 539 struct regcache *regs) 540 { 541 size_t len = gdbarch_max_insn_length (gdbarch); 542 gdb_byte *buf = xmalloc (len); 543 544 read_memory (from, buf, len); 545 546 /* GDB may get control back after the insn after the syscall. 547 Presumably this is a kernel bug. 548 If this is a syscall, make sure there's a nop afterwards. */ 549 { 550 int syscall_length; 551 gdb_byte *insn; 552 553 insn = i386_skip_prefixes (buf, len); 554 if (insn != NULL && i386_syscall_p (insn, &syscall_length)) 555 insn[syscall_length] = NOP_OPCODE; 556 } 557 558 write_memory (to, buf, len); 559 560 if (debug_displaced) 561 { 562 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", 563 paddress (gdbarch, from), paddress (gdbarch, to)); 564 displaced_step_dump_bytes (gdb_stdlog, buf, len); 565 } 566 567 return (struct displaced_step_closure *) buf; 568 } 569 570 /* Fix up the state of registers and memory after having single-stepped 571 a displaced instruction. */ 572 573 void 574 i386_displaced_step_fixup (struct gdbarch *gdbarch, 575 struct displaced_step_closure *closure, 576 CORE_ADDR from, CORE_ADDR to, 577 struct regcache *regs) 578 { 579 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 580 581 /* The offset we applied to the instruction's address. 582 This could well be negative (when viewed as a signed 32-bit 583 value), but ULONGEST won't reflect that, so take care when 584 applying it. */ 585 ULONGEST insn_offset = to - from; 586 587 /* Since we use simple_displaced_step_copy_insn, our closure is a 588 copy of the instruction. */ 589 gdb_byte *insn = (gdb_byte *) closure; 590 /* The start of the insn, needed in case we see some prefixes. */ 591 gdb_byte *insn_start = insn; 592 593 if (debug_displaced) 594 fprintf_unfiltered (gdb_stdlog, 595 "displaced: fixup (%s, %s), " 596 "insn = 0x%02x 0x%02x ...\n", 597 paddress (gdbarch, from), paddress (gdbarch, to), 598 insn[0], insn[1]); 599 600 /* The list of issues to contend with here is taken from 601 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. 602 Yay for Free Software! */ 603 604 /* Relocate the %eip, if necessary. */ 605 606 /* The instruction recognizers we use assume any leading prefixes 607 have been skipped. */ 608 { 609 /* This is the size of the buffer in closure. */ 610 size_t max_insn_len = gdbarch_max_insn_length (gdbarch); 611 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); 612 /* If there are too many prefixes, just ignore the insn. 613 It will fault when run. */ 614 if (opcode != NULL) 615 insn = opcode; 616 } 617 618 /* Except in the case of absolute or indirect jump or call 619 instructions, or a return instruction, the new eip is relative to 620 the displaced instruction; make it relative. Well, signal 621 handler returns don't need relocation either, but we use the 622 value of %eip to recognize those; see below. */ 623 if (! i386_absolute_jmp_p (insn) 624 && ! i386_absolute_call_p (insn) 625 && ! i386_ret_p (insn)) 626 { 627 ULONGEST orig_eip; 628 int insn_len; 629 630 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); 631 632 /* A signal trampoline system call changes the %eip, resuming 633 execution of the main program after the signal handler has 634 returned. That makes them like 'return' instructions; we 635 shouldn't relocate %eip. 636 637 But most system calls don't, and we do need to relocate %eip. 638 639 Our heuristic for distinguishing these cases: if stepping 640 over the system call instruction left control directly after 641 the instruction, the we relocate --- control almost certainly 642 doesn't belong in the displaced copy. Otherwise, we assume 643 the instruction has put control where it belongs, and leave 644 it unrelocated. Goodness help us if there are PC-relative 645 system calls. */ 646 if (i386_syscall_p (insn, &insn_len) 647 && orig_eip != to + (insn - insn_start) + insn_len 648 /* GDB can get control back after the insn after the syscall. 649 Presumably this is a kernel bug. 650 i386_displaced_step_copy_insn ensures its a nop, 651 we add one to the length for it. */ 652 && orig_eip != to + (insn - insn_start) + insn_len + 1) 653 { 654 if (debug_displaced) 655 fprintf_unfiltered (gdb_stdlog, 656 "displaced: syscall changed %%eip; " 657 "not relocating\n"); 658 } 659 else 660 { 661 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; 662 663 /* If we just stepped over a breakpoint insn, we don't backup 664 the pc on purpose; this is to match behaviour without 665 stepping. */ 666 667 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); 668 669 if (debug_displaced) 670 fprintf_unfiltered (gdb_stdlog, 671 "displaced: " 672 "relocated %%eip from %s to %s\n", 673 paddress (gdbarch, orig_eip), 674 paddress (gdbarch, eip)); 675 } 676 } 677 678 /* If the instruction was PUSHFL, then the TF bit will be set in the 679 pushed value, and should be cleared. We'll leave this for later, 680 since GDB already messes up the TF flag when stepping over a 681 pushfl. */ 682 683 /* If the instruction was a call, the return address now atop the 684 stack is the address following the copied instruction. We need 685 to make it the address following the original instruction. */ 686 if (i386_call_p (insn)) 687 { 688 ULONGEST esp; 689 ULONGEST retaddr; 690 const ULONGEST retaddr_len = 4; 691 692 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); 693 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); 694 retaddr = (retaddr - insn_offset) & 0xffffffffUL; 695 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); 696 697 if (debug_displaced) 698 fprintf_unfiltered (gdb_stdlog, 699 "displaced: relocated return addr at %s to %s\n", 700 paddress (gdbarch, esp), 701 paddress (gdbarch, retaddr)); 702 } 703 } 704 705 static void 706 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) 707 { 708 target_write_memory (*to, buf, len); 709 *to += len; 710 } 711 712 static void 713 i386_relocate_instruction (struct gdbarch *gdbarch, 714 CORE_ADDR *to, CORE_ADDR oldloc) 715 { 716 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 717 gdb_byte buf[I386_MAX_INSN_LEN]; 718 int offset = 0, rel32, newrel; 719 int insn_length; 720 gdb_byte *insn = buf; 721 722 read_memory (oldloc, buf, I386_MAX_INSN_LEN); 723 724 insn_length = gdb_buffered_insn_length (gdbarch, insn, 725 I386_MAX_INSN_LEN, oldloc); 726 727 /* Get past the prefixes. */ 728 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); 729 730 /* Adjust calls with 32-bit relative addresses as push/jump, with 731 the address pushed being the location where the original call in 732 the user program would return to. */ 733 if (insn[0] == 0xe8) 734 { 735 gdb_byte push_buf[16]; 736 unsigned int ret_addr; 737 738 /* Where "ret" in the original code will return to. */ 739 ret_addr = oldloc + insn_length; 740 push_buf[0] = 0x68; /* pushq $... */ 741 memcpy (&push_buf[1], &ret_addr, 4); 742 /* Push the push. */ 743 append_insns (to, 5, push_buf); 744 745 /* Convert the relative call to a relative jump. */ 746 insn[0] = 0xe9; 747 748 /* Adjust the destination offset. */ 749 rel32 = extract_signed_integer (insn + 1, 4, byte_order); 750 newrel = (oldloc - *to) + rel32; 751 store_signed_integer (insn + 1, 4, byte_order, newrel); 752 753 if (debug_displaced) 754 fprintf_unfiltered (gdb_stdlog, 755 "Adjusted insn rel32=%s at %s to" 756 " rel32=%s at %s\n", 757 hex_string (rel32), paddress (gdbarch, oldloc), 758 hex_string (newrel), paddress (gdbarch, *to)); 759 760 /* Write the adjusted jump into its displaced location. */ 761 append_insns (to, 5, insn); 762 return; 763 } 764 765 /* Adjust jumps with 32-bit relative addresses. Calls are already 766 handled above. */ 767 if (insn[0] == 0xe9) 768 offset = 1; 769 /* Adjust conditional jumps. */ 770 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) 771 offset = 2; 772 773 if (offset) 774 { 775 rel32 = extract_signed_integer (insn + offset, 4, byte_order); 776 newrel = (oldloc - *to) + rel32; 777 store_signed_integer (insn + offset, 4, byte_order, newrel); 778 if (debug_displaced) 779 fprintf_unfiltered (gdb_stdlog, 780 "Adjusted insn rel32=%s at %s to" 781 " rel32=%s at %s\n", 782 hex_string (rel32), paddress (gdbarch, oldloc), 783 hex_string (newrel), paddress (gdbarch, *to)); 784 } 785 786 /* Write the adjusted instructions into their displaced 787 location. */ 788 append_insns (to, insn_length, buf); 789 } 790 791 792 #ifdef I386_REGNO_TO_SYMMETRY 793 #error "The Sequent Symmetry is no longer supported." 794 #endif 795 796 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi 797 and %esp "belong" to the calling function. Therefore these 798 registers should be saved if they're going to be modified. */ 799 800 /* The maximum number of saved registers. This should include all 801 registers mentioned above, and %eip. */ 802 #define I386_NUM_SAVED_REGS I386_NUM_GREGS 803 804 struct i386_frame_cache 805 { 806 /* Base address. */ 807 CORE_ADDR base; 808 int base_p; 809 LONGEST sp_offset; 810 CORE_ADDR pc; 811 812 /* Saved registers. */ 813 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; 814 CORE_ADDR saved_sp; 815 int saved_sp_reg; 816 int pc_in_eax; 817 818 /* Stack space reserved for local variables. */ 819 long locals; 820 }; 821 822 /* Allocate and initialize a frame cache. */ 823 824 static struct i386_frame_cache * 825 i386_alloc_frame_cache (void) 826 { 827 struct i386_frame_cache *cache; 828 int i; 829 830 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); 831 832 /* Base address. */ 833 cache->base_p = 0; 834 cache->base = 0; 835 cache->sp_offset = -4; 836 cache->pc = 0; 837 838 /* Saved registers. We initialize these to -1 since zero is a valid 839 offset (that's where %ebp is supposed to be stored). */ 840 for (i = 0; i < I386_NUM_SAVED_REGS; i++) 841 cache->saved_regs[i] = -1; 842 cache->saved_sp = 0; 843 cache->saved_sp_reg = -1; 844 cache->pc_in_eax = 0; 845 846 /* Frameless until proven otherwise. */ 847 cache->locals = -1; 848 849 return cache; 850 } 851 852 /* If the instruction at PC is a jump, return the address of its 853 target. Otherwise, return PC. */ 854 855 static CORE_ADDR 856 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) 857 { 858 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 859 gdb_byte op; 860 long delta = 0; 861 int data16 = 0; 862 863 if (target_read_memory (pc, &op, 1)) 864 return pc; 865 866 if (op == 0x66) 867 { 868 data16 = 1; 869 op = read_memory_unsigned_integer (pc + 1, 1, byte_order); 870 } 871 872 switch (op) 873 { 874 case 0xe9: 875 /* Relative jump: if data16 == 0, disp32, else disp16. */ 876 if (data16) 877 { 878 delta = read_memory_integer (pc + 2, 2, byte_order); 879 880 /* Include the size of the jmp instruction (including the 881 0x66 prefix). */ 882 delta += 4; 883 } 884 else 885 { 886 delta = read_memory_integer (pc + 1, 4, byte_order); 887 888 /* Include the size of the jmp instruction. */ 889 delta += 5; 890 } 891 break; 892 case 0xeb: 893 /* Relative jump, disp8 (ignore data16). */ 894 delta = read_memory_integer (pc + data16 + 1, 1, byte_order); 895 896 delta += data16 + 2; 897 break; 898 } 899 900 return pc + delta; 901 } 902 903 /* Check whether PC points at a prologue for a function returning a 904 structure or union. If so, it updates CACHE and returns the 905 address of the first instruction after the code sequence that 906 removes the "hidden" argument from the stack or CURRENT_PC, 907 whichever is smaller. Otherwise, return PC. */ 908 909 static CORE_ADDR 910 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, 911 struct i386_frame_cache *cache) 912 { 913 /* Functions that return a structure or union start with: 914 915 popl %eax 0x58 916 xchgl %eax, (%esp) 0x87 0x04 0x24 917 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 918 919 (the System V compiler puts out the second `xchg' instruction, 920 and the assembler doesn't try to optimize it, so the 'sib' form 921 gets generated). This sequence is used to get the address of the 922 return buffer for a function that returns a structure. */ 923 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; 924 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; 925 gdb_byte buf[4]; 926 gdb_byte op; 927 928 if (current_pc <= pc) 929 return pc; 930 931 if (target_read_memory (pc, &op, 1)) 932 return pc; 933 934 if (op != 0x58) /* popl %eax */ 935 return pc; 936 937 if (target_read_memory (pc + 1, buf, 4)) 938 return pc; 939 940 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) 941 return pc; 942 943 if (current_pc == pc) 944 { 945 cache->sp_offset += 4; 946 return current_pc; 947 } 948 949 if (current_pc == pc + 1) 950 { 951 cache->pc_in_eax = 1; 952 return current_pc; 953 } 954 955 if (buf[1] == proto1[1]) 956 return pc + 4; 957 else 958 return pc + 5; 959 } 960 961 static CORE_ADDR 962 i386_skip_probe (CORE_ADDR pc) 963 { 964 /* A function may start with 965 966 pushl constant 967 call _probe 968 addl $4, %esp 969 970 followed by 971 972 pushl %ebp 973 974 etc. */ 975 gdb_byte buf[8]; 976 gdb_byte op; 977 978 if (target_read_memory (pc, &op, 1)) 979 return pc; 980 981 if (op == 0x68 || op == 0x6a) 982 { 983 int delta; 984 985 /* Skip past the `pushl' instruction; it has either a one-byte or a 986 four-byte operand, depending on the opcode. */ 987 if (op == 0x68) 988 delta = 5; 989 else 990 delta = 2; 991 992 /* Read the following 8 bytes, which should be `call _probe' (6 993 bytes) followed by `addl $4,%esp' (2 bytes). */ 994 read_memory (pc + delta, buf, sizeof (buf)); 995 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) 996 pc += delta + sizeof (buf); 997 } 998 999 return pc; 1000 } 1001 1002 /* GCC 4.1 and later, can put code in the prologue to realign the 1003 stack pointer. Check whether PC points to such code, and update 1004 CACHE accordingly. Return the first instruction after the code 1005 sequence or CURRENT_PC, whichever is smaller. If we don't 1006 recognize the code, return PC. */ 1007 1008 static CORE_ADDR 1009 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, 1010 struct i386_frame_cache *cache) 1011 { 1012 /* There are 2 code sequences to re-align stack before the frame 1013 gets set up: 1014 1015 1. Use a caller-saved saved register: 1016 1017 leal 4(%esp), %reg 1018 andl $-XXX, %esp 1019 pushl -4(%reg) 1020 1021 2. Use a callee-saved saved register: 1022 1023 pushl %reg 1024 leal 8(%esp), %reg 1025 andl $-XXX, %esp 1026 pushl -4(%reg) 1027 1028 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: 1029 1030 0x83 0xe4 0xf0 andl $-16, %esp 1031 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp 1032 */ 1033 1034 gdb_byte buf[14]; 1035 int reg; 1036 int offset, offset_and; 1037 static int regnums[8] = { 1038 I386_EAX_REGNUM, /* %eax */ 1039 I386_ECX_REGNUM, /* %ecx */ 1040 I386_EDX_REGNUM, /* %edx */ 1041 I386_EBX_REGNUM, /* %ebx */ 1042 I386_ESP_REGNUM, /* %esp */ 1043 I386_EBP_REGNUM, /* %ebp */ 1044 I386_ESI_REGNUM, /* %esi */ 1045 I386_EDI_REGNUM /* %edi */ 1046 }; 1047 1048 if (target_read_memory (pc, buf, sizeof buf)) 1049 return pc; 1050 1051 /* Check caller-saved saved register. The first instruction has 1052 to be "leal 4(%esp), %reg". */ 1053 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) 1054 { 1055 /* MOD must be binary 10 and R/M must be binary 100. */ 1056 if ((buf[1] & 0xc7) != 0x44) 1057 return pc; 1058 1059 /* REG has register number. */ 1060 reg = (buf[1] >> 3) & 7; 1061 offset = 4; 1062 } 1063 else 1064 { 1065 /* Check callee-saved saved register. The first instruction 1066 has to be "pushl %reg". */ 1067 if ((buf[0] & 0xf8) != 0x50) 1068 return pc; 1069 1070 /* Get register. */ 1071 reg = buf[0] & 0x7; 1072 1073 /* The next instruction has to be "leal 8(%esp), %reg". */ 1074 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) 1075 return pc; 1076 1077 /* MOD must be binary 10 and R/M must be binary 100. */ 1078 if ((buf[2] & 0xc7) != 0x44) 1079 return pc; 1080 1081 /* REG has register number. Registers in pushl and leal have to 1082 be the same. */ 1083 if (reg != ((buf[2] >> 3) & 7)) 1084 return pc; 1085 1086 offset = 5; 1087 } 1088 1089 /* Rigister can't be %esp nor %ebp. */ 1090 if (reg == 4 || reg == 5) 1091 return pc; 1092 1093 /* The next instruction has to be "andl $-XXX, %esp". */ 1094 if (buf[offset + 1] != 0xe4 1095 || (buf[offset] != 0x81 && buf[offset] != 0x83)) 1096 return pc; 1097 1098 offset_and = offset; 1099 offset += buf[offset] == 0x81 ? 6 : 3; 1100 1101 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is 1102 0xfc. REG must be binary 110 and MOD must be binary 01. */ 1103 if (buf[offset] != 0xff 1104 || buf[offset + 2] != 0xfc 1105 || (buf[offset + 1] & 0xf8) != 0x70) 1106 return pc; 1107 1108 /* R/M has register. Registers in leal and pushl have to be the 1109 same. */ 1110 if (reg != (buf[offset + 1] & 7)) 1111 return pc; 1112 1113 if (current_pc > pc + offset_and) 1114 cache->saved_sp_reg = regnums[reg]; 1115 1116 return min (pc + offset + 3, current_pc); 1117 } 1118 1119 /* Maximum instruction length we need to handle. */ 1120 #define I386_MAX_MATCHED_INSN_LEN 6 1121 1122 /* Instruction description. */ 1123 struct i386_insn 1124 { 1125 size_t len; 1126 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; 1127 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; 1128 }; 1129 1130 /* Return whether instruction at PC matches PATTERN. */ 1131 1132 static int 1133 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) 1134 { 1135 gdb_byte op; 1136 1137 if (target_read_memory (pc, &op, 1)) 1138 return 0; 1139 1140 if ((op & pattern.mask[0]) == pattern.insn[0]) 1141 { 1142 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; 1143 int insn_matched = 1; 1144 size_t i; 1145 1146 gdb_assert (pattern.len > 1); 1147 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); 1148 1149 if (target_read_memory (pc + 1, buf, pattern.len - 1)) 1150 return 0; 1151 1152 for (i = 1; i < pattern.len; i++) 1153 { 1154 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) 1155 insn_matched = 0; 1156 } 1157 return insn_matched; 1158 } 1159 return 0; 1160 } 1161 1162 /* Search for the instruction at PC in the list INSN_PATTERNS. Return 1163 the first instruction description that matches. Otherwise, return 1164 NULL. */ 1165 1166 static struct i386_insn * 1167 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) 1168 { 1169 struct i386_insn *pattern; 1170 1171 for (pattern = insn_patterns; pattern->len > 0; pattern++) 1172 { 1173 if (i386_match_pattern (pc, *pattern)) 1174 return pattern; 1175 } 1176 1177 return NULL; 1178 } 1179 1180 /* Return whether PC points inside a sequence of instructions that 1181 matches INSN_PATTERNS. */ 1182 1183 static int 1184 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) 1185 { 1186 CORE_ADDR current_pc; 1187 int ix, i; 1188 gdb_byte op; 1189 struct i386_insn *insn; 1190 1191 insn = i386_match_insn (pc, insn_patterns); 1192 if (insn == NULL) 1193 return 0; 1194 1195 current_pc = pc; 1196 ix = insn - insn_patterns; 1197 for (i = ix - 1; i >= 0; i--) 1198 { 1199 current_pc -= insn_patterns[i].len; 1200 1201 if (!i386_match_pattern (current_pc, insn_patterns[i])) 1202 return 0; 1203 } 1204 1205 current_pc = pc + insn->len; 1206 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) 1207 { 1208 if (!i386_match_pattern (current_pc, *insn)) 1209 return 0; 1210 1211 current_pc += insn->len; 1212 } 1213 1214 return 1; 1215 } 1216 1217 /* Some special instructions that might be migrated by GCC into the 1218 part of the prologue that sets up the new stack frame. Because the 1219 stack frame hasn't been setup yet, no registers have been saved 1220 yet, and only the scratch registers %eax, %ecx and %edx can be 1221 touched. */ 1222 1223 struct i386_insn i386_frame_setup_skip_insns[] = 1224 { 1225 /* Check for `movb imm8, r' and `movl imm32, r'. 1226 1227 ??? Should we handle 16-bit operand-sizes here? */ 1228 1229 /* `movb imm8, %al' and `movb imm8, %ah' */ 1230 /* `movb imm8, %cl' and `movb imm8, %ch' */ 1231 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, 1232 /* `movb imm8, %dl' and `movb imm8, %dh' */ 1233 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, 1234 /* `movl imm32, %eax' and `movl imm32, %ecx' */ 1235 { 5, { 0xb8 }, { 0xfe } }, 1236 /* `movl imm32, %edx' */ 1237 { 5, { 0xba }, { 0xff } }, 1238 1239 /* Check for `mov imm32, r32'. Note that there is an alternative 1240 encoding for `mov m32, %eax'. 1241 1242 ??? Should we handle SIB adressing here? 1243 ??? Should we handle 16-bit operand-sizes here? */ 1244 1245 /* `movl m32, %eax' */ 1246 { 5, { 0xa1 }, { 0xff } }, 1247 /* `movl m32, %eax' and `mov; m32, %ecx' */ 1248 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, 1249 /* `movl m32, %edx' */ 1250 { 6, { 0x89, 0x15 }, {0xff, 0xff } }, 1251 1252 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. 1253 Because of the symmetry, there are actually two ways to encode 1254 these instructions; opcode bytes 0x29 and 0x2b for `subl' and 1255 opcode bytes 0x31 and 0x33 for `xorl'. */ 1256 1257 /* `subl %eax, %eax' */ 1258 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, 1259 /* `subl %ecx, %ecx' */ 1260 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, 1261 /* `subl %edx, %edx' */ 1262 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, 1263 /* `xorl %eax, %eax' */ 1264 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, 1265 /* `xorl %ecx, %ecx' */ 1266 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, 1267 /* `xorl %edx, %edx' */ 1268 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, 1269 { 0 } 1270 }; 1271 1272 1273 /* Check whether PC points to a no-op instruction. */ 1274 static CORE_ADDR 1275 i386_skip_noop (CORE_ADDR pc) 1276 { 1277 gdb_byte op; 1278 int check = 1; 1279 1280 if (target_read_memory (pc, &op, 1)) 1281 return pc; 1282 1283 while (check) 1284 { 1285 check = 0; 1286 /* Ignore `nop' instruction. */ 1287 if (op == 0x90) 1288 { 1289 pc += 1; 1290 if (target_read_memory (pc, &op, 1)) 1291 return pc; 1292 check = 1; 1293 } 1294 /* Ignore no-op instruction `mov %edi, %edi'. 1295 Microsoft system dlls often start with 1296 a `mov %edi,%edi' instruction. 1297 The 5 bytes before the function start are 1298 filled with `nop' instructions. 1299 This pattern can be used for hot-patching: 1300 The `mov %edi, %edi' instruction can be replaced by a 1301 near jump to the location of the 5 `nop' instructions 1302 which can be replaced by a 32-bit jump to anywhere 1303 in the 32-bit address space. */ 1304 1305 else if (op == 0x8b) 1306 { 1307 if (target_read_memory (pc + 1, &op, 1)) 1308 return pc; 1309 1310 if (op == 0xff) 1311 { 1312 pc += 2; 1313 if (target_read_memory (pc, &op, 1)) 1314 return pc; 1315 1316 check = 1; 1317 } 1318 } 1319 } 1320 return pc; 1321 } 1322 1323 /* Check whether PC points at a code that sets up a new stack frame. 1324 If so, it updates CACHE and returns the address of the first 1325 instruction after the sequence that sets up the frame or LIMIT, 1326 whichever is smaller. If we don't recognize the code, return PC. */ 1327 1328 static CORE_ADDR 1329 i386_analyze_frame_setup (struct gdbarch *gdbarch, 1330 CORE_ADDR pc, CORE_ADDR limit, 1331 struct i386_frame_cache *cache) 1332 { 1333 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1334 struct i386_insn *insn; 1335 gdb_byte op; 1336 int skip = 0; 1337 1338 if (limit <= pc) 1339 return limit; 1340 1341 if (target_read_memory (pc, &op, 1)) 1342 return pc; 1343 1344 if (op == 0x55) /* pushl %ebp */ 1345 { 1346 /* Take into account that we've executed the `pushl %ebp' that 1347 starts this instruction sequence. */ 1348 cache->saved_regs[I386_EBP_REGNUM] = 0; 1349 cache->sp_offset += 4; 1350 pc++; 1351 1352 /* If that's all, return now. */ 1353 if (limit <= pc) 1354 return limit; 1355 1356 /* Check for some special instructions that might be migrated by 1357 GCC into the prologue and skip them. At this point in the 1358 prologue, code should only touch the scratch registers %eax, 1359 %ecx and %edx, so while the number of posibilities is sheer, 1360 it is limited. 1361 1362 Make sure we only skip these instructions if we later see the 1363 `movl %esp, %ebp' that actually sets up the frame. */ 1364 while (pc + skip < limit) 1365 { 1366 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); 1367 if (insn == NULL) 1368 break; 1369 1370 skip += insn->len; 1371 } 1372 1373 /* If that's all, return now. */ 1374 if (limit <= pc + skip) 1375 return limit; 1376 1377 if (target_read_memory (pc + skip, &op, 1)) 1378 return pc + skip; 1379 1380 /* Check for `movl %esp, %ebp' -- can be written in two ways. */ 1381 switch (op) 1382 { 1383 case 0x8b: 1384 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) 1385 != 0xec) 1386 return pc; 1387 break; 1388 case 0x89: 1389 if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) 1390 != 0xe5) 1391 return pc; 1392 break; 1393 default: 1394 return pc; 1395 } 1396 1397 /* OK, we actually have a frame. We just don't know how large 1398 it is yet. Set its size to zero. We'll adjust it if 1399 necessary. We also now commit to skipping the special 1400 instructions mentioned before. */ 1401 cache->locals = 0; 1402 pc += (skip + 2); 1403 1404 /* If that's all, return now. */ 1405 if (limit <= pc) 1406 return limit; 1407 1408 /* Check for stack adjustment 1409 1410 subl $XXX, %esp 1411 1412 NOTE: You can't subtract a 16-bit immediate from a 32-bit 1413 reg, so we don't have to worry about a data16 prefix. */ 1414 if (target_read_memory (pc, &op, 1)) 1415 return pc; 1416 if (op == 0x83) 1417 { 1418 /* `subl' with 8-bit immediate. */ 1419 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) 1420 /* Some instruction starting with 0x83 other than `subl'. */ 1421 return pc; 1422 1423 /* `subl' with signed 8-bit immediate (though it wouldn't 1424 make sense to be negative). */ 1425 cache->locals = read_memory_integer (pc + 2, 1, byte_order); 1426 return pc + 3; 1427 } 1428 else if (op == 0x81) 1429 { 1430 /* Maybe it is `subl' with a 32-bit immediate. */ 1431 if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) 1432 /* Some instruction starting with 0x81 other than `subl'. */ 1433 return pc; 1434 1435 /* It is `subl' with a 32-bit immediate. */ 1436 cache->locals = read_memory_integer (pc + 2, 4, byte_order); 1437 return pc + 6; 1438 } 1439 else 1440 { 1441 /* Some instruction other than `subl'. */ 1442 return pc; 1443 } 1444 } 1445 else if (op == 0xc8) /* enter */ 1446 { 1447 cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); 1448 return pc + 4; 1449 } 1450 1451 return pc; 1452 } 1453 1454 /* Check whether PC points at code that saves registers on the stack. 1455 If so, it updates CACHE and returns the address of the first 1456 instruction after the register saves or CURRENT_PC, whichever is 1457 smaller. Otherwise, return PC. */ 1458 1459 static CORE_ADDR 1460 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, 1461 struct i386_frame_cache *cache) 1462 { 1463 CORE_ADDR offset = 0; 1464 gdb_byte op; 1465 int i; 1466 1467 if (cache->locals > 0) 1468 offset -= cache->locals; 1469 for (i = 0; i < 8 && pc < current_pc; i++) 1470 { 1471 if (target_read_memory (pc, &op, 1)) 1472 return pc; 1473 if (op < 0x50 || op > 0x57) 1474 break; 1475 1476 offset -= 4; 1477 cache->saved_regs[op - 0x50] = offset; 1478 cache->sp_offset += 4; 1479 pc++; 1480 } 1481 1482 return pc; 1483 } 1484 1485 /* Do a full analysis of the prologue at PC and update CACHE 1486 accordingly. Bail out early if CURRENT_PC is reached. Return the 1487 address where the analysis stopped. 1488 1489 We handle these cases: 1490 1491 The startup sequence can be at the start of the function, or the 1492 function can start with a branch to startup code at the end. 1493 1494 %ebp can be set up with either the 'enter' instruction, or "pushl 1495 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was 1496 once used in the System V compiler). 1497 1498 Local space is allocated just below the saved %ebp by either the 1499 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a 1500 16-bit unsigned argument for space to allocate, and the 'addl' 1501 instruction could have either a signed byte, or 32-bit immediate. 1502 1503 Next, the registers used by this function are pushed. With the 1504 System V compiler they will always be in the order: %edi, %esi, 1505 %ebx (and sometimes a harmless bug causes it to also save but not 1506 restore %eax); however, the code below is willing to see the pushes 1507 in any order, and will handle up to 8 of them. 1508 1509 If the setup sequence is at the end of the function, then the next 1510 instruction will be a branch back to the start. */ 1511 1512 static CORE_ADDR 1513 i386_analyze_prologue (struct gdbarch *gdbarch, 1514 CORE_ADDR pc, CORE_ADDR current_pc, 1515 struct i386_frame_cache *cache) 1516 { 1517 pc = i386_skip_noop (pc); 1518 pc = i386_follow_jump (gdbarch, pc); 1519 pc = i386_analyze_struct_return (pc, current_pc, cache); 1520 pc = i386_skip_probe (pc); 1521 pc = i386_analyze_stack_align (pc, current_pc, cache); 1522 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); 1523 return i386_analyze_register_saves (pc, current_pc, cache); 1524 } 1525 1526 /* Return PC of first real instruction. */ 1527 1528 static CORE_ADDR 1529 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1530 { 1531 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1532 1533 static gdb_byte pic_pat[6] = 1534 { 1535 0xe8, 0, 0, 0, 0, /* call 0x0 */ 1536 0x5b, /* popl %ebx */ 1537 }; 1538 struct i386_frame_cache cache; 1539 CORE_ADDR pc; 1540 gdb_byte op; 1541 int i; 1542 1543 cache.locals = -1; 1544 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); 1545 if (cache.locals < 0) 1546 return start_pc; 1547 1548 /* Found valid frame setup. */ 1549 1550 /* The native cc on SVR4 in -K PIC mode inserts the following code 1551 to get the address of the global offset table (GOT) into register 1552 %ebx: 1553 1554 call 0x0 1555 popl %ebx 1556 movl %ebx,x(%ebp) (optional) 1557 addl y,%ebx 1558 1559 This code is with the rest of the prologue (at the end of the 1560 function), so we have to skip it to get to the first real 1561 instruction at the start of the function. */ 1562 1563 for (i = 0; i < 6; i++) 1564 { 1565 if (target_read_memory (pc + i, &op, 1)) 1566 return pc; 1567 1568 if (pic_pat[i] != op) 1569 break; 1570 } 1571 if (i == 6) 1572 { 1573 int delta = 6; 1574 1575 if (target_read_memory (pc + delta, &op, 1)) 1576 return pc; 1577 1578 if (op == 0x89) /* movl %ebx, x(%ebp) */ 1579 { 1580 op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); 1581 1582 if (op == 0x5d) /* One byte offset from %ebp. */ 1583 delta += 3; 1584 else if (op == 0x9d) /* Four byte offset from %ebp. */ 1585 delta += 6; 1586 else /* Unexpected instruction. */ 1587 delta = 0; 1588 1589 if (target_read_memory (pc + delta, &op, 1)) 1590 return pc; 1591 } 1592 1593 /* addl y,%ebx */ 1594 if (delta > 0 && op == 0x81 1595 && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) 1596 == 0xc3) 1597 { 1598 pc += delta + 6; 1599 } 1600 } 1601 1602 /* If the function starts with a branch (to startup code at the end) 1603 the last instruction should bring us back to the first 1604 instruction of the real code. */ 1605 if (i386_follow_jump (gdbarch, start_pc) != start_pc) 1606 pc = i386_follow_jump (gdbarch, pc); 1607 1608 return pc; 1609 } 1610 1611 /* Check that the code pointed to by PC corresponds to a call to 1612 __main, skip it if so. Return PC otherwise. */ 1613 1614 CORE_ADDR 1615 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 1616 { 1617 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1618 gdb_byte op; 1619 1620 if (target_read_memory (pc, &op, 1)) 1621 return pc; 1622 if (op == 0xe8) 1623 { 1624 gdb_byte buf[4]; 1625 1626 if (target_read_memory (pc + 1, buf, sizeof buf) == 0) 1627 { 1628 /* Make sure address is computed correctly as a 32bit 1629 integer even if CORE_ADDR is 64 bit wide. */ 1630 struct minimal_symbol *s; 1631 CORE_ADDR call_dest; 1632 1633 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); 1634 call_dest = call_dest & 0xffffffffU; 1635 s = lookup_minimal_symbol_by_pc (call_dest); 1636 if (s != NULL 1637 && SYMBOL_LINKAGE_NAME (s) != NULL 1638 && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) 1639 pc += 5; 1640 } 1641 } 1642 1643 return pc; 1644 } 1645 1646 /* This function is 64-bit safe. */ 1647 1648 static CORE_ADDR 1649 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1650 { 1651 gdb_byte buf[8]; 1652 1653 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); 1654 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); 1655 } 1656 1657 1658 /* Normal frames. */ 1659 1660 static void 1661 i386_frame_cache_1 (struct frame_info *this_frame, 1662 struct i386_frame_cache *cache) 1663 { 1664 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1665 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1666 gdb_byte buf[4]; 1667 int i; 1668 1669 cache->pc = get_frame_func (this_frame); 1670 1671 /* In principle, for normal frames, %ebp holds the frame pointer, 1672 which holds the base address for the current stack frame. 1673 However, for functions that don't need it, the frame pointer is 1674 optional. For these "frameless" functions the frame pointer is 1675 actually the frame pointer of the calling frame. Signal 1676 trampolines are just a special case of a "frameless" function. 1677 They (usually) share their frame pointer with the frame that was 1678 in progress when the signal occurred. */ 1679 1680 get_frame_register (this_frame, I386_EBP_REGNUM, buf); 1681 cache->base = extract_unsigned_integer (buf, 4, byte_order); 1682 if (cache->base == 0) 1683 { 1684 cache->base_p = 1; 1685 return; 1686 } 1687 1688 /* For normal frames, %eip is stored at 4(%ebp). */ 1689 cache->saved_regs[I386_EIP_REGNUM] = 4; 1690 1691 if (cache->pc != 0) 1692 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), 1693 cache); 1694 1695 if (cache->locals < 0) 1696 { 1697 /* We didn't find a valid frame, which means that CACHE->base 1698 currently holds the frame pointer for our calling frame. If 1699 we're at the start of a function, or somewhere half-way its 1700 prologue, the function's frame probably hasn't been fully 1701 setup yet. Try to reconstruct the base address for the stack 1702 frame by looking at the stack pointer. For truly "frameless" 1703 functions this might work too. */ 1704 1705 if (cache->saved_sp_reg != -1) 1706 { 1707 /* Saved stack pointer has been saved. */ 1708 get_frame_register (this_frame, cache->saved_sp_reg, buf); 1709 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); 1710 1711 /* We're halfway aligning the stack. */ 1712 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; 1713 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; 1714 1715 /* This will be added back below. */ 1716 cache->saved_regs[I386_EIP_REGNUM] -= cache->base; 1717 } 1718 else if (cache->pc != 0 1719 || target_read_memory (get_frame_pc (this_frame), buf, 1)) 1720 { 1721 /* We're in a known function, but did not find a frame 1722 setup. Assume that the function does not use %ebp. 1723 Alternatively, we may have jumped to an invalid 1724 address; in that case there is definitely no new 1725 frame in %ebp. */ 1726 get_frame_register (this_frame, I386_ESP_REGNUM, buf); 1727 cache->base = extract_unsigned_integer (buf, 4, byte_order) 1728 + cache->sp_offset; 1729 } 1730 else 1731 /* We're in an unknown function. We could not find the start 1732 of the function to analyze the prologue; our best option is 1733 to assume a typical frame layout with the caller's %ebp 1734 saved. */ 1735 cache->saved_regs[I386_EBP_REGNUM] = 0; 1736 } 1737 1738 if (cache->saved_sp_reg != -1) 1739 { 1740 /* Saved stack pointer has been saved (but the SAVED_SP_REG 1741 register may be unavailable). */ 1742 if (cache->saved_sp == 0 1743 && frame_register_read (this_frame, cache->saved_sp_reg, buf)) 1744 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); 1745 } 1746 /* Now that we have the base address for the stack frame we can 1747 calculate the value of %esp in the calling frame. */ 1748 else if (cache->saved_sp == 0) 1749 cache->saved_sp = cache->base + 8; 1750 1751 /* Adjust all the saved registers such that they contain addresses 1752 instead of offsets. */ 1753 for (i = 0; i < I386_NUM_SAVED_REGS; i++) 1754 if (cache->saved_regs[i] != -1) 1755 cache->saved_regs[i] += cache->base; 1756 1757 cache->base_p = 1; 1758 } 1759 1760 static struct i386_frame_cache * 1761 i386_frame_cache (struct frame_info *this_frame, void **this_cache) 1762 { 1763 volatile struct gdb_exception ex; 1764 struct i386_frame_cache *cache; 1765 1766 if (*this_cache) 1767 return *this_cache; 1768 1769 cache = i386_alloc_frame_cache (); 1770 *this_cache = cache; 1771 1772 TRY_CATCH (ex, RETURN_MASK_ERROR) 1773 { 1774 i386_frame_cache_1 (this_frame, cache); 1775 } 1776 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) 1777 throw_exception (ex); 1778 1779 return cache; 1780 } 1781 1782 static void 1783 i386_frame_this_id (struct frame_info *this_frame, void **this_cache, 1784 struct frame_id *this_id) 1785 { 1786 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 1787 1788 /* This marks the outermost frame. */ 1789 if (cache->base == 0) 1790 return; 1791 1792 /* See the end of i386_push_dummy_call. */ 1793 (*this_id) = frame_id_build (cache->base + 8, cache->pc); 1794 } 1795 1796 static enum unwind_stop_reason 1797 i386_frame_unwind_stop_reason (struct frame_info *this_frame, 1798 void **this_cache) 1799 { 1800 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 1801 1802 if (!cache->base_p) 1803 return UNWIND_UNAVAILABLE; 1804 1805 /* This marks the outermost frame. */ 1806 if (cache->base == 0) 1807 return UNWIND_OUTERMOST; 1808 1809 return UNWIND_NO_REASON; 1810 } 1811 1812 static struct value * 1813 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, 1814 int regnum) 1815 { 1816 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 1817 1818 gdb_assert (regnum >= 0); 1819 1820 /* The System V ABI says that: 1821 1822 "The flags register contains the system flags, such as the 1823 direction flag and the carry flag. The direction flag must be 1824 set to the forward (that is, zero) direction before entry and 1825 upon exit from a function. Other user flags have no specified 1826 role in the standard calling sequence and are not preserved." 1827 1828 To guarantee the "upon exit" part of that statement we fake a 1829 saved flags register that has its direction flag cleared. 1830 1831 Note that GCC doesn't seem to rely on the fact that the direction 1832 flag is cleared after a function return; it always explicitly 1833 clears the flag before operations where it matters. 1834 1835 FIXME: kettenis/20030316: I'm not quite sure whether this is the 1836 right thing to do. The way we fake the flags register here makes 1837 it impossible to change it. */ 1838 1839 if (regnum == I386_EFLAGS_REGNUM) 1840 { 1841 ULONGEST val; 1842 1843 val = get_frame_register_unsigned (this_frame, regnum); 1844 val &= ~(1 << 10); 1845 return frame_unwind_got_constant (this_frame, regnum, val); 1846 } 1847 1848 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) 1849 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); 1850 1851 if (regnum == I386_ESP_REGNUM 1852 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) 1853 { 1854 /* If the SP has been saved, but we don't know where, then this 1855 means that SAVED_SP_REG register was found unavailable back 1856 when we built the cache. */ 1857 if (cache->saved_sp == 0) 1858 return frame_unwind_got_register (this_frame, regnum, 1859 cache->saved_sp_reg); 1860 else 1861 return frame_unwind_got_constant (this_frame, regnum, 1862 cache->saved_sp); 1863 } 1864 1865 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) 1866 return frame_unwind_got_memory (this_frame, regnum, 1867 cache->saved_regs[regnum]); 1868 1869 return frame_unwind_got_register (this_frame, regnum, regnum); 1870 } 1871 1872 static const struct frame_unwind i386_frame_unwind = 1873 { 1874 NORMAL_FRAME, 1875 i386_frame_unwind_stop_reason, 1876 i386_frame_this_id, 1877 i386_frame_prev_register, 1878 NULL, 1879 default_frame_sniffer 1880 }; 1881 1882 /* Normal frames, but in a function epilogue. */ 1883 1884 /* The epilogue is defined here as the 'ret' instruction, which will 1885 follow any instruction such as 'leave' or 'pop %ebp' that destroys 1886 the function's stack frame. */ 1887 1888 static int 1889 i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) 1890 { 1891 gdb_byte insn; 1892 struct symtab *symtab; 1893 1894 symtab = find_pc_symtab (pc); 1895 if (symtab && symtab->epilogue_unwind_valid) 1896 return 0; 1897 1898 if (target_read_memory (pc, &insn, 1)) 1899 return 0; /* Can't read memory at pc. */ 1900 1901 if (insn != 0xc3) /* 'ret' instruction. */ 1902 return 0; 1903 1904 return 1; 1905 } 1906 1907 static int 1908 i386_epilogue_frame_sniffer (const struct frame_unwind *self, 1909 struct frame_info *this_frame, 1910 void **this_prologue_cache) 1911 { 1912 if (frame_relative_level (this_frame) == 0) 1913 return i386_in_function_epilogue_p (get_frame_arch (this_frame), 1914 get_frame_pc (this_frame)); 1915 else 1916 return 0; 1917 } 1918 1919 static struct i386_frame_cache * 1920 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) 1921 { 1922 volatile struct gdb_exception ex; 1923 struct i386_frame_cache *cache; 1924 CORE_ADDR sp; 1925 1926 if (*this_cache) 1927 return *this_cache; 1928 1929 cache = i386_alloc_frame_cache (); 1930 *this_cache = cache; 1931 1932 TRY_CATCH (ex, RETURN_MASK_ERROR) 1933 { 1934 cache->pc = get_frame_func (this_frame); 1935 1936 /* At this point the stack looks as if we just entered the 1937 function, with the return address at the top of the 1938 stack. */ 1939 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); 1940 cache->base = sp + cache->sp_offset; 1941 cache->saved_sp = cache->base + 8; 1942 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; 1943 1944 cache->base_p = 1; 1945 } 1946 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) 1947 throw_exception (ex); 1948 1949 return cache; 1950 } 1951 1952 static enum unwind_stop_reason 1953 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, 1954 void **this_cache) 1955 { 1956 struct i386_frame_cache *cache = 1957 i386_epilogue_frame_cache (this_frame, this_cache); 1958 1959 if (!cache->base_p) 1960 return UNWIND_UNAVAILABLE; 1961 1962 return UNWIND_NO_REASON; 1963 } 1964 1965 static void 1966 i386_epilogue_frame_this_id (struct frame_info *this_frame, 1967 void **this_cache, 1968 struct frame_id *this_id) 1969 { 1970 struct i386_frame_cache *cache = 1971 i386_epilogue_frame_cache (this_frame, this_cache); 1972 1973 if (!cache->base_p) 1974 return; 1975 1976 (*this_id) = frame_id_build (cache->base + 8, cache->pc); 1977 } 1978 1979 static struct value * 1980 i386_epilogue_frame_prev_register (struct frame_info *this_frame, 1981 void **this_cache, int regnum) 1982 { 1983 /* Make sure we've initialized the cache. */ 1984 i386_epilogue_frame_cache (this_frame, this_cache); 1985 1986 return i386_frame_prev_register (this_frame, this_cache, regnum); 1987 } 1988 1989 static const struct frame_unwind i386_epilogue_frame_unwind = 1990 { 1991 NORMAL_FRAME, 1992 i386_epilogue_frame_unwind_stop_reason, 1993 i386_epilogue_frame_this_id, 1994 i386_epilogue_frame_prev_register, 1995 NULL, 1996 i386_epilogue_frame_sniffer 1997 }; 1998 1999 2000 /* Stack-based trampolines. */ 2001 2002 /* These trampolines are used on cross x86 targets, when taking the 2003 address of a nested function. When executing these trampolines, 2004 no stack frame is set up, so we are in a similar situation as in 2005 epilogues and i386_epilogue_frame_this_id can be re-used. */ 2006 2007 /* Static chain passed in register. */ 2008 2009 struct i386_insn i386_tramp_chain_in_reg_insns[] = 2010 { 2011 /* `movl imm32, %eax' and `movl imm32, %ecx' */ 2012 { 5, { 0xb8 }, { 0xfe } }, 2013 2014 /* `jmp imm32' */ 2015 { 5, { 0xe9 }, { 0xff } }, 2016 2017 {0} 2018 }; 2019 2020 /* Static chain passed on stack (when regparm=3). */ 2021 2022 struct i386_insn i386_tramp_chain_on_stack_insns[] = 2023 { 2024 /* `push imm32' */ 2025 { 5, { 0x68 }, { 0xff } }, 2026 2027 /* `jmp imm32' */ 2028 { 5, { 0xe9 }, { 0xff } }, 2029 2030 {0} 2031 }; 2032 2033 /* Return whether PC points inside a stack trampoline. */ 2034 2035 static int 2036 i386_in_stack_tramp_p (struct gdbarch *gdbarch, CORE_ADDR pc) 2037 { 2038 gdb_byte insn; 2039 char *name; 2040 2041 /* A stack trampoline is detected if no name is associated 2042 to the current pc and if it points inside a trampoline 2043 sequence. */ 2044 2045 find_pc_partial_function (pc, &name, NULL, NULL); 2046 if (name) 2047 return 0; 2048 2049 if (target_read_memory (pc, &insn, 1)) 2050 return 0; 2051 2052 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) 2053 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) 2054 return 0; 2055 2056 return 1; 2057 } 2058 2059 static int 2060 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, 2061 struct frame_info *this_frame, 2062 void **this_cache) 2063 { 2064 if (frame_relative_level (this_frame) == 0) 2065 return i386_in_stack_tramp_p (get_frame_arch (this_frame), 2066 get_frame_pc (this_frame)); 2067 else 2068 return 0; 2069 } 2070 2071 static const struct frame_unwind i386_stack_tramp_frame_unwind = 2072 { 2073 NORMAL_FRAME, 2074 i386_epilogue_frame_unwind_stop_reason, 2075 i386_epilogue_frame_this_id, 2076 i386_epilogue_frame_prev_register, 2077 NULL, 2078 i386_stack_tramp_frame_sniffer 2079 }; 2080 2081 /* Generate a bytecode expression to get the value of the saved PC. */ 2082 2083 static void 2084 i386_gen_return_address (struct gdbarch *gdbarch, 2085 struct agent_expr *ax, struct axs_value *value, 2086 CORE_ADDR scope) 2087 { 2088 /* The following sequence assumes the traditional use of the base 2089 register. */ 2090 ax_reg (ax, I386_EBP_REGNUM); 2091 ax_const_l (ax, 4); 2092 ax_simple (ax, aop_add); 2093 value->type = register_type (gdbarch, I386_EIP_REGNUM); 2094 value->kind = axs_lvalue_memory; 2095 } 2096 2097 2098 /* Signal trampolines. */ 2099 2100 static struct i386_frame_cache * 2101 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) 2102 { 2103 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2104 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2105 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2106 volatile struct gdb_exception ex; 2107 struct i386_frame_cache *cache; 2108 CORE_ADDR addr; 2109 gdb_byte buf[4]; 2110 2111 if (*this_cache) 2112 return *this_cache; 2113 2114 cache = i386_alloc_frame_cache (); 2115 2116 TRY_CATCH (ex, RETURN_MASK_ERROR) 2117 { 2118 get_frame_register (this_frame, I386_ESP_REGNUM, buf); 2119 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; 2120 2121 addr = tdep->sigcontext_addr (this_frame); 2122 if (tdep->sc_reg_offset) 2123 { 2124 int i; 2125 2126 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); 2127 2128 for (i = 0; i < tdep->sc_num_regs; i++) 2129 if (tdep->sc_reg_offset[i] != -1) 2130 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; 2131 } 2132 else 2133 { 2134 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; 2135 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; 2136 } 2137 2138 cache->base_p = 1; 2139 } 2140 if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) 2141 throw_exception (ex); 2142 2143 *this_cache = cache; 2144 return cache; 2145 } 2146 2147 static enum unwind_stop_reason 2148 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, 2149 void **this_cache) 2150 { 2151 struct i386_frame_cache *cache = 2152 i386_sigtramp_frame_cache (this_frame, this_cache); 2153 2154 if (!cache->base_p) 2155 return UNWIND_UNAVAILABLE; 2156 2157 return UNWIND_NO_REASON; 2158 } 2159 2160 static void 2161 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, 2162 struct frame_id *this_id) 2163 { 2164 struct i386_frame_cache *cache = 2165 i386_sigtramp_frame_cache (this_frame, this_cache); 2166 2167 if (!cache->base_p) 2168 return; 2169 2170 /* See the end of i386_push_dummy_call. */ 2171 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); 2172 } 2173 2174 static struct value * 2175 i386_sigtramp_frame_prev_register (struct frame_info *this_frame, 2176 void **this_cache, int regnum) 2177 { 2178 /* Make sure we've initialized the cache. */ 2179 i386_sigtramp_frame_cache (this_frame, this_cache); 2180 2181 return i386_frame_prev_register (this_frame, this_cache, regnum); 2182 } 2183 2184 static int 2185 i386_sigtramp_frame_sniffer (const struct frame_unwind *self, 2186 struct frame_info *this_frame, 2187 void **this_prologue_cache) 2188 { 2189 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); 2190 2191 /* We shouldn't even bother if we don't have a sigcontext_addr 2192 handler. */ 2193 if (tdep->sigcontext_addr == NULL) 2194 return 0; 2195 2196 if (tdep->sigtramp_p != NULL) 2197 { 2198 if (tdep->sigtramp_p (this_frame)) 2199 return 1; 2200 } 2201 2202 if (tdep->sigtramp_start != 0) 2203 { 2204 CORE_ADDR pc = get_frame_pc (this_frame); 2205 2206 gdb_assert (tdep->sigtramp_end != 0); 2207 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) 2208 return 1; 2209 } 2210 2211 return 0; 2212 } 2213 2214 static const struct frame_unwind i386_sigtramp_frame_unwind = 2215 { 2216 SIGTRAMP_FRAME, 2217 i386_sigtramp_frame_unwind_stop_reason, 2218 i386_sigtramp_frame_this_id, 2219 i386_sigtramp_frame_prev_register, 2220 NULL, 2221 i386_sigtramp_frame_sniffer 2222 }; 2223 2224 2225 static CORE_ADDR 2226 i386_frame_base_address (struct frame_info *this_frame, void **this_cache) 2227 { 2228 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 2229 2230 return cache->base; 2231 } 2232 2233 static const struct frame_base i386_frame_base = 2234 { 2235 &i386_frame_unwind, 2236 i386_frame_base_address, 2237 i386_frame_base_address, 2238 i386_frame_base_address 2239 }; 2240 2241 static struct frame_id 2242 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 2243 { 2244 CORE_ADDR fp; 2245 2246 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); 2247 2248 /* See the end of i386_push_dummy_call. */ 2249 return frame_id_build (fp + 8, get_frame_pc (this_frame)); 2250 } 2251 2252 /* _Decimal128 function return values need 16-byte alignment on the 2253 stack. */ 2254 2255 static CORE_ADDR 2256 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 2257 { 2258 return sp & -(CORE_ADDR)16; 2259 } 2260 2261 2262 /* Figure out where the longjmp will land. Slurp the args out of the 2263 stack. We expect the first arg to be a pointer to the jmp_buf 2264 structure from which we extract the address that we will land at. 2265 This address is copied into PC. This routine returns non-zero on 2266 success. */ 2267 2268 static int 2269 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 2270 { 2271 gdb_byte buf[4]; 2272 CORE_ADDR sp, jb_addr; 2273 struct gdbarch *gdbarch = get_frame_arch (frame); 2274 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2275 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; 2276 2277 /* If JB_PC_OFFSET is -1, we have no way to find out where the 2278 longjmp will land. */ 2279 if (jb_pc_offset == -1) 2280 return 0; 2281 2282 get_frame_register (frame, I386_ESP_REGNUM, buf); 2283 sp = extract_unsigned_integer (buf, 4, byte_order); 2284 if (target_read_memory (sp + 4, buf, 4)) 2285 return 0; 2286 2287 jb_addr = extract_unsigned_integer (buf, 4, byte_order); 2288 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) 2289 return 0; 2290 2291 *pc = extract_unsigned_integer (buf, 4, byte_order); 2292 return 1; 2293 } 2294 2295 2296 /* Check whether TYPE must be 16-byte-aligned when passed as a 2297 function argument. 16-byte vectors, _Decimal128 and structures or 2298 unions containing such types must be 16-byte-aligned; other 2299 arguments are 4-byte-aligned. */ 2300 2301 static int 2302 i386_16_byte_align_p (struct type *type) 2303 { 2304 type = check_typedef (type); 2305 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT 2306 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) 2307 && TYPE_LENGTH (type) == 16) 2308 return 1; 2309 if (TYPE_CODE (type) == TYPE_CODE_ARRAY) 2310 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); 2311 if (TYPE_CODE (type) == TYPE_CODE_STRUCT 2312 || TYPE_CODE (type) == TYPE_CODE_UNION) 2313 { 2314 int i; 2315 for (i = 0; i < TYPE_NFIELDS (type); i++) 2316 { 2317 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) 2318 return 1; 2319 } 2320 } 2321 return 0; 2322 } 2323 2324 static CORE_ADDR 2325 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 2326 struct regcache *regcache, CORE_ADDR bp_addr, int nargs, 2327 struct value **args, CORE_ADDR sp, int struct_return, 2328 CORE_ADDR struct_addr) 2329 { 2330 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2331 gdb_byte buf[4]; 2332 int i; 2333 int write_pass; 2334 int args_space = 0; 2335 2336 /* Determine the total space required for arguments and struct 2337 return address in a first pass (allowing for 16-byte-aligned 2338 arguments), then push arguments in a second pass. */ 2339 2340 for (write_pass = 0; write_pass < 2; write_pass++) 2341 { 2342 int args_space_used = 0; 2343 int have_16_byte_aligned_arg = 0; 2344 2345 if (struct_return) 2346 { 2347 if (write_pass) 2348 { 2349 /* Push value address. */ 2350 store_unsigned_integer (buf, 4, byte_order, struct_addr); 2351 write_memory (sp, buf, 4); 2352 args_space_used += 4; 2353 } 2354 else 2355 args_space += 4; 2356 } 2357 2358 for (i = 0; i < nargs; i++) 2359 { 2360 int len = TYPE_LENGTH (value_enclosing_type (args[i])); 2361 2362 if (write_pass) 2363 { 2364 if (i386_16_byte_align_p (value_enclosing_type (args[i]))) 2365 args_space_used = align_up (args_space_used, 16); 2366 2367 write_memory (sp + args_space_used, 2368 value_contents_all (args[i]), len); 2369 /* The System V ABI says that: 2370 2371 "An argument's size is increased, if necessary, to make it a 2372 multiple of [32-bit] words. This may require tail padding, 2373 depending on the size of the argument." 2374 2375 This makes sure the stack stays word-aligned. */ 2376 args_space_used += align_up (len, 4); 2377 } 2378 else 2379 { 2380 if (i386_16_byte_align_p (value_enclosing_type (args[i]))) 2381 { 2382 args_space = align_up (args_space, 16); 2383 have_16_byte_aligned_arg = 1; 2384 } 2385 args_space += align_up (len, 4); 2386 } 2387 } 2388 2389 if (!write_pass) 2390 { 2391 if (have_16_byte_aligned_arg) 2392 args_space = align_up (args_space, 16); 2393 sp -= args_space; 2394 } 2395 } 2396 2397 /* Store return address. */ 2398 sp -= 4; 2399 store_unsigned_integer (buf, 4, byte_order, bp_addr); 2400 write_memory (sp, buf, 4); 2401 2402 /* Finally, update the stack pointer... */ 2403 store_unsigned_integer (buf, 4, byte_order, sp); 2404 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); 2405 2406 /* ...and fake a frame pointer. */ 2407 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); 2408 2409 /* MarkK wrote: This "+ 8" is all over the place: 2410 (i386_frame_this_id, i386_sigtramp_frame_this_id, 2411 i386_dummy_id). It's there, since all frame unwinders for 2412 a given target have to agree (within a certain margin) on the 2413 definition of the stack address of a frame. Otherwise frame id 2414 comparison might not work correctly. Since DWARF2/GCC uses the 2415 stack address *before* the function call as a frame's CFA. On 2416 the i386, when %ebp is used as a frame pointer, the offset 2417 between the contents %ebp and the CFA as defined by GCC. */ 2418 return sp + 8; 2419 } 2420 2421 /* These registers are used for returning integers (and on some 2422 targets also for returning `struct' and `union' values when their 2423 size and alignment match an integer type). */ 2424 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ 2425 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ 2426 2427 /* Read, for architecture GDBARCH, a function return value of TYPE 2428 from REGCACHE, and copy that into VALBUF. */ 2429 2430 static void 2431 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, 2432 struct regcache *regcache, gdb_byte *valbuf) 2433 { 2434 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2435 int len = TYPE_LENGTH (type); 2436 gdb_byte buf[I386_MAX_REGISTER_SIZE]; 2437 2438 if (TYPE_CODE (type) == TYPE_CODE_FLT) 2439 { 2440 if (tdep->st0_regnum < 0) 2441 { 2442 warning (_("Cannot find floating-point return value.")); 2443 memset (valbuf, 0, len); 2444 return; 2445 } 2446 2447 /* Floating-point return values can be found in %st(0). Convert 2448 its contents to the desired type. This is probably not 2449 exactly how it would happen on the target itself, but it is 2450 the best we can do. */ 2451 regcache_raw_read (regcache, I386_ST0_REGNUM, buf); 2452 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); 2453 } 2454 else 2455 { 2456 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); 2457 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); 2458 2459 if (len <= low_size) 2460 { 2461 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); 2462 memcpy (valbuf, buf, len); 2463 } 2464 else if (len <= (low_size + high_size)) 2465 { 2466 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); 2467 memcpy (valbuf, buf, low_size); 2468 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); 2469 memcpy (valbuf + low_size, buf, len - low_size); 2470 } 2471 else 2472 internal_error (__FILE__, __LINE__, 2473 _("Cannot extract return value of %d bytes long."), 2474 len); 2475 } 2476 } 2477 2478 /* Write, for architecture GDBARCH, a function return value of TYPE 2479 from VALBUF into REGCACHE. */ 2480 2481 static void 2482 i386_store_return_value (struct gdbarch *gdbarch, struct type *type, 2483 struct regcache *regcache, const gdb_byte *valbuf) 2484 { 2485 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2486 int len = TYPE_LENGTH (type); 2487 2488 if (TYPE_CODE (type) == TYPE_CODE_FLT) 2489 { 2490 ULONGEST fstat; 2491 gdb_byte buf[I386_MAX_REGISTER_SIZE]; 2492 2493 if (tdep->st0_regnum < 0) 2494 { 2495 warning (_("Cannot set floating-point return value.")); 2496 return; 2497 } 2498 2499 /* Returning floating-point values is a bit tricky. Apart from 2500 storing the return value in %st(0), we have to simulate the 2501 state of the FPU at function return point. */ 2502 2503 /* Convert the value found in VALBUF to the extended 2504 floating-point format used by the FPU. This is probably 2505 not exactly how it would happen on the target itself, but 2506 it is the best we can do. */ 2507 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); 2508 regcache_raw_write (regcache, I386_ST0_REGNUM, buf); 2509 2510 /* Set the top of the floating-point register stack to 7. The 2511 actual value doesn't really matter, but 7 is what a normal 2512 function return would end up with if the program started out 2513 with a freshly initialized FPU. */ 2514 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); 2515 fstat |= (7 << 11); 2516 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); 2517 2518 /* Mark %st(1) through %st(7) as empty. Since we set the top of 2519 the floating-point register stack to 7, the appropriate value 2520 for the tag word is 0x3fff. */ 2521 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); 2522 } 2523 else 2524 { 2525 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); 2526 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); 2527 2528 if (len <= low_size) 2529 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); 2530 else if (len <= (low_size + high_size)) 2531 { 2532 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); 2533 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, 2534 len - low_size, valbuf + low_size); 2535 } 2536 else 2537 internal_error (__FILE__, __LINE__, 2538 _("Cannot store return value of %d bytes long."), len); 2539 } 2540 } 2541 2542 2543 /* This is the variable that is set with "set struct-convention", and 2544 its legitimate values. */ 2545 static const char default_struct_convention[] = "default"; 2546 static const char pcc_struct_convention[] = "pcc"; 2547 static const char reg_struct_convention[] = "reg"; 2548 static const char *valid_conventions[] = 2549 { 2550 default_struct_convention, 2551 pcc_struct_convention, 2552 reg_struct_convention, 2553 NULL 2554 }; 2555 static const char *struct_convention = default_struct_convention; 2556 2557 /* Return non-zero if TYPE, which is assumed to be a structure, 2558 a union type, or an array type, should be returned in registers 2559 for architecture GDBARCH. */ 2560 2561 static int 2562 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) 2563 { 2564 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2565 enum type_code code = TYPE_CODE (type); 2566 int len = TYPE_LENGTH (type); 2567 2568 gdb_assert (code == TYPE_CODE_STRUCT 2569 || code == TYPE_CODE_UNION 2570 || code == TYPE_CODE_ARRAY); 2571 2572 if (struct_convention == pcc_struct_convention 2573 || (struct_convention == default_struct_convention 2574 && tdep->struct_return == pcc_struct_return)) 2575 return 0; 2576 2577 /* Structures consisting of a single `float', `double' or 'long 2578 double' member are returned in %st(0). */ 2579 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) 2580 { 2581 type = check_typedef (TYPE_FIELD_TYPE (type, 0)); 2582 if (TYPE_CODE (type) == TYPE_CODE_FLT) 2583 return (len == 4 || len == 8 || len == 12); 2584 } 2585 2586 return (len == 1 || len == 2 || len == 4 || len == 8); 2587 } 2588 2589 /* Determine, for architecture GDBARCH, how a return value of TYPE 2590 should be returned. If it is supposed to be returned in registers, 2591 and READBUF is non-zero, read the appropriate value from REGCACHE, 2592 and copy it into READBUF. If WRITEBUF is non-zero, write the value 2593 from WRITEBUF into REGCACHE. */ 2594 2595 static enum return_value_convention 2596 i386_return_value (struct gdbarch *gdbarch, struct type *func_type, 2597 struct type *type, struct regcache *regcache, 2598 gdb_byte *readbuf, const gdb_byte *writebuf) 2599 { 2600 enum type_code code = TYPE_CODE (type); 2601 2602 if (((code == TYPE_CODE_STRUCT 2603 || code == TYPE_CODE_UNION 2604 || code == TYPE_CODE_ARRAY) 2605 && !i386_reg_struct_return_p (gdbarch, type)) 2606 /* 128-bit decimal float uses the struct return convention. */ 2607 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) 2608 { 2609 /* The System V ABI says that: 2610 2611 "A function that returns a structure or union also sets %eax 2612 to the value of the original address of the caller's area 2613 before it returns. Thus when the caller receives control 2614 again, the address of the returned object resides in register 2615 %eax and can be used to access the object." 2616 2617 So the ABI guarantees that we can always find the return 2618 value just after the function has returned. */ 2619 2620 /* Note that the ABI doesn't mention functions returning arrays, 2621 which is something possible in certain languages such as Ada. 2622 In this case, the value is returned as if it was wrapped in 2623 a record, so the convention applied to records also applies 2624 to arrays. */ 2625 2626 if (readbuf) 2627 { 2628 ULONGEST addr; 2629 2630 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); 2631 read_memory (addr, readbuf, TYPE_LENGTH (type)); 2632 } 2633 2634 return RETURN_VALUE_ABI_RETURNS_ADDRESS; 2635 } 2636 2637 /* This special case is for structures consisting of a single 2638 `float', `double' or 'long double' member. These structures are 2639 returned in %st(0). For these structures, we call ourselves 2640 recursively, changing TYPE into the type of the first member of 2641 the structure. Since that should work for all structures that 2642 have only one member, we don't bother to check the member's type 2643 here. */ 2644 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) 2645 { 2646 type = check_typedef (TYPE_FIELD_TYPE (type, 0)); 2647 return i386_return_value (gdbarch, func_type, type, regcache, 2648 readbuf, writebuf); 2649 } 2650 2651 if (readbuf) 2652 i386_extract_return_value (gdbarch, type, regcache, readbuf); 2653 if (writebuf) 2654 i386_store_return_value (gdbarch, type, regcache, writebuf); 2655 2656 return RETURN_VALUE_REGISTER_CONVENTION; 2657 } 2658 2659 2660 struct type * 2661 i387_ext_type (struct gdbarch *gdbarch) 2662 { 2663 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2664 2665 if (!tdep->i387_ext_type) 2666 { 2667 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); 2668 gdb_assert (tdep->i387_ext_type != NULL); 2669 } 2670 2671 return tdep->i387_ext_type; 2672 } 2673 2674 /* Construct vector type for pseudo YMM registers. We can't use 2675 tdesc_find_type since YMM isn't described in target description. */ 2676 2677 static struct type * 2678 i386_ymm_type (struct gdbarch *gdbarch) 2679 { 2680 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2681 2682 if (!tdep->i386_ymm_type) 2683 { 2684 const struct builtin_type *bt = builtin_type (gdbarch); 2685 2686 /* The type we're building is this: */ 2687 #if 0 2688 union __gdb_builtin_type_vec256i 2689 { 2690 int128_t uint128[2]; 2691 int64_t v2_int64[4]; 2692 int32_t v4_int32[8]; 2693 int16_t v8_int16[16]; 2694 int8_t v16_int8[32]; 2695 double v2_double[4]; 2696 float v4_float[8]; 2697 }; 2698 #endif 2699 2700 struct type *t; 2701 2702 t = arch_composite_type (gdbarch, 2703 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); 2704 append_composite_type_field (t, "v8_float", 2705 init_vector_type (bt->builtin_float, 8)); 2706 append_composite_type_field (t, "v4_double", 2707 init_vector_type (bt->builtin_double, 4)); 2708 append_composite_type_field (t, "v32_int8", 2709 init_vector_type (bt->builtin_int8, 32)); 2710 append_composite_type_field (t, "v16_int16", 2711 init_vector_type (bt->builtin_int16, 16)); 2712 append_composite_type_field (t, "v8_int32", 2713 init_vector_type (bt->builtin_int32, 8)); 2714 append_composite_type_field (t, "v4_int64", 2715 init_vector_type (bt->builtin_int64, 4)); 2716 append_composite_type_field (t, "v2_int128", 2717 init_vector_type (bt->builtin_int128, 2)); 2718 2719 TYPE_VECTOR (t) = 1; 2720 TYPE_NAME (t) = "builtin_type_vec256i"; 2721 tdep->i386_ymm_type = t; 2722 } 2723 2724 return tdep->i386_ymm_type; 2725 } 2726 2727 /* Construct vector type for MMX registers. */ 2728 static struct type * 2729 i386_mmx_type (struct gdbarch *gdbarch) 2730 { 2731 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2732 2733 if (!tdep->i386_mmx_type) 2734 { 2735 const struct builtin_type *bt = builtin_type (gdbarch); 2736 2737 /* The type we're building is this: */ 2738 #if 0 2739 union __gdb_builtin_type_vec64i 2740 { 2741 int64_t uint64; 2742 int32_t v2_int32[2]; 2743 int16_t v4_int16[4]; 2744 int8_t v8_int8[8]; 2745 }; 2746 #endif 2747 2748 struct type *t; 2749 2750 t = arch_composite_type (gdbarch, 2751 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); 2752 2753 append_composite_type_field (t, "uint64", bt->builtin_int64); 2754 append_composite_type_field (t, "v2_int32", 2755 init_vector_type (bt->builtin_int32, 2)); 2756 append_composite_type_field (t, "v4_int16", 2757 init_vector_type (bt->builtin_int16, 4)); 2758 append_composite_type_field (t, "v8_int8", 2759 init_vector_type (bt->builtin_int8, 8)); 2760 2761 TYPE_VECTOR (t) = 1; 2762 TYPE_NAME (t) = "builtin_type_vec64i"; 2763 tdep->i386_mmx_type = t; 2764 } 2765 2766 return tdep->i386_mmx_type; 2767 } 2768 2769 /* Return the GDB type object for the "standard" data type of data in 2770 register REGNUM. */ 2771 2772 static struct type * 2773 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 2774 { 2775 if (i386_mmx_regnum_p (gdbarch, regnum)) 2776 return i386_mmx_type (gdbarch); 2777 else if (i386_ymm_regnum_p (gdbarch, regnum)) 2778 return i386_ymm_type (gdbarch); 2779 else 2780 { 2781 const struct builtin_type *bt = builtin_type (gdbarch); 2782 if (i386_byte_regnum_p (gdbarch, regnum)) 2783 return bt->builtin_int8; 2784 else if (i386_word_regnum_p (gdbarch, regnum)) 2785 return bt->builtin_int16; 2786 else if (i386_dword_regnum_p (gdbarch, regnum)) 2787 return bt->builtin_int32; 2788 } 2789 2790 internal_error (__FILE__, __LINE__, _("invalid regnum")); 2791 } 2792 2793 /* Map a cooked register onto a raw register or memory. For the i386, 2794 the MMX registers need to be mapped onto floating point registers. */ 2795 2796 static int 2797 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) 2798 { 2799 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); 2800 int mmxreg, fpreg; 2801 ULONGEST fstat; 2802 int tos; 2803 2804 mmxreg = regnum - tdep->mm0_regnum; 2805 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); 2806 tos = (fstat >> 11) & 0x7; 2807 fpreg = (mmxreg + tos) % 8; 2808 2809 return (I387_ST0_REGNUM (tdep) + fpreg); 2810 } 2811 2812 /* A helper function for us by i386_pseudo_register_read_value and 2813 amd64_pseudo_register_read_value. It does all the work but reads 2814 the data into an already-allocated value. */ 2815 2816 void 2817 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, 2818 struct regcache *regcache, 2819 int regnum, 2820 struct value *result_value) 2821 { 2822 gdb_byte raw_buf[MAX_REGISTER_SIZE]; 2823 enum register_status status; 2824 gdb_byte *buf = value_contents_raw (result_value); 2825 2826 if (i386_mmx_regnum_p (gdbarch, regnum)) 2827 { 2828 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); 2829 2830 /* Extract (always little endian). */ 2831 status = regcache_raw_read (regcache, fpnum, raw_buf); 2832 if (status != REG_VALID) 2833 mark_value_bytes_unavailable (result_value, 0, 2834 TYPE_LENGTH (value_type (result_value))); 2835 else 2836 memcpy (buf, raw_buf, register_size (gdbarch, regnum)); 2837 } 2838 else 2839 { 2840 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2841 2842 if (i386_ymm_regnum_p (gdbarch, regnum)) 2843 { 2844 regnum -= tdep->ymm0_regnum; 2845 2846 /* Extract (always little endian). Read lower 128bits. */ 2847 status = regcache_raw_read (regcache, 2848 I387_XMM0_REGNUM (tdep) + regnum, 2849 raw_buf); 2850 if (status != REG_VALID) 2851 mark_value_bytes_unavailable (result_value, 0, 16); 2852 else 2853 memcpy (buf, raw_buf, 16); 2854 /* Read upper 128bits. */ 2855 status = regcache_raw_read (regcache, 2856 tdep->ymm0h_regnum + regnum, 2857 raw_buf); 2858 if (status != REG_VALID) 2859 mark_value_bytes_unavailable (result_value, 16, 32); 2860 else 2861 memcpy (buf + 16, raw_buf, 16); 2862 } 2863 else if (i386_word_regnum_p (gdbarch, regnum)) 2864 { 2865 int gpnum = regnum - tdep->ax_regnum; 2866 2867 /* Extract (always little endian). */ 2868 status = regcache_raw_read (regcache, gpnum, raw_buf); 2869 if (status != REG_VALID) 2870 mark_value_bytes_unavailable (result_value, 0, 2871 TYPE_LENGTH (value_type (result_value))); 2872 else 2873 memcpy (buf, raw_buf, 2); 2874 } 2875 else if (i386_byte_regnum_p (gdbarch, regnum)) 2876 { 2877 /* Check byte pseudo registers last since this function will 2878 be called from amd64_pseudo_register_read, which handles 2879 byte pseudo registers differently. */ 2880 int gpnum = regnum - tdep->al_regnum; 2881 2882 /* Extract (always little endian). We read both lower and 2883 upper registers. */ 2884 status = regcache_raw_read (regcache, gpnum % 4, raw_buf); 2885 if (status != REG_VALID) 2886 mark_value_bytes_unavailable (result_value, 0, 2887 TYPE_LENGTH (value_type (result_value))); 2888 else if (gpnum >= 4) 2889 memcpy (buf, raw_buf + 1, 1); 2890 else 2891 memcpy (buf, raw_buf, 1); 2892 } 2893 else 2894 internal_error (__FILE__, __LINE__, _("invalid regnum")); 2895 } 2896 } 2897 2898 static struct value * 2899 i386_pseudo_register_read_value (struct gdbarch *gdbarch, 2900 struct regcache *regcache, 2901 int regnum) 2902 { 2903 struct value *result; 2904 2905 result = allocate_value (register_type (gdbarch, regnum)); 2906 VALUE_LVAL (result) = lval_register; 2907 VALUE_REGNUM (result) = regnum; 2908 2909 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); 2910 2911 return result; 2912 } 2913 2914 void 2915 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 2916 int regnum, const gdb_byte *buf) 2917 { 2918 gdb_byte raw_buf[MAX_REGISTER_SIZE]; 2919 2920 if (i386_mmx_regnum_p (gdbarch, regnum)) 2921 { 2922 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); 2923 2924 /* Read ... */ 2925 regcache_raw_read (regcache, fpnum, raw_buf); 2926 /* ... Modify ... (always little endian). */ 2927 memcpy (raw_buf, buf, register_size (gdbarch, regnum)); 2928 /* ... Write. */ 2929 regcache_raw_write (regcache, fpnum, raw_buf); 2930 } 2931 else 2932 { 2933 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2934 2935 if (i386_ymm_regnum_p (gdbarch, regnum)) 2936 { 2937 regnum -= tdep->ymm0_regnum; 2938 2939 /* ... Write lower 128bits. */ 2940 regcache_raw_write (regcache, 2941 I387_XMM0_REGNUM (tdep) + regnum, 2942 buf); 2943 /* ... Write upper 128bits. */ 2944 regcache_raw_write (regcache, 2945 tdep->ymm0h_regnum + regnum, 2946 buf + 16); 2947 } 2948 else if (i386_word_regnum_p (gdbarch, regnum)) 2949 { 2950 int gpnum = regnum - tdep->ax_regnum; 2951 2952 /* Read ... */ 2953 regcache_raw_read (regcache, gpnum, raw_buf); 2954 /* ... Modify ... (always little endian). */ 2955 memcpy (raw_buf, buf, 2); 2956 /* ... Write. */ 2957 regcache_raw_write (regcache, gpnum, raw_buf); 2958 } 2959 else if (i386_byte_regnum_p (gdbarch, regnum)) 2960 { 2961 /* Check byte pseudo registers last since this function will 2962 be called from amd64_pseudo_register_read, which handles 2963 byte pseudo registers differently. */ 2964 int gpnum = regnum - tdep->al_regnum; 2965 2966 /* Read ... We read both lower and upper registers. */ 2967 regcache_raw_read (regcache, gpnum % 4, raw_buf); 2968 /* ... Modify ... (always little endian). */ 2969 if (gpnum >= 4) 2970 memcpy (raw_buf + 1, buf, 1); 2971 else 2972 memcpy (raw_buf, buf, 1); 2973 /* ... Write. */ 2974 regcache_raw_write (regcache, gpnum % 4, raw_buf); 2975 } 2976 else 2977 internal_error (__FILE__, __LINE__, _("invalid regnum")); 2978 } 2979 } 2980 2981 2982 /* Return the register number of the register allocated by GCC after 2983 REGNUM, or -1 if there is no such register. */ 2984 2985 static int 2986 i386_next_regnum (int regnum) 2987 { 2988 /* GCC allocates the registers in the order: 2989 2990 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... 2991 2992 Since storing a variable in %esp doesn't make any sense we return 2993 -1 for %ebp and for %esp itself. */ 2994 static int next_regnum[] = 2995 { 2996 I386_EDX_REGNUM, /* Slot for %eax. */ 2997 I386_EBX_REGNUM, /* Slot for %ecx. */ 2998 I386_ECX_REGNUM, /* Slot for %edx. */ 2999 I386_ESI_REGNUM, /* Slot for %ebx. */ 3000 -1, -1, /* Slots for %esp and %ebp. */ 3001 I386_EDI_REGNUM, /* Slot for %esi. */ 3002 I386_EBP_REGNUM /* Slot for %edi. */ 3003 }; 3004 3005 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) 3006 return next_regnum[regnum]; 3007 3008 return -1; 3009 } 3010 3011 /* Return nonzero if a value of type TYPE stored in register REGNUM 3012 needs any special handling. */ 3013 3014 static int 3015 i386_convert_register_p (struct gdbarch *gdbarch, 3016 int regnum, struct type *type) 3017 { 3018 int len = TYPE_LENGTH (type); 3019 3020 /* Values may be spread across multiple registers. Most debugging 3021 formats aren't expressive enough to specify the locations, so 3022 some heuristics is involved. Right now we only handle types that 3023 have a length that is a multiple of the word size, since GCC 3024 doesn't seem to put any other types into registers. */ 3025 if (len > 4 && len % 4 == 0) 3026 { 3027 int last_regnum = regnum; 3028 3029 while (len > 4) 3030 { 3031 last_regnum = i386_next_regnum (last_regnum); 3032 len -= 4; 3033 } 3034 3035 if (last_regnum != -1) 3036 return 1; 3037 } 3038 3039 return i387_convert_register_p (gdbarch, regnum, type); 3040 } 3041 3042 /* Read a value of type TYPE from register REGNUM in frame FRAME, and 3043 return its contents in TO. */ 3044 3045 static int 3046 i386_register_to_value (struct frame_info *frame, int regnum, 3047 struct type *type, gdb_byte *to, 3048 int *optimizedp, int *unavailablep) 3049 { 3050 struct gdbarch *gdbarch = get_frame_arch (frame); 3051 int len = TYPE_LENGTH (type); 3052 3053 if (i386_fp_regnum_p (gdbarch, regnum)) 3054 return i387_register_to_value (frame, regnum, type, to, 3055 optimizedp, unavailablep); 3056 3057 /* Read a value spread across multiple registers. */ 3058 3059 gdb_assert (len > 4 && len % 4 == 0); 3060 3061 while (len > 0) 3062 { 3063 gdb_assert (regnum != -1); 3064 gdb_assert (register_size (gdbarch, regnum) == 4); 3065 3066 if (!get_frame_register_bytes (frame, regnum, 0, 3067 register_size (gdbarch, regnum), 3068 to, optimizedp, unavailablep)) 3069 return 0; 3070 3071 regnum = i386_next_regnum (regnum); 3072 len -= 4; 3073 to += 4; 3074 } 3075 3076 *optimizedp = *unavailablep = 0; 3077 return 1; 3078 } 3079 3080 /* Write the contents FROM of a value of type TYPE into register 3081 REGNUM in frame FRAME. */ 3082 3083 static void 3084 i386_value_to_register (struct frame_info *frame, int regnum, 3085 struct type *type, const gdb_byte *from) 3086 { 3087 int len = TYPE_LENGTH (type); 3088 3089 if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) 3090 { 3091 i387_value_to_register (frame, regnum, type, from); 3092 return; 3093 } 3094 3095 /* Write a value spread across multiple registers. */ 3096 3097 gdb_assert (len > 4 && len % 4 == 0); 3098 3099 while (len > 0) 3100 { 3101 gdb_assert (regnum != -1); 3102 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); 3103 3104 put_frame_register (frame, regnum, from); 3105 regnum = i386_next_regnum (regnum); 3106 len -= 4; 3107 from += 4; 3108 } 3109 } 3110 3111 /* Supply register REGNUM from the buffer specified by GREGS and LEN 3112 in the general-purpose register set REGSET to register cache 3113 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 3114 3115 void 3116 i386_supply_gregset (const struct regset *regset, struct regcache *regcache, 3117 int regnum, const void *gregs, size_t len) 3118 { 3119 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 3120 const gdb_byte *regs = gregs; 3121 int i; 3122 3123 gdb_assert (len == tdep->sizeof_gregset); 3124 3125 for (i = 0; i < tdep->gregset_num_regs; i++) 3126 { 3127 if ((regnum == i || regnum == -1) 3128 && tdep->gregset_reg_offset[i] != -1) 3129 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); 3130 } 3131 } 3132 3133 /* Collect register REGNUM from the register cache REGCACHE and store 3134 it in the buffer specified by GREGS and LEN as described by the 3135 general-purpose register set REGSET. If REGNUM is -1, do this for 3136 all registers in REGSET. */ 3137 3138 void 3139 i386_collect_gregset (const struct regset *regset, 3140 const struct regcache *regcache, 3141 int regnum, void *gregs, size_t len) 3142 { 3143 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 3144 gdb_byte *regs = gregs; 3145 int i; 3146 3147 gdb_assert (len == tdep->sizeof_gregset); 3148 3149 for (i = 0; i < tdep->gregset_num_regs; i++) 3150 { 3151 if ((regnum == i || regnum == -1) 3152 && tdep->gregset_reg_offset[i] != -1) 3153 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); 3154 } 3155 } 3156 3157 /* Supply register REGNUM from the buffer specified by FPREGS and LEN 3158 in the floating-point register set REGSET to register cache 3159 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 3160 3161 static void 3162 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, 3163 int regnum, const void *fpregs, size_t len) 3164 { 3165 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 3166 3167 if (len == I387_SIZEOF_FXSAVE) 3168 { 3169 i387_supply_fxsave (regcache, regnum, fpregs); 3170 return; 3171 } 3172 3173 gdb_assert (len == tdep->sizeof_fpregset); 3174 i387_supply_fsave (regcache, regnum, fpregs); 3175 } 3176 3177 /* Collect register REGNUM from the register cache REGCACHE and store 3178 it in the buffer specified by FPREGS and LEN as described by the 3179 floating-point register set REGSET. If REGNUM is -1, do this for 3180 all registers in REGSET. */ 3181 3182 static void 3183 i386_collect_fpregset (const struct regset *regset, 3184 const struct regcache *regcache, 3185 int regnum, void *fpregs, size_t len) 3186 { 3187 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 3188 3189 if (len == I387_SIZEOF_FXSAVE) 3190 { 3191 i387_collect_fxsave (regcache, regnum, fpregs); 3192 return; 3193 } 3194 3195 gdb_assert (len == tdep->sizeof_fpregset); 3196 i387_collect_fsave (regcache, regnum, fpregs); 3197 } 3198 3199 /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ 3200 3201 static void 3202 i386_supply_xstateregset (const struct regset *regset, 3203 struct regcache *regcache, int regnum, 3204 const void *xstateregs, size_t len) 3205 { 3206 i387_supply_xsave (regcache, regnum, xstateregs); 3207 } 3208 3209 /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ 3210 3211 static void 3212 i386_collect_xstateregset (const struct regset *regset, 3213 const struct regcache *regcache, 3214 int regnum, void *xstateregs, size_t len) 3215 { 3216 i387_collect_xsave (regcache, regnum, xstateregs, 1); 3217 } 3218 3219 /* Return the appropriate register set for the core section identified 3220 by SECT_NAME and SECT_SIZE. */ 3221 3222 const struct regset * 3223 i386_regset_from_core_section (struct gdbarch *gdbarch, 3224 const char *sect_name, size_t sect_size) 3225 { 3226 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3227 3228 if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) 3229 { 3230 if (tdep->gregset == NULL) 3231 tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, 3232 i386_collect_gregset); 3233 return tdep->gregset; 3234 } 3235 3236 if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) 3237 || (strcmp (sect_name, ".reg-xfp") == 0 3238 && sect_size == I387_SIZEOF_FXSAVE)) 3239 { 3240 if (tdep->fpregset == NULL) 3241 tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, 3242 i386_collect_fpregset); 3243 return tdep->fpregset; 3244 } 3245 3246 if (strcmp (sect_name, ".reg-xstate") == 0) 3247 { 3248 if (tdep->xstateregset == NULL) 3249 tdep->xstateregset = regset_alloc (gdbarch, 3250 i386_supply_xstateregset, 3251 i386_collect_xstateregset); 3252 3253 return tdep->xstateregset; 3254 } 3255 3256 return NULL; 3257 } 3258 3259 3260 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ 3261 3262 CORE_ADDR 3263 i386_pe_skip_trampoline_code (struct frame_info *frame, 3264 CORE_ADDR pc, char *name) 3265 { 3266 struct gdbarch *gdbarch = get_frame_arch (frame); 3267 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 3268 3269 /* jmp *(dest) */ 3270 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) 3271 { 3272 unsigned long indirect = 3273 read_memory_unsigned_integer (pc + 2, 4, byte_order); 3274 struct minimal_symbol *indsym = 3275 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; 3276 char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; 3277 3278 if (symname) 3279 { 3280 if (strncmp (symname, "__imp_", 6) == 0 3281 || strncmp (symname, "_imp_", 5) == 0) 3282 return name ? 1 : 3283 read_memory_unsigned_integer (indirect, 4, byte_order); 3284 } 3285 } 3286 return 0; /* Not a trampoline. */ 3287 } 3288 3289 3290 /* Return whether the THIS_FRAME corresponds to a sigtramp 3291 routine. */ 3292 3293 int 3294 i386_sigtramp_p (struct frame_info *this_frame) 3295 { 3296 CORE_ADDR pc = get_frame_pc (this_frame); 3297 char *name; 3298 3299 find_pc_partial_function (pc, &name, NULL, NULL); 3300 return (name && strcmp ("_sigtramp", name) == 0); 3301 } 3302 3303 3304 /* We have two flavours of disassembly. The machinery on this page 3305 deals with switching between those. */ 3306 3307 static int 3308 i386_print_insn (bfd_vma pc, struct disassemble_info *info) 3309 { 3310 gdb_assert (disassembly_flavor == att_flavor 3311 || disassembly_flavor == intel_flavor); 3312 3313 /* FIXME: kettenis/20020915: Until disassembler_options is properly 3314 constified, cast to prevent a compiler warning. */ 3315 info->disassembler_options = (char *) disassembly_flavor; 3316 3317 return print_insn_i386 (pc, info); 3318 } 3319 3320 3321 /* There are a few i386 architecture variants that differ only 3322 slightly from the generic i386 target. For now, we don't give them 3323 their own source file, but include them here. As a consequence, 3324 they'll always be included. */ 3325 3326 /* System V Release 4 (SVR4). */ 3327 3328 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp 3329 routine. */ 3330 3331 static int 3332 i386_svr4_sigtramp_p (struct frame_info *this_frame) 3333 { 3334 CORE_ADDR pc = get_frame_pc (this_frame); 3335 char *name; 3336 3337 /* UnixWare uses _sigacthandler. The origin of the other symbols is 3338 currently unknown. */ 3339 find_pc_partial_function (pc, &name, NULL, NULL); 3340 return (name && (strcmp ("_sigreturn", name) == 0 3341 || strcmp ("_sigacthandler", name) == 0 3342 || strcmp ("sigvechandler", name) == 0)); 3343 } 3344 3345 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the 3346 address of the associated sigcontext (ucontext) structure. */ 3347 3348 static CORE_ADDR 3349 i386_svr4_sigcontext_addr (struct frame_info *this_frame) 3350 { 3351 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3352 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 3353 gdb_byte buf[4]; 3354 CORE_ADDR sp; 3355 3356 get_frame_register (this_frame, I386_ESP_REGNUM, buf); 3357 sp = extract_unsigned_integer (buf, 4, byte_order); 3358 3359 return read_memory_unsigned_integer (sp + 8, 4, byte_order); 3360 } 3361 3362 3363 /* Generic ELF. */ 3364 3365 void 3366 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 3367 { 3368 /* We typically use stabs-in-ELF with the SVR4 register numbering. */ 3369 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); 3370 } 3371 3372 /* System V Release 4 (SVR4). */ 3373 3374 void 3375 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 3376 { 3377 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3378 3379 /* System V Release 4 uses ELF. */ 3380 i386_elf_init_abi (info, gdbarch); 3381 3382 /* System V Release 4 has shared libraries. */ 3383 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); 3384 3385 tdep->sigtramp_p = i386_svr4_sigtramp_p; 3386 tdep->sigcontext_addr = i386_svr4_sigcontext_addr; 3387 tdep->sc_pc_offset = 36 + 14 * 4; 3388 tdep->sc_sp_offset = 36 + 17 * 4; 3389 3390 tdep->jb_pc_offset = 20; 3391 } 3392 3393 /* DJGPP. */ 3394 3395 static void 3396 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 3397 { 3398 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3399 3400 /* DJGPP doesn't have any special frames for signal handlers. */ 3401 tdep->sigtramp_p = NULL; 3402 3403 tdep->jb_pc_offset = 36; 3404 3405 /* DJGPP does not support the SSE registers. */ 3406 if (! tdesc_has_registers (info.target_desc)) 3407 tdep->tdesc = tdesc_i386_mmx; 3408 3409 /* Native compiler is GCC, which uses the SVR4 register numbering 3410 even in COFF and STABS. See the comment in i386_gdbarch_init, 3411 before the calls to set_gdbarch_stab_reg_to_regnum and 3412 set_gdbarch_sdb_reg_to_regnum. */ 3413 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); 3414 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); 3415 3416 set_gdbarch_has_dos_based_file_system (gdbarch, 1); 3417 } 3418 3419 3420 /* i386 register groups. In addition to the normal groups, add "mmx" 3421 and "sse". */ 3422 3423 static struct reggroup *i386_sse_reggroup; 3424 static struct reggroup *i386_mmx_reggroup; 3425 3426 static void 3427 i386_init_reggroups (void) 3428 { 3429 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); 3430 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); 3431 } 3432 3433 static void 3434 i386_add_reggroups (struct gdbarch *gdbarch) 3435 { 3436 reggroup_add (gdbarch, i386_sse_reggroup); 3437 reggroup_add (gdbarch, i386_mmx_reggroup); 3438 reggroup_add (gdbarch, general_reggroup); 3439 reggroup_add (gdbarch, float_reggroup); 3440 reggroup_add (gdbarch, all_reggroup); 3441 reggroup_add (gdbarch, save_reggroup); 3442 reggroup_add (gdbarch, restore_reggroup); 3443 reggroup_add (gdbarch, vector_reggroup); 3444 reggroup_add (gdbarch, system_reggroup); 3445 } 3446 3447 int 3448 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 3449 struct reggroup *group) 3450 { 3451 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3452 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, 3453 ymm_regnum_p, ymmh_regnum_p; 3454 3455 /* Don't include pseudo registers, except for MMX, in any register 3456 groups. */ 3457 if (i386_byte_regnum_p (gdbarch, regnum)) 3458 return 0; 3459 3460 if (i386_word_regnum_p (gdbarch, regnum)) 3461 return 0; 3462 3463 if (i386_dword_regnum_p (gdbarch, regnum)) 3464 return 0; 3465 3466 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); 3467 if (group == i386_mmx_reggroup) 3468 return mmx_regnum_p; 3469 3470 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); 3471 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); 3472 if (group == i386_sse_reggroup) 3473 return xmm_regnum_p || mxcsr_regnum_p; 3474 3475 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); 3476 if (group == vector_reggroup) 3477 return (mmx_regnum_p 3478 || ymm_regnum_p 3479 || mxcsr_regnum_p 3480 || (xmm_regnum_p 3481 && ((tdep->xcr0 & I386_XSTATE_AVX_MASK) 3482 == I386_XSTATE_SSE_MASK))); 3483 3484 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) 3485 || i386_fpc_regnum_p (gdbarch, regnum)); 3486 if (group == float_reggroup) 3487 return fp_regnum_p; 3488 3489 /* For "info reg all", don't include upper YMM registers nor XMM 3490 registers when AVX is supported. */ 3491 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); 3492 if (group == all_reggroup 3493 && ((xmm_regnum_p 3494 && (tdep->xcr0 & I386_XSTATE_AVX)) 3495 || ymmh_regnum_p)) 3496 return 0; 3497 3498 if (group == general_reggroup) 3499 return (!fp_regnum_p 3500 && !mmx_regnum_p 3501 && !mxcsr_regnum_p 3502 && !xmm_regnum_p 3503 && !ymm_regnum_p 3504 && !ymmh_regnum_p); 3505 3506 return default_register_reggroup_p (gdbarch, regnum, group); 3507 } 3508 3509 3510 /* Get the ARGIth function argument for the current function. */ 3511 3512 static CORE_ADDR 3513 i386_fetch_pointer_argument (struct frame_info *frame, int argi, 3514 struct type *type) 3515 { 3516 struct gdbarch *gdbarch = get_frame_arch (frame); 3517 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 3518 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); 3519 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); 3520 } 3521 3522 static void 3523 i386_skip_permanent_breakpoint (struct regcache *regcache) 3524 { 3525 CORE_ADDR current_pc = regcache_read_pc (regcache); 3526 3527 /* On i386, breakpoint is exactly 1 byte long, so we just 3528 adjust the PC in the regcache. */ 3529 current_pc += 1; 3530 regcache_write_pc (regcache, current_pc); 3531 } 3532 3533 3534 #define PREFIX_REPZ 0x01 3535 #define PREFIX_REPNZ 0x02 3536 #define PREFIX_LOCK 0x04 3537 #define PREFIX_DATA 0x08 3538 #define PREFIX_ADDR 0x10 3539 3540 /* operand size */ 3541 enum 3542 { 3543 OT_BYTE = 0, 3544 OT_WORD, 3545 OT_LONG, 3546 OT_QUAD, 3547 OT_DQUAD, 3548 }; 3549 3550 /* i386 arith/logic operations */ 3551 enum 3552 { 3553 OP_ADDL, 3554 OP_ORL, 3555 OP_ADCL, 3556 OP_SBBL, 3557 OP_ANDL, 3558 OP_SUBL, 3559 OP_XORL, 3560 OP_CMPL, 3561 }; 3562 3563 struct i386_record_s 3564 { 3565 struct gdbarch *gdbarch; 3566 struct regcache *regcache; 3567 CORE_ADDR orig_addr; 3568 CORE_ADDR addr; 3569 int aflag; 3570 int dflag; 3571 int override; 3572 uint8_t modrm; 3573 uint8_t mod, reg, rm; 3574 int ot; 3575 uint8_t rex_x; 3576 uint8_t rex_b; 3577 int rip_offset; 3578 int popl_esp_hack; 3579 const int *regmap; 3580 }; 3581 3582 /* Parse "modrm" part in current memory address that irp->addr point to 3583 Return -1 if something wrong. */ 3584 3585 static int 3586 i386_record_modrm (struct i386_record_s *irp) 3587 { 3588 struct gdbarch *gdbarch = irp->gdbarch; 3589 3590 if (target_read_memory (irp->addr, &irp->modrm, 1)) 3591 { 3592 if (record_debug) 3593 printf_unfiltered (_("Process record: error reading memory at " 3594 "addr %s len = 1.\n"), 3595 paddress (gdbarch, irp->addr)); 3596 return -1; 3597 } 3598 irp->addr++; 3599 irp->mod = (irp->modrm >> 6) & 3; 3600 irp->reg = (irp->modrm >> 3) & 7; 3601 irp->rm = irp->modrm & 7; 3602 3603 return 0; 3604 } 3605 3606 /* Get the memory address that current instruction write to and set it to 3607 the argument "addr". 3608 Return -1 if something wrong. */ 3609 3610 static int 3611 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) 3612 { 3613 struct gdbarch *gdbarch = irp->gdbarch; 3614 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 3615 gdb_byte buf[4]; 3616 ULONGEST offset64; 3617 3618 *addr = 0; 3619 if (irp->aflag) 3620 { 3621 /* 32 bits */ 3622 int havesib = 0; 3623 uint8_t scale = 0; 3624 uint8_t byte; 3625 uint8_t index = 0; 3626 uint8_t base = irp->rm; 3627 3628 if (base == 4) 3629 { 3630 havesib = 1; 3631 if (target_read_memory (irp->addr, &byte, 1)) 3632 { 3633 if (record_debug) 3634 printf_unfiltered (_("Process record: error reading memory " 3635 "at addr %s len = 1.\n"), 3636 paddress (gdbarch, irp->addr)); 3637 return -1; 3638 } 3639 irp->addr++; 3640 scale = (byte >> 6) & 3; 3641 index = ((byte >> 3) & 7) | irp->rex_x; 3642 base = (byte & 7); 3643 } 3644 base |= irp->rex_b; 3645 3646 switch (irp->mod) 3647 { 3648 case 0: 3649 if ((base & 7) == 5) 3650 { 3651 base = 0xff; 3652 if (target_read_memory (irp->addr, buf, 4)) 3653 { 3654 if (record_debug) 3655 printf_unfiltered (_("Process record: error reading " 3656 "memory at addr %s len = 4.\n"), 3657 paddress (gdbarch, irp->addr)); 3658 return -1; 3659 } 3660 irp->addr += 4; 3661 *addr = extract_signed_integer (buf, 4, byte_order); 3662 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) 3663 *addr += irp->addr + irp->rip_offset; 3664 } 3665 break; 3666 case 1: 3667 if (target_read_memory (irp->addr, buf, 1)) 3668 { 3669 if (record_debug) 3670 printf_unfiltered (_("Process record: error reading memory " 3671 "at addr %s len = 1.\n"), 3672 paddress (gdbarch, irp->addr)); 3673 return -1; 3674 } 3675 irp->addr++; 3676 *addr = (int8_t) buf[0]; 3677 break; 3678 case 2: 3679 if (target_read_memory (irp->addr, buf, 4)) 3680 { 3681 if (record_debug) 3682 printf_unfiltered (_("Process record: error reading memory " 3683 "at addr %s len = 4.\n"), 3684 paddress (gdbarch, irp->addr)); 3685 return -1; 3686 } 3687 *addr = extract_signed_integer (buf, 4, byte_order); 3688 irp->addr += 4; 3689 break; 3690 } 3691 3692 offset64 = 0; 3693 if (base != 0xff) 3694 { 3695 if (base == 4 && irp->popl_esp_hack) 3696 *addr += irp->popl_esp_hack; 3697 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], 3698 &offset64); 3699 } 3700 if (irp->aflag == 2) 3701 { 3702 *addr += offset64; 3703 } 3704 else 3705 *addr = (uint32_t) (offset64 + *addr); 3706 3707 if (havesib && (index != 4 || scale != 0)) 3708 { 3709 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], 3710 &offset64); 3711 if (irp->aflag == 2) 3712 *addr += offset64 << scale; 3713 else 3714 *addr = (uint32_t) (*addr + (offset64 << scale)); 3715 } 3716 } 3717 else 3718 { 3719 /* 16 bits */ 3720 switch (irp->mod) 3721 { 3722 case 0: 3723 if (irp->rm == 6) 3724 { 3725 if (target_read_memory (irp->addr, buf, 2)) 3726 { 3727 if (record_debug) 3728 printf_unfiltered (_("Process record: error reading " 3729 "memory at addr %s len = 2.\n"), 3730 paddress (gdbarch, irp->addr)); 3731 return -1; 3732 } 3733 irp->addr += 2; 3734 *addr = extract_signed_integer (buf, 2, byte_order); 3735 irp->rm = 0; 3736 goto no_rm; 3737 } 3738 break; 3739 case 1: 3740 if (target_read_memory (irp->addr, buf, 1)) 3741 { 3742 if (record_debug) 3743 printf_unfiltered (_("Process record: error reading memory " 3744 "at addr %s len = 1.\n"), 3745 paddress (gdbarch, irp->addr)); 3746 return -1; 3747 } 3748 irp->addr++; 3749 *addr = (int8_t) buf[0]; 3750 break; 3751 case 2: 3752 if (target_read_memory (irp->addr, buf, 2)) 3753 { 3754 if (record_debug) 3755 printf_unfiltered (_("Process record: error reading memory " 3756 "at addr %s len = 2.\n"), 3757 paddress (gdbarch, irp->addr)); 3758 return -1; 3759 } 3760 irp->addr += 2; 3761 *addr = extract_signed_integer (buf, 2, byte_order); 3762 break; 3763 } 3764 3765 switch (irp->rm) 3766 { 3767 case 0: 3768 regcache_raw_read_unsigned (irp->regcache, 3769 irp->regmap[X86_RECORD_REBX_REGNUM], 3770 &offset64); 3771 *addr = (uint32_t) (*addr + offset64); 3772 regcache_raw_read_unsigned (irp->regcache, 3773 irp->regmap[X86_RECORD_RESI_REGNUM], 3774 &offset64); 3775 *addr = (uint32_t) (*addr + offset64); 3776 break; 3777 case 1: 3778 regcache_raw_read_unsigned (irp->regcache, 3779 irp->regmap[X86_RECORD_REBX_REGNUM], 3780 &offset64); 3781 *addr = (uint32_t) (*addr + offset64); 3782 regcache_raw_read_unsigned (irp->regcache, 3783 irp->regmap[X86_RECORD_REDI_REGNUM], 3784 &offset64); 3785 *addr = (uint32_t) (*addr + offset64); 3786 break; 3787 case 2: 3788 regcache_raw_read_unsigned (irp->regcache, 3789 irp->regmap[X86_RECORD_REBP_REGNUM], 3790 &offset64); 3791 *addr = (uint32_t) (*addr + offset64); 3792 regcache_raw_read_unsigned (irp->regcache, 3793 irp->regmap[X86_RECORD_RESI_REGNUM], 3794 &offset64); 3795 *addr = (uint32_t) (*addr + offset64); 3796 break; 3797 case 3: 3798 regcache_raw_read_unsigned (irp->regcache, 3799 irp->regmap[X86_RECORD_REBP_REGNUM], 3800 &offset64); 3801 *addr = (uint32_t) (*addr + offset64); 3802 regcache_raw_read_unsigned (irp->regcache, 3803 irp->regmap[X86_RECORD_REDI_REGNUM], 3804 &offset64); 3805 *addr = (uint32_t) (*addr + offset64); 3806 break; 3807 case 4: 3808 regcache_raw_read_unsigned (irp->regcache, 3809 irp->regmap[X86_RECORD_RESI_REGNUM], 3810 &offset64); 3811 *addr = (uint32_t) (*addr + offset64); 3812 break; 3813 case 5: 3814 regcache_raw_read_unsigned (irp->regcache, 3815 irp->regmap[X86_RECORD_REDI_REGNUM], 3816 &offset64); 3817 *addr = (uint32_t) (*addr + offset64); 3818 break; 3819 case 6: 3820 regcache_raw_read_unsigned (irp->regcache, 3821 irp->regmap[X86_RECORD_REBP_REGNUM], 3822 &offset64); 3823 *addr = (uint32_t) (*addr + offset64); 3824 break; 3825 case 7: 3826 regcache_raw_read_unsigned (irp->regcache, 3827 irp->regmap[X86_RECORD_REBX_REGNUM], 3828 &offset64); 3829 *addr = (uint32_t) (*addr + offset64); 3830 break; 3831 } 3832 *addr &= 0xffff; 3833 } 3834 3835 no_rm: 3836 return 0; 3837 } 3838 3839 /* Record the value of the memory that willbe changed in current instruction 3840 to "record_arch_list". 3841 Return -1 if something wrong. */ 3842 3843 static int 3844 i386_record_lea_modrm (struct i386_record_s *irp) 3845 { 3846 struct gdbarch *gdbarch = irp->gdbarch; 3847 uint64_t addr; 3848 3849 if (irp->override >= 0) 3850 { 3851 if (record_memory_query) 3852 { 3853 int q; 3854 3855 target_terminal_ours (); 3856 q = yquery (_("\ 3857 Process record ignores the memory change of instruction at address %s\n\ 3858 because it can't get the value of the segment register.\n\ 3859 Do you want to stop the program?"), 3860 paddress (gdbarch, irp->orig_addr)); 3861 target_terminal_inferior (); 3862 if (q) 3863 return -1; 3864 } 3865 3866 return 0; 3867 } 3868 3869 if (i386_record_lea_modrm_addr (irp, &addr)) 3870 return -1; 3871 3872 if (record_arch_list_add_mem (addr, 1 << irp->ot)) 3873 return -1; 3874 3875 return 0; 3876 } 3877 3878 /* Record the push operation to "record_arch_list". 3879 Return -1 if something wrong. */ 3880 3881 static int 3882 i386_record_push (struct i386_record_s *irp, int size) 3883 { 3884 ULONGEST addr; 3885 3886 if (record_arch_list_add_reg (irp->regcache, 3887 irp->regmap[X86_RECORD_RESP_REGNUM])) 3888 return -1; 3889 regcache_raw_read_unsigned (irp->regcache, 3890 irp->regmap[X86_RECORD_RESP_REGNUM], 3891 &addr); 3892 if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size)) 3893 return -1; 3894 3895 return 0; 3896 } 3897 3898 3899 /* Defines contents to record. */ 3900 #define I386_SAVE_FPU_REGS 0xfffd 3901 #define I386_SAVE_FPU_ENV 0xfffe 3902 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff 3903 3904 /* Record the value of floating point registers which will be changed 3905 by the current instruction to "record_arch_list". Return -1 if 3906 something is wrong. */ 3907 3908 static int i386_record_floats (struct gdbarch *gdbarch, 3909 struct i386_record_s *ir, 3910 uint32_t iregnum) 3911 { 3912 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3913 int i; 3914 3915 /* Oza: Because of floating point insn push/pop of fpu stack is going to 3916 happen. Currently we store st0-st7 registers, but we need not store all 3917 registers all the time, in future we use ftag register and record only 3918 those who are not marked as an empty. */ 3919 3920 if (I386_SAVE_FPU_REGS == iregnum) 3921 { 3922 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) 3923 { 3924 if (record_arch_list_add_reg (ir->regcache, i)) 3925 return -1; 3926 } 3927 } 3928 else if (I386_SAVE_FPU_ENV == iregnum) 3929 { 3930 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) 3931 { 3932 if (record_arch_list_add_reg (ir->regcache, i)) 3933 return -1; 3934 } 3935 } 3936 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) 3937 { 3938 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) 3939 { 3940 if (record_arch_list_add_reg (ir->regcache, i)) 3941 return -1; 3942 } 3943 } 3944 else if ((iregnum >= I387_ST0_REGNUM (tdep)) && 3945 (iregnum <= I387_FOP_REGNUM (tdep))) 3946 { 3947 if (record_arch_list_add_reg (ir->regcache,iregnum)) 3948 return -1; 3949 } 3950 else 3951 { 3952 /* Parameter error. */ 3953 return -1; 3954 } 3955 if(I386_SAVE_FPU_ENV != iregnum) 3956 { 3957 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) 3958 { 3959 if (record_arch_list_add_reg (ir->regcache, i)) 3960 return -1; 3961 } 3962 } 3963 return 0; 3964 } 3965 3966 /* Parse the current instruction and record the values of the registers and 3967 memory that will be changed in current instruction to "record_arch_list". 3968 Return -1 if something wrong. */ 3969 3970 #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ 3971 record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) 3972 3973 int 3974 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, 3975 CORE_ADDR input_addr) 3976 { 3977 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 3978 int prefixes = 0; 3979 int regnum = 0; 3980 uint32_t opcode; 3981 uint8_t opcode8; 3982 ULONGEST addr; 3983 gdb_byte buf[MAX_REGISTER_SIZE]; 3984 struct i386_record_s ir; 3985 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3986 int rex = 0; 3987 uint8_t rex_w = -1; 3988 uint8_t rex_r = 0; 3989 3990 memset (&ir, 0, sizeof (struct i386_record_s)); 3991 ir.regcache = regcache; 3992 ir.addr = input_addr; 3993 ir.orig_addr = input_addr; 3994 ir.aflag = 1; 3995 ir.dflag = 1; 3996 ir.override = -1; 3997 ir.popl_esp_hack = 0; 3998 ir.regmap = tdep->record_regmap; 3999 ir.gdbarch = gdbarch; 4000 4001 if (record_debug > 1) 4002 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " 4003 "addr = %s\n", 4004 paddress (gdbarch, ir.addr)); 4005 4006 /* prefixes */ 4007 while (1) 4008 { 4009 if (target_read_memory (ir.addr, &opcode8, 1)) 4010 { 4011 if (record_debug) 4012 printf_unfiltered (_("Process record: error reading memory at " 4013 "addr %s len = 1.\n"), 4014 paddress (gdbarch, ir.addr)); 4015 return -1; 4016 } 4017 ir.addr++; 4018 switch (opcode8) /* Instruction prefixes */ 4019 { 4020 case REPE_PREFIX_OPCODE: 4021 prefixes |= PREFIX_REPZ; 4022 break; 4023 case REPNE_PREFIX_OPCODE: 4024 prefixes |= PREFIX_REPNZ; 4025 break; 4026 case LOCK_PREFIX_OPCODE: 4027 prefixes |= PREFIX_LOCK; 4028 break; 4029 case CS_PREFIX_OPCODE: 4030 ir.override = X86_RECORD_CS_REGNUM; 4031 break; 4032 case SS_PREFIX_OPCODE: 4033 ir.override = X86_RECORD_SS_REGNUM; 4034 break; 4035 case DS_PREFIX_OPCODE: 4036 ir.override = X86_RECORD_DS_REGNUM; 4037 break; 4038 case ES_PREFIX_OPCODE: 4039 ir.override = X86_RECORD_ES_REGNUM; 4040 break; 4041 case FS_PREFIX_OPCODE: 4042 ir.override = X86_RECORD_FS_REGNUM; 4043 break; 4044 case GS_PREFIX_OPCODE: 4045 ir.override = X86_RECORD_GS_REGNUM; 4046 break; 4047 case DATA_PREFIX_OPCODE: 4048 prefixes |= PREFIX_DATA; 4049 break; 4050 case ADDR_PREFIX_OPCODE: 4051 prefixes |= PREFIX_ADDR; 4052 break; 4053 case 0x40: /* i386 inc %eax */ 4054 case 0x41: /* i386 inc %ecx */ 4055 case 0x42: /* i386 inc %edx */ 4056 case 0x43: /* i386 inc %ebx */ 4057 case 0x44: /* i386 inc %esp */ 4058 case 0x45: /* i386 inc %ebp */ 4059 case 0x46: /* i386 inc %esi */ 4060 case 0x47: /* i386 inc %edi */ 4061 case 0x48: /* i386 dec %eax */ 4062 case 0x49: /* i386 dec %ecx */ 4063 case 0x4a: /* i386 dec %edx */ 4064 case 0x4b: /* i386 dec %ebx */ 4065 case 0x4c: /* i386 dec %esp */ 4066 case 0x4d: /* i386 dec %ebp */ 4067 case 0x4e: /* i386 dec %esi */ 4068 case 0x4f: /* i386 dec %edi */ 4069 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ 4070 { 4071 /* REX */ 4072 rex = 1; 4073 rex_w = (opcode8 >> 3) & 1; 4074 rex_r = (opcode8 & 0x4) << 1; 4075 ir.rex_x = (opcode8 & 0x2) << 2; 4076 ir.rex_b = (opcode8 & 0x1) << 3; 4077 } 4078 else /* 32 bit target */ 4079 goto out_prefixes; 4080 break; 4081 default: 4082 goto out_prefixes; 4083 break; 4084 } 4085 } 4086 out_prefixes: 4087 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) 4088 { 4089 ir.dflag = 2; 4090 } 4091 else 4092 { 4093 if (prefixes & PREFIX_DATA) 4094 ir.dflag ^= 1; 4095 } 4096 if (prefixes & PREFIX_ADDR) 4097 ir.aflag ^= 1; 4098 else if (ir.regmap[X86_RECORD_R8_REGNUM]) 4099 ir.aflag = 2; 4100 4101 /* Now check op code. */ 4102 opcode = (uint32_t) opcode8; 4103 reswitch: 4104 switch (opcode) 4105 { 4106 case 0x0f: 4107 if (target_read_memory (ir.addr, &opcode8, 1)) 4108 { 4109 if (record_debug) 4110 printf_unfiltered (_("Process record: error reading memory at " 4111 "addr %s len = 1.\n"), 4112 paddress (gdbarch, ir.addr)); 4113 return -1; 4114 } 4115 ir.addr++; 4116 opcode = (uint32_t) opcode8 | 0x0f00; 4117 goto reswitch; 4118 break; 4119 4120 case 0x00: /* arith & logic */ 4121 case 0x01: 4122 case 0x02: 4123 case 0x03: 4124 case 0x04: 4125 case 0x05: 4126 case 0x08: 4127 case 0x09: 4128 case 0x0a: 4129 case 0x0b: 4130 case 0x0c: 4131 case 0x0d: 4132 case 0x10: 4133 case 0x11: 4134 case 0x12: 4135 case 0x13: 4136 case 0x14: 4137 case 0x15: 4138 case 0x18: 4139 case 0x19: 4140 case 0x1a: 4141 case 0x1b: 4142 case 0x1c: 4143 case 0x1d: 4144 case 0x20: 4145 case 0x21: 4146 case 0x22: 4147 case 0x23: 4148 case 0x24: 4149 case 0x25: 4150 case 0x28: 4151 case 0x29: 4152 case 0x2a: 4153 case 0x2b: 4154 case 0x2c: 4155 case 0x2d: 4156 case 0x30: 4157 case 0x31: 4158 case 0x32: 4159 case 0x33: 4160 case 0x34: 4161 case 0x35: 4162 case 0x38: 4163 case 0x39: 4164 case 0x3a: 4165 case 0x3b: 4166 case 0x3c: 4167 case 0x3d: 4168 if (((opcode >> 3) & 7) != OP_CMPL) 4169 { 4170 if ((opcode & 1) == 0) 4171 ir.ot = OT_BYTE; 4172 else 4173 ir.ot = ir.dflag + OT_WORD; 4174 4175 switch ((opcode >> 1) & 3) 4176 { 4177 case 0: /* OP Ev, Gv */ 4178 if (i386_record_modrm (&ir)) 4179 return -1; 4180 if (ir.mod != 3) 4181 { 4182 if (i386_record_lea_modrm (&ir)) 4183 return -1; 4184 } 4185 else 4186 { 4187 ir.rm |= ir.rex_b; 4188 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4189 ir.rm &= 0x3; 4190 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 4191 } 4192 break; 4193 case 1: /* OP Gv, Ev */ 4194 if (i386_record_modrm (&ir)) 4195 return -1; 4196 ir.reg |= rex_r; 4197 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4198 ir.reg &= 0x3; 4199 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4200 break; 4201 case 2: /* OP A, Iv */ 4202 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4203 break; 4204 } 4205 } 4206 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4207 break; 4208 4209 case 0x80: /* GRP1 */ 4210 case 0x81: 4211 case 0x82: 4212 case 0x83: 4213 if (i386_record_modrm (&ir)) 4214 return -1; 4215 4216 if (ir.reg != OP_CMPL) 4217 { 4218 if ((opcode & 1) == 0) 4219 ir.ot = OT_BYTE; 4220 else 4221 ir.ot = ir.dflag + OT_WORD; 4222 4223 if (ir.mod != 3) 4224 { 4225 if (opcode == 0x83) 4226 ir.rip_offset = 1; 4227 else 4228 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 4229 if (i386_record_lea_modrm (&ir)) 4230 return -1; 4231 } 4232 else 4233 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 4234 } 4235 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4236 break; 4237 4238 case 0x40: /* inc */ 4239 case 0x41: 4240 case 0x42: 4241 case 0x43: 4242 case 0x44: 4243 case 0x45: 4244 case 0x46: 4245 case 0x47: 4246 4247 case 0x48: /* dec */ 4248 case 0x49: 4249 case 0x4a: 4250 case 0x4b: 4251 case 0x4c: 4252 case 0x4d: 4253 case 0x4e: 4254 case 0x4f: 4255 4256 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); 4257 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4258 break; 4259 4260 case 0xf6: /* GRP3 */ 4261 case 0xf7: 4262 if ((opcode & 1) == 0) 4263 ir.ot = OT_BYTE; 4264 else 4265 ir.ot = ir.dflag + OT_WORD; 4266 if (i386_record_modrm (&ir)) 4267 return -1; 4268 4269 if (ir.mod != 3 && ir.reg == 0) 4270 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 4271 4272 switch (ir.reg) 4273 { 4274 case 0: /* test */ 4275 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4276 break; 4277 case 2: /* not */ 4278 case 3: /* neg */ 4279 if (ir.mod != 3) 4280 { 4281 if (i386_record_lea_modrm (&ir)) 4282 return -1; 4283 } 4284 else 4285 { 4286 ir.rm |= ir.rex_b; 4287 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4288 ir.rm &= 0x3; 4289 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 4290 } 4291 if (ir.reg == 3) /* neg */ 4292 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4293 break; 4294 case 4: /* mul */ 4295 case 5: /* imul */ 4296 case 6: /* div */ 4297 case 7: /* idiv */ 4298 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4299 if (ir.ot != OT_BYTE) 4300 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 4301 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4302 break; 4303 default: 4304 ir.addr -= 2; 4305 opcode = opcode << 8 | ir.modrm; 4306 goto no_support; 4307 break; 4308 } 4309 break; 4310 4311 case 0xfe: /* GRP4 */ 4312 case 0xff: /* GRP5 */ 4313 if (i386_record_modrm (&ir)) 4314 return -1; 4315 if (ir.reg >= 2 && opcode == 0xfe) 4316 { 4317 ir.addr -= 2; 4318 opcode = opcode << 8 | ir.modrm; 4319 goto no_support; 4320 } 4321 switch (ir.reg) 4322 { 4323 case 0: /* inc */ 4324 case 1: /* dec */ 4325 if ((opcode & 1) == 0) 4326 ir.ot = OT_BYTE; 4327 else 4328 ir.ot = ir.dflag + OT_WORD; 4329 if (ir.mod != 3) 4330 { 4331 if (i386_record_lea_modrm (&ir)) 4332 return -1; 4333 } 4334 else 4335 { 4336 ir.rm |= ir.rex_b; 4337 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4338 ir.rm &= 0x3; 4339 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 4340 } 4341 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4342 break; 4343 case 2: /* call */ 4344 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 4345 ir.dflag = 2; 4346 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4347 return -1; 4348 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4349 break; 4350 case 3: /* lcall */ 4351 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); 4352 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4353 return -1; 4354 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4355 break; 4356 case 4: /* jmp */ 4357 case 5: /* ljmp */ 4358 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4359 break; 4360 case 6: /* push */ 4361 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 4362 ir.dflag = 2; 4363 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4364 return -1; 4365 break; 4366 default: 4367 ir.addr -= 2; 4368 opcode = opcode << 8 | ir.modrm; 4369 goto no_support; 4370 break; 4371 } 4372 break; 4373 4374 case 0x84: /* test */ 4375 case 0x85: 4376 case 0xa8: 4377 case 0xa9: 4378 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4379 break; 4380 4381 case 0x98: /* CWDE/CBW */ 4382 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4383 break; 4384 4385 case 0x99: /* CDQ/CWD */ 4386 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4387 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 4388 break; 4389 4390 case 0x0faf: /* imul */ 4391 case 0x69: 4392 case 0x6b: 4393 ir.ot = ir.dflag + OT_WORD; 4394 if (i386_record_modrm (&ir)) 4395 return -1; 4396 if (opcode == 0x69) 4397 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 4398 else if (opcode == 0x6b) 4399 ir.rip_offset = 1; 4400 ir.reg |= rex_r; 4401 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4402 ir.reg &= 0x3; 4403 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4404 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4405 break; 4406 4407 case 0x0fc0: /* xadd */ 4408 case 0x0fc1: 4409 if ((opcode & 1) == 0) 4410 ir.ot = OT_BYTE; 4411 else 4412 ir.ot = ir.dflag + OT_WORD; 4413 if (i386_record_modrm (&ir)) 4414 return -1; 4415 ir.reg |= rex_r; 4416 if (ir.mod == 3) 4417 { 4418 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4419 ir.reg &= 0x3; 4420 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4421 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4422 ir.rm &= 0x3; 4423 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 4424 } 4425 else 4426 { 4427 if (i386_record_lea_modrm (&ir)) 4428 return -1; 4429 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4430 ir.reg &= 0x3; 4431 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4432 } 4433 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4434 break; 4435 4436 case 0x0fb0: /* cmpxchg */ 4437 case 0x0fb1: 4438 if ((opcode & 1) == 0) 4439 ir.ot = OT_BYTE; 4440 else 4441 ir.ot = ir.dflag + OT_WORD; 4442 if (i386_record_modrm (&ir)) 4443 return -1; 4444 if (ir.mod == 3) 4445 { 4446 ir.reg |= rex_r; 4447 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4448 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4449 ir.reg &= 0x3; 4450 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4451 } 4452 else 4453 { 4454 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4455 if (i386_record_lea_modrm (&ir)) 4456 return -1; 4457 } 4458 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4459 break; 4460 4461 case 0x0fc7: /* cmpxchg8b */ 4462 if (i386_record_modrm (&ir)) 4463 return -1; 4464 if (ir.mod == 3) 4465 { 4466 ir.addr -= 2; 4467 opcode = opcode << 8 | ir.modrm; 4468 goto no_support; 4469 } 4470 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4471 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 4472 if (i386_record_lea_modrm (&ir)) 4473 return -1; 4474 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4475 break; 4476 4477 case 0x50: /* push */ 4478 case 0x51: 4479 case 0x52: 4480 case 0x53: 4481 case 0x54: 4482 case 0x55: 4483 case 0x56: 4484 case 0x57: 4485 case 0x68: 4486 case 0x6a: 4487 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 4488 ir.dflag = 2; 4489 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4490 return -1; 4491 break; 4492 4493 case 0x06: /* push es */ 4494 case 0x0e: /* push cs */ 4495 case 0x16: /* push ss */ 4496 case 0x1e: /* push ds */ 4497 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4498 { 4499 ir.addr -= 1; 4500 goto no_support; 4501 } 4502 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4503 return -1; 4504 break; 4505 4506 case 0x0fa0: /* push fs */ 4507 case 0x0fa8: /* push gs */ 4508 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4509 { 4510 ir.addr -= 2; 4511 goto no_support; 4512 } 4513 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4514 return -1; 4515 break; 4516 4517 case 0x60: /* pusha */ 4518 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4519 { 4520 ir.addr -= 1; 4521 goto no_support; 4522 } 4523 if (i386_record_push (&ir, 1 << (ir.dflag + 4))) 4524 return -1; 4525 break; 4526 4527 case 0x58: /* pop */ 4528 case 0x59: 4529 case 0x5a: 4530 case 0x5b: 4531 case 0x5c: 4532 case 0x5d: 4533 case 0x5e: 4534 case 0x5f: 4535 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4536 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); 4537 break; 4538 4539 case 0x61: /* popa */ 4540 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4541 { 4542 ir.addr -= 1; 4543 goto no_support; 4544 } 4545 for (regnum = X86_RECORD_REAX_REGNUM; 4546 regnum <= X86_RECORD_REDI_REGNUM; 4547 regnum++) 4548 I386_RECORD_ARCH_LIST_ADD_REG (regnum); 4549 break; 4550 4551 case 0x8f: /* pop */ 4552 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4553 ir.ot = ir.dflag ? OT_QUAD : OT_WORD; 4554 else 4555 ir.ot = ir.dflag + OT_WORD; 4556 if (i386_record_modrm (&ir)) 4557 return -1; 4558 if (ir.mod == 3) 4559 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 4560 else 4561 { 4562 ir.popl_esp_hack = 1 << ir.ot; 4563 if (i386_record_lea_modrm (&ir)) 4564 return -1; 4565 } 4566 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4567 break; 4568 4569 case 0xc8: /* enter */ 4570 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); 4571 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 4572 ir.dflag = 2; 4573 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 4574 return -1; 4575 break; 4576 4577 case 0xc9: /* leave */ 4578 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4579 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); 4580 break; 4581 4582 case 0x07: /* pop es */ 4583 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4584 { 4585 ir.addr -= 1; 4586 goto no_support; 4587 } 4588 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4589 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); 4590 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4591 break; 4592 4593 case 0x17: /* pop ss */ 4594 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4595 { 4596 ir.addr -= 1; 4597 goto no_support; 4598 } 4599 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4600 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); 4601 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4602 break; 4603 4604 case 0x1f: /* pop ds */ 4605 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4606 { 4607 ir.addr -= 1; 4608 goto no_support; 4609 } 4610 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4611 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); 4612 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4613 break; 4614 4615 case 0x0fa1: /* pop fs */ 4616 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4617 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); 4618 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4619 break; 4620 4621 case 0x0fa9: /* pop gs */ 4622 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 4623 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); 4624 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4625 break; 4626 4627 case 0x88: /* mov */ 4628 case 0x89: 4629 case 0xc6: 4630 case 0xc7: 4631 if ((opcode & 1) == 0) 4632 ir.ot = OT_BYTE; 4633 else 4634 ir.ot = ir.dflag + OT_WORD; 4635 4636 if (i386_record_modrm (&ir)) 4637 return -1; 4638 4639 if (ir.mod != 3) 4640 { 4641 if (opcode == 0xc6 || opcode == 0xc7) 4642 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 4643 if (i386_record_lea_modrm (&ir)) 4644 return -1; 4645 } 4646 else 4647 { 4648 if (opcode == 0xc6 || opcode == 0xc7) 4649 ir.rm |= ir.rex_b; 4650 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4651 ir.rm &= 0x3; 4652 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 4653 } 4654 break; 4655 4656 case 0x8a: /* mov */ 4657 case 0x8b: 4658 if ((opcode & 1) == 0) 4659 ir.ot = OT_BYTE; 4660 else 4661 ir.ot = ir.dflag + OT_WORD; 4662 if (i386_record_modrm (&ir)) 4663 return -1; 4664 ir.reg |= rex_r; 4665 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4666 ir.reg &= 0x3; 4667 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4668 break; 4669 4670 case 0x8c: /* mov seg */ 4671 if (i386_record_modrm (&ir)) 4672 return -1; 4673 if (ir.reg > 5) 4674 { 4675 ir.addr -= 2; 4676 opcode = opcode << 8 | ir.modrm; 4677 goto no_support; 4678 } 4679 4680 if (ir.mod == 3) 4681 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 4682 else 4683 { 4684 ir.ot = OT_WORD; 4685 if (i386_record_lea_modrm (&ir)) 4686 return -1; 4687 } 4688 break; 4689 4690 case 0x8e: /* mov seg */ 4691 if (i386_record_modrm (&ir)) 4692 return -1; 4693 switch (ir.reg) 4694 { 4695 case 0: 4696 regnum = X86_RECORD_ES_REGNUM; 4697 break; 4698 case 2: 4699 regnum = X86_RECORD_SS_REGNUM; 4700 break; 4701 case 3: 4702 regnum = X86_RECORD_DS_REGNUM; 4703 break; 4704 case 4: 4705 regnum = X86_RECORD_FS_REGNUM; 4706 break; 4707 case 5: 4708 regnum = X86_RECORD_GS_REGNUM; 4709 break; 4710 default: 4711 ir.addr -= 2; 4712 opcode = opcode << 8 | ir.modrm; 4713 goto no_support; 4714 break; 4715 } 4716 I386_RECORD_ARCH_LIST_ADD_REG (regnum); 4717 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4718 break; 4719 4720 case 0x0fb6: /* movzbS */ 4721 case 0x0fb7: /* movzwS */ 4722 case 0x0fbe: /* movsbS */ 4723 case 0x0fbf: /* movswS */ 4724 if (i386_record_modrm (&ir)) 4725 return -1; 4726 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); 4727 break; 4728 4729 case 0x8d: /* lea */ 4730 if (i386_record_modrm (&ir)) 4731 return -1; 4732 if (ir.mod == 3) 4733 { 4734 ir.addr -= 2; 4735 opcode = opcode << 8 | ir.modrm; 4736 goto no_support; 4737 } 4738 ir.ot = ir.dflag; 4739 ir.reg |= rex_r; 4740 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4741 ir.reg &= 0x3; 4742 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4743 break; 4744 4745 case 0xa0: /* mov EAX */ 4746 case 0xa1: 4747 4748 case 0xd7: /* xlat */ 4749 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4750 break; 4751 4752 case 0xa2: /* mov EAX */ 4753 case 0xa3: 4754 if (ir.override >= 0) 4755 { 4756 if (record_memory_query) 4757 { 4758 int q; 4759 4760 target_terminal_ours (); 4761 q = yquery (_("\ 4762 Process record ignores the memory change of instruction at address %s\n\ 4763 because it can't get the value of the segment register.\n\ 4764 Do you want to stop the program?"), 4765 paddress (gdbarch, ir.orig_addr)); 4766 target_terminal_inferior (); 4767 if (q) 4768 return -1; 4769 } 4770 } 4771 else 4772 { 4773 if ((opcode & 1) == 0) 4774 ir.ot = OT_BYTE; 4775 else 4776 ir.ot = ir.dflag + OT_WORD; 4777 if (ir.aflag == 2) 4778 { 4779 if (target_read_memory (ir.addr, buf, 8)) 4780 { 4781 if (record_debug) 4782 printf_unfiltered (_("Process record: error reading " 4783 "memory at addr 0x%s len = 8.\n"), 4784 paddress (gdbarch, ir.addr)); 4785 return -1; 4786 } 4787 ir.addr += 8; 4788 addr = extract_unsigned_integer (buf, 8, byte_order); 4789 } 4790 else if (ir.aflag) 4791 { 4792 if (target_read_memory (ir.addr, buf, 4)) 4793 { 4794 if (record_debug) 4795 printf_unfiltered (_("Process record: error reading " 4796 "memory at addr 0x%s len = 4.\n"), 4797 paddress (gdbarch, ir.addr)); 4798 return -1; 4799 } 4800 ir.addr += 4; 4801 addr = extract_unsigned_integer (buf, 4, byte_order); 4802 } 4803 else 4804 { 4805 if (target_read_memory (ir.addr, buf, 2)) 4806 { 4807 if (record_debug) 4808 printf_unfiltered (_("Process record: error reading " 4809 "memory at addr 0x%s len = 2.\n"), 4810 paddress (gdbarch, ir.addr)); 4811 return -1; 4812 } 4813 ir.addr += 2; 4814 addr = extract_unsigned_integer (buf, 2, byte_order); 4815 } 4816 if (record_arch_list_add_mem (addr, 1 << ir.ot)) 4817 return -1; 4818 } 4819 break; 4820 4821 case 0xb0: /* mov R, Ib */ 4822 case 0xb1: 4823 case 0xb2: 4824 case 0xb3: 4825 case 0xb4: 4826 case 0xb5: 4827 case 0xb6: 4828 case 0xb7: 4829 I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) 4830 ? ((opcode & 0x7) | ir.rex_b) 4831 : ((opcode & 0x7) & 0x3)); 4832 break; 4833 4834 case 0xb8: /* mov R, Iv */ 4835 case 0xb9: 4836 case 0xba: 4837 case 0xbb: 4838 case 0xbc: 4839 case 0xbd: 4840 case 0xbe: 4841 case 0xbf: 4842 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); 4843 break; 4844 4845 case 0x91: /* xchg R, EAX */ 4846 case 0x92: 4847 case 0x93: 4848 case 0x94: 4849 case 0x95: 4850 case 0x96: 4851 case 0x97: 4852 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 4853 I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); 4854 break; 4855 4856 case 0x86: /* xchg Ev, Gv */ 4857 case 0x87: 4858 if ((opcode & 1) == 0) 4859 ir.ot = OT_BYTE; 4860 else 4861 ir.ot = ir.dflag + OT_WORD; 4862 if (i386_record_modrm (&ir)) 4863 return -1; 4864 if (ir.mod == 3) 4865 { 4866 ir.rm |= ir.rex_b; 4867 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4868 ir.rm &= 0x3; 4869 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 4870 } 4871 else 4872 { 4873 if (i386_record_lea_modrm (&ir)) 4874 return -1; 4875 } 4876 ir.reg |= rex_r; 4877 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4878 ir.reg &= 0x3; 4879 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 4880 break; 4881 4882 case 0xc4: /* les Gv */ 4883 case 0xc5: /* lds Gv */ 4884 if (ir.regmap[X86_RECORD_R8_REGNUM]) 4885 { 4886 ir.addr -= 1; 4887 goto no_support; 4888 } 4889 /* FALLTHROUGH */ 4890 case 0x0fb2: /* lss Gv */ 4891 case 0x0fb4: /* lfs Gv */ 4892 case 0x0fb5: /* lgs Gv */ 4893 if (i386_record_modrm (&ir)) 4894 return -1; 4895 if (ir.mod == 3) 4896 { 4897 if (opcode > 0xff) 4898 ir.addr -= 3; 4899 else 4900 ir.addr -= 2; 4901 opcode = opcode << 8 | ir.modrm; 4902 goto no_support; 4903 } 4904 switch (opcode) 4905 { 4906 case 0xc4: /* les Gv */ 4907 regnum = X86_RECORD_ES_REGNUM; 4908 break; 4909 case 0xc5: /* lds Gv */ 4910 regnum = X86_RECORD_DS_REGNUM; 4911 break; 4912 case 0x0fb2: /* lss Gv */ 4913 regnum = X86_RECORD_SS_REGNUM; 4914 break; 4915 case 0x0fb4: /* lfs Gv */ 4916 regnum = X86_RECORD_FS_REGNUM; 4917 break; 4918 case 0x0fb5: /* lgs Gv */ 4919 regnum = X86_RECORD_GS_REGNUM; 4920 break; 4921 } 4922 I386_RECORD_ARCH_LIST_ADD_REG (regnum); 4923 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); 4924 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4925 break; 4926 4927 case 0xc0: /* shifts */ 4928 case 0xc1: 4929 case 0xd0: 4930 case 0xd1: 4931 case 0xd2: 4932 case 0xd3: 4933 if ((opcode & 1) == 0) 4934 ir.ot = OT_BYTE; 4935 else 4936 ir.ot = ir.dflag + OT_WORD; 4937 if (i386_record_modrm (&ir)) 4938 return -1; 4939 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) 4940 { 4941 if (i386_record_lea_modrm (&ir)) 4942 return -1; 4943 } 4944 else 4945 { 4946 ir.rm |= ir.rex_b; 4947 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 4948 ir.rm &= 0x3; 4949 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); 4950 } 4951 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 4952 break; 4953 4954 case 0x0fa4: 4955 case 0x0fa5: 4956 case 0x0fac: 4957 case 0x0fad: 4958 if (i386_record_modrm (&ir)) 4959 return -1; 4960 if (ir.mod == 3) 4961 { 4962 if (record_arch_list_add_reg (ir.regcache, ir.rm)) 4963 return -1; 4964 } 4965 else 4966 { 4967 if (i386_record_lea_modrm (&ir)) 4968 return -1; 4969 } 4970 break; 4971 4972 case 0xd8: /* Floats. */ 4973 case 0xd9: 4974 case 0xda: 4975 case 0xdb: 4976 case 0xdc: 4977 case 0xdd: 4978 case 0xde: 4979 case 0xdf: 4980 if (i386_record_modrm (&ir)) 4981 return -1; 4982 ir.reg |= ((opcode & 7) << 3); 4983 if (ir.mod != 3) 4984 { 4985 /* Memory. */ 4986 uint64_t addr64; 4987 4988 if (i386_record_lea_modrm_addr (&ir, &addr64)) 4989 return -1; 4990 switch (ir.reg) 4991 { 4992 case 0x02: 4993 case 0x12: 4994 case 0x22: 4995 case 0x32: 4996 /* For fcom, ficom nothing to do. */ 4997 break; 4998 case 0x03: 4999 case 0x13: 5000 case 0x23: 5001 case 0x33: 5002 /* For fcomp, ficomp pop FPU stack, store all. */ 5003 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 5004 return -1; 5005 break; 5006 case 0x00: 5007 case 0x01: 5008 case 0x04: 5009 case 0x05: 5010 case 0x06: 5011 case 0x07: 5012 case 0x10: 5013 case 0x11: 5014 case 0x14: 5015 case 0x15: 5016 case 0x16: 5017 case 0x17: 5018 case 0x20: 5019 case 0x21: 5020 case 0x24: 5021 case 0x25: 5022 case 0x26: 5023 case 0x27: 5024 case 0x30: 5025 case 0x31: 5026 case 0x34: 5027 case 0x35: 5028 case 0x36: 5029 case 0x37: 5030 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, 5031 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension 5032 of code, always affects st(0) register. */ 5033 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) 5034 return -1; 5035 break; 5036 case 0x08: 5037 case 0x0a: 5038 case 0x0b: 5039 case 0x18: 5040 case 0x19: 5041 case 0x1a: 5042 case 0x1b: 5043 case 0x1d: 5044 case 0x28: 5045 case 0x29: 5046 case 0x2a: 5047 case 0x2b: 5048 case 0x38: 5049 case 0x39: 5050 case 0x3a: 5051 case 0x3b: 5052 case 0x3c: 5053 case 0x3d: 5054 switch (ir.reg & 7) 5055 { 5056 case 0: 5057 /* Handling fld, fild. */ 5058 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 5059 return -1; 5060 break; 5061 case 1: 5062 switch (ir.reg >> 4) 5063 { 5064 case 0: 5065 if (record_arch_list_add_mem (addr64, 4)) 5066 return -1; 5067 break; 5068 case 2: 5069 if (record_arch_list_add_mem (addr64, 8)) 5070 return -1; 5071 break; 5072 case 3: 5073 break; 5074 default: 5075 if (record_arch_list_add_mem (addr64, 2)) 5076 return -1; 5077 break; 5078 } 5079 break; 5080 default: 5081 switch (ir.reg >> 4) 5082 { 5083 case 0: 5084 if (record_arch_list_add_mem (addr64, 4)) 5085 return -1; 5086 if (3 == (ir.reg & 7)) 5087 { 5088 /* For fstp m32fp. */ 5089 if (i386_record_floats (gdbarch, &ir, 5090 I386_SAVE_FPU_REGS)) 5091 return -1; 5092 } 5093 break; 5094 case 1: 5095 if (record_arch_list_add_mem (addr64, 4)) 5096 return -1; 5097 if ((3 == (ir.reg & 7)) 5098 || (5 == (ir.reg & 7)) 5099 || (7 == (ir.reg & 7))) 5100 { 5101 /* For fstp insn. */ 5102 if (i386_record_floats (gdbarch, &ir, 5103 I386_SAVE_FPU_REGS)) 5104 return -1; 5105 } 5106 break; 5107 case 2: 5108 if (record_arch_list_add_mem (addr64, 8)) 5109 return -1; 5110 if (3 == (ir.reg & 7)) 5111 { 5112 /* For fstp m64fp. */ 5113 if (i386_record_floats (gdbarch, &ir, 5114 I386_SAVE_FPU_REGS)) 5115 return -1; 5116 } 5117 break; 5118 case 3: 5119 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) 5120 { 5121 /* For fistp, fbld, fild, fbstp. */ 5122 if (i386_record_floats (gdbarch, &ir, 5123 I386_SAVE_FPU_REGS)) 5124 return -1; 5125 } 5126 /* Fall through */ 5127 default: 5128 if (record_arch_list_add_mem (addr64, 2)) 5129 return -1; 5130 break; 5131 } 5132 break; 5133 } 5134 break; 5135 case 0x0c: 5136 /* Insn fldenv. */ 5137 if (i386_record_floats (gdbarch, &ir, 5138 I386_SAVE_FPU_ENV_REG_STACK)) 5139 return -1; 5140 break; 5141 case 0x0d: 5142 /* Insn fldcw. */ 5143 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) 5144 return -1; 5145 break; 5146 case 0x2c: 5147 /* Insn frstor. */ 5148 if (i386_record_floats (gdbarch, &ir, 5149 I386_SAVE_FPU_ENV_REG_STACK)) 5150 return -1; 5151 break; 5152 case 0x0e: 5153 if (ir.dflag) 5154 { 5155 if (record_arch_list_add_mem (addr64, 28)) 5156 return -1; 5157 } 5158 else 5159 { 5160 if (record_arch_list_add_mem (addr64, 14)) 5161 return -1; 5162 } 5163 break; 5164 case 0x0f: 5165 case 0x2f: 5166 if (record_arch_list_add_mem (addr64, 2)) 5167 return -1; 5168 /* Insn fstp, fbstp. */ 5169 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 5170 return -1; 5171 break; 5172 case 0x1f: 5173 case 0x3e: 5174 if (record_arch_list_add_mem (addr64, 10)) 5175 return -1; 5176 break; 5177 case 0x2e: 5178 if (ir.dflag) 5179 { 5180 if (record_arch_list_add_mem (addr64, 28)) 5181 return -1; 5182 addr64 += 28; 5183 } 5184 else 5185 { 5186 if (record_arch_list_add_mem (addr64, 14)) 5187 return -1; 5188 addr64 += 14; 5189 } 5190 if (record_arch_list_add_mem (addr64, 80)) 5191 return -1; 5192 /* Insn fsave. */ 5193 if (i386_record_floats (gdbarch, &ir, 5194 I386_SAVE_FPU_ENV_REG_STACK)) 5195 return -1; 5196 break; 5197 case 0x3f: 5198 if (record_arch_list_add_mem (addr64, 8)) 5199 return -1; 5200 /* Insn fistp. */ 5201 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 5202 return -1; 5203 break; 5204 default: 5205 ir.addr -= 2; 5206 opcode = opcode << 8 | ir.modrm; 5207 goto no_support; 5208 break; 5209 } 5210 } 5211 /* Opcode is an extension of modR/M byte. */ 5212 else 5213 { 5214 switch (opcode) 5215 { 5216 case 0xd8: 5217 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) 5218 return -1; 5219 break; 5220 case 0xd9: 5221 if (0x0c == (ir.modrm >> 4)) 5222 { 5223 if ((ir.modrm & 0x0f) <= 7) 5224 { 5225 if (i386_record_floats (gdbarch, &ir, 5226 I386_SAVE_FPU_REGS)) 5227 return -1; 5228 } 5229 else 5230 { 5231 if (i386_record_floats (gdbarch, &ir, 5232 I387_ST0_REGNUM (tdep))) 5233 return -1; 5234 /* If only st(0) is changing, then we have already 5235 recorded. */ 5236 if ((ir.modrm & 0x0f) - 0x08) 5237 { 5238 if (i386_record_floats (gdbarch, &ir, 5239 I387_ST0_REGNUM (tdep) + 5240 ((ir.modrm & 0x0f) - 0x08))) 5241 return -1; 5242 } 5243 } 5244 } 5245 else 5246 { 5247 switch (ir.modrm) 5248 { 5249 case 0xe0: 5250 case 0xe1: 5251 case 0xf0: 5252 case 0xf5: 5253 case 0xf8: 5254 case 0xfa: 5255 case 0xfc: 5256 case 0xfe: 5257 case 0xff: 5258 if (i386_record_floats (gdbarch, &ir, 5259 I387_ST0_REGNUM (tdep))) 5260 return -1; 5261 break; 5262 case 0xf1: 5263 case 0xf2: 5264 case 0xf3: 5265 case 0xf4: 5266 case 0xf6: 5267 case 0xf7: 5268 case 0xe8: 5269 case 0xe9: 5270 case 0xea: 5271 case 0xeb: 5272 case 0xec: 5273 case 0xed: 5274 case 0xee: 5275 case 0xf9: 5276 case 0xfb: 5277 if (i386_record_floats (gdbarch, &ir, 5278 I386_SAVE_FPU_REGS)) 5279 return -1; 5280 break; 5281 case 0xfd: 5282 if (i386_record_floats (gdbarch, &ir, 5283 I387_ST0_REGNUM (tdep))) 5284 return -1; 5285 if (i386_record_floats (gdbarch, &ir, 5286 I387_ST0_REGNUM (tdep) + 1)) 5287 return -1; 5288 break; 5289 } 5290 } 5291 break; 5292 case 0xda: 5293 if (0xe9 == ir.modrm) 5294 { 5295 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 5296 return -1; 5297 } 5298 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) 5299 { 5300 if (i386_record_floats (gdbarch, &ir, 5301 I387_ST0_REGNUM (tdep))) 5302 return -1; 5303 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) 5304 { 5305 if (i386_record_floats (gdbarch, &ir, 5306 I387_ST0_REGNUM (tdep) + 5307 (ir.modrm & 0x0f))) 5308 return -1; 5309 } 5310 else if ((ir.modrm & 0x0f) - 0x08) 5311 { 5312 if (i386_record_floats (gdbarch, &ir, 5313 I387_ST0_REGNUM (tdep) + 5314 ((ir.modrm & 0x0f) - 0x08))) 5315 return -1; 5316 } 5317 } 5318 break; 5319 case 0xdb: 5320 if (0xe3 == ir.modrm) 5321 { 5322 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) 5323 return -1; 5324 } 5325 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) 5326 { 5327 if (i386_record_floats (gdbarch, &ir, 5328 I387_ST0_REGNUM (tdep))) 5329 return -1; 5330 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) 5331 { 5332 if (i386_record_floats (gdbarch, &ir, 5333 I387_ST0_REGNUM (tdep) + 5334 (ir.modrm & 0x0f))) 5335 return -1; 5336 } 5337 else if ((ir.modrm & 0x0f) - 0x08) 5338 { 5339 if (i386_record_floats (gdbarch, &ir, 5340 I387_ST0_REGNUM (tdep) + 5341 ((ir.modrm & 0x0f) - 0x08))) 5342 return -1; 5343 } 5344 } 5345 break; 5346 case 0xdc: 5347 if ((0x0c == ir.modrm >> 4) 5348 || (0x0d == ir.modrm >> 4) 5349 || (0x0f == ir.modrm >> 4)) 5350 { 5351 if ((ir.modrm & 0x0f) <= 7) 5352 { 5353 if (i386_record_floats (gdbarch, &ir, 5354 I387_ST0_REGNUM (tdep) + 5355 (ir.modrm & 0x0f))) 5356 return -1; 5357 } 5358 else 5359 { 5360 if (i386_record_floats (gdbarch, &ir, 5361 I387_ST0_REGNUM (tdep) + 5362 ((ir.modrm & 0x0f) - 0x08))) 5363 return -1; 5364 } 5365 } 5366 break; 5367 case 0xdd: 5368 if (0x0c == ir.modrm >> 4) 5369 { 5370 if (i386_record_floats (gdbarch, &ir, 5371 I387_FTAG_REGNUM (tdep))) 5372 return -1; 5373 } 5374 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) 5375 { 5376 if ((ir.modrm & 0x0f) <= 7) 5377 { 5378 if (i386_record_floats (gdbarch, &ir, 5379 I387_ST0_REGNUM (tdep) + 5380 (ir.modrm & 0x0f))) 5381 return -1; 5382 } 5383 else 5384 { 5385 if (i386_record_floats (gdbarch, &ir, 5386 I386_SAVE_FPU_REGS)) 5387 return -1; 5388 } 5389 } 5390 break; 5391 case 0xde: 5392 if ((0x0c == ir.modrm >> 4) 5393 || (0x0e == ir.modrm >> 4) 5394 || (0x0f == ir.modrm >> 4) 5395 || (0xd9 == ir.modrm)) 5396 { 5397 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 5398 return -1; 5399 } 5400 break; 5401 case 0xdf: 5402 if (0xe0 == ir.modrm) 5403 { 5404 if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) 5405 return -1; 5406 } 5407 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) 5408 { 5409 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 5410 return -1; 5411 } 5412 break; 5413 } 5414 } 5415 break; 5416 /* string ops */ 5417 case 0xa4: /* movsS */ 5418 case 0xa5: 5419 case 0xaa: /* stosS */ 5420 case 0xab: 5421 case 0x6c: /* insS */ 5422 case 0x6d: 5423 regcache_raw_read_unsigned (ir.regcache, 5424 ir.regmap[X86_RECORD_RECX_REGNUM], 5425 &addr); 5426 if (addr) 5427 { 5428 ULONGEST es, ds; 5429 5430 if ((opcode & 1) == 0) 5431 ir.ot = OT_BYTE; 5432 else 5433 ir.ot = ir.dflag + OT_WORD; 5434 regcache_raw_read_unsigned (ir.regcache, 5435 ir.regmap[X86_RECORD_REDI_REGNUM], 5436 &addr); 5437 5438 regcache_raw_read_unsigned (ir.regcache, 5439 ir.regmap[X86_RECORD_ES_REGNUM], 5440 &es); 5441 regcache_raw_read_unsigned (ir.regcache, 5442 ir.regmap[X86_RECORD_DS_REGNUM], 5443 &ds); 5444 if (ir.aflag && (es != ds)) 5445 { 5446 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ 5447 if (record_memory_query) 5448 { 5449 int q; 5450 5451 target_terminal_ours (); 5452 q = yquery (_("\ 5453 Process record ignores the memory change of instruction at address %s\n\ 5454 because it can't get the value of the segment register.\n\ 5455 Do you want to stop the program?"), 5456 paddress (gdbarch, ir.orig_addr)); 5457 target_terminal_inferior (); 5458 if (q) 5459 return -1; 5460 } 5461 } 5462 else 5463 { 5464 if (record_arch_list_add_mem (addr, 1 << ir.ot)) 5465 return -1; 5466 } 5467 5468 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 5469 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5470 if (opcode == 0xa4 || opcode == 0xa5) 5471 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 5472 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 5473 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5474 } 5475 break; 5476 5477 case 0xa6: /* cmpsS */ 5478 case 0xa7: 5479 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 5480 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 5481 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 5482 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5483 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5484 break; 5485 5486 case 0xac: /* lodsS */ 5487 case 0xad: 5488 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5489 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 5490 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 5491 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5492 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5493 break; 5494 5495 case 0xae: /* scasS */ 5496 case 0xaf: 5497 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 5498 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 5499 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5500 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5501 break; 5502 5503 case 0x6e: /* outsS */ 5504 case 0x6f: 5505 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 5506 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 5507 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5508 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5509 break; 5510 5511 case 0xe4: /* port I/O */ 5512 case 0xe5: 5513 case 0xec: 5514 case 0xed: 5515 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5516 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5517 break; 5518 5519 case 0xe6: 5520 case 0xe7: 5521 case 0xee: 5522 case 0xef: 5523 break; 5524 5525 /* control */ 5526 case 0xc2: /* ret im */ 5527 case 0xc3: /* ret */ 5528 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5529 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5530 break; 5531 5532 case 0xca: /* lret im */ 5533 case 0xcb: /* lret */ 5534 case 0xcf: /* iret */ 5535 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); 5536 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5537 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5538 break; 5539 5540 case 0xe8: /* call im */ 5541 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 5542 ir.dflag = 2; 5543 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5544 return -1; 5545 break; 5546 5547 case 0x9a: /* lcall im */ 5548 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5549 { 5550 ir.addr -= 1; 5551 goto no_support; 5552 } 5553 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); 5554 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5555 return -1; 5556 break; 5557 5558 case 0xe9: /* jmp im */ 5559 case 0xea: /* ljmp im */ 5560 case 0xeb: /* jmp Jb */ 5561 case 0x70: /* jcc Jb */ 5562 case 0x71: 5563 case 0x72: 5564 case 0x73: 5565 case 0x74: 5566 case 0x75: 5567 case 0x76: 5568 case 0x77: 5569 case 0x78: 5570 case 0x79: 5571 case 0x7a: 5572 case 0x7b: 5573 case 0x7c: 5574 case 0x7d: 5575 case 0x7e: 5576 case 0x7f: 5577 case 0x0f80: /* jcc Jv */ 5578 case 0x0f81: 5579 case 0x0f82: 5580 case 0x0f83: 5581 case 0x0f84: 5582 case 0x0f85: 5583 case 0x0f86: 5584 case 0x0f87: 5585 case 0x0f88: 5586 case 0x0f89: 5587 case 0x0f8a: 5588 case 0x0f8b: 5589 case 0x0f8c: 5590 case 0x0f8d: 5591 case 0x0f8e: 5592 case 0x0f8f: 5593 break; 5594 5595 case 0x0f90: /* setcc Gv */ 5596 case 0x0f91: 5597 case 0x0f92: 5598 case 0x0f93: 5599 case 0x0f94: 5600 case 0x0f95: 5601 case 0x0f96: 5602 case 0x0f97: 5603 case 0x0f98: 5604 case 0x0f99: 5605 case 0x0f9a: 5606 case 0x0f9b: 5607 case 0x0f9c: 5608 case 0x0f9d: 5609 case 0x0f9e: 5610 case 0x0f9f: 5611 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5612 ir.ot = OT_BYTE; 5613 if (i386_record_modrm (&ir)) 5614 return -1; 5615 if (ir.mod == 3) 5616 I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) 5617 : (ir.rm & 0x3)); 5618 else 5619 { 5620 if (i386_record_lea_modrm (&ir)) 5621 return -1; 5622 } 5623 break; 5624 5625 case 0x0f40: /* cmov Gv, Ev */ 5626 case 0x0f41: 5627 case 0x0f42: 5628 case 0x0f43: 5629 case 0x0f44: 5630 case 0x0f45: 5631 case 0x0f46: 5632 case 0x0f47: 5633 case 0x0f48: 5634 case 0x0f49: 5635 case 0x0f4a: 5636 case 0x0f4b: 5637 case 0x0f4c: 5638 case 0x0f4d: 5639 case 0x0f4e: 5640 case 0x0f4f: 5641 if (i386_record_modrm (&ir)) 5642 return -1; 5643 ir.reg |= rex_r; 5644 if (ir.dflag == OT_BYTE) 5645 ir.reg &= 0x3; 5646 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 5647 break; 5648 5649 /* flags */ 5650 case 0x9c: /* pushf */ 5651 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5652 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 5653 ir.dflag = 2; 5654 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5655 return -1; 5656 break; 5657 5658 case 0x9d: /* popf */ 5659 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5660 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5661 break; 5662 5663 case 0x9e: /* sahf */ 5664 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5665 { 5666 ir.addr -= 1; 5667 goto no_support; 5668 } 5669 /* FALLTHROUGH */ 5670 case 0xf5: /* cmc */ 5671 case 0xf8: /* clc */ 5672 case 0xf9: /* stc */ 5673 case 0xfc: /* cld */ 5674 case 0xfd: /* std */ 5675 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5676 break; 5677 5678 case 0x9f: /* lahf */ 5679 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5680 { 5681 ir.addr -= 1; 5682 goto no_support; 5683 } 5684 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5685 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5686 break; 5687 5688 /* bit operations */ 5689 case 0x0fba: /* bt/bts/btr/btc Gv, im */ 5690 ir.ot = ir.dflag + OT_WORD; 5691 if (i386_record_modrm (&ir)) 5692 return -1; 5693 if (ir.reg < 4) 5694 { 5695 ir.addr -= 2; 5696 opcode = opcode << 8 | ir.modrm; 5697 goto no_support; 5698 } 5699 if (ir.reg != 4) 5700 { 5701 if (ir.mod == 3) 5702 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 5703 else 5704 { 5705 if (i386_record_lea_modrm (&ir)) 5706 return -1; 5707 } 5708 } 5709 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5710 break; 5711 5712 case 0x0fa3: /* bt Gv, Ev */ 5713 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5714 break; 5715 5716 case 0x0fab: /* bts */ 5717 case 0x0fb3: /* btr */ 5718 case 0x0fbb: /* btc */ 5719 ir.ot = ir.dflag + OT_WORD; 5720 if (i386_record_modrm (&ir)) 5721 return -1; 5722 if (ir.mod == 3) 5723 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 5724 else 5725 { 5726 uint64_t addr64; 5727 if (i386_record_lea_modrm_addr (&ir, &addr64)) 5728 return -1; 5729 regcache_raw_read_unsigned (ir.regcache, 5730 ir.regmap[ir.reg | rex_r], 5731 &addr); 5732 switch (ir.dflag) 5733 { 5734 case 0: 5735 addr64 += ((int16_t) addr >> 4) << 4; 5736 break; 5737 case 1: 5738 addr64 += ((int32_t) addr >> 5) << 5; 5739 break; 5740 case 2: 5741 addr64 += ((int64_t) addr >> 6) << 6; 5742 break; 5743 } 5744 if (record_arch_list_add_mem (addr64, 1 << ir.ot)) 5745 return -1; 5746 if (i386_record_lea_modrm (&ir)) 5747 return -1; 5748 } 5749 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5750 break; 5751 5752 case 0x0fbc: /* bsf */ 5753 case 0x0fbd: /* bsr */ 5754 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); 5755 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5756 break; 5757 5758 /* bcd */ 5759 case 0x27: /* daa */ 5760 case 0x2f: /* das */ 5761 case 0x37: /* aaa */ 5762 case 0x3f: /* aas */ 5763 case 0xd4: /* aam */ 5764 case 0xd5: /* aad */ 5765 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5766 { 5767 ir.addr -= 1; 5768 goto no_support; 5769 } 5770 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5771 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5772 break; 5773 5774 /* misc */ 5775 case 0x90: /* nop */ 5776 if (prefixes & PREFIX_LOCK) 5777 { 5778 ir.addr -= 1; 5779 goto no_support; 5780 } 5781 break; 5782 5783 case 0x9b: /* fwait */ 5784 if (target_read_memory (ir.addr, &opcode8, 1)) 5785 { 5786 if (record_debug) 5787 printf_unfiltered (_("Process record: error reading memory at " 5788 "addr 0x%s len = 1.\n"), 5789 paddress (gdbarch, ir.addr)); 5790 return -1; 5791 } 5792 opcode = (uint32_t) opcode8; 5793 ir.addr++; 5794 goto reswitch; 5795 break; 5796 5797 /* XXX */ 5798 case 0xcc: /* int3 */ 5799 printf_unfiltered (_("Process record does not support instruction " 5800 "int3.\n")); 5801 ir.addr -= 1; 5802 goto no_support; 5803 break; 5804 5805 /* XXX */ 5806 case 0xcd: /* int */ 5807 { 5808 int ret; 5809 uint8_t interrupt; 5810 if (target_read_memory (ir.addr, &interrupt, 1)) 5811 { 5812 if (record_debug) 5813 printf_unfiltered (_("Process record: error reading memory " 5814 "at addr %s len = 1.\n"), 5815 paddress (gdbarch, ir.addr)); 5816 return -1; 5817 } 5818 ir.addr++; 5819 if (interrupt != 0x80 5820 || tdep->i386_intx80_record == NULL) 5821 { 5822 printf_unfiltered (_("Process record does not support " 5823 "instruction int 0x%02x.\n"), 5824 interrupt); 5825 ir.addr -= 2; 5826 goto no_support; 5827 } 5828 ret = tdep->i386_intx80_record (ir.regcache); 5829 if (ret) 5830 return ret; 5831 } 5832 break; 5833 5834 /* XXX */ 5835 case 0xce: /* into */ 5836 printf_unfiltered (_("Process record does not support " 5837 "instruction into.\n")); 5838 ir.addr -= 1; 5839 goto no_support; 5840 break; 5841 5842 case 0xfa: /* cli */ 5843 case 0xfb: /* sti */ 5844 break; 5845 5846 case 0x62: /* bound */ 5847 printf_unfiltered (_("Process record does not support " 5848 "instruction bound.\n")); 5849 ir.addr -= 1; 5850 goto no_support; 5851 break; 5852 5853 case 0x0fc8: /* bswap reg */ 5854 case 0x0fc9: 5855 case 0x0fca: 5856 case 0x0fcb: 5857 case 0x0fcc: 5858 case 0x0fcd: 5859 case 0x0fce: 5860 case 0x0fcf: 5861 I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); 5862 break; 5863 5864 case 0xd6: /* salc */ 5865 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5866 { 5867 ir.addr -= 1; 5868 goto no_support; 5869 } 5870 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5871 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5872 break; 5873 5874 case 0xe0: /* loopnz */ 5875 case 0xe1: /* loopz */ 5876 case 0xe2: /* loop */ 5877 case 0xe3: /* jecxz */ 5878 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5879 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5880 break; 5881 5882 case 0x0f30: /* wrmsr */ 5883 printf_unfiltered (_("Process record does not support " 5884 "instruction wrmsr.\n")); 5885 ir.addr -= 2; 5886 goto no_support; 5887 break; 5888 5889 case 0x0f32: /* rdmsr */ 5890 printf_unfiltered (_("Process record does not support " 5891 "instruction rdmsr.\n")); 5892 ir.addr -= 2; 5893 goto no_support; 5894 break; 5895 5896 case 0x0f31: /* rdtsc */ 5897 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5898 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 5899 break; 5900 5901 case 0x0f34: /* sysenter */ 5902 { 5903 int ret; 5904 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5905 { 5906 ir.addr -= 2; 5907 goto no_support; 5908 } 5909 if (tdep->i386_sysenter_record == NULL) 5910 { 5911 printf_unfiltered (_("Process record does not support " 5912 "instruction sysenter.\n")); 5913 ir.addr -= 2; 5914 goto no_support; 5915 } 5916 ret = tdep->i386_sysenter_record (ir.regcache); 5917 if (ret) 5918 return ret; 5919 } 5920 break; 5921 5922 case 0x0f35: /* sysexit */ 5923 printf_unfiltered (_("Process record does not support " 5924 "instruction sysexit.\n")); 5925 ir.addr -= 2; 5926 goto no_support; 5927 break; 5928 5929 case 0x0f05: /* syscall */ 5930 { 5931 int ret; 5932 if (tdep->i386_syscall_record == NULL) 5933 { 5934 printf_unfiltered (_("Process record does not support " 5935 "instruction syscall.\n")); 5936 ir.addr -= 2; 5937 goto no_support; 5938 } 5939 ret = tdep->i386_syscall_record (ir.regcache); 5940 if (ret) 5941 return ret; 5942 } 5943 break; 5944 5945 case 0x0f07: /* sysret */ 5946 printf_unfiltered (_("Process record does not support " 5947 "instruction sysret.\n")); 5948 ir.addr -= 2; 5949 goto no_support; 5950 break; 5951 5952 case 0x0fa2: /* cpuid */ 5953 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5954 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 5955 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 5956 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); 5957 break; 5958 5959 case 0xf4: /* hlt */ 5960 printf_unfiltered (_("Process record does not support " 5961 "instruction hlt.\n")); 5962 ir.addr -= 1; 5963 goto no_support; 5964 break; 5965 5966 case 0x0f00: 5967 if (i386_record_modrm (&ir)) 5968 return -1; 5969 switch (ir.reg) 5970 { 5971 case 0: /* sldt */ 5972 case 1: /* str */ 5973 if (ir.mod == 3) 5974 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 5975 else 5976 { 5977 ir.ot = OT_WORD; 5978 if (i386_record_lea_modrm (&ir)) 5979 return -1; 5980 } 5981 break; 5982 case 2: /* lldt */ 5983 case 3: /* ltr */ 5984 break; 5985 case 4: /* verr */ 5986 case 5: /* verw */ 5987 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5988 break; 5989 default: 5990 ir.addr -= 3; 5991 opcode = opcode << 8 | ir.modrm; 5992 goto no_support; 5993 break; 5994 } 5995 break; 5996 5997 case 0x0f01: 5998 if (i386_record_modrm (&ir)) 5999 return -1; 6000 switch (ir.reg) 6001 { 6002 case 0: /* sgdt */ 6003 { 6004 uint64_t addr64; 6005 6006 if (ir.mod == 3) 6007 { 6008 ir.addr -= 3; 6009 opcode = opcode << 8 | ir.modrm; 6010 goto no_support; 6011 } 6012 if (ir.override >= 0) 6013 { 6014 if (record_memory_query) 6015 { 6016 int q; 6017 6018 target_terminal_ours (); 6019 q = yquery (_("\ 6020 Process record ignores the memory change of instruction at address %s\n\ 6021 because it can't get the value of the segment register.\n\ 6022 Do you want to stop the program?"), 6023 paddress (gdbarch, ir.orig_addr)); 6024 target_terminal_inferior (); 6025 if (q) 6026 return -1; 6027 } 6028 } 6029 else 6030 { 6031 if (i386_record_lea_modrm_addr (&ir, &addr64)) 6032 return -1; 6033 if (record_arch_list_add_mem (addr64, 2)) 6034 return -1; 6035 addr64 += 2; 6036 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6037 { 6038 if (record_arch_list_add_mem (addr64, 8)) 6039 return -1; 6040 } 6041 else 6042 { 6043 if (record_arch_list_add_mem (addr64, 4)) 6044 return -1; 6045 } 6046 } 6047 } 6048 break; 6049 case 1: 6050 if (ir.mod == 3) 6051 { 6052 switch (ir.rm) 6053 { 6054 case 0: /* monitor */ 6055 break; 6056 case 1: /* mwait */ 6057 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6058 break; 6059 default: 6060 ir.addr -= 3; 6061 opcode = opcode << 8 | ir.modrm; 6062 goto no_support; 6063 break; 6064 } 6065 } 6066 else 6067 { 6068 /* sidt */ 6069 if (ir.override >= 0) 6070 { 6071 if (record_memory_query) 6072 { 6073 int q; 6074 6075 target_terminal_ours (); 6076 q = yquery (_("\ 6077 Process record ignores the memory change of instruction at address %s\n\ 6078 because it can't get the value of the segment register.\n\ 6079 Do you want to stop the program?"), 6080 paddress (gdbarch, ir.orig_addr)); 6081 target_terminal_inferior (); 6082 if (q) 6083 return -1; 6084 } 6085 } 6086 else 6087 { 6088 uint64_t addr64; 6089 6090 if (i386_record_lea_modrm_addr (&ir, &addr64)) 6091 return -1; 6092 if (record_arch_list_add_mem (addr64, 2)) 6093 return -1; 6094 addr64 += 2; 6095 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6096 { 6097 if (record_arch_list_add_mem (addr64, 8)) 6098 return -1; 6099 } 6100 else 6101 { 6102 if (record_arch_list_add_mem (addr64, 4)) 6103 return -1; 6104 } 6105 } 6106 } 6107 break; 6108 case 2: /* lgdt */ 6109 if (ir.mod == 3) 6110 { 6111 /* xgetbv */ 6112 if (ir.rm == 0) 6113 { 6114 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6115 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 6116 break; 6117 } 6118 /* xsetbv */ 6119 else if (ir.rm == 1) 6120 break; 6121 } 6122 case 3: /* lidt */ 6123 if (ir.mod == 3) 6124 { 6125 ir.addr -= 3; 6126 opcode = opcode << 8 | ir.modrm; 6127 goto no_support; 6128 } 6129 break; 6130 case 4: /* smsw */ 6131 if (ir.mod == 3) 6132 { 6133 if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) 6134 return -1; 6135 } 6136 else 6137 { 6138 ir.ot = OT_WORD; 6139 if (i386_record_lea_modrm (&ir)) 6140 return -1; 6141 } 6142 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6143 break; 6144 case 6: /* lmsw */ 6145 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6146 break; 6147 case 7: /* invlpg */ 6148 if (ir.mod == 3) 6149 { 6150 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) 6151 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); 6152 else 6153 { 6154 ir.addr -= 3; 6155 opcode = opcode << 8 | ir.modrm; 6156 goto no_support; 6157 } 6158 } 6159 else 6160 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6161 break; 6162 default: 6163 ir.addr -= 3; 6164 opcode = opcode << 8 | ir.modrm; 6165 goto no_support; 6166 break; 6167 } 6168 break; 6169 6170 case 0x0f08: /* invd */ 6171 case 0x0f09: /* wbinvd */ 6172 break; 6173 6174 case 0x63: /* arpl */ 6175 if (i386_record_modrm (&ir)) 6176 return -1; 6177 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) 6178 { 6179 I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] 6180 ? (ir.reg | rex_r) : ir.rm); 6181 } 6182 else 6183 { 6184 ir.ot = ir.dflag ? OT_LONG : OT_WORD; 6185 if (i386_record_lea_modrm (&ir)) 6186 return -1; 6187 } 6188 if (!ir.regmap[X86_RECORD_R8_REGNUM]) 6189 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6190 break; 6191 6192 case 0x0f02: /* lar */ 6193 case 0x0f03: /* lsl */ 6194 if (i386_record_modrm (&ir)) 6195 return -1; 6196 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); 6197 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6198 break; 6199 6200 case 0x0f18: 6201 if (i386_record_modrm (&ir)) 6202 return -1; 6203 if (ir.mod == 3 && ir.reg == 3) 6204 { 6205 ir.addr -= 3; 6206 opcode = opcode << 8 | ir.modrm; 6207 goto no_support; 6208 } 6209 break; 6210 6211 case 0x0f19: 6212 case 0x0f1a: 6213 case 0x0f1b: 6214 case 0x0f1c: 6215 case 0x0f1d: 6216 case 0x0f1e: 6217 case 0x0f1f: 6218 /* nop (multi byte) */ 6219 break; 6220 6221 case 0x0f20: /* mov reg, crN */ 6222 case 0x0f22: /* mov crN, reg */ 6223 if (i386_record_modrm (&ir)) 6224 return -1; 6225 if ((ir.modrm & 0xc0) != 0xc0) 6226 { 6227 ir.addr -= 3; 6228 opcode = opcode << 8 | ir.modrm; 6229 goto no_support; 6230 } 6231 switch (ir.reg) 6232 { 6233 case 0: 6234 case 2: 6235 case 3: 6236 case 4: 6237 case 8: 6238 if (opcode & 2) 6239 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6240 else 6241 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 6242 break; 6243 default: 6244 ir.addr -= 3; 6245 opcode = opcode << 8 | ir.modrm; 6246 goto no_support; 6247 break; 6248 } 6249 break; 6250 6251 case 0x0f21: /* mov reg, drN */ 6252 case 0x0f23: /* mov drN, reg */ 6253 if (i386_record_modrm (&ir)) 6254 return -1; 6255 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 6256 || ir.reg == 5 || ir.reg >= 8) 6257 { 6258 ir.addr -= 3; 6259 opcode = opcode << 8 | ir.modrm; 6260 goto no_support; 6261 } 6262 if (opcode & 2) 6263 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6264 else 6265 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 6266 break; 6267 6268 case 0x0f06: /* clts */ 6269 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6270 break; 6271 6272 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ 6273 6274 case 0x0f0d: /* 3DNow! prefetch */ 6275 break; 6276 6277 case 0x0f0e: /* 3DNow! femms */ 6278 case 0x0f77: /* emms */ 6279 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) 6280 goto no_support; 6281 record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); 6282 break; 6283 6284 case 0x0f0f: /* 3DNow! data */ 6285 if (i386_record_modrm (&ir)) 6286 return -1; 6287 if (target_read_memory (ir.addr, &opcode8, 1)) 6288 { 6289 printf_unfiltered (_("Process record: error reading memory at " 6290 "addr %s len = 1.\n"), 6291 paddress (gdbarch, ir.addr)); 6292 return -1; 6293 } 6294 ir.addr++; 6295 switch (opcode8) 6296 { 6297 case 0x0c: /* 3DNow! pi2fw */ 6298 case 0x0d: /* 3DNow! pi2fd */ 6299 case 0x1c: /* 3DNow! pf2iw */ 6300 case 0x1d: /* 3DNow! pf2id */ 6301 case 0x8a: /* 3DNow! pfnacc */ 6302 case 0x8e: /* 3DNow! pfpnacc */ 6303 case 0x90: /* 3DNow! pfcmpge */ 6304 case 0x94: /* 3DNow! pfmin */ 6305 case 0x96: /* 3DNow! pfrcp */ 6306 case 0x97: /* 3DNow! pfrsqrt */ 6307 case 0x9a: /* 3DNow! pfsub */ 6308 case 0x9e: /* 3DNow! pfadd */ 6309 case 0xa0: /* 3DNow! pfcmpgt */ 6310 case 0xa4: /* 3DNow! pfmax */ 6311 case 0xa6: /* 3DNow! pfrcpit1 */ 6312 case 0xa7: /* 3DNow! pfrsqit1 */ 6313 case 0xaa: /* 3DNow! pfsubr */ 6314 case 0xae: /* 3DNow! pfacc */ 6315 case 0xb0: /* 3DNow! pfcmpeq */ 6316 case 0xb4: /* 3DNow! pfmul */ 6317 case 0xb6: /* 3DNow! pfrcpit2 */ 6318 case 0xb7: /* 3DNow! pmulhrw */ 6319 case 0xbb: /* 3DNow! pswapd */ 6320 case 0xbf: /* 3DNow! pavgusb */ 6321 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) 6322 goto no_support_3dnow_data; 6323 record_arch_list_add_reg (ir.regcache, ir.reg); 6324 break; 6325 6326 default: 6327 no_support_3dnow_data: 6328 opcode = (opcode << 8) | opcode8; 6329 goto no_support; 6330 break; 6331 } 6332 break; 6333 6334 case 0x0faa: /* rsm */ 6335 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6336 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6337 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6338 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 6339 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); 6340 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 6341 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); 6342 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 6343 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 6344 break; 6345 6346 case 0x0fae: 6347 if (i386_record_modrm (&ir)) 6348 return -1; 6349 switch(ir.reg) 6350 { 6351 case 0: /* fxsave */ 6352 { 6353 uint64_t tmpu64; 6354 6355 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6356 if (i386_record_lea_modrm_addr (&ir, &tmpu64)) 6357 return -1; 6358 if (record_arch_list_add_mem (tmpu64, 512)) 6359 return -1; 6360 } 6361 break; 6362 6363 case 1: /* fxrstor */ 6364 { 6365 int i; 6366 6367 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6368 6369 for (i = I387_MM0_REGNUM (tdep); 6370 i386_mmx_regnum_p (gdbarch, i); i++) 6371 record_arch_list_add_reg (ir.regcache, i); 6372 6373 for (i = I387_XMM0_REGNUM (tdep); 6374 i386_xmm_regnum_p (gdbarch, i); i++) 6375 record_arch_list_add_reg (ir.regcache, i); 6376 6377 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) 6378 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); 6379 6380 for (i = I387_ST0_REGNUM (tdep); 6381 i386_fp_regnum_p (gdbarch, i); i++) 6382 record_arch_list_add_reg (ir.regcache, i); 6383 6384 for (i = I387_FCTRL_REGNUM (tdep); 6385 i386_fpc_regnum_p (gdbarch, i); i++) 6386 record_arch_list_add_reg (ir.regcache, i); 6387 } 6388 break; 6389 6390 case 2: /* ldmxcsr */ 6391 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) 6392 goto no_support; 6393 record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); 6394 break; 6395 6396 case 3: /* stmxcsr */ 6397 ir.ot = OT_LONG; 6398 if (i386_record_lea_modrm (&ir)) 6399 return -1; 6400 break; 6401 6402 case 5: /* lfence */ 6403 case 6: /* mfence */ 6404 case 7: /* sfence clflush */ 6405 break; 6406 6407 default: 6408 opcode = (opcode << 8) | ir.modrm; 6409 goto no_support; 6410 break; 6411 } 6412 break; 6413 6414 case 0x0fc3: /* movnti */ 6415 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; 6416 if (i386_record_modrm (&ir)) 6417 return -1; 6418 if (ir.mod == 3) 6419 goto no_support; 6420 ir.reg |= rex_r; 6421 if (i386_record_lea_modrm (&ir)) 6422 return -1; 6423 break; 6424 6425 /* Add prefix to opcode. */ 6426 case 0x0f10: 6427 case 0x0f11: 6428 case 0x0f12: 6429 case 0x0f13: 6430 case 0x0f14: 6431 case 0x0f15: 6432 case 0x0f16: 6433 case 0x0f17: 6434 case 0x0f28: 6435 case 0x0f29: 6436 case 0x0f2a: 6437 case 0x0f2b: 6438 case 0x0f2c: 6439 case 0x0f2d: 6440 case 0x0f2e: 6441 case 0x0f2f: 6442 case 0x0f38: 6443 case 0x0f39: 6444 case 0x0f3a: 6445 case 0x0f50: 6446 case 0x0f51: 6447 case 0x0f52: 6448 case 0x0f53: 6449 case 0x0f54: 6450 case 0x0f55: 6451 case 0x0f56: 6452 case 0x0f57: 6453 case 0x0f58: 6454 case 0x0f59: 6455 case 0x0f5a: 6456 case 0x0f5b: 6457 case 0x0f5c: 6458 case 0x0f5d: 6459 case 0x0f5e: 6460 case 0x0f5f: 6461 case 0x0f60: 6462 case 0x0f61: 6463 case 0x0f62: 6464 case 0x0f63: 6465 case 0x0f64: 6466 case 0x0f65: 6467 case 0x0f66: 6468 case 0x0f67: 6469 case 0x0f68: 6470 case 0x0f69: 6471 case 0x0f6a: 6472 case 0x0f6b: 6473 case 0x0f6c: 6474 case 0x0f6d: 6475 case 0x0f6e: 6476 case 0x0f6f: 6477 case 0x0f70: 6478 case 0x0f71: 6479 case 0x0f72: 6480 case 0x0f73: 6481 case 0x0f74: 6482 case 0x0f75: 6483 case 0x0f76: 6484 case 0x0f7c: 6485 case 0x0f7d: 6486 case 0x0f7e: 6487 case 0x0f7f: 6488 case 0x0fb8: 6489 case 0x0fc2: 6490 case 0x0fc4: 6491 case 0x0fc5: 6492 case 0x0fc6: 6493 case 0x0fd0: 6494 case 0x0fd1: 6495 case 0x0fd2: 6496 case 0x0fd3: 6497 case 0x0fd4: 6498 case 0x0fd5: 6499 case 0x0fd6: 6500 case 0x0fd7: 6501 case 0x0fd8: 6502 case 0x0fd9: 6503 case 0x0fda: 6504 case 0x0fdb: 6505 case 0x0fdc: 6506 case 0x0fdd: 6507 case 0x0fde: 6508 case 0x0fdf: 6509 case 0x0fe0: 6510 case 0x0fe1: 6511 case 0x0fe2: 6512 case 0x0fe3: 6513 case 0x0fe4: 6514 case 0x0fe5: 6515 case 0x0fe6: 6516 case 0x0fe7: 6517 case 0x0fe8: 6518 case 0x0fe9: 6519 case 0x0fea: 6520 case 0x0feb: 6521 case 0x0fec: 6522 case 0x0fed: 6523 case 0x0fee: 6524 case 0x0fef: 6525 case 0x0ff0: 6526 case 0x0ff1: 6527 case 0x0ff2: 6528 case 0x0ff3: 6529 case 0x0ff4: 6530 case 0x0ff5: 6531 case 0x0ff6: 6532 case 0x0ff7: 6533 case 0x0ff8: 6534 case 0x0ff9: 6535 case 0x0ffa: 6536 case 0x0ffb: 6537 case 0x0ffc: 6538 case 0x0ffd: 6539 case 0x0ffe: 6540 switch (prefixes) 6541 { 6542 case PREFIX_REPNZ: 6543 opcode |= 0xf20000; 6544 break; 6545 case PREFIX_DATA: 6546 opcode |= 0x660000; 6547 break; 6548 case PREFIX_REPZ: 6549 opcode |= 0xf30000; 6550 break; 6551 } 6552 reswitch_prefix_add: 6553 switch (opcode) 6554 { 6555 case 0x0f38: 6556 case 0x660f38: 6557 case 0xf20f38: 6558 case 0x0f3a: 6559 case 0x660f3a: 6560 if (target_read_memory (ir.addr, &opcode8, 1)) 6561 { 6562 printf_unfiltered (_("Process record: error reading memory at " 6563 "addr %s len = 1.\n"), 6564 paddress (gdbarch, ir.addr)); 6565 return -1; 6566 } 6567 ir.addr++; 6568 opcode = (uint32_t) opcode8 | opcode << 8; 6569 goto reswitch_prefix_add; 6570 break; 6571 6572 case 0x0f10: /* movups */ 6573 case 0x660f10: /* movupd */ 6574 case 0xf30f10: /* movss */ 6575 case 0xf20f10: /* movsd */ 6576 case 0x0f12: /* movlps */ 6577 case 0x660f12: /* movlpd */ 6578 case 0xf30f12: /* movsldup */ 6579 case 0xf20f12: /* movddup */ 6580 case 0x0f14: /* unpcklps */ 6581 case 0x660f14: /* unpcklpd */ 6582 case 0x0f15: /* unpckhps */ 6583 case 0x660f15: /* unpckhpd */ 6584 case 0x0f16: /* movhps */ 6585 case 0x660f16: /* movhpd */ 6586 case 0xf30f16: /* movshdup */ 6587 case 0x0f28: /* movaps */ 6588 case 0x660f28: /* movapd */ 6589 case 0x0f2a: /* cvtpi2ps */ 6590 case 0x660f2a: /* cvtpi2pd */ 6591 case 0xf30f2a: /* cvtsi2ss */ 6592 case 0xf20f2a: /* cvtsi2sd */ 6593 case 0x0f2c: /* cvttps2pi */ 6594 case 0x660f2c: /* cvttpd2pi */ 6595 case 0x0f2d: /* cvtps2pi */ 6596 case 0x660f2d: /* cvtpd2pi */ 6597 case 0x660f3800: /* pshufb */ 6598 case 0x660f3801: /* phaddw */ 6599 case 0x660f3802: /* phaddd */ 6600 case 0x660f3803: /* phaddsw */ 6601 case 0x660f3804: /* pmaddubsw */ 6602 case 0x660f3805: /* phsubw */ 6603 case 0x660f3806: /* phsubd */ 6604 case 0x660f3807: /* phsubsw */ 6605 case 0x660f3808: /* psignb */ 6606 case 0x660f3809: /* psignw */ 6607 case 0x660f380a: /* psignd */ 6608 case 0x660f380b: /* pmulhrsw */ 6609 case 0x660f3810: /* pblendvb */ 6610 case 0x660f3814: /* blendvps */ 6611 case 0x660f3815: /* blendvpd */ 6612 case 0x660f381c: /* pabsb */ 6613 case 0x660f381d: /* pabsw */ 6614 case 0x660f381e: /* pabsd */ 6615 case 0x660f3820: /* pmovsxbw */ 6616 case 0x660f3821: /* pmovsxbd */ 6617 case 0x660f3822: /* pmovsxbq */ 6618 case 0x660f3823: /* pmovsxwd */ 6619 case 0x660f3824: /* pmovsxwq */ 6620 case 0x660f3825: /* pmovsxdq */ 6621 case 0x660f3828: /* pmuldq */ 6622 case 0x660f3829: /* pcmpeqq */ 6623 case 0x660f382a: /* movntdqa */ 6624 case 0x660f3a08: /* roundps */ 6625 case 0x660f3a09: /* roundpd */ 6626 case 0x660f3a0a: /* roundss */ 6627 case 0x660f3a0b: /* roundsd */ 6628 case 0x660f3a0c: /* blendps */ 6629 case 0x660f3a0d: /* blendpd */ 6630 case 0x660f3a0e: /* pblendw */ 6631 case 0x660f3a0f: /* palignr */ 6632 case 0x660f3a20: /* pinsrb */ 6633 case 0x660f3a21: /* insertps */ 6634 case 0x660f3a22: /* pinsrd pinsrq */ 6635 case 0x660f3a40: /* dpps */ 6636 case 0x660f3a41: /* dppd */ 6637 case 0x660f3a42: /* mpsadbw */ 6638 case 0x660f3a60: /* pcmpestrm */ 6639 case 0x660f3a61: /* pcmpestri */ 6640 case 0x660f3a62: /* pcmpistrm */ 6641 case 0x660f3a63: /* pcmpistri */ 6642 case 0x0f51: /* sqrtps */ 6643 case 0x660f51: /* sqrtpd */ 6644 case 0xf20f51: /* sqrtsd */ 6645 case 0xf30f51: /* sqrtss */ 6646 case 0x0f52: /* rsqrtps */ 6647 case 0xf30f52: /* rsqrtss */ 6648 case 0x0f53: /* rcpps */ 6649 case 0xf30f53: /* rcpss */ 6650 case 0x0f54: /* andps */ 6651 case 0x660f54: /* andpd */ 6652 case 0x0f55: /* andnps */ 6653 case 0x660f55: /* andnpd */ 6654 case 0x0f56: /* orps */ 6655 case 0x660f56: /* orpd */ 6656 case 0x0f57: /* xorps */ 6657 case 0x660f57: /* xorpd */ 6658 case 0x0f58: /* addps */ 6659 case 0x660f58: /* addpd */ 6660 case 0xf20f58: /* addsd */ 6661 case 0xf30f58: /* addss */ 6662 case 0x0f59: /* mulps */ 6663 case 0x660f59: /* mulpd */ 6664 case 0xf20f59: /* mulsd */ 6665 case 0xf30f59: /* mulss */ 6666 case 0x0f5a: /* cvtps2pd */ 6667 case 0x660f5a: /* cvtpd2ps */ 6668 case 0xf20f5a: /* cvtsd2ss */ 6669 case 0xf30f5a: /* cvtss2sd */ 6670 case 0x0f5b: /* cvtdq2ps */ 6671 case 0x660f5b: /* cvtps2dq */ 6672 case 0xf30f5b: /* cvttps2dq */ 6673 case 0x0f5c: /* subps */ 6674 case 0x660f5c: /* subpd */ 6675 case 0xf20f5c: /* subsd */ 6676 case 0xf30f5c: /* subss */ 6677 case 0x0f5d: /* minps */ 6678 case 0x660f5d: /* minpd */ 6679 case 0xf20f5d: /* minsd */ 6680 case 0xf30f5d: /* minss */ 6681 case 0x0f5e: /* divps */ 6682 case 0x660f5e: /* divpd */ 6683 case 0xf20f5e: /* divsd */ 6684 case 0xf30f5e: /* divss */ 6685 case 0x0f5f: /* maxps */ 6686 case 0x660f5f: /* maxpd */ 6687 case 0xf20f5f: /* maxsd */ 6688 case 0xf30f5f: /* maxss */ 6689 case 0x660f60: /* punpcklbw */ 6690 case 0x660f61: /* punpcklwd */ 6691 case 0x660f62: /* punpckldq */ 6692 case 0x660f63: /* packsswb */ 6693 case 0x660f64: /* pcmpgtb */ 6694 case 0x660f65: /* pcmpgtw */ 6695 case 0x660f66: /* pcmpgtd */ 6696 case 0x660f67: /* packuswb */ 6697 case 0x660f68: /* punpckhbw */ 6698 case 0x660f69: /* punpckhwd */ 6699 case 0x660f6a: /* punpckhdq */ 6700 case 0x660f6b: /* packssdw */ 6701 case 0x660f6c: /* punpcklqdq */ 6702 case 0x660f6d: /* punpckhqdq */ 6703 case 0x660f6e: /* movd */ 6704 case 0x660f6f: /* movdqa */ 6705 case 0xf30f6f: /* movdqu */ 6706 case 0x660f70: /* pshufd */ 6707 case 0xf20f70: /* pshuflw */ 6708 case 0xf30f70: /* pshufhw */ 6709 case 0x660f74: /* pcmpeqb */ 6710 case 0x660f75: /* pcmpeqw */ 6711 case 0x660f76: /* pcmpeqd */ 6712 case 0x660f7c: /* haddpd */ 6713 case 0xf20f7c: /* haddps */ 6714 case 0x660f7d: /* hsubpd */ 6715 case 0xf20f7d: /* hsubps */ 6716 case 0xf30f7e: /* movq */ 6717 case 0x0fc2: /* cmpps */ 6718 case 0x660fc2: /* cmppd */ 6719 case 0xf20fc2: /* cmpsd */ 6720 case 0xf30fc2: /* cmpss */ 6721 case 0x660fc4: /* pinsrw */ 6722 case 0x0fc6: /* shufps */ 6723 case 0x660fc6: /* shufpd */ 6724 case 0x660fd0: /* addsubpd */ 6725 case 0xf20fd0: /* addsubps */ 6726 case 0x660fd1: /* psrlw */ 6727 case 0x660fd2: /* psrld */ 6728 case 0x660fd3: /* psrlq */ 6729 case 0x660fd4: /* paddq */ 6730 case 0x660fd5: /* pmullw */ 6731 case 0xf30fd6: /* movq2dq */ 6732 case 0x660fd8: /* psubusb */ 6733 case 0x660fd9: /* psubusw */ 6734 case 0x660fda: /* pminub */ 6735 case 0x660fdb: /* pand */ 6736 case 0x660fdc: /* paddusb */ 6737 case 0x660fdd: /* paddusw */ 6738 case 0x660fde: /* pmaxub */ 6739 case 0x660fdf: /* pandn */ 6740 case 0x660fe0: /* pavgb */ 6741 case 0x660fe1: /* psraw */ 6742 case 0x660fe2: /* psrad */ 6743 case 0x660fe3: /* pavgw */ 6744 case 0x660fe4: /* pmulhuw */ 6745 case 0x660fe5: /* pmulhw */ 6746 case 0x660fe6: /* cvttpd2dq */ 6747 case 0xf20fe6: /* cvtpd2dq */ 6748 case 0xf30fe6: /* cvtdq2pd */ 6749 case 0x660fe8: /* psubsb */ 6750 case 0x660fe9: /* psubsw */ 6751 case 0x660fea: /* pminsw */ 6752 case 0x660feb: /* por */ 6753 case 0x660fec: /* paddsb */ 6754 case 0x660fed: /* paddsw */ 6755 case 0x660fee: /* pmaxsw */ 6756 case 0x660fef: /* pxor */ 6757 case 0xf20ff0: /* lddqu */ 6758 case 0x660ff1: /* psllw */ 6759 case 0x660ff2: /* pslld */ 6760 case 0x660ff3: /* psllq */ 6761 case 0x660ff4: /* pmuludq */ 6762 case 0x660ff5: /* pmaddwd */ 6763 case 0x660ff6: /* psadbw */ 6764 case 0x660ff8: /* psubb */ 6765 case 0x660ff9: /* psubw */ 6766 case 0x660ffa: /* psubd */ 6767 case 0x660ffb: /* psubq */ 6768 case 0x660ffc: /* paddb */ 6769 case 0x660ffd: /* paddw */ 6770 case 0x660ffe: /* paddd */ 6771 if (i386_record_modrm (&ir)) 6772 return -1; 6773 ir.reg |= rex_r; 6774 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) 6775 goto no_support; 6776 record_arch_list_add_reg (ir.regcache, 6777 I387_XMM0_REGNUM (tdep) + ir.reg); 6778 if ((opcode & 0xfffffffc) == 0x660f3a60) 6779 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6780 break; 6781 6782 case 0x0f11: /* movups */ 6783 case 0x660f11: /* movupd */ 6784 case 0xf30f11: /* movss */ 6785 case 0xf20f11: /* movsd */ 6786 case 0x0f13: /* movlps */ 6787 case 0x660f13: /* movlpd */ 6788 case 0x0f17: /* movhps */ 6789 case 0x660f17: /* movhpd */ 6790 case 0x0f29: /* movaps */ 6791 case 0x660f29: /* movapd */ 6792 case 0x660f3a14: /* pextrb */ 6793 case 0x660f3a15: /* pextrw */ 6794 case 0x660f3a16: /* pextrd pextrq */ 6795 case 0x660f3a17: /* extractps */ 6796 case 0x660f7f: /* movdqa */ 6797 case 0xf30f7f: /* movdqu */ 6798 if (i386_record_modrm (&ir)) 6799 return -1; 6800 if (ir.mod == 3) 6801 { 6802 if (opcode == 0x0f13 || opcode == 0x660f13 6803 || opcode == 0x0f17 || opcode == 0x660f17) 6804 goto no_support; 6805 ir.rm |= ir.rex_b; 6806 if (!i386_xmm_regnum_p (gdbarch, 6807 I387_XMM0_REGNUM (tdep) + ir.rm)) 6808 goto no_support; 6809 record_arch_list_add_reg (ir.regcache, 6810 I387_XMM0_REGNUM (tdep) + ir.rm); 6811 } 6812 else 6813 { 6814 switch (opcode) 6815 { 6816 case 0x660f3a14: 6817 ir.ot = OT_BYTE; 6818 break; 6819 case 0x660f3a15: 6820 ir.ot = OT_WORD; 6821 break; 6822 case 0x660f3a16: 6823 ir.ot = OT_LONG; 6824 break; 6825 case 0x660f3a17: 6826 ir.ot = OT_QUAD; 6827 break; 6828 default: 6829 ir.ot = OT_DQUAD; 6830 break; 6831 } 6832 if (i386_record_lea_modrm (&ir)) 6833 return -1; 6834 } 6835 break; 6836 6837 case 0x0f2b: /* movntps */ 6838 case 0x660f2b: /* movntpd */ 6839 case 0x0fe7: /* movntq */ 6840 case 0x660fe7: /* movntdq */ 6841 if (ir.mod == 3) 6842 goto no_support; 6843 if (opcode == 0x0fe7) 6844 ir.ot = OT_QUAD; 6845 else 6846 ir.ot = OT_DQUAD; 6847 if (i386_record_lea_modrm (&ir)) 6848 return -1; 6849 break; 6850 6851 case 0xf30f2c: /* cvttss2si */ 6852 case 0xf20f2c: /* cvttsd2si */ 6853 case 0xf30f2d: /* cvtss2si */ 6854 case 0xf20f2d: /* cvtsd2si */ 6855 case 0xf20f38f0: /* crc32 */ 6856 case 0xf20f38f1: /* crc32 */ 6857 case 0x0f50: /* movmskps */ 6858 case 0x660f50: /* movmskpd */ 6859 case 0x0fc5: /* pextrw */ 6860 case 0x660fc5: /* pextrw */ 6861 case 0x0fd7: /* pmovmskb */ 6862 case 0x660fd7: /* pmovmskb */ 6863 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); 6864 break; 6865 6866 case 0x0f3800: /* pshufb */ 6867 case 0x0f3801: /* phaddw */ 6868 case 0x0f3802: /* phaddd */ 6869 case 0x0f3803: /* phaddsw */ 6870 case 0x0f3804: /* pmaddubsw */ 6871 case 0x0f3805: /* phsubw */ 6872 case 0x0f3806: /* phsubd */ 6873 case 0x0f3807: /* phsubsw */ 6874 case 0x0f3808: /* psignb */ 6875 case 0x0f3809: /* psignw */ 6876 case 0x0f380a: /* psignd */ 6877 case 0x0f380b: /* pmulhrsw */ 6878 case 0x0f381c: /* pabsb */ 6879 case 0x0f381d: /* pabsw */ 6880 case 0x0f381e: /* pabsd */ 6881 case 0x0f382b: /* packusdw */ 6882 case 0x0f3830: /* pmovzxbw */ 6883 case 0x0f3831: /* pmovzxbd */ 6884 case 0x0f3832: /* pmovzxbq */ 6885 case 0x0f3833: /* pmovzxwd */ 6886 case 0x0f3834: /* pmovzxwq */ 6887 case 0x0f3835: /* pmovzxdq */ 6888 case 0x0f3837: /* pcmpgtq */ 6889 case 0x0f3838: /* pminsb */ 6890 case 0x0f3839: /* pminsd */ 6891 case 0x0f383a: /* pminuw */ 6892 case 0x0f383b: /* pminud */ 6893 case 0x0f383c: /* pmaxsb */ 6894 case 0x0f383d: /* pmaxsd */ 6895 case 0x0f383e: /* pmaxuw */ 6896 case 0x0f383f: /* pmaxud */ 6897 case 0x0f3840: /* pmulld */ 6898 case 0x0f3841: /* phminposuw */ 6899 case 0x0f3a0f: /* palignr */ 6900 case 0x0f60: /* punpcklbw */ 6901 case 0x0f61: /* punpcklwd */ 6902 case 0x0f62: /* punpckldq */ 6903 case 0x0f63: /* packsswb */ 6904 case 0x0f64: /* pcmpgtb */ 6905 case 0x0f65: /* pcmpgtw */ 6906 case 0x0f66: /* pcmpgtd */ 6907 case 0x0f67: /* packuswb */ 6908 case 0x0f68: /* punpckhbw */ 6909 case 0x0f69: /* punpckhwd */ 6910 case 0x0f6a: /* punpckhdq */ 6911 case 0x0f6b: /* packssdw */ 6912 case 0x0f6e: /* movd */ 6913 case 0x0f6f: /* movq */ 6914 case 0x0f70: /* pshufw */ 6915 case 0x0f74: /* pcmpeqb */ 6916 case 0x0f75: /* pcmpeqw */ 6917 case 0x0f76: /* pcmpeqd */ 6918 case 0x0fc4: /* pinsrw */ 6919 case 0x0fd1: /* psrlw */ 6920 case 0x0fd2: /* psrld */ 6921 case 0x0fd3: /* psrlq */ 6922 case 0x0fd4: /* paddq */ 6923 case 0x0fd5: /* pmullw */ 6924 case 0xf20fd6: /* movdq2q */ 6925 case 0x0fd8: /* psubusb */ 6926 case 0x0fd9: /* psubusw */ 6927 case 0x0fda: /* pminub */ 6928 case 0x0fdb: /* pand */ 6929 case 0x0fdc: /* paddusb */ 6930 case 0x0fdd: /* paddusw */ 6931 case 0x0fde: /* pmaxub */ 6932 case 0x0fdf: /* pandn */ 6933 case 0x0fe0: /* pavgb */ 6934 case 0x0fe1: /* psraw */ 6935 case 0x0fe2: /* psrad */ 6936 case 0x0fe3: /* pavgw */ 6937 case 0x0fe4: /* pmulhuw */ 6938 case 0x0fe5: /* pmulhw */ 6939 case 0x0fe8: /* psubsb */ 6940 case 0x0fe9: /* psubsw */ 6941 case 0x0fea: /* pminsw */ 6942 case 0x0feb: /* por */ 6943 case 0x0fec: /* paddsb */ 6944 case 0x0fed: /* paddsw */ 6945 case 0x0fee: /* pmaxsw */ 6946 case 0x0fef: /* pxor */ 6947 case 0x0ff1: /* psllw */ 6948 case 0x0ff2: /* pslld */ 6949 case 0x0ff3: /* psllq */ 6950 case 0x0ff4: /* pmuludq */ 6951 case 0x0ff5: /* pmaddwd */ 6952 case 0x0ff6: /* psadbw */ 6953 case 0x0ff8: /* psubb */ 6954 case 0x0ff9: /* psubw */ 6955 case 0x0ffa: /* psubd */ 6956 case 0x0ffb: /* psubq */ 6957 case 0x0ffc: /* paddb */ 6958 case 0x0ffd: /* paddw */ 6959 case 0x0ffe: /* paddd */ 6960 if (i386_record_modrm (&ir)) 6961 return -1; 6962 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) 6963 goto no_support; 6964 record_arch_list_add_reg (ir.regcache, 6965 I387_MM0_REGNUM (tdep) + ir.reg); 6966 break; 6967 6968 case 0x0f71: /* psllw */ 6969 case 0x0f72: /* pslld */ 6970 case 0x0f73: /* psllq */ 6971 if (i386_record_modrm (&ir)) 6972 return -1; 6973 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) 6974 goto no_support; 6975 record_arch_list_add_reg (ir.regcache, 6976 I387_MM0_REGNUM (tdep) + ir.rm); 6977 break; 6978 6979 case 0x660f71: /* psllw */ 6980 case 0x660f72: /* pslld */ 6981 case 0x660f73: /* psllq */ 6982 if (i386_record_modrm (&ir)) 6983 return -1; 6984 ir.rm |= ir.rex_b; 6985 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) 6986 goto no_support; 6987 record_arch_list_add_reg (ir.regcache, 6988 I387_XMM0_REGNUM (tdep) + ir.rm); 6989 break; 6990 6991 case 0x0f7e: /* movd */ 6992 case 0x660f7e: /* movd */ 6993 if (i386_record_modrm (&ir)) 6994 return -1; 6995 if (ir.mod == 3) 6996 I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 6997 else 6998 { 6999 if (ir.dflag == 2) 7000 ir.ot = OT_QUAD; 7001 else 7002 ir.ot = OT_LONG; 7003 if (i386_record_lea_modrm (&ir)) 7004 return -1; 7005 } 7006 break; 7007 7008 case 0x0f7f: /* movq */ 7009 if (i386_record_modrm (&ir)) 7010 return -1; 7011 if (ir.mod == 3) 7012 { 7013 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) 7014 goto no_support; 7015 record_arch_list_add_reg (ir.regcache, 7016 I387_MM0_REGNUM (tdep) + ir.rm); 7017 } 7018 else 7019 { 7020 ir.ot = OT_QUAD; 7021 if (i386_record_lea_modrm (&ir)) 7022 return -1; 7023 } 7024 break; 7025 7026 case 0xf30fb8: /* popcnt */ 7027 if (i386_record_modrm (&ir)) 7028 return -1; 7029 I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); 7030 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7031 break; 7032 7033 case 0x660fd6: /* movq */ 7034 if (i386_record_modrm (&ir)) 7035 return -1; 7036 if (ir.mod == 3) 7037 { 7038 ir.rm |= ir.rex_b; 7039 if (!i386_xmm_regnum_p (gdbarch, 7040 I387_XMM0_REGNUM (tdep) + ir.rm)) 7041 goto no_support; 7042 record_arch_list_add_reg (ir.regcache, 7043 I387_XMM0_REGNUM (tdep) + ir.rm); 7044 } 7045 else 7046 { 7047 ir.ot = OT_QUAD; 7048 if (i386_record_lea_modrm (&ir)) 7049 return -1; 7050 } 7051 break; 7052 7053 case 0x660f3817: /* ptest */ 7054 case 0x0f2e: /* ucomiss */ 7055 case 0x660f2e: /* ucomisd */ 7056 case 0x0f2f: /* comiss */ 7057 case 0x660f2f: /* comisd */ 7058 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7059 break; 7060 7061 case 0x0ff7: /* maskmovq */ 7062 regcache_raw_read_unsigned (ir.regcache, 7063 ir.regmap[X86_RECORD_REDI_REGNUM], 7064 &addr); 7065 if (record_arch_list_add_mem (addr, 64)) 7066 return -1; 7067 break; 7068 7069 case 0x660ff7: /* maskmovdqu */ 7070 regcache_raw_read_unsigned (ir.regcache, 7071 ir.regmap[X86_RECORD_REDI_REGNUM], 7072 &addr); 7073 if (record_arch_list_add_mem (addr, 128)) 7074 return -1; 7075 break; 7076 7077 default: 7078 goto no_support; 7079 break; 7080 } 7081 break; 7082 7083 default: 7084 goto no_support; 7085 break; 7086 } 7087 7088 /* In the future, maybe still need to deal with need_dasm. */ 7089 I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); 7090 if (record_arch_list_add_end ()) 7091 return -1; 7092 7093 return 0; 7094 7095 no_support: 7096 printf_unfiltered (_("Process record does not support instruction 0x%02x " 7097 "at address %s.\n"), 7098 (unsigned int) (opcode), 7099 paddress (gdbarch, ir.orig_addr)); 7100 return -1; 7101 } 7102 7103 static const int i386_record_regmap[] = 7104 { 7105 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, 7106 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, 7107 0, 0, 0, 0, 0, 0, 0, 0, 7108 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, 7109 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM 7110 }; 7111 7112 /* Check that the given address appears suitable for a fast 7113 tracepoint, which on x86-64 means that we need an instruction of at 7114 least 5 bytes, so that we can overwrite it with a 4-byte-offset 7115 jump and not have to worry about program jumps to an address in the 7116 middle of the tracepoint jump. On x86, it may be possible to use 7117 4-byte jumps with a 2-byte offset to a trampoline located in the 7118 bottom 64 KiB of memory. Returns 1 if OK, and writes a size 7119 of instruction to replace, and 0 if not, plus an explanatory 7120 string. */ 7121 7122 static int 7123 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, 7124 CORE_ADDR addr, int *isize, char **msg) 7125 { 7126 int len, jumplen; 7127 static struct ui_file *gdb_null = NULL; 7128 7129 /* Ask the target for the minimum instruction length supported. */ 7130 jumplen = target_get_min_fast_tracepoint_insn_len (); 7131 7132 if (jumplen < 0) 7133 { 7134 /* If the target does not support the get_min_fast_tracepoint_insn_len 7135 operation, assume that fast tracepoints will always be implemented 7136 using 4-byte relative jumps on both x86 and x86-64. */ 7137 jumplen = 5; 7138 } 7139 else if (jumplen == 0) 7140 { 7141 /* If the target does support get_min_fast_tracepoint_insn_len but 7142 returns zero, then the IPA has not loaded yet. In this case, 7143 we optimistically assume that truncated 2-byte relative jumps 7144 will be available on x86, and compensate later if this assumption 7145 turns out to be incorrect. On x86-64 architectures, 4-byte relative 7146 jumps will always be used. */ 7147 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; 7148 } 7149 7150 /* Dummy file descriptor for the disassembler. */ 7151 if (!gdb_null) 7152 gdb_null = ui_file_new (); 7153 7154 /* Check for fit. */ 7155 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); 7156 if (isize) 7157 *isize = len; 7158 7159 if (len < jumplen) 7160 { 7161 /* Return a bit of target-specific detail to add to the caller's 7162 generic failure message. */ 7163 if (msg) 7164 *msg = xstrprintf (_("; instruction is only %d bytes long, " 7165 "need at least %d bytes for the jump"), 7166 len, jumplen); 7167 return 0; 7168 } 7169 else 7170 { 7171 if (msg) 7172 *msg = NULL; 7173 return 1; 7174 } 7175 } 7176 7177 static int 7178 i386_validate_tdesc_p (struct gdbarch_tdep *tdep, 7179 struct tdesc_arch_data *tdesc_data) 7180 { 7181 const struct target_desc *tdesc = tdep->tdesc; 7182 const struct tdesc_feature *feature_core; 7183 const struct tdesc_feature *feature_sse, *feature_avx; 7184 int i, num_regs, valid_p; 7185 7186 if (! tdesc_has_registers (tdesc)) 7187 return 0; 7188 7189 /* Get core registers. */ 7190 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); 7191 if (feature_core == NULL) 7192 return 0; 7193 7194 /* Get SSE registers. */ 7195 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); 7196 7197 /* Try AVX registers. */ 7198 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); 7199 7200 valid_p = 1; 7201 7202 /* The XCR0 bits. */ 7203 if (feature_avx) 7204 { 7205 /* AVX register description requires SSE register description. */ 7206 if (!feature_sse) 7207 return 0; 7208 7209 tdep->xcr0 = I386_XSTATE_AVX_MASK; 7210 7211 /* It may have been set by OSABI initialization function. */ 7212 if (tdep->num_ymm_regs == 0) 7213 { 7214 tdep->ymmh_register_names = i386_ymmh_names; 7215 tdep->num_ymm_regs = 8; 7216 tdep->ymm0h_regnum = I386_YMM0H_REGNUM; 7217 } 7218 7219 for (i = 0; i < tdep->num_ymm_regs; i++) 7220 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, 7221 tdep->ymm0h_regnum + i, 7222 tdep->ymmh_register_names[i]); 7223 } 7224 else if (feature_sse) 7225 tdep->xcr0 = I386_XSTATE_SSE_MASK; 7226 else 7227 { 7228 tdep->xcr0 = I386_XSTATE_X87_MASK; 7229 tdep->num_xmm_regs = 0; 7230 } 7231 7232 num_regs = tdep->num_core_regs; 7233 for (i = 0; i < num_regs; i++) 7234 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, 7235 tdep->register_names[i]); 7236 7237 if (feature_sse) 7238 { 7239 /* Need to include %mxcsr, so add one. */ 7240 num_regs += tdep->num_xmm_regs + 1; 7241 for (; i < num_regs; i++) 7242 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, 7243 tdep->register_names[i]); 7244 } 7245 7246 return valid_p; 7247 } 7248 7249 7250 static struct gdbarch * 7251 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 7252 { 7253 struct gdbarch_tdep *tdep; 7254 struct gdbarch *gdbarch; 7255 struct tdesc_arch_data *tdesc_data; 7256 const struct target_desc *tdesc; 7257 int mm0_regnum; 7258 int ymm0_regnum; 7259 7260 /* If there is already a candidate, use it. */ 7261 arches = gdbarch_list_lookup_by_info (arches, &info); 7262 if (arches != NULL) 7263 return arches->gdbarch; 7264 7265 /* Allocate space for the new architecture. */ 7266 tdep = XCALLOC (1, struct gdbarch_tdep); 7267 gdbarch = gdbarch_alloc (&info, tdep); 7268 7269 /* General-purpose registers. */ 7270 tdep->gregset = NULL; 7271 tdep->gregset_reg_offset = NULL; 7272 tdep->gregset_num_regs = I386_NUM_GREGS; 7273 tdep->sizeof_gregset = 0; 7274 7275 /* Floating-point registers. */ 7276 tdep->fpregset = NULL; 7277 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; 7278 7279 tdep->xstateregset = NULL; 7280 7281 /* The default settings include the FPU registers, the MMX registers 7282 and the SSE registers. This can be overridden for a specific ABI 7283 by adjusting the members `st0_regnum', `mm0_regnum' and 7284 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers 7285 will show up in the output of "info all-registers". */ 7286 7287 tdep->st0_regnum = I386_ST0_REGNUM; 7288 7289 /* I386_NUM_XREGS includes %mxcsr, so substract one. */ 7290 tdep->num_xmm_regs = I386_NUM_XREGS - 1; 7291 7292 tdep->jb_pc_offset = -1; 7293 tdep->struct_return = pcc_struct_return; 7294 tdep->sigtramp_start = 0; 7295 tdep->sigtramp_end = 0; 7296 tdep->sigtramp_p = i386_sigtramp_p; 7297 tdep->sigcontext_addr = NULL; 7298 tdep->sc_reg_offset = NULL; 7299 tdep->sc_pc_offset = -1; 7300 tdep->sc_sp_offset = -1; 7301 7302 tdep->xsave_xcr0_offset = -1; 7303 7304 tdep->record_regmap = i386_record_regmap; 7305 7306 set_gdbarch_long_long_align_bit (gdbarch, 32); 7307 7308 /* The format used for `long double' on almost all i386 targets is 7309 the i387 extended floating-point format. In fact, of all targets 7310 in the GCC 2.95 tree, only OSF/1 does it different, and insists 7311 on having a `long double' that's not `long' at all. */ 7312 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); 7313 7314 /* Although the i387 extended floating-point has only 80 significant 7315 bits, a `long double' actually takes up 96, probably to enforce 7316 alignment. */ 7317 set_gdbarch_long_double_bit (gdbarch, 96); 7318 7319 /* Register numbers of various important registers. */ 7320 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ 7321 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ 7322 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ 7323 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ 7324 7325 /* NOTE: kettenis/20040418: GCC does have two possible register 7326 numbering schemes on the i386: dbx and SVR4. These schemes 7327 differ in how they number %ebp, %esp, %eflags, and the 7328 floating-point registers, and are implemented by the arrays 7329 dbx_register_map[] and svr4_dbx_register_map in 7330 gcc/config/i386.c. GCC also defines a third numbering scheme in 7331 gcc/config/i386.c, which it designates as the "default" register 7332 map used in 64bit mode. This last register numbering scheme is 7333 implemented in dbx64_register_map, and is used for AMD64; see 7334 amd64-tdep.c. 7335 7336 Currently, each GCC i386 target always uses the same register 7337 numbering scheme across all its supported debugging formats 7338 i.e. SDB (COFF), stabs and DWARF 2. This is because 7339 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the 7340 DBX_REGISTER_NUMBER macro which is defined by each target's 7341 respective config header in a manner independent of the requested 7342 output debugging format. 7343 7344 This does not match the arrangement below, which presumes that 7345 the SDB and stabs numbering schemes differ from the DWARF and 7346 DWARF 2 ones. The reason for this arrangement is that it is 7347 likely to get the numbering scheme for the target's 7348 default/native debug format right. For targets where GCC is the 7349 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for 7350 targets where the native toolchain uses a different numbering 7351 scheme for a particular debug format (stabs-in-ELF on Solaris) 7352 the defaults below will have to be overridden, like 7353 i386_elf_init_abi() does. */ 7354 7355 /* Use the dbx register numbering scheme for stabs and COFF. */ 7356 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); 7357 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); 7358 7359 /* Use the SVR4 register numbering scheme for DWARF 2. */ 7360 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); 7361 7362 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to 7363 be in use on any of the supported i386 targets. */ 7364 7365 set_gdbarch_print_float_info (gdbarch, i387_print_float_info); 7366 7367 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); 7368 7369 /* Call dummy code. */ 7370 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); 7371 set_gdbarch_frame_align (gdbarch, i386_frame_align); 7372 7373 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); 7374 set_gdbarch_register_to_value (gdbarch, i386_register_to_value); 7375 set_gdbarch_value_to_register (gdbarch, i386_value_to_register); 7376 7377 set_gdbarch_return_value (gdbarch, i386_return_value); 7378 7379 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); 7380 7381 /* Stack grows downward. */ 7382 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 7383 7384 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); 7385 set_gdbarch_decr_pc_after_break (gdbarch, 1); 7386 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); 7387 7388 set_gdbarch_frame_args_skip (gdbarch, 8); 7389 7390 set_gdbarch_print_insn (gdbarch, i386_print_insn); 7391 7392 set_gdbarch_dummy_id (gdbarch, i386_dummy_id); 7393 7394 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); 7395 7396 /* Add the i386 register groups. */ 7397 i386_add_reggroups (gdbarch); 7398 tdep->register_reggroup_p = i386_register_reggroup_p; 7399 7400 /* Helper for function argument information. */ 7401 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); 7402 7403 /* Hook the function epilogue frame unwinder. This unwinder is 7404 appended to the list first, so that it supercedes the DWARF 7405 unwinder in function epilogues (where the DWARF unwinder 7406 currently fails). */ 7407 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); 7408 7409 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended 7410 to the list before the prologue-based unwinders, so that DWARF 7411 CFI info will be used if it is available. */ 7412 dwarf2_append_unwinders (gdbarch); 7413 7414 frame_base_set_default (gdbarch, &i386_frame_base); 7415 7416 /* Pseudo registers may be changed by amd64_init_abi. */ 7417 set_gdbarch_pseudo_register_read_value (gdbarch, 7418 i386_pseudo_register_read_value); 7419 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); 7420 7421 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); 7422 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); 7423 7424 /* Override the normal target description method to make the AVX 7425 upper halves anonymous. */ 7426 set_gdbarch_register_name (gdbarch, i386_register_name); 7427 7428 /* Even though the default ABI only includes general-purpose registers, 7429 floating-point registers and the SSE registers, we have to leave a 7430 gap for the upper AVX registers. */ 7431 set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS); 7432 7433 /* Get the x86 target description from INFO. */ 7434 tdesc = info.target_desc; 7435 if (! tdesc_has_registers (tdesc)) 7436 tdesc = tdesc_i386; 7437 tdep->tdesc = tdesc; 7438 7439 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; 7440 tdep->register_names = i386_register_names; 7441 7442 /* No upper YMM registers. */ 7443 tdep->ymmh_register_names = NULL; 7444 tdep->ymm0h_regnum = -1; 7445 7446 tdep->num_byte_regs = 8; 7447 tdep->num_word_regs = 8; 7448 tdep->num_dword_regs = 0; 7449 tdep->num_mmx_regs = 8; 7450 tdep->num_ymm_regs = 0; 7451 7452 tdesc_data = tdesc_data_alloc (); 7453 7454 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); 7455 7456 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); 7457 7458 /* Hook in ABI-specific overrides, if they have been registered. */ 7459 info.tdep_info = (void *) tdesc_data; 7460 gdbarch_init_osabi (info, gdbarch); 7461 7462 if (!i386_validate_tdesc_p (tdep, tdesc_data)) 7463 { 7464 tdesc_data_cleanup (tdesc_data); 7465 xfree (tdep); 7466 gdbarch_free (gdbarch); 7467 return NULL; 7468 } 7469 7470 /* Wire in pseudo registers. Number of pseudo registers may be 7471 changed. */ 7472 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs 7473 + tdep->num_word_regs 7474 + tdep->num_dword_regs 7475 + tdep->num_mmx_regs 7476 + tdep->num_ymm_regs)); 7477 7478 /* Target description may be changed. */ 7479 tdesc = tdep->tdesc; 7480 7481 tdesc_use_registers (gdbarch, tdesc, tdesc_data); 7482 7483 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ 7484 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); 7485 7486 /* Make %al the first pseudo-register. */ 7487 tdep->al_regnum = gdbarch_num_regs (gdbarch); 7488 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; 7489 7490 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; 7491 if (tdep->num_dword_regs) 7492 { 7493 /* Support dword pseudo-register if it hasn't been disabled. */ 7494 tdep->eax_regnum = ymm0_regnum; 7495 ymm0_regnum += tdep->num_dword_regs; 7496 } 7497 else 7498 tdep->eax_regnum = -1; 7499 7500 mm0_regnum = ymm0_regnum; 7501 if (tdep->num_ymm_regs) 7502 { 7503 /* Support YMM pseudo-register if it is available. */ 7504 tdep->ymm0_regnum = ymm0_regnum; 7505 mm0_regnum += tdep->num_ymm_regs; 7506 } 7507 else 7508 tdep->ymm0_regnum = -1; 7509 7510 if (tdep->num_mmx_regs != 0) 7511 { 7512 /* Support MMX pseudo-register if MMX hasn't been disabled. */ 7513 tdep->mm0_regnum = mm0_regnum; 7514 } 7515 else 7516 tdep->mm0_regnum = -1; 7517 7518 /* Hook in the legacy prologue-based unwinders last (fallback). */ 7519 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); 7520 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); 7521 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); 7522 7523 /* If we have a register mapping, enable the generic core file 7524 support, unless it has already been enabled. */ 7525 if (tdep->gregset_reg_offset 7526 && !gdbarch_regset_from_core_section_p (gdbarch)) 7527 set_gdbarch_regset_from_core_section (gdbarch, 7528 i386_regset_from_core_section); 7529 7530 set_gdbarch_skip_permanent_breakpoint (gdbarch, 7531 i386_skip_permanent_breakpoint); 7532 7533 set_gdbarch_fast_tracepoint_valid_at (gdbarch, 7534 i386_fast_tracepoint_valid_at); 7535 7536 return gdbarch; 7537 } 7538 7539 static enum gdb_osabi 7540 i386_coff_osabi_sniffer (bfd *abfd) 7541 { 7542 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 7543 || strcmp (bfd_get_target (abfd), "coff-go32") == 0) 7544 return GDB_OSABI_GO32; 7545 7546 return GDB_OSABI_UNKNOWN; 7547 } 7548 7549 7550 /* Provide a prototype to silence -Wmissing-prototypes. */ 7551 void _initialize_i386_tdep (void); 7552 7553 void 7554 _initialize_i386_tdep (void) 7555 { 7556 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); 7557 7558 /* Add the variable that controls the disassembly flavor. */ 7559 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, 7560 &disassembly_flavor, _("\ 7561 Set the disassembly flavor."), _("\ 7562 Show the disassembly flavor."), _("\ 7563 The valid values are \"att\" and \"intel\", and the default value is \"att\"."), 7564 NULL, 7565 NULL, /* FIXME: i18n: */ 7566 &setlist, &showlist); 7567 7568 /* Add the variable that controls the convention for returning 7569 structs. */ 7570 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, 7571 &struct_convention, _("\ 7572 Set the convention for returning small structs."), _("\ 7573 Show the convention for returning small structs."), _("\ 7574 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ 7575 is \"default\"."), 7576 NULL, 7577 NULL, /* FIXME: i18n: */ 7578 &setlist, &showlist); 7579 7580 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, 7581 i386_coff_osabi_sniffer); 7582 7583 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, 7584 i386_svr4_init_abi); 7585 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, 7586 i386_go32_init_abi); 7587 7588 /* Initialize the i386-specific register groups. */ 7589 i386_init_reggroups (); 7590 7591 /* Initialize the standard target descriptions. */ 7592 initialize_tdesc_i386 (); 7593 initialize_tdesc_i386_mmx (); 7594 initialize_tdesc_i386_avx (); 7595 7596 /* Tell remote stub that we support XML target description. */ 7597 register_remote_support_xml ("i386"); 7598 } 7599