1.\" Copyright (c) 2001-2008, Intel Corporation 2.\" All rights reserved. 3.\" 4.\" Redistribution and use in source and binary forms, with or without 5.\" modification, are permitted provided that the following conditions are met: 6.\" 7.\" 1. Redistributions of source code must retain the above copyright notice, 8.\" this list of conditions and the following disclaimer. 9.\" 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 14.\" 3. Neither the name of the Intel Corporation nor the names of its 15.\" contributors may be used to endorse or promote products derived from 16.\" this software without specific prior written permission. 17.\" 18.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19.\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 22.\" LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28.\" POSSIBILITY OF SUCH DAMAGE. 29.\" 30.\" * Other names and brands may be claimed as the property of others. 31.\" 32.\" $FreeBSD: src/share/man/man4/ixgbe.4,v 1.2 2008/06/17 21:14:02 brueffer Exp $ 33.\" 34.Dd May 11, 2014 35.Dt IX 4 36.Os 37.Sh NAME 38.Nm ix 39.Nd "Intel(R) 10Gb Ethernet driver" 40.Sh SYNOPSIS 41To compile this driver into the kernel, 42place the following line in your 43kernel configuration file: 44.Bd -ragged -offset indent 45.Cd "device ix" 46.Ed 47.Pp 48Alternatively, to load the driver as a 49module at boot time, place the following line in 50.Xr loader.conf 5 : 51.Bd -literal -offset indent 52if_ix_load="YES" 53.Ed 54.Sh DESCRIPTION 55The 56.Nm 57driver provides support for PCI Express 10Gb Ethernet adapters based on 58the Intel 5982598, 6082599, 61and 62X540 63Ethernet controller chips. 64The 65.Nm 66driver supports: 67.Pp 68.Bl -item -offset indent -compact 69.It 70Transmit/Receive checksum offload for IP/UDP/TCP. 71.\"Jumbo Frames. 72.It 73Interrupt moderation 74.It 75TCP segmentation offload (TSO) 76.It 77Receive side scaling (RSS) 78.It 79Multiple tranmission queues 80.It 81Multiple vector MSI-X 82.It 83VLAN tag stripping and inserting 84.El 85.Pp 86If 87.Xr polling 4 88or MSI-X is used, 89by default, 90the 91.Nm 92driver will try enabling as many reception queues and transmission queues 93as are allowed by the number of CPUs in the system. 94.Pp 95If multiple transmission queues are used, 96the round-robin arbitration is performed among the transmission queues. 97And if both TSO and multiple tranmission queues are used, 98the round-robin arbitration between transmission queues is done at the 99TCP segment boundary after the hardware segmentation is performed. 100.Pp 10182598 supports 16 reception queues and 32 transmission queues. 102MSI-X is not enabled due to hardware errata. 103Under MSI or legacy interrupt mode, 1042 reception queues are enabled for hardware RSS hash 105and only 1 transmission queue is enable. 106.Pp 10782599 and X540 supports 16 reception queues and 64 transmission queues. 108MSI-X is enable by default. 109However, 110due to the number of MSI-X vectors is 64, 111at most 16 reception queues and 32 transmission queues will be enabled 112under MSI-X mode. 113.Pp 114For more information on configuring this device, see 115.Xr ifconfig 8 . 116The 117.Nm 118driver supports 119.Xr polling 4 . 120.Sh HARDWARE 121The 122.Nm 123driver supports Gigabit Ethernet adapters based on the Intel 12482598, 12582599, 126and 127X540 128controller chips: 129.Pp 130.Bl -bullet -compact 131.It 132Intel 10 Gigabit AF DA Dual Port Server Adapter 133.It 134Intel 10 Gigabit AT Server Adapter 135.It 136Intel 10 Gigabit AT2 Server Adapter 137.It 138Intel 10 Gigabit CX4 Dual Port Server Adapter 139.It 140Intel 10 Gigabit XF LR Server Adapter 141.It 142Intel 10 Gigabit XF SR Dual Port Server Adapter 143.It 144Intel 10 Gigabit XF SR Server Adapter 145.It 146Intel 82598 10 Gigabit Ethernet Controller 147.It 148Intel 82599 10 Gigabit Ethernet Controller 149.It 150Intel Ethernet Controller X540-AT2 151.It 152Intel Ethernet Converged Network Adapter X520 Series 153.It 154Intel Ethernet Converged Network Adapter X540-T1 155.It 156Intel Ethernet Converged Network Adapter X540-T2 157.It 158Intel Ethernet Server Adapter X520 Series 159.It 160Intel Ethernet Server Adapter X520-DA2 161.It 162Intel Ethernet Server Adapter X520-LR1 163.It 164Intel Ethernet Server Adapter X520-SR1 165.It 166Intel Ethernet Server Adapter X520-SR2 167.It 168Intel Ethernet Server Adapter X520-T2 169.El 170.Sh TUNABLES 171Tunables can be set at the 172.Xr loader 8 173prompt before booting the kernel or stored in 174.Xr loader.conf 5 . 175.Em X 176is the device unit number. 177.Bl -tag -width ".Va hw.ixX.unsupported_sfp" 178.It Va hw.ix.rxd Va hw.ixX.rxd 179Number of receive descriptors allocated by the driver. 180The default value is 2048. 181The minimum is 64, 182and the maximum is 4096. 183.It Va hw.ix.txd Va hw.ixX.txd 184Number of transmit descriptors allocated by the driver. 185The default value is 2048. 186The minimum is 64, 187and the maximum is 4096. 188.It Va hw.ix.rxr Va hw.ixX.rxr 189This tunable specifies the number of reception queues could be enabled. 190Maximum allowed value for these tunables is device specific 191and it must be power of 2 aligned. 192Setting these tunables to 0 allows the driver to make 193as many reception queues ready-for-use as allowed by the number of CPUs. 194.It Va hw.ix.txr Va hw.ixX.txr 195This tunable specifies the number of transmission queues could be enabled. 196Maximum allowed value for these tunables is device specific 197and it must be power of 2 aligned. 198Setting these tunables to 0 allows the driver to make 199as many transmission queues ready-for-use as allowed by the number of CPUs. 200.It Va hw.ix.msix.enable Va hw.ixX.msix.enable 201By default, 202the driver will use MSI-X if it is supported. 203This behaviour can be turned off by setting this tunable to 0. 204.It Va hw.ix.msix.agg_rxtx Va hw.ixX.msix.agg_rxtx 205If MSI-X is used, 206the driver aggregates transmission queue and reception queue processing 207by default. 208This behaviour could be turned off by setting this tunable to 0. 209If the number of MSI-X vectors is not enough to 210put transmission queue processing and reception queue processing 211onto independent MSI-X vector, 212then transmission queue and reception queue processing are always 213aggregated. 214.It Va hw.ixX.msix.off 215If MSI-X is used, 216and transmission queue and reception queue processing are aggregated, 217this tunable specifies the leading target CPU for 218transmission and reception queues processing. 219The value specificed must be aligned to the maximum of 220the number of reception queues 221and the number of transmission queues enabled, 222and must be less than the power of 2 number of CPUs. 223.It Va hw.ixX.msix.rxoff 224If MSI-X is used, 225and transmission queue and reception queue processing are not aggregated, 226this tunable specifies the leading target CPU for reception queues processing. 227The value specificed must be aligned to the number of reception queues enabled 228and must be less than the power of 2 number of CPUs. 229.It Va hw.ixX.msix.txoff 230If MSI-X is used, 231and transmission queue and reception queue processing are not aggregated, 232this tunable specifies the leading target CPU 233for transmission queues processing. 234The value specificed must be aligned to 235the number of transmission queues enabled 236and must be less than the power of 2 number of CPUs. 237.It Va hw.ix.msi.enable Va hw.ixX.msi.enable 238If MSI-X is disabled and MSI is supported, 239the driver will use MSI. 240This behavior can be turned off by setting this tunable to 0. 241.It Va hw.ixX.msi.cpu 242If MSI is used, 243it specifies the MSI's target CPU. 244.It Va hw.ixX.npoll.txoff 245This tunable specifies the leading target CPU for 246transmission queue 247.Xr polling 4 248processing. 249The value specificed must be aligned to the number of transmission queues 250enabled and must be less than the power of 2 number of CPUs. 251.It Va hw.ixX.npoll.rxoff 252This tunable specifies the leading target CPU for 253reception queue 254.Xr polling 4 255processing. 256The value specificed must be aligned to the number of reception queues 257enabled and must be less than the power of 2 number of CPUs. 258.It Va hw.ix.unsupported_sfp 259By default, 260this driver does not allow "unsupported" SFP modules. 261This behavior can be changed by setting this tunable to 1. 262.El 263.Sh MIB Variables 264A number of per-interface variables are implemented in the 265.Va hw.ix Ns Em X 266branch of the 267.Xr sysctl 3 268MIB. 269.Bl -tag -width "rxtx_intr_rate" 270.It Va rxr 271Number of reception queues could be enabled (read-only). 272Use the tunable 273.Va hw.ix.rxr 274or 275.Va hw.ixX.rxr 276to configure it. 277.It Va rxr_inuse 278Number of reception queues being used (read-only). 279.It Va txr 280Number of transmission queues could be enabled (read-only). 281Use the tunable 282.Va hw.ix.txr 283or 284.Va hw.ixX.txr 285to configure it. 286.It Va txr_inuse 287Number of transmission queues being used (read-only). 288.It Va rxd 289Number of descriptors per reception queue (read-only). 290Use the tunable 291.Va hw.ix.rxd 292or 293.Va hw.ixX.rxd 294to configure it. 295.It Va txd 296Number of descriptors per transmission queue (read-only). 297Use the tunable 298.Va hw.ix.txd 299or 300.Va hw.ixX.txd 301to configure it. 302.It Va rxtx_intr_rate 303If MSI or legacy interrupt is used, 304this sysctl controls the highest possible frequency 305that interrupt could be generated by the device. 306If MSI-X is used, 307this sysctl controls the highest possible frequency 308that interrupt could be generated by the MSI-X vectors, 309which aggregate transmission queue and reception queue procecssing. 310It is 8000 by default (125us). 311.It Va rx_intr_rate 312If MSI-X is used, 313this sysctl controls the highest possible frequency 314that interrupt could be generated by the MSI-X vectors, 315which only process reception queue. 316It is 8000 by default (125us). 317.It Va tx_intr_rate 318If MSI-X is used, 319this sysctl controls the highest possible frequency 320that interrupt could be generated by the MSI-X vectors, 321which only process transmission queue. 322It is 6000 by default (~150us). 323.It Va sts_intr_rate 324If MSI-X is used, 325this sysctl controls the highest possible frequency 326that interrupt could be generated by the MSI-X vectors, 327which only process chip status changes. 328It is 8000 by default (125us). 329.It Va tx_intr_nsegs 330Transmission interrupt is asked to be generated upon every 331.Va tx_intr_nsegs 332transmission descritors having been setup. 333The default value is 1/16 of the number of transmission descriptors per queue. 334.It Va tx_wreg_nsegs 335The number of transmission descriptors should be setup 336before the hardware register is written. 337Setting this value too high will have negative effect 338on transmission timeliness. 339Setting this value too low will hurt overall transmission performance 340due to the frequent hardware register writing. 341The default value is 8. 342.It Va rx_wreg_nsegs 343The number of reception descriptors should be setup 344before the hardware register is written. 345Setting this value too high will make device drop incoming packets. 346Setting this value too low will hurt overall reception performance 347due to the frequent hardware register writing. 348The default value is 32. 349.It Va npoll_rxoff 350See the tunable 351.Va hw.ixX.npoll.rxoff . 352The set value will take effect the next time 353.Xr polling 4 354is enabled on the device. 355.It Va npoll_txoff 356See the tunable 357.Va hw.ixX.npoll.txoff . 358The set value will take effect the next time 359.Xr polling 4 360is enabled on the device. 361.It Va flowctrl 362Flow control setting. 363Set it to 0 to turn off flow control. 364Set it to 1 to enable only the reception of pause frames. 365Set it to 2 to enable only the generation of pause frames. 366Set it to 3 to enable both the reception of pause frames 367and generation of pause frames, 368i.e. full flow control. 369.El 370.Sh SEE ALSO 371.Xr altq 4 , 372.Xr arp 4 , 373.Xr ifmedia 4 , 374.Xr netintro 4 , 375.Xr ng_ether 4 , 376.Xr polling 4 , 377.Xr vlan 4 , 378.Xr ifconfig 8 379.Sh HISTORY 380The 381.Nm 382device driver first appeared in 383.Dx 3.1 . 384.Sh AUTHORS 385The 386.Nm 387driver was written by 388.An Intel Corporation Aq Mt freebsdnic@mailbox.intel.com . 389