1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $ 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.52 2008/06/05 18:06:31 swildner Exp $ 28 * 29 */ 30 31 #include "opt_bus.h" 32 #include "opt_pci.h" 33 34 #include "opt_compat_oldpci.h" 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/fcntl.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #include <sys/queue.h> 44 #include <sys/types.h> 45 #include <sys/buf.h> 46 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 #include <vm/vm_extern.h> 50 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <machine/smp.h> 54 #ifdef __i386__ 55 #include <bus/pci/i386/pci_cfgreg.h> 56 #endif 57 58 #include <sys/pciio.h> 59 #include "pcireg.h" 60 #include "pcivar.h" 61 #include "pci_private.h" 62 63 #include "pcib_if.h" 64 65 devclass_t pci_devclass; 66 const char *pcib_owner; 67 68 static void pci_read_capabilities(device_t dev, pcicfgregs *cfg); 69 static int pcie_slotimpl(const pcicfgregs *); 70 71 struct pci_quirk { 72 u_int32_t devid; /* Vendor/device of the card */ 73 int type; 74 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 75 int arg1; 76 int arg2; 77 }; 78 79 struct pci_quirk pci_quirks[] = { 80 /* 81 * The Intel 82371AB and 82443MX has a map register at offset 0x90. 82 */ 83 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 84 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 85 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 86 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 87 88 { 0 } 89 }; 90 91 /* map register information */ 92 #define PCI_MAPMEM 0x01 /* memory map */ 93 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 94 #define PCI_MAPPORT 0x04 /* port map */ 95 96 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 97 u_int32_t pci_numdevs = 0; 98 static u_int32_t pci_generation = 0; 99 100 device_t 101 pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func) 102 { 103 struct pci_devinfo *dinfo; 104 105 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 106 if ((dinfo->cfg.bus == bus) && 107 (dinfo->cfg.slot == slot) && 108 (dinfo->cfg.func == func)) { 109 return (dinfo->cfg.dev); 110 } 111 } 112 113 return (NULL); 114 } 115 116 device_t 117 pci_find_device(u_int16_t vendor, u_int16_t device) 118 { 119 struct pci_devinfo *dinfo; 120 121 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 122 if ((dinfo->cfg.vendor == vendor) && 123 (dinfo->cfg.device == device)) { 124 return (dinfo->cfg.dev); 125 } 126 } 127 128 return (NULL); 129 } 130 131 int 132 pcie_slot_implemented(device_t dev) 133 { 134 struct pci_devinfo *dinfo = device_get_ivars(dev); 135 136 return pcie_slotimpl(&dinfo->cfg); 137 } 138 139 /* return base address of memory or port map */ 140 141 static u_int32_t 142 pci_mapbase(unsigned mapreg) 143 { 144 int mask = 0x03; 145 if ((mapreg & 0x01) == 0) 146 mask = 0x0f; 147 return (mapreg & ~mask); 148 } 149 150 /* return map type of memory or port map */ 151 152 static int 153 pci_maptype(unsigned mapreg) 154 { 155 static u_int8_t maptype[0x10] = { 156 PCI_MAPMEM, PCI_MAPPORT, 157 PCI_MAPMEM, 0, 158 PCI_MAPMEM, PCI_MAPPORT, 159 0, 0, 160 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 161 PCI_MAPMEM|PCI_MAPMEMP, 0, 162 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 163 0, 0, 164 }; 165 166 return maptype[mapreg & 0x0f]; 167 } 168 169 /* return log2 of map size decoded for memory or port map */ 170 171 static int 172 pci_mapsize(unsigned testval) 173 { 174 int ln2size; 175 176 testval = pci_mapbase(testval); 177 ln2size = 0; 178 if (testval != 0) { 179 while ((testval & 1) == 0) 180 { 181 ln2size++; 182 testval >>= 1; 183 } 184 } 185 return (ln2size); 186 } 187 188 /* return log2 of address range supported by map register */ 189 190 static int 191 pci_maprange(unsigned mapreg) 192 { 193 int ln2range = 0; 194 switch (mapreg & 0x07) { 195 case 0x00: 196 case 0x01: 197 case 0x05: 198 ln2range = 32; 199 break; 200 case 0x02: 201 ln2range = 20; 202 break; 203 case 0x04: 204 ln2range = 64; 205 break; 206 } 207 return (ln2range); 208 } 209 210 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 211 212 static void 213 pci_fixancient(pcicfgregs *cfg) 214 { 215 if (cfg->hdrtype != 0) 216 return; 217 218 /* PCI to PCI bridges use header type 1 */ 219 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 220 cfg->hdrtype = 1; 221 } 222 223 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 224 225 static void * 226 pci_readppb(device_t pcib, int b, int s, int f) 227 { 228 pcih1cfgregs *p; 229 230 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 231 232 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2); 233 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2); 234 235 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1); 236 237 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f, 238 PCIR_IOBASEH_1, 2), 239 PCIB_READ_CONFIG(pcib, b, s, f, 240 PCIR_IOBASEL_1, 1)); 241 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f, 242 PCIR_IOLIMITH_1, 2), 243 PCIB_READ_CONFIG(pcib, b, s, f, 244 PCIR_IOLIMITL_1, 1)); 245 246 p->membase = PCI_PPBMEMBASE (0, 247 PCIB_READ_CONFIG(pcib, b, s, f, 248 PCIR_MEMBASE_1, 2)); 249 p->memlimit = PCI_PPBMEMLIMIT (0, 250 PCIB_READ_CONFIG(pcib, b, s, f, 251 PCIR_MEMLIMIT_1, 2)); 252 253 p->pmembase = PCI_PPBMEMBASE ( 254 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4), 255 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2)); 256 257 p->pmemlimit = PCI_PPBMEMLIMIT ( 258 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, 259 PCIR_PMLIMITH_1, 4), 260 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2)); 261 262 return (p); 263 } 264 265 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 266 267 static void * 268 pci_readpcb(device_t pcib, int b, int s, int f) 269 { 270 pcih2cfgregs *p; 271 272 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO); 273 274 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2); 275 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2); 276 277 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1); 278 279 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4); 280 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4); 281 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4); 282 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4); 283 284 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4); 285 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4); 286 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4); 287 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4); 288 289 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4); 290 return p; 291 } 292 293 /* extract header type specific config data */ 294 295 static void 296 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 297 { 298 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 299 switch (cfg->hdrtype) { 300 case 0: 301 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 302 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 303 cfg->nummaps = PCI_MAXMAPS_0; 304 break; 305 case 1: 306 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 307 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 308 cfg->secondarybus = REG(PCIR_SECBUS_1, 1); 309 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1); 310 cfg->nummaps = PCI_MAXMAPS_1; 311 cfg->hdrspec = pci_readppb(pcib, b, s, f); 312 break; 313 case 2: 314 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 315 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 316 cfg->secondarybus = REG(PCIR_SECBUS_2, 1); 317 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1); 318 cfg->nummaps = PCI_MAXMAPS_2; 319 cfg->hdrspec = pci_readpcb(pcib, b, s, f); 320 break; 321 } 322 #undef REG 323 } 324 325 /* read configuration header into pcicfgrect structure */ 326 327 struct pci_devinfo * 328 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 329 { 330 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 331 332 pcicfgregs *cfg = NULL; 333 struct pci_devinfo *devlist_entry; 334 struct devlist *devlist_head; 335 336 devlist_head = &pci_devq; 337 338 devlist_entry = NULL; 339 340 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 341 342 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 343 344 cfg = &devlist_entry->cfg; 345 346 cfg->bus = b; 347 cfg->slot = s; 348 cfg->func = f; 349 cfg->vendor = REG(PCIR_VENDOR, 2); 350 cfg->device = REG(PCIR_DEVICE, 2); 351 cfg->cmdreg = REG(PCIR_COMMAND, 2); 352 cfg->statreg = REG(PCIR_STATUS, 2); 353 cfg->baseclass = REG(PCIR_CLASS, 1); 354 cfg->subclass = REG(PCIR_SUBCLASS, 1); 355 cfg->progif = REG(PCIR_PROGIF, 1); 356 cfg->revid = REG(PCIR_REVID, 1); 357 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 358 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 359 cfg->lattimer = REG(PCIR_LATTIMER, 1); 360 cfg->intpin = REG(PCIR_INTPIN, 1); 361 cfg->intline = REG(PCIR_INTLINE, 1); 362 363 #ifdef APIC_IO 364 /* 365 * If using the APIC the intpin is probably wrong, since it 366 * is often setup by the BIOS with the PIC in mind. 367 */ 368 if (cfg->intpin != 0) { 369 int airq; 370 371 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 372 if (airq >= 0) { 373 /* PCI specific entry found in MP table */ 374 if (airq != cfg->intline) { 375 undirect_pci_irq(cfg->intline); 376 cfg->intline = airq; 377 } 378 } else { 379 /* 380 * PCI interrupts might be redirected to the 381 * ISA bus according to some MP tables. Use the 382 * same methods as used by the ISA devices 383 * devices to find the proper IOAPIC int pin. 384 */ 385 airq = isa_apic_irq(cfg->intline); 386 if ((airq >= 0) && (airq != cfg->intline)) { 387 /* XXX: undirect_pci_irq() ? */ 388 undirect_isa_irq(cfg->intline); 389 cfg->intline = airq; 390 } 391 } 392 } 393 #endif /* APIC_IO */ 394 395 cfg->mingnt = REG(PCIR_MINGNT, 1); 396 cfg->maxlat = REG(PCIR_MAXLAT, 1); 397 398 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 399 cfg->hdrtype &= ~PCIM_MFDEV; 400 401 pci_fixancient(cfg); 402 pci_hdrtypedata(pcib, b, s, f, cfg); 403 pci_read_capabilities(pcib, cfg); 404 405 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 406 407 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 408 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 409 devlist_entry->conf.pc_sel.pc_func = cfg->func; 410 devlist_entry->conf.pc_hdr = cfg->hdrtype; 411 412 devlist_entry->conf.pc_subvendor = cfg->subvendor; 413 devlist_entry->conf.pc_subdevice = cfg->subdevice; 414 devlist_entry->conf.pc_vendor = cfg->vendor; 415 devlist_entry->conf.pc_device = cfg->device; 416 417 devlist_entry->conf.pc_class = cfg->baseclass; 418 devlist_entry->conf.pc_subclass = cfg->subclass; 419 devlist_entry->conf.pc_progif = cfg->progif; 420 devlist_entry->conf.pc_revid = cfg->revid; 421 422 pci_numdevs++; 423 pci_generation++; 424 } 425 return (devlist_entry); 426 #undef REG 427 } 428 429 static int 430 pci_fixup_nextptr(int *nextptr0) 431 { 432 int nextptr = *nextptr0; 433 434 /* "Next pointer" is only one byte */ 435 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr)); 436 437 if (nextptr & 0x3) { 438 /* 439 * PCI local bus spec 3.0: 440 * 441 * "... The bottom two bits of all pointers are reserved 442 * and must be implemented as 00b although software must 443 * mask them to allow for future uses of these bits ..." 444 */ 445 if (bootverbose) { 446 kprintf("Illegal PCI extended capability " 447 "offset, fixup 0x%02x -> 0x%02x\n", 448 nextptr, nextptr & ~0x3); 449 } 450 nextptr &= ~0x3; 451 } 452 *nextptr0 = nextptr; 453 454 if (nextptr < 0x40) { 455 if (nextptr != 0) { 456 kprintf("Illegal PCI extended capability " 457 "offset 0x%02x", nextptr); 458 } 459 return 0; 460 } 461 return 1; 462 } 463 464 static void 465 pci_read_cap_pmgt(device_t pcib, int ptr, pcicfgregs *cfg) 466 { 467 #define REG(n, w) \ 468 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 469 470 struct pcicfg_pmgt *pmgt = &cfg->pmgt; 471 472 if (pmgt->pp_cap) 473 return; 474 475 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 476 pmgt->pp_status = ptr + PCIR_POWER_STATUS; 477 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 478 /* 479 * XXX 480 * Following way may be used to to test whether 481 * 'data' register exists: 482 * if 'data_select' register of 483 * PCIR_POWER_STATUS(bits[12,9]) is read-only 484 * then 'data' register is _not_ implemented. 485 */ 486 pmgt->pp_data = 0; 487 488 #undef REG 489 } 490 491 static int 492 pcie_slotimpl(const pcicfgregs *cfg) 493 { 494 const struct pcicfg_expr *expr = &cfg->expr; 495 uint16_t port_type; 496 497 /* 498 * Only version 1 can be parsed currently 499 */ 500 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1) 501 return 0; 502 503 /* 504 * - Slot implemented bit is meaningful iff current port is 505 * root port or down stream port. 506 * - Testing for root port or down stream port is meanningful 507 * iff PCI configure has type 1 header. 508 */ 509 510 if (cfg->hdrtype != 1) 511 return 0; 512 513 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE; 514 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT) 515 return 0; 516 517 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL)) 518 return 0; 519 520 return 1; 521 } 522 523 static void 524 pci_read_cap_expr(device_t pcib, int ptr, pcicfgregs *cfg) 525 { 526 #define REG(n, w) \ 527 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 528 529 struct pcicfg_expr *expr = &cfg->expr; 530 531 expr->expr_ptr = ptr; 532 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2); 533 534 /* 535 * Only version 1 can be parsed currently 536 */ 537 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1) 538 return; 539 540 /* 541 * Read slot capabilities. Slot capabilities exists iff 542 * current port's slot is implemented 543 */ 544 if (pcie_slotimpl(cfg)) 545 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4); 546 547 #undef REG 548 } 549 550 static void 551 pci_read_capabilities(device_t pcib, pcicfgregs *cfg) 552 { 553 #define REG(n, w) \ 554 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 555 556 int nextptr, ptrptr; 557 558 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) { 559 /* No capabilities */ 560 return; 561 } 562 563 switch (cfg->hdrtype) { 564 case 0: 565 case 1: 566 ptrptr = PCIR_CAP_PTR; 567 break; 568 case 2: 569 ptrptr = PCIR_CAP_PTR_2; 570 break; 571 default: 572 return; /* No capabilities support */ 573 } 574 nextptr = REG(ptrptr, 1); 575 576 /* 577 * Read capability entries. 578 */ 579 while (pci_fixup_nextptr(&nextptr)) { 580 int ptr = nextptr; 581 582 /* Process this entry */ 583 switch (REG(ptr, 1)) { 584 case PCIY_PMG: /* PCI power management */ 585 pci_read_cap_pmgt(pcib, ptr, cfg); 586 break; 587 case PCIY_PCIX: /* PCI-X */ 588 cfg->pcixcap_ptr = ptr; 589 break; 590 case PCIY_EXPRESS: /* PCI Express */ 591 pci_read_cap_expr(pcib, ptr, cfg); 592 break; 593 default: 594 break; 595 } 596 597 /* Find the next entry */ 598 nextptr = REG(ptr + 1, 1); 599 } 600 601 #undef REG 602 } 603 604 /* free pcicfgregs structure and all depending data structures */ 605 606 int 607 pci_freecfg(struct pci_devinfo *dinfo) 608 { 609 struct devlist *devlist_head; 610 611 devlist_head = &pci_devq; 612 613 if (dinfo->cfg.hdrspec != NULL) 614 kfree(dinfo->cfg.hdrspec, M_DEVBUF); 615 /* XXX this hasn't been tested */ 616 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 617 kfree(dinfo, M_DEVBUF); 618 619 /* increment the generation count */ 620 pci_generation++; 621 622 /* we're losing one device */ 623 pci_numdevs--; 624 return (0); 625 } 626 627 628 /* 629 * PCI power manangement 630 */ 631 int 632 pci_set_powerstate_method(device_t dev, device_t child, int state) 633 { 634 struct pci_devinfo *dinfo = device_get_ivars(child); 635 pcicfgregs *cfg = &dinfo->cfg; 636 struct pcicfg_pmgt *pmgt = &cfg->pmgt; 637 u_int16_t status; 638 int result; 639 640 if (pmgt->pp_cap != 0) { 641 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2) & ~PCIM_PSTAT_DMASK; 642 result = 0; 643 switch (state) { 644 case PCI_POWERSTATE_D0: 645 status |= PCIM_PSTAT_D0; 646 break; 647 case PCI_POWERSTATE_D1: 648 if (pmgt->pp_cap & PCIM_PCAP_D1SUPP) { 649 status |= PCIM_PSTAT_D1; 650 } else { 651 result = EOPNOTSUPP; 652 } 653 break; 654 case PCI_POWERSTATE_D2: 655 if (pmgt->pp_cap & PCIM_PCAP_D2SUPP) { 656 status |= PCIM_PSTAT_D2; 657 } else { 658 result = EOPNOTSUPP; 659 } 660 break; 661 case PCI_POWERSTATE_D3: 662 status |= PCIM_PSTAT_D3; 663 break; 664 default: 665 result = EINVAL; 666 } 667 if (result == 0) 668 PCI_WRITE_CONFIG(dev, child, pmgt->pp_status, status, 2); 669 } else { 670 result = ENXIO; 671 } 672 return(result); 673 } 674 675 int 676 pci_get_powerstate_method(device_t dev, device_t child) 677 { 678 struct pci_devinfo *dinfo = device_get_ivars(child); 679 pcicfgregs *cfg = &dinfo->cfg; 680 struct pcicfg_pmgt *pmgt = &cfg->pmgt; 681 u_int16_t status; 682 int result; 683 684 if (pmgt->pp_cap != 0) { 685 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2); 686 switch (status & PCIM_PSTAT_DMASK) { 687 case PCIM_PSTAT_D0: 688 result = PCI_POWERSTATE_D0; 689 break; 690 case PCIM_PSTAT_D1: 691 result = PCI_POWERSTATE_D1; 692 break; 693 case PCIM_PSTAT_D2: 694 result = PCI_POWERSTATE_D2; 695 break; 696 case PCIM_PSTAT_D3: 697 result = PCI_POWERSTATE_D3; 698 break; 699 default: 700 result = PCI_POWERSTATE_UNKNOWN; 701 break; 702 } 703 } else { 704 /* No support, device is always at D0 */ 705 result = PCI_POWERSTATE_D0; 706 } 707 return(result); 708 } 709 710 /* 711 * Some convenience functions for PCI device drivers. 712 */ 713 714 static __inline void 715 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 716 { 717 u_int16_t command; 718 719 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 720 command |= bit; 721 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 722 } 723 724 static __inline void 725 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 726 { 727 u_int16_t command; 728 729 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 730 command &= ~bit; 731 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 732 } 733 734 int 735 pci_enable_busmaster_method(device_t dev, device_t child) 736 { 737 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 738 return(0); 739 } 740 741 int 742 pci_disable_busmaster_method(device_t dev, device_t child) 743 { 744 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 745 return(0); 746 } 747 748 int 749 pci_enable_io_method(device_t dev, device_t child, int space) 750 { 751 uint16_t command; 752 uint16_t bit; 753 char *error; 754 755 bit = 0; 756 error = NULL; 757 758 switch(space) { 759 case SYS_RES_IOPORT: 760 bit = PCIM_CMD_PORTEN; 761 error = "port"; 762 break; 763 case SYS_RES_MEMORY: 764 bit = PCIM_CMD_MEMEN; 765 error = "memory"; 766 break; 767 default: 768 return(EINVAL); 769 } 770 pci_set_command_bit(dev, child, bit); 771 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 772 if (command & bit) 773 return(0); 774 device_printf(child, "failed to enable %s mapping!\n", error); 775 return(ENXIO); 776 } 777 778 int 779 pci_disable_io_method(device_t dev, device_t child, int space) 780 { 781 uint16_t command; 782 uint16_t bit; 783 char *error; 784 785 bit = 0; 786 error = NULL; 787 788 switch(space) { 789 case SYS_RES_IOPORT: 790 bit = PCIM_CMD_PORTEN; 791 error = "port"; 792 break; 793 case SYS_RES_MEMORY: 794 bit = PCIM_CMD_MEMEN; 795 error = "memory"; 796 break; 797 default: 798 return (EINVAL); 799 } 800 pci_clear_command_bit(dev, child, bit); 801 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 802 if (command & bit) { 803 device_printf(child, "failed to disable %s mapping!\n", error); 804 return (ENXIO); 805 } 806 return (0); 807 } 808 809 /* 810 * This is the user interface to PCI configuration space. 811 */ 812 813 static int 814 pci_open(struct dev_open_args *ap) 815 { 816 if ((ap->a_oflags & FWRITE) && securelevel > 0) { 817 return EPERM; 818 } 819 return 0; 820 } 821 822 static int 823 pci_close(struct dev_close_args *ap) 824 { 825 return 0; 826 } 827 828 /* 829 * Match a single pci_conf structure against an array of pci_match_conf 830 * structures. The first argument, 'matches', is an array of num_matches 831 * pci_match_conf structures. match_buf is a pointer to the pci_conf 832 * structure that will be compared to every entry in the matches array. 833 * This function returns 1 on failure, 0 on success. 834 */ 835 static int 836 pci_conf_match(struct pci_match_conf *matches, int num_matches, 837 struct pci_conf *match_buf) 838 { 839 int i; 840 841 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 842 return(1); 843 844 for (i = 0; i < num_matches; i++) { 845 /* 846 * I'm not sure why someone would do this...but... 847 */ 848 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 849 continue; 850 851 /* 852 * Look at each of the match flags. If it's set, do the 853 * comparison. If the comparison fails, we don't have a 854 * match, go on to the next item if there is one. 855 */ 856 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 857 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 858 continue; 859 860 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 861 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 862 continue; 863 864 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 865 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 866 continue; 867 868 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 869 && (match_buf->pc_vendor != matches[i].pc_vendor)) 870 continue; 871 872 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 873 && (match_buf->pc_device != matches[i].pc_device)) 874 continue; 875 876 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 877 && (match_buf->pc_class != matches[i].pc_class)) 878 continue; 879 880 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 881 && (match_buf->pd_unit != matches[i].pd_unit)) 882 continue; 883 884 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 885 && (strncmp(matches[i].pd_name, match_buf->pd_name, 886 sizeof(match_buf->pd_name)) != 0)) 887 continue; 888 889 return(0); 890 } 891 892 return(1); 893 } 894 895 /* 896 * Locate the parent of a PCI device by scanning the PCI devlist 897 * and return the entry for the parent. 898 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 899 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 900 */ 901 902 pcicfgregs * 903 pci_devlist_get_parent(pcicfgregs *cfg) 904 { 905 struct devlist *devlist_head; 906 struct pci_devinfo *dinfo; 907 pcicfgregs *bridge_cfg; 908 int i; 909 910 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 911 912 /* If the device is on PCI bus 0, look for the host */ 913 if (cfg->bus == 0) { 914 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 915 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 916 bridge_cfg = &dinfo->cfg; 917 if (bridge_cfg->baseclass == PCIC_BRIDGE 918 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 919 && bridge_cfg->bus == cfg->bus) { 920 return bridge_cfg; 921 } 922 } 923 } 924 925 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 926 if (cfg->bus > 0) { 927 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 928 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 929 bridge_cfg = &dinfo->cfg; 930 if (bridge_cfg->baseclass == PCIC_BRIDGE 931 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 932 && bridge_cfg->secondarybus == cfg->bus) { 933 return bridge_cfg; 934 } 935 } 936 } 937 938 return NULL; 939 } 940 941 static int 942 pci_ioctl(struct dev_ioctl_args *ap) 943 { 944 device_t pci, pcib; 945 struct pci_io *io; 946 const char *name; 947 int error; 948 949 if (!(ap->a_fflag & FWRITE)) 950 return EPERM; 951 952 switch(ap->a_cmd) { 953 case PCIOCGETCONF: 954 { 955 struct pci_devinfo *dinfo; 956 struct pci_conf_io *cio; 957 struct devlist *devlist_head; 958 struct pci_match_conf *pattern_buf; 959 int num_patterns; 960 size_t iolen; 961 int ionum, i; 962 963 cio = (struct pci_conf_io *)ap->a_data; 964 965 num_patterns = 0; 966 dinfo = NULL; 967 968 /* 969 * Hopefully the user won't pass in a null pointer, but it 970 * can't hurt to check. 971 */ 972 if (cio == NULL) { 973 error = EINVAL; 974 break; 975 } 976 977 /* 978 * If the user specified an offset into the device list, 979 * but the list has changed since they last called this 980 * ioctl, tell them that the list has changed. They will 981 * have to get the list from the beginning. 982 */ 983 if ((cio->offset != 0) 984 && (cio->generation != pci_generation)){ 985 cio->num_matches = 0; 986 cio->status = PCI_GETCONF_LIST_CHANGED; 987 error = 0; 988 break; 989 } 990 991 /* 992 * Check to see whether the user has asked for an offset 993 * past the end of our list. 994 */ 995 if (cio->offset >= pci_numdevs) { 996 cio->num_matches = 0; 997 cio->status = PCI_GETCONF_LAST_DEVICE; 998 error = 0; 999 break; 1000 } 1001 1002 /* get the head of the device queue */ 1003 devlist_head = &pci_devq; 1004 1005 /* 1006 * Determine how much room we have for pci_conf structures. 1007 * Round the user's buffer size down to the nearest 1008 * multiple of sizeof(struct pci_conf) in case the user 1009 * didn't specify a multiple of that size. 1010 */ 1011 iolen = min(cio->match_buf_len - 1012 (cio->match_buf_len % sizeof(struct pci_conf)), 1013 pci_numdevs * sizeof(struct pci_conf)); 1014 1015 /* 1016 * Since we know that iolen is a multiple of the size of 1017 * the pciconf union, it's okay to do this. 1018 */ 1019 ionum = iolen / sizeof(struct pci_conf); 1020 1021 /* 1022 * If this test is true, the user wants the pci_conf 1023 * structures returned to match the supplied entries. 1024 */ 1025 if ((cio->num_patterns > 0) 1026 && (cio->pat_buf_len > 0)) { 1027 /* 1028 * pat_buf_len needs to be: 1029 * num_patterns * sizeof(struct pci_match_conf) 1030 * While it is certainly possible the user just 1031 * allocated a large buffer, but set the number of 1032 * matches correctly, it is far more likely that 1033 * their kernel doesn't match the userland utility 1034 * they're using. It's also possible that the user 1035 * forgot to initialize some variables. Yes, this 1036 * may be overly picky, but I hazard to guess that 1037 * it's far more likely to just catch folks that 1038 * updated their kernel but not their userland. 1039 */ 1040 if ((cio->num_patterns * 1041 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 1042 /* The user made a mistake, return an error*/ 1043 cio->status = PCI_GETCONF_ERROR; 1044 kprintf("pci_ioctl: pat_buf_len %d != " 1045 "num_patterns (%d) * sizeof(struct " 1046 "pci_match_conf) (%d)\npci_ioctl: " 1047 "pat_buf_len should be = %d\n", 1048 cio->pat_buf_len, cio->num_patterns, 1049 (int)sizeof(struct pci_match_conf), 1050 (int)sizeof(struct pci_match_conf) * 1051 cio->num_patterns); 1052 kprintf("pci_ioctl: do your headers match your " 1053 "kernel?\n"); 1054 cio->num_matches = 0; 1055 error = EINVAL; 1056 break; 1057 } 1058 1059 /* 1060 * Check the user's buffer to make sure it's readable. 1061 */ 1062 if (!useracc((caddr_t)cio->patterns, 1063 cio->pat_buf_len, VM_PROT_READ)) { 1064 kprintf("pci_ioctl: pattern buffer %p, " 1065 "length %u isn't user accessible for" 1066 " READ\n", cio->patterns, 1067 cio->pat_buf_len); 1068 error = EACCES; 1069 break; 1070 } 1071 /* 1072 * Allocate a buffer to hold the patterns. 1073 */ 1074 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP, 1075 M_WAITOK); 1076 error = copyin(cio->patterns, pattern_buf, 1077 cio->pat_buf_len); 1078 if (error != 0) 1079 break; 1080 num_patterns = cio->num_patterns; 1081 1082 } else if ((cio->num_patterns > 0) 1083 || (cio->pat_buf_len > 0)) { 1084 /* 1085 * The user made a mistake, spit out an error. 1086 */ 1087 cio->status = PCI_GETCONF_ERROR; 1088 cio->num_matches = 0; 1089 kprintf("pci_ioctl: invalid GETCONF arguments\n"); 1090 error = EINVAL; 1091 break; 1092 } else 1093 pattern_buf = NULL; 1094 1095 /* 1096 * Make sure we can write to the match buffer. 1097 */ 1098 if (!useracc((caddr_t)cio->matches, 1099 cio->match_buf_len, VM_PROT_WRITE)) { 1100 kprintf("pci_ioctl: match buffer %p, length %u " 1101 "isn't user accessible for WRITE\n", 1102 cio->matches, cio->match_buf_len); 1103 error = EACCES; 1104 break; 1105 } 1106 1107 /* 1108 * Go through the list of devices and copy out the devices 1109 * that match the user's criteria. 1110 */ 1111 for (cio->num_matches = 0, error = 0, i = 0, 1112 dinfo = STAILQ_FIRST(devlist_head); 1113 (dinfo != NULL) && (cio->num_matches < ionum) 1114 && (error == 0) && (i < pci_numdevs); 1115 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1116 1117 if (i < cio->offset) 1118 continue; 1119 1120 /* Populate pd_name and pd_unit */ 1121 name = NULL; 1122 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 1123 name = device_get_name(dinfo->cfg.dev); 1124 if (name) { 1125 strncpy(dinfo->conf.pd_name, name, 1126 sizeof(dinfo->conf.pd_name)); 1127 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 1128 dinfo->conf.pd_unit = 1129 device_get_unit(dinfo->cfg.dev); 1130 } 1131 1132 if ((pattern_buf == NULL) || 1133 (pci_conf_match(pattern_buf, num_patterns, 1134 &dinfo->conf) == 0)) { 1135 1136 /* 1137 * If we've filled up the user's buffer, 1138 * break out at this point. Since we've 1139 * got a match here, we'll pick right back 1140 * up at the matching entry. We can also 1141 * tell the user that there are more matches 1142 * left. 1143 */ 1144 if (cio->num_matches >= ionum) 1145 break; 1146 1147 error = copyout(&dinfo->conf, 1148 &cio->matches[cio->num_matches], 1149 sizeof(struct pci_conf)); 1150 cio->num_matches++; 1151 } 1152 } 1153 1154 /* 1155 * Set the pointer into the list, so if the user is getting 1156 * n records at a time, where n < pci_numdevs, 1157 */ 1158 cio->offset = i; 1159 1160 /* 1161 * Set the generation, the user will need this if they make 1162 * another ioctl call with offset != 0. 1163 */ 1164 cio->generation = pci_generation; 1165 1166 /* 1167 * If this is the last device, inform the user so he won't 1168 * bother asking for more devices. If dinfo isn't NULL, we 1169 * know that there are more matches in the list because of 1170 * the way the traversal is done. 1171 */ 1172 if (dinfo == NULL) 1173 cio->status = PCI_GETCONF_LAST_DEVICE; 1174 else 1175 cio->status = PCI_GETCONF_MORE_DEVS; 1176 1177 if (pattern_buf != NULL) 1178 kfree(pattern_buf, M_TEMP); 1179 1180 break; 1181 } 1182 case PCIOCREAD: 1183 io = (struct pci_io *)ap->a_data; 1184 switch(io->pi_width) { 1185 case 4: 1186 case 2: 1187 case 1: 1188 /* 1189 * Assume that the user-level bus number is 1190 * actually the pciN instance number. We map 1191 * from that to the real pcib+bus combination. 1192 */ 1193 pci = devclass_get_device(pci_devclass, 1194 io->pi_sel.pc_bus); 1195 if (pci) { 1196 /* 1197 * pci is the pci device and may contain 1198 * several children (for each function code). 1199 * The governing pci bus is the parent to 1200 * the pci device. 1201 */ 1202 int b; 1203 1204 pcib = device_get_parent(pci); 1205 b = pcib_get_bus(pcib); 1206 io->pi_data = 1207 PCIB_READ_CONFIG(pcib, 1208 b, 1209 io->pi_sel.pc_dev, 1210 io->pi_sel.pc_func, 1211 io->pi_reg, 1212 io->pi_width); 1213 error = 0; 1214 } else { 1215 error = ENODEV; 1216 } 1217 break; 1218 default: 1219 error = ENODEV; 1220 break; 1221 } 1222 break; 1223 1224 case PCIOCWRITE: 1225 io = (struct pci_io *)ap->a_data; 1226 switch(io->pi_width) { 1227 case 4: 1228 case 2: 1229 case 1: 1230 /* 1231 * Assume that the user-level bus number is 1232 * actually the pciN instance number. We map 1233 * from that to the real pcib+bus combination. 1234 */ 1235 pci = devclass_get_device(pci_devclass, 1236 io->pi_sel.pc_bus); 1237 if (pci) { 1238 /* 1239 * pci is the pci device and may contain 1240 * several children (for each function code). 1241 * The governing pci bus is the parent to 1242 * the pci device. 1243 */ 1244 int b; 1245 1246 pcib = device_get_parent(pci); 1247 b = pcib_get_bus(pcib); 1248 PCIB_WRITE_CONFIG(pcib, 1249 b, 1250 io->pi_sel.pc_dev, 1251 io->pi_sel.pc_func, 1252 io->pi_reg, 1253 io->pi_data, 1254 io->pi_width); 1255 error = 0; 1256 } else { 1257 error = ENODEV; 1258 } 1259 break; 1260 default: 1261 error = ENODEV; 1262 break; 1263 } 1264 break; 1265 1266 default: 1267 error = ENOTTY; 1268 break; 1269 } 1270 1271 return (error); 1272 } 1273 1274 #define PCI_CDEV 78 1275 1276 static struct dev_ops pcic_ops = { 1277 { "pci", PCI_CDEV, 0 }, 1278 .d_open = pci_open, 1279 .d_close = pci_close, 1280 .d_ioctl = pci_ioctl, 1281 }; 1282 1283 #include "pci_if.h" 1284 1285 /* 1286 * New style pci driver. Parent device is either a pci-host-bridge or a 1287 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1288 */ 1289 const char * 1290 pci_class_to_string(int baseclass) 1291 { 1292 const char *name; 1293 1294 switch(baseclass) { 1295 case PCIC_OLD: 1296 name = "OLD"; 1297 break; 1298 case PCIC_STORAGE: 1299 name = "STORAGE"; 1300 break; 1301 case PCIC_NETWORK: 1302 name = "NETWORK"; 1303 break; 1304 case PCIC_DISPLAY: 1305 name = "DISPLAY"; 1306 break; 1307 case PCIC_MULTIMEDIA: 1308 name = "MULTIMEDIA"; 1309 break; 1310 case PCIC_MEMORY: 1311 name = "MEMORY"; 1312 break; 1313 case PCIC_BRIDGE: 1314 name = "BRIDGE"; 1315 break; 1316 case PCIC_SIMPLECOMM: 1317 name = "SIMPLECOMM"; 1318 break; 1319 case PCIC_BASEPERIPH: 1320 name = "BASEPERIPH"; 1321 break; 1322 case PCIC_INPUTDEV: 1323 name = "INPUTDEV"; 1324 break; 1325 case PCIC_DOCKING: 1326 name = "DOCKING"; 1327 break; 1328 case PCIC_PROCESSOR: 1329 name = "PROCESSOR"; 1330 break; 1331 case PCIC_SERIALBUS: 1332 name = "SERIALBUS"; 1333 break; 1334 case PCIC_WIRELESS: 1335 name = "WIRELESS"; 1336 break; 1337 case PCIC_I2O: 1338 name = "I20"; 1339 break; 1340 case PCIC_SATELLITE: 1341 name = "SATELLITE"; 1342 break; 1343 case PCIC_CRYPTO: 1344 name = "CRYPTO"; 1345 break; 1346 case PCIC_SIGPROC: 1347 name = "SIGPROC"; 1348 break; 1349 case PCIC_OTHER: 1350 name = "OTHER"; 1351 break; 1352 default: 1353 name = "?"; 1354 break; 1355 } 1356 return(name); 1357 } 1358 1359 static void 1360 pci_print_verbose_expr(const pcicfgregs *cfg) 1361 { 1362 const struct pcicfg_expr *expr = &cfg->expr; 1363 const char *port_name; 1364 uint16_t port_type; 1365 1366 if (!bootverbose) 1367 return; 1368 1369 if (expr->expr_ptr == 0) /* No PCI Express capability */ 1370 return; 1371 1372 kprintf("\tPCI Express ver.%d cap=0x%04x", 1373 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap); 1374 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1) 1375 goto back; 1376 1377 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE; 1378 1379 switch (port_type) { 1380 case PCIE_END_POINT: 1381 port_name = "DEVICE"; 1382 break; 1383 case PCIE_LEG_END_POINT: 1384 port_name = "LEGDEV"; 1385 break; 1386 case PCIE_ROOT_PORT: 1387 port_name = "ROOT"; 1388 break; 1389 case PCIE_UP_STREAM_PORT: 1390 port_name = "UPSTREAM"; 1391 break; 1392 case PCIE_DOWN_STREAM_PORT: 1393 port_name = "DOWNSTRM"; 1394 break; 1395 case PCIE_PCIE2PCI_BRIDGE: 1396 port_name = "PCIE2PCI"; 1397 break; 1398 case PCIE_PCI2PCIE_BRIDGE: 1399 port_name = "PCI2PCIE"; 1400 break; 1401 default: 1402 port_name = NULL; 1403 break; 1404 } 1405 if ((port_type == PCIE_ROOT_PORT || 1406 port_type == PCIE_DOWN_STREAM_PORT) && 1407 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL)) 1408 port_name = NULL; 1409 if (port_name != NULL) 1410 kprintf("[%s]", port_name); 1411 1412 if (pcie_slotimpl(cfg)) { 1413 kprintf(", slotcap=0x%08x", expr->expr_slotcap); 1414 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP) 1415 kprintf("[HOTPLUG]"); 1416 } 1417 back: 1418 kprintf("\n"); 1419 } 1420 1421 void 1422 pci_print_verbose(struct pci_devinfo *dinfo) 1423 { 1424 if (bootverbose) { 1425 pcicfgregs *cfg = &dinfo->cfg; 1426 1427 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1428 cfg->vendor, cfg->device, cfg->revid); 1429 kprintf("\tbus=%d, slot=%d, func=%d\n", 1430 cfg->bus, cfg->slot, cfg->func); 1431 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1432 pci_class_to_string(cfg->baseclass), 1433 cfg->baseclass, cfg->subclass, cfg->progif, 1434 cfg->hdrtype, cfg->mfdev); 1435 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n", 1436 cfg->subordinatebus, cfg->secondarybus); 1437 #ifdef PCI_DEBUG 1438 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1439 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1440 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1441 cfg->lattimer, cfg->lattimer * 30, 1442 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1443 #endif /* PCI_DEBUG */ 1444 if (cfg->intpin > 0) 1445 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 1446 1447 pci_print_verbose_expr(cfg); 1448 } 1449 } 1450 1451 static int 1452 pci_porten(device_t pcib, int b, int s, int f) 1453 { 1454 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1455 & PCIM_CMD_PORTEN) != 0; 1456 } 1457 1458 static int 1459 pci_memen(device_t pcib, int b, int s, int f) 1460 { 1461 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1462 & PCIM_CMD_MEMEN) != 0; 1463 } 1464 1465 /* 1466 * Add a resource based on a pci map register. Return 1 if the map 1467 * register is a 32bit map register or 2 if it is a 64bit register. 1468 */ 1469 static int 1470 pci_add_map(device_t pcib, int b, int s, int f, int reg, 1471 struct resource_list *rl) 1472 { 1473 u_int32_t map; 1474 u_int64_t base; 1475 u_int8_t ln2size; 1476 u_int8_t ln2range; 1477 u_int32_t testval; 1478 1479 1480 #ifdef PCI_ENABLE_IO_MODES 1481 u_int16_t cmd; 1482 #endif 1483 int type; 1484 1485 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1486 1487 if (map == 0 || map == 0xffffffff) 1488 return 1; /* skip invalid entry */ 1489 1490 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1491 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1492 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1493 1494 base = pci_mapbase(map); 1495 if (pci_maptype(map) & PCI_MAPMEM) 1496 type = SYS_RES_MEMORY; 1497 else 1498 type = SYS_RES_IOPORT; 1499 ln2size = pci_mapsize(testval); 1500 ln2range = pci_maprange(testval); 1501 if (ln2range == 64) { 1502 /* Read the other half of a 64bit map register */ 1503 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4); 1504 } 1505 1506 /* 1507 * This code theoretically does the right thing, but has 1508 * undesirable side effects in some cases where 1509 * peripherals respond oddly to having these bits 1510 * enabled. Leave them alone by default. 1511 */ 1512 #ifdef PCI_ENABLE_IO_MODES 1513 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1514 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1515 cmd |= PCIM_CMD_PORTEN; 1516 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1517 } 1518 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1519 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1520 cmd |= PCIM_CMD_MEMEN; 1521 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1522 } 1523 #else 1524 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1525 return 1; 1526 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1527 return 1; 1528 #endif 1529 1530 resource_list_add(rl, type, reg, 1531 base, base + (1 << ln2size) - 1, 1532 (1 << ln2size)); 1533 1534 if (bootverbose) { 1535 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n", 1536 reg, pci_maptype(base), ln2range, 1537 (unsigned int) base, ln2size); 1538 } 1539 1540 return (ln2range == 64) ? 2 : 1; 1541 } 1542 1543 #ifdef PCI_MAP_FIXUP 1544 /* 1545 * For ATA devices we need to decide early on what addressing mode to use. 1546 * Legacy demands that the primary and secondary ATA ports sits on the 1547 * same addresses that old ISA hardware did. This dictates that we use 1548 * those addresses and ignore the BARs if we cannot set PCI native 1549 * addressing mode. 1550 */ 1551 static void 1552 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f, 1553 struct resource_list *rl) 1554 { 1555 int rid, type, progif; 1556 #if 0 1557 /* if this device supports PCI native addressing use it */ 1558 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1559 if ((progif &0x8a) == 0x8a) { 1560 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 1561 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 1562 kprintf("Trying ATA native PCI addressing mode\n"); 1563 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 1564 } 1565 } 1566 #endif 1567 /* 1568 * Because we return any preallocated resources for lazy 1569 * allocation for PCI devices in pci_alloc_resource(), we can 1570 * allocate our legacy resources here. 1571 */ 1572 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1573 type = SYS_RES_IOPORT; 1574 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 1575 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl); 1576 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl); 1577 } else { 1578 rid = PCIR_BAR(0); 1579 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 1580 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 1581 0); 1582 rid = PCIR_BAR(1); 1583 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 1584 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 1585 0); 1586 } 1587 if (progif & PCIP_STORAGE_IDE_MODESEC) { 1588 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl); 1589 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl); 1590 } else { 1591 rid = PCIR_BAR(2); 1592 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 1593 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 1594 0); 1595 rid = PCIR_BAR(3); 1596 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 1597 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 1598 0); 1599 } 1600 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl); 1601 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl); 1602 } 1603 #endif /* PCI_MAP_FIXUP */ 1604 1605 static void 1606 pci_add_resources(device_t pcib, device_t bus, device_t dev) 1607 { 1608 struct pci_devinfo *dinfo = device_get_ivars(dev); 1609 pcicfgregs *cfg = &dinfo->cfg; 1610 struct resource_list *rl = &dinfo->resources; 1611 struct pci_quirk *q; 1612 int b, i, f, s; 1613 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */ 1614 int irq; 1615 #endif 1616 1617 b = cfg->bus; 1618 s = cfg->slot; 1619 f = cfg->func; 1620 #ifdef PCI_MAP_FIXUP 1621 /* atapci devices in legacy mode need special map treatment */ 1622 if ((pci_get_class(dev) == PCIC_STORAGE) && 1623 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1624 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 1625 (!pci_read_config(dev, PCIR_BAR(0), 4) && 1626 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 1627 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 1628 else 1629 #endif /* PCI_MAP_FIXUP */ 1630 for (i = 0; i < cfg->nummaps;) { 1631 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl); 1632 } 1633 1634 for (q = &pci_quirks[0]; q->devid; q++) { 1635 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1636 && q->type == PCI_QUIRK_MAP_REG) 1637 pci_add_map(pcib, b, s, f, q->arg1, rl); 1638 } 1639 1640 if (cfg->intpin > 0 && cfg->intline != 255) 1641 resource_list_add(rl, SYS_RES_IRQ, 0, 1642 cfg->intline, cfg->intline, 1); 1643 } 1644 1645 void 1646 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1647 { 1648 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1649 device_t pcib = device_get_parent(dev); 1650 struct pci_devinfo *dinfo; 1651 int maxslots; 1652 int s, f, pcifunchigh; 1653 uint8_t hdrtype; 1654 1655 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo)); 1656 1657 maxslots = PCIB_MAXSLOTS(pcib); 1658 1659 for (s = 0; s <= maxslots; s++) { 1660 pcifunchigh = 0; 1661 f = 0; 1662 hdrtype = REG(PCIR_HDRTYPE, 1); 1663 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1664 continue; 1665 if (hdrtype & PCIM_MFDEV) 1666 pcifunchigh = PCI_FUNCMAX; 1667 for (f = 0; f <= pcifunchigh; f++) { 1668 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1669 if (dinfo != NULL) { 1670 pci_add_child(dev, dinfo); 1671 } 1672 } 1673 } 1674 #undef REG 1675 } 1676 1677 /* 1678 * The actual PCI child that we add has a NULL driver whos parent 1679 * device will be "pci". The child contains the ivars, not the parent. 1680 */ 1681 void 1682 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1683 { 1684 device_t pcib; 1685 1686 pcib = device_get_parent(bus); 1687 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1688 device_set_ivars(dinfo->cfg.dev, dinfo); 1689 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1690 pci_print_verbose(dinfo); 1691 } 1692 1693 /* 1694 * Probe the PCI bus. Note: probe code is not supposed to add children 1695 * or call attach. 1696 */ 1697 static int 1698 pci_probe(device_t dev) 1699 { 1700 device_set_desc(dev, "PCI bus"); 1701 1702 /* Allow other subclasses to override this driver */ 1703 return(-1000); 1704 } 1705 1706 static int 1707 pci_attach(device_t dev) 1708 { 1709 int busno; 1710 int lunit = device_get_unit(dev); 1711 1712 dev_ops_add(&pcic_ops, -1, lunit); 1713 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit); 1714 1715 /* 1716 * Since there can be multiple independantly numbered PCI 1717 * busses on some large alpha systems, we can't use the unit 1718 * number to decide what bus we are probing. We ask the parent 1719 * pcib what our bus number is. 1720 * 1721 * pcib_get_bus() must act on the pci bus device, not on the pci 1722 * device, because it uses badly hacked nexus-based ivars to 1723 * store and retrieve the physical bus number. XXX 1724 */ 1725 busno = pcib_get_bus(device_get_parent(dev)); 1726 if (bootverbose) 1727 device_printf(dev, "pci_attach() physical bus=%d\n", busno); 1728 1729 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1730 1731 return (bus_generic_attach(dev)); 1732 } 1733 1734 static int 1735 pci_print_resources(struct resource_list *rl, const char *name, int type, 1736 const char *format) 1737 { 1738 struct resource_list_entry *rle; 1739 int printed, retval; 1740 1741 printed = 0; 1742 retval = 0; 1743 /* Yes, this is kinda cheating */ 1744 SLIST_FOREACH(rle, rl, link) { 1745 if (rle->type == type) { 1746 if (printed == 0) 1747 retval += kprintf(" %s ", name); 1748 else if (printed > 0) 1749 retval += kprintf(","); 1750 printed++; 1751 retval += kprintf(format, rle->start); 1752 if (rle->count > 1) { 1753 retval += kprintf("-"); 1754 retval += kprintf(format, rle->start + 1755 rle->count - 1); 1756 } 1757 } 1758 } 1759 return retval; 1760 } 1761 1762 int 1763 pci_print_child(device_t dev, device_t child) 1764 { 1765 struct pci_devinfo *dinfo; 1766 struct resource_list *rl; 1767 pcicfgregs *cfg; 1768 int retval = 0; 1769 1770 dinfo = device_get_ivars(child); 1771 cfg = &dinfo->cfg; 1772 rl = &dinfo->resources; 1773 1774 retval += bus_print_child_header(dev, child); 1775 1776 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); 1777 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1778 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); 1779 if (device_get_flags(dev)) 1780 retval += kprintf(" flags %#x", device_get_flags(dev)); 1781 1782 retval += kprintf(" at device %d.%d", pci_get_slot(child), 1783 pci_get_function(child)); 1784 1785 retval += bus_print_child_footer(dev, child); 1786 1787 return (retval); 1788 } 1789 1790 void 1791 pci_probe_nomatch(device_t dev, device_t child) 1792 { 1793 struct pci_devinfo *dinfo; 1794 pcicfgregs *cfg; 1795 const char *desc; 1796 int unknown; 1797 1798 unknown = 0; 1799 dinfo = device_get_ivars(child); 1800 cfg = &dinfo->cfg; 1801 desc = pci_ata_match(child); 1802 if (!desc) desc = pci_usb_match(child); 1803 if (!desc) desc = pci_vga_match(child); 1804 if (!desc) desc = pci_chip_match(child); 1805 if (!desc) { 1806 desc = "unknown card"; 1807 unknown++; 1808 } 1809 device_printf(dev, "<%s>", desc); 1810 if (bootverbose || unknown) { 1811 kprintf(" (vendor=0x%04x, dev=0x%04x)", 1812 cfg->vendor, 1813 cfg->device); 1814 } 1815 kprintf(" at %d.%d", 1816 pci_get_slot(child), 1817 pci_get_function(child)); 1818 if (cfg->intpin > 0 && cfg->intline != 255) { 1819 kprintf(" irq %d", cfg->intline); 1820 } 1821 kprintf("\n"); 1822 1823 return; 1824 } 1825 1826 int 1827 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1828 { 1829 struct pci_devinfo *dinfo; 1830 pcicfgregs *cfg; 1831 1832 dinfo = device_get_ivars(child); 1833 cfg = &dinfo->cfg; 1834 1835 switch (which) { 1836 case PCI_IVAR_SUBVENDOR: 1837 *result = cfg->subvendor; 1838 break; 1839 case PCI_IVAR_SUBDEVICE: 1840 *result = cfg->subdevice; 1841 break; 1842 case PCI_IVAR_VENDOR: 1843 *result = cfg->vendor; 1844 break; 1845 case PCI_IVAR_DEVICE: 1846 *result = cfg->device; 1847 break; 1848 case PCI_IVAR_DEVID: 1849 *result = (cfg->device << 16) | cfg->vendor; 1850 break; 1851 case PCI_IVAR_CLASS: 1852 *result = cfg->baseclass; 1853 break; 1854 case PCI_IVAR_SUBCLASS: 1855 *result = cfg->subclass; 1856 break; 1857 case PCI_IVAR_PROGIF: 1858 *result = cfg->progif; 1859 break; 1860 case PCI_IVAR_REVID: 1861 *result = cfg->revid; 1862 break; 1863 case PCI_IVAR_INTPIN: 1864 *result = cfg->intpin; 1865 break; 1866 case PCI_IVAR_IRQ: 1867 *result = cfg->intline; 1868 break; 1869 case PCI_IVAR_BUS: 1870 *result = cfg->bus; 1871 break; 1872 case PCI_IVAR_SLOT: 1873 *result = cfg->slot; 1874 break; 1875 case PCI_IVAR_FUNCTION: 1876 *result = cfg->func; 1877 break; 1878 case PCI_IVAR_SECONDARYBUS: 1879 *result = cfg->secondarybus; 1880 break; 1881 case PCI_IVAR_SUBORDINATEBUS: 1882 *result = cfg->subordinatebus; 1883 break; 1884 case PCI_IVAR_ETHADDR: 1885 /* 1886 * The generic accessor doesn't deal with failure, so 1887 * we set the return value, then return an error. 1888 */ 1889 *result = 0; 1890 return (EINVAL); 1891 case PCI_IVAR_PCIXCAP_PTR: 1892 *result = cfg->pcixcap_ptr; 1893 break; 1894 case PCI_IVAR_PCIECAP_PTR: 1895 *result = cfg->expr.expr_ptr; 1896 break; 1897 default: 1898 return ENOENT; 1899 } 1900 return 0; 1901 } 1902 1903 int 1904 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1905 { 1906 struct pci_devinfo *dinfo; 1907 pcicfgregs *cfg; 1908 1909 dinfo = device_get_ivars(child); 1910 cfg = &dinfo->cfg; 1911 1912 switch (which) { 1913 case PCI_IVAR_SUBVENDOR: 1914 case PCI_IVAR_SUBDEVICE: 1915 case PCI_IVAR_VENDOR: 1916 case PCI_IVAR_DEVICE: 1917 case PCI_IVAR_DEVID: 1918 case PCI_IVAR_CLASS: 1919 case PCI_IVAR_SUBCLASS: 1920 case PCI_IVAR_PROGIF: 1921 case PCI_IVAR_REVID: 1922 case PCI_IVAR_INTPIN: 1923 case PCI_IVAR_IRQ: 1924 case PCI_IVAR_BUS: 1925 case PCI_IVAR_SLOT: 1926 case PCI_IVAR_FUNCTION: 1927 case PCI_IVAR_ETHADDR: 1928 case PCI_IVAR_PCIXCAP_PTR: 1929 case PCI_IVAR_PCIECAP_PTR: 1930 return EINVAL; /* disallow for now */ 1931 1932 case PCI_IVAR_SECONDARYBUS: 1933 cfg->secondarybus = value; 1934 break; 1935 case PCI_IVAR_SUBORDINATEBUS: 1936 cfg->subordinatebus = value; 1937 break; 1938 default: 1939 return ENOENT; 1940 } 1941 return 0; 1942 } 1943 1944 #ifdef PCI_MAP_FIXUP 1945 static struct resource * 1946 pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start, 1947 u_long end, u_long count, u_int flags) 1948 { 1949 struct pci_devinfo *dinfo = device_get_ivars(child); 1950 struct resource_list *rl = &dinfo->resources; 1951 struct resource_list_entry *rle; 1952 struct resource *res; 1953 uint32_t map, testval; 1954 int mapsize; 1955 1956 /* 1957 * Weed out the bogons, and figure out how large the BAR/map 1958 * is. BARs that read back 0 here are bogus and unimplemented. 1959 * 1960 * Note: atapci in legacy mode are special and handled elsewhere 1961 * in the code. If you have an atapci device in legacy mode and 1962 * it fails here, that other code is broken. 1963 */ 1964 res = NULL; 1965 map = pci_read_config(child, *rid, 4); 1966 pci_write_config(child, *rid, 0xffffffff, 4); 1967 testval = pci_read_config(child, *rid, 4); 1968 if (pci_mapbase(testval) == 0) 1969 goto out; 1970 if (pci_maptype(testval) & PCI_MAPMEM) { 1971 if (type != SYS_RES_MEMORY) { 1972 if (bootverbose) 1973 device_printf(dev, "child %s requested type %d" 1974 " for rid %#x, but the BAR says " 1975 "it is a memio\n", 1976 device_get_nameunit(child), type, 1977 *rid); 1978 goto out; 1979 } 1980 } else { 1981 if (type != SYS_RES_IOPORT) { 1982 if (bootverbose) 1983 device_printf(dev, "child %s requested type %d" 1984 " for rid %#x, but the BAR says " 1985 "it is an ioport\n", 1986 device_get_nameunit(child), type, 1987 *rid); 1988 goto out; 1989 } 1990 } 1991 /* 1992 * For real BARs, we need to override the size that 1993 * the driver requests, because that's what the BAR 1994 * actually uses and we would otherwise have a 1995 * situation where we might allocate the excess to 1996 * another driver, which won't work. 1997 */ 1998 mapsize = pci_mapsize(testval); 1999 count = 1 << mapsize; 2000 if (RF_ALIGNMENT(flags) < mapsize) 2001 flags = (flags & ~RF_ALIGNMENT_MASK) | 2002 RF_ALIGNMENT_LOG2(mapsize); 2003 /* 2004 * Allocate enough resource, and then write back the 2005 * appropriate BAR for that resource. 2006 */ 2007 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 2008 start, end, count, flags); 2009 if (res == NULL) { 2010 device_printf(child, "%#lx bytes at rid %#x res %d failed " 2011 "(%#lx, %#lx)\n", count, *rid, type, start, end); 2012 goto out; 2013 } 2014 resource_list_add(rl, type, *rid, start, end, count); 2015 rle = resource_list_find(rl, type, *rid); 2016 if (rle == NULL) 2017 panic("pci_alloc_map: unexpectedly can't find resource."); 2018 rle->res = res; 2019 rle->start = rman_get_start(res); 2020 rle->end = rman_get_end(res); 2021 rle->count = count; 2022 if (bootverbose) 2023 device_printf(child, "lazy allocation of %#lx bytes rid %#x " 2024 "type %d at %#lx\n", count, *rid, type, 2025 rman_get_start(res)); 2026 map = rman_get_start(res); 2027 out:; 2028 pci_write_config(child, *rid, map, 4); 2029 return res; 2030 } 2031 #endif /* PCI_MAP_FIXUP */ 2032 2033 struct resource * 2034 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 2035 u_long start, u_long end, u_long count, u_int flags) 2036 { 2037 struct pci_devinfo *dinfo = device_get_ivars(child); 2038 struct resource_list *rl = &dinfo->resources; 2039 #ifdef PCI_MAP_FIXUP 2040 struct resource_list_entry *rle; 2041 #endif /* PCI_MAP_FIXUP */ 2042 pcicfgregs *cfg = &dinfo->cfg; 2043 2044 /* 2045 * Perform lazy resource allocation 2046 */ 2047 if (device_get_parent(child) == dev) { 2048 switch (type) { 2049 case SYS_RES_IRQ: 2050 #ifdef __i386__ 2051 /* 2052 * If device doesn't have an interrupt routed, and is 2053 * deserving of an interrupt, try to assign it one. 2054 */ 2055 if ((cfg->intline == 255 || cfg->intline == 0) && 2056 (cfg->intpin != 0) && 2057 (start == 0) && (end == ~0UL)) { 2058 cfg->intline = PCIB_ROUTE_INTERRUPT( 2059 device_get_parent(dev), child, 2060 cfg->intpin); 2061 if (cfg->intline != 255) { 2062 pci_write_config(child, PCIR_INTLINE, 2063 cfg->intline, 1); 2064 resource_list_add(rl, SYS_RES_IRQ, 0, 2065 cfg->intline, cfg->intline, 1); 2066 } 2067 } 2068 break; 2069 #endif 2070 case SYS_RES_IOPORT: 2071 /* FALLTHROUGH */ 2072 case SYS_RES_MEMORY: 2073 if (*rid < PCIR_BAR(cfg->nummaps)) { 2074 /* 2075 * Enable the I/O mode. We should 2076 * also be assigning resources too 2077 * when none are present. The 2078 * resource_list_alloc kind of sorta does 2079 * this... 2080 */ 2081 if (PCI_ENABLE_IO(dev, child, type)) 2082 return (NULL); 2083 } 2084 #ifdef PCI_MAP_FIXUP 2085 rle = resource_list_find(rl, type, *rid); 2086 if (rle == NULL) 2087 return pci_alloc_map(dev, child, type, rid, 2088 start, end, count, flags); 2089 #endif /* PCI_MAP_FIXUP */ 2090 break; 2091 } 2092 #ifdef PCI_MAP_FIXUP 2093 /* 2094 * If we've already allocated the resource, then 2095 * return it now. But first we may need to activate 2096 * it, since we don't allocate the resource as active 2097 * above. Normally this would be done down in the 2098 * nexus, but since we short-circuit that path we have 2099 * to do its job here. Not sure if we should free the 2100 * resource if it fails to activate. 2101 * 2102 * Note: this also finds and returns resources for 2103 * atapci devices in legacy mode as allocated in 2104 * pci_ata_maps(). 2105 */ 2106 rle = resource_list_find(rl, type, *rid); 2107 if (rle != NULL && rle->res != NULL) { 2108 if (bootverbose) 2109 device_printf(child, "reserved %#lx bytes for " 2110 "rid %#x type %d at %#lx\n", 2111 rman_get_size(rle->res), *rid, 2112 type, rman_get_start(rle->res)); 2113 if ((flags & RF_ACTIVE) && 2114 bus_generic_activate_resource(dev, child, type, 2115 *rid, rle->res) != 0) 2116 return NULL; 2117 return rle->res; 2118 } 2119 #endif /* PCI_MAP_FIXUP */ 2120 } 2121 return resource_list_alloc(rl, dev, child, type, rid, 2122 start, end, count, flags); 2123 } 2124 2125 static int 2126 pci_release_resource(device_t dev, device_t child, int type, int rid, 2127 struct resource *r) 2128 { 2129 struct pci_devinfo *dinfo = device_get_ivars(child); 2130 struct resource_list *rl = &dinfo->resources; 2131 2132 return resource_list_release(rl, dev, child, type, rid, r); 2133 } 2134 2135 static int 2136 pci_set_resource(device_t dev, device_t child, int type, int rid, 2137 u_long start, u_long count) 2138 { 2139 struct pci_devinfo *dinfo = device_get_ivars(child); 2140 struct resource_list *rl = &dinfo->resources; 2141 2142 resource_list_add(rl, type, rid, start, start + count - 1, count); 2143 return 0; 2144 } 2145 2146 static int 2147 pci_get_resource(device_t dev, device_t child, int type, int rid, 2148 u_long *startp, u_long *countp) 2149 { 2150 struct pci_devinfo *dinfo = device_get_ivars(child); 2151 struct resource_list *rl = &dinfo->resources; 2152 struct resource_list_entry *rle; 2153 2154 rle = resource_list_find(rl, type, rid); 2155 if (!rle) 2156 return ENOENT; 2157 2158 if (startp) 2159 *startp = rle->start; 2160 if (countp) 2161 *countp = rle->count; 2162 2163 return 0; 2164 } 2165 2166 void 2167 pci_delete_resource(device_t dev, device_t child, int type, int rid) 2168 { 2169 kprintf("pci_delete_resource: PCI resources can not be deleted\n"); 2170 } 2171 2172 struct resource_list * 2173 pci_get_resource_list (device_t dev, device_t child) 2174 { 2175 struct pci_devinfo *dinfo = device_get_ivars(child); 2176 2177 if (dinfo == NULL) 2178 return (NULL); 2179 return (&dinfo->resources); 2180 } 2181 2182 u_int32_t 2183 pci_read_config_method(device_t dev, device_t child, int reg, int width) 2184 { 2185 struct pci_devinfo *dinfo = device_get_ivars(child); 2186 pcicfgregs *cfg = &dinfo->cfg; 2187 2188 return PCIB_READ_CONFIG(device_get_parent(dev), 2189 cfg->bus, cfg->slot, cfg->func, 2190 reg, width); 2191 } 2192 2193 void 2194 pci_write_config_method(device_t dev, device_t child, int reg, 2195 u_int32_t val, int width) 2196 { 2197 struct pci_devinfo *dinfo = device_get_ivars(child); 2198 pcicfgregs *cfg = &dinfo->cfg; 2199 2200 PCIB_WRITE_CONFIG(device_get_parent(dev), 2201 cfg->bus, cfg->slot, cfg->func, 2202 reg, val, width); 2203 } 2204 2205 int 2206 pci_child_location_str_method(device_t cbdev, device_t child, char *buf, 2207 size_t buflen) 2208 { 2209 struct pci_devinfo *dinfo; 2210 2211 dinfo = device_get_ivars(child); 2212 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 2213 pci_get_function(child)); 2214 return (0); 2215 } 2216 2217 int 2218 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf, 2219 size_t buflen) 2220 { 2221 struct pci_devinfo *dinfo; 2222 pcicfgregs *cfg; 2223 2224 dinfo = device_get_ivars(child); 2225 cfg = &dinfo->cfg; 2226 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 2227 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 2228 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 2229 cfg->progif); 2230 return (0); 2231 } 2232 2233 int 2234 pci_assign_interrupt_method(device_t dev, device_t child) 2235 { 2236 struct pci_devinfo *dinfo = device_get_ivars(child); 2237 pcicfgregs *cfg = &dinfo->cfg; 2238 2239 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 2240 cfg->intpin)); 2241 } 2242 2243 static int 2244 pci_modevent(module_t mod, int what, void *arg) 2245 { 2246 switch (what) { 2247 case MOD_LOAD: 2248 STAILQ_INIT(&pci_devq); 2249 break; 2250 case MOD_UNLOAD: 2251 break; 2252 } 2253 2254 return 0; 2255 } 2256 2257 int 2258 pci_resume(device_t dev) 2259 { 2260 int numdevs; 2261 int i; 2262 device_t *children; 2263 device_t child; 2264 struct pci_devinfo *dinfo; 2265 pcicfgregs *cfg; 2266 2267 device_get_children(dev, &children, &numdevs); 2268 2269 for (i = 0; i < numdevs; i++) { 2270 child = children[i]; 2271 2272 dinfo = device_get_ivars(child); 2273 cfg = &dinfo->cfg; 2274 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 2275 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 2276 if (PCI_INTERRUPT_VALID(cfg->intline)) { 2277 pci_write_config(child, PCIR_INTLINE, 2278 cfg->intline, 1); 2279 } 2280 } 2281 } 2282 2283 kfree(children, M_TEMP); 2284 2285 return (bus_generic_resume(dev)); 2286 } 2287 2288 static device_method_t pci_methods[] = { 2289 /* Device interface */ 2290 DEVMETHOD(device_probe, pci_probe), 2291 DEVMETHOD(device_attach, pci_attach), 2292 DEVMETHOD(device_shutdown, bus_generic_shutdown), 2293 DEVMETHOD(device_suspend, bus_generic_suspend), 2294 DEVMETHOD(device_resume, pci_resume), 2295 2296 /* Bus interface */ 2297 DEVMETHOD(bus_print_child, pci_print_child), 2298 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 2299 DEVMETHOD(bus_read_ivar, pci_read_ivar), 2300 DEVMETHOD(bus_write_ivar, pci_write_ivar), 2301 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2302 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 2303 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 2304 2305 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 2306 DEVMETHOD(bus_set_resource, pci_set_resource), 2307 DEVMETHOD(bus_get_resource, pci_get_resource), 2308 DEVMETHOD(bus_delete_resource, pci_delete_resource), 2309 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 2310 DEVMETHOD(bus_release_resource, pci_release_resource), 2311 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 2312 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 2313 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 2314 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 2315 2316 /* PCI interface */ 2317 DEVMETHOD(pci_read_config, pci_read_config_method), 2318 DEVMETHOD(pci_write_config, pci_write_config_method), 2319 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 2320 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 2321 DEVMETHOD(pci_enable_io, pci_enable_io_method), 2322 DEVMETHOD(pci_disable_io, pci_disable_io_method), 2323 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 2324 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 2325 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 2326 2327 { 0, 0 } 2328 }; 2329 2330 driver_t pci_driver = { 2331 "pci", 2332 pci_methods, 2333 1, /* no softc */ 2334 }; 2335 2336 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 2337 MODULE_VERSION(pci, 1); 2338