1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: src/sys/dev/pci/pci_pci.c,v 1.50.2.2.4.1 2009/04/15 03:14:26 kensmith Exp $ 31 */ 32 33 /* 34 * PCI:PCI bridge support. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/module.h> 41 #include <sys/bus.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 45 #include <bus/pci/pcivar.h> 46 #include <bus/pci/pcireg.h> 47 #include <bus/pci/pcib_private.h> 48 49 #include "pcib_if.h" 50 51 static int pcib_probe(device_t dev); 52 53 static device_method_t pcib_methods[] = { 54 /* Device interface */ 55 DEVMETHOD(device_probe, pcib_probe), 56 DEVMETHOD(device_attach, pcib_attach), 57 DEVMETHOD(device_detach, bus_generic_detach), 58 DEVMETHOD(device_shutdown, bus_generic_shutdown), 59 DEVMETHOD(device_suspend, bus_generic_suspend), 60 DEVMETHOD(device_resume, bus_generic_resume), 61 62 /* Bus interface */ 63 DEVMETHOD(bus_print_child, bus_generic_print_child), 64 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 65 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 66 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 67 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 68 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 69 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 70 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 71 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 72 73 /* pcib interface */ 74 DEVMETHOD(pcib_maxslots, pcib_maxslots), 75 DEVMETHOD(pcib_read_config, pcib_read_config), 76 DEVMETHOD(pcib_write_config, pcib_write_config), 77 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 78 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 79 DEVMETHOD(pcib_release_msi, pcib_release_msi), 80 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 81 DEVMETHOD(pcib_release_msix, pcib_release_msix), 82 DEVMETHOD(pcib_map_msi, pcib_map_msi), 83 84 { 0, 0 } 85 }; 86 87 static devclass_t pcib_devclass; 88 89 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 90 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0); 91 92 /* 93 * Is the prefetch window open (eg, can we allocate memory in it?) 94 */ 95 static int 96 pcib_is_prefetch_open(struct pcib_softc *sc) 97 { 98 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 99 } 100 101 /* 102 * Is the nonprefetch window open (eg, can we allocate memory in it?) 103 */ 104 static int 105 pcib_is_nonprefetch_open(struct pcib_softc *sc) 106 { 107 return (sc->membase > 0 && sc->membase < sc->memlimit); 108 } 109 110 /* 111 * Is the io window open (eg, can we allocate ports in it?) 112 */ 113 static int 114 pcib_is_io_open(struct pcib_softc *sc) 115 { 116 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 117 } 118 119 /* 120 * Generic device interface 121 */ 122 static int 123 pcib_probe(device_t dev) 124 { 125 if ((pci_get_class(dev) == PCIC_BRIDGE) && 126 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 127 device_set_desc(dev, "PCI-PCI bridge"); 128 #ifndef APIC_IO 129 return (-10000); 130 #else 131 /* PCIBIOS PCI-PCI bridge is -2000 */ 132 return (-1000); 133 #endif 134 } 135 return(ENXIO); 136 } 137 138 void 139 pcib_attach_common(device_t dev) 140 { 141 struct pcib_softc *sc; 142 uint8_t iolow; 143 144 sc = device_get_softc(dev); 145 sc->dev = dev; 146 147 /* 148 * Get current bridge configuration. 149 */ 150 sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 151 sc->domain = pci_get_domain(dev); 152 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 153 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 154 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 155 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 156 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 157 158 /* 159 * Determine current I/O decode. 160 */ 161 if (sc->command & PCIM_CMD_PORTEN) { 162 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 163 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 164 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 165 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 166 } else { 167 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 168 } 169 170 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 171 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 172 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 173 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 174 } else { 175 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 176 } 177 } 178 179 /* 180 * Determine current memory decode. 181 */ 182 if (sc->command & PCIM_CMD_MEMEN) { 183 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 184 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 185 iolow = pci_read_config(dev, PCIR_PMBASEL_1, 1); 186 if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 187 sc->pmembase = PCI_PPBMEMBASE( 188 pci_read_config(dev, PCIR_PMBASEH_1, 4), 189 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 190 else 191 sc->pmembase = PCI_PPBMEMBASE(0, 192 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 193 iolow = pci_read_config(dev, PCIR_PMLIMITL_1, 1); 194 if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 195 sc->pmemlimit = PCI_PPBMEMLIMIT( 196 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 197 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 198 else 199 sc->pmemlimit = PCI_PPBMEMLIMIT(0, 200 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 201 } 202 203 /* 204 * Quirk handling. 205 */ 206 switch (pci_get_devid(dev)) { 207 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 208 { 209 uint8_t supbus; 210 211 supbus = pci_read_config(dev, 0x41, 1); 212 if (supbus != 0xff) { 213 sc->secbus = supbus + 1; 214 sc->subbus = supbus + 1; 215 } 216 break; 217 } 218 219 /* 220 * The i82380FB mobile docking controller is a PCI-PCI bridge, 221 * and it is a subtractive bridge. However, the ProgIf is wrong 222 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 223 * happen. There's also a Toshiba bridge that behaves this 224 * way. 225 */ 226 case 0x124b8086: /* Intel 82380FB Mobile */ 227 case 0x060513d7: /* Toshiba ???? */ 228 sc->flags |= PCIB_SUBTRACTIVE; 229 break; 230 231 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 232 case 0x00dd10de: 233 { 234 char *cp; 235 236 if ((cp = kgetenv("smbios.planar.maker")) == NULL) 237 break; 238 if (strncmp(cp, "Compal", 6) != 0) { 239 kfreeenv(cp); 240 break; 241 } 242 kfreeenv(cp); 243 if ((cp = kgetenv("smbios.planar.product")) == NULL) 244 break; 245 if (strncmp(cp, "08A0", 4) != 0) { 246 kfreeenv(cp); 247 break; 248 } 249 kfreeenv(cp); 250 if (sc->subbus < 0xa) { 251 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 252 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 253 } 254 break; 255 } 256 } 257 258 if (pci_msi_device_blacklisted(dev)) 259 sc->flags |= PCIB_DISABLE_MSI; 260 261 /* 262 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 263 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 264 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 265 * This means they act as if they were subtractively decoding 266 * bridges and pass all transactions. Mark them and real ProgIf 1 267 * parts as subtractive. 268 */ 269 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 270 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 271 sc->flags |= PCIB_SUBTRACTIVE; 272 273 if (bootverbose) { 274 device_printf(dev, " domain %d\n", sc->domain); 275 device_printf(dev, " secondary bus %d\n", sc->secbus); 276 device_printf(dev, " subordinate bus %d\n", sc->subbus); 277 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 278 if (pcib_is_nonprefetch_open(sc)) 279 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 280 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 281 if (pcib_is_prefetch_open(sc)) 282 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 283 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 284 else 285 device_printf(dev, " no prefetched decode\n"); 286 if (sc->flags & PCIB_SUBTRACTIVE) 287 device_printf(dev, " Subtractively decoded bridge.\n"); 288 } 289 290 if (pci_is_pcie(dev) && pcie_slot_implemented(dev)) { 291 uint16_t slot_ctrl; 292 uint8_t ptr; 293 294 /* 295 * XXX 296 * Before proper PCI Express hot-plug support is in place, 297 * disable all hot-plug interrupts on the PCI Express root 298 * port or down stream port for now. 299 */ 300 #define HPINTRS (PCIEM_SLTCTL_HPINTR_MASK | PCIEM_SLTCTL_HPINTR_EN) 301 302 ptr = pci_get_pciecap_ptr(dev); 303 slot_ctrl = pci_read_config(dev, ptr + PCIER_SLOTCTRL, 2); 304 if (slot_ctrl & HPINTRS) { 305 device_printf(dev, "Disable PCI Express hot-plug " 306 "interrupts(0x%04x)\n", slot_ctrl & HPINTRS); 307 slot_ctrl &= ~HPINTRS; 308 pci_write_config(dev, ptr + PCIER_SLOTCTRL, slot_ctrl, 2); 309 } 310 311 #undef HPINTRS 312 } 313 314 /* 315 * XXX If the secondary bus number is zero, we should assign a bus number 316 * since the BIOS hasn't, then initialise the bridge. 317 */ 318 319 /* 320 * XXX If the subordinate bus number is less than the secondary bus number, 321 * we should pick a better value. One sensible alternative would be to 322 * pick 255; the only tradeoff here is that configuration transactions 323 * would be more widely routed than absolutely necessary. 324 */ 325 } 326 327 int 328 pcib_attach(device_t dev) 329 { 330 struct pcib_softc *sc; 331 device_t child; 332 333 pcib_attach_common(dev); 334 sc = device_get_softc(dev); 335 if (sc->secbus != 0) { 336 child = device_add_child(dev, "pci", sc->secbus); 337 if (child != NULL) 338 return(bus_generic_attach(dev)); 339 } 340 341 /* no secondary bus; we should have fixed this */ 342 return(0); 343 } 344 345 int 346 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 347 { 348 struct pcib_softc *sc = device_get_softc(dev); 349 350 switch (which) { 351 case PCIB_IVAR_DOMAIN: 352 *result = sc->domain; 353 return(0); 354 case PCIB_IVAR_BUS: 355 *result = sc->secbus; 356 return(0); 357 } 358 return(ENOENT); 359 } 360 361 int 362 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 363 { 364 struct pcib_softc *sc = device_get_softc(dev); 365 366 switch (which) { 367 case PCIB_IVAR_DOMAIN: 368 return(EINVAL); 369 case PCIB_IVAR_BUS: 370 sc->secbus = value; 371 return(0); 372 } 373 return(ENOENT); 374 } 375 376 /* 377 * We have to trap resource allocation requests and ensure that the bridge 378 * is set up to, or capable of handling them. 379 */ 380 struct resource * 381 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 382 u_long start, u_long end, u_long count, u_int flags) 383 { 384 struct pcib_softc *sc = device_get_softc(dev); 385 const char *name, *suffix; 386 int ok; 387 388 /* 389 * Fail the allocation for this range if it's not supported. 390 */ 391 name = device_get_nameunit(child); 392 if (name == NULL) { 393 name = ""; 394 suffix = ""; 395 } else 396 suffix = " "; 397 switch (type) { 398 case SYS_RES_IOPORT: 399 ok = 0; 400 if (!pcib_is_io_open(sc)) 401 break; 402 ok = (start >= sc->iobase && end <= sc->iolimit); 403 404 /* 405 * Make sure we allow access to VGA I/O addresses when the 406 * bridge has the "VGA Enable" bit set. 407 */ 408 if (!ok && pci_is_vga_ioport_range(start, end)) 409 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 410 411 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 412 if (!ok) { 413 if (start < sc->iobase) 414 start = sc->iobase; 415 if (end > sc->iolimit) 416 end = sc->iolimit; 417 if (start < end) 418 ok = 1; 419 } 420 } else { 421 ok = 1; 422 #if 1 423 if (start < sc->iobase && end > sc->iolimit) { 424 start = sc->iobase; 425 end = sc->iolimit; 426 } 427 #endif 428 } 429 if (end < start) { 430 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 431 end, start); 432 start = 0; 433 end = 0; 434 ok = 0; 435 } 436 if (!ok) { 437 device_printf(dev, "%s%srequested unsupported I/O " 438 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 439 name, suffix, start, end, sc->iobase, sc->iolimit); 440 return (NULL); 441 } 442 if (bootverbose) 443 device_printf(dev, 444 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 445 name, suffix, start, end); 446 break; 447 448 case SYS_RES_MEMORY: 449 ok = 0; 450 if (pcib_is_nonprefetch_open(sc)) 451 ok = ok || (start >= sc->membase && end <= sc->memlimit); 452 if (pcib_is_prefetch_open(sc)) 453 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 454 455 /* 456 * Make sure we allow access to VGA memory addresses when the 457 * bridge has the "VGA Enable" bit set. 458 */ 459 if (!ok && pci_is_vga_memory_range(start, end)) 460 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 461 462 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 463 if (!ok) { 464 ok = 1; 465 if (flags & RF_PREFETCHABLE) { 466 if (pcib_is_prefetch_open(sc)) { 467 if (start < sc->pmembase) 468 start = sc->pmembase; 469 if (end > sc->pmemlimit) 470 end = sc->pmemlimit; 471 } else { 472 ok = 0; 473 } 474 } else { /* non-prefetchable */ 475 if (pcib_is_nonprefetch_open(sc)) { 476 if (start < sc->membase) 477 start = sc->membase; 478 if (end > sc->memlimit) 479 end = sc->memlimit; 480 } else { 481 ok = 0; 482 } 483 } 484 } 485 } else if (!ok) { 486 ok = 1; /* subtractive bridge: always ok */ 487 #if 1 488 if (pcib_is_nonprefetch_open(sc)) { 489 if (start < sc->membase && end > sc->memlimit) { 490 start = sc->membase; 491 end = sc->memlimit; 492 } 493 } 494 if (pcib_is_prefetch_open(sc)) { 495 if (start < sc->pmembase && end > sc->pmemlimit) { 496 start = sc->pmembase; 497 end = sc->pmemlimit; 498 } 499 } 500 #endif 501 } 502 if (end < start) { 503 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 504 end, start); 505 start = 0; 506 end = 0; 507 ok = 0; 508 } 509 if (!ok && bootverbose) 510 device_printf(dev, 511 "%s%srequested unsupported memory range %#lx-%#lx " 512 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 513 name, suffix, start, end, 514 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 515 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 516 if (!ok) 517 return (NULL); 518 if (bootverbose) 519 device_printf(dev,"%s%srequested memory range " 520 "0x%lx-0x%lx: good\n", 521 name, suffix, start, end); 522 break; 523 524 default: 525 break; 526 } 527 /* 528 * Bridge is OK decoding this resource, so pass it up. 529 */ 530 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 531 count, flags)); 532 } 533 534 /* 535 * PCIB interface. 536 */ 537 int 538 pcib_maxslots(device_t dev) 539 { 540 return(PCI_SLOTMAX); 541 } 542 543 /* 544 * Since we are a child of a PCI bus, its parent must support the pcib interface. 545 */ 546 uint32_t 547 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 548 { 549 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 550 } 551 552 void 553 pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width) 554 { 555 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 556 } 557 558 /* 559 * Route an interrupt across a PCI bridge. 560 */ 561 int 562 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 563 { 564 device_t bus; 565 int parent_intpin; 566 int intnum; 567 568 /* 569 * 570 * The PCI standard defines a swizzle of the child-side device/intpin to 571 * the parent-side intpin as follows. 572 * 573 * device = device on child bus 574 * child_intpin = intpin on child bus slot (0-3) 575 * parent_intpin = intpin on parent bus slot (0-3) 576 * 577 * parent_intpin = (device + child_intpin) % 4 578 */ 579 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 580 581 /* 582 * Our parent is a PCI bus. Its parent must export the pcib interface 583 * which includes the ability to route interrupts. 584 */ 585 bus = device_get_parent(pcib); 586 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 587 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 588 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 589 pci_get_slot(dev), 'A' + pin - 1, intnum); 590 } 591 return(intnum); 592 } 593 594 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 595 int 596 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 597 { 598 struct pcib_softc *sc = device_get_softc(pcib); 599 device_t bus; 600 601 if (sc->flags & PCIB_DISABLE_MSI) 602 return (ENXIO); 603 bus = device_get_parent(pcib); 604 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 605 irqs)); 606 } 607 608 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 609 int 610 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 611 { 612 device_t bus; 613 614 bus = device_get_parent(pcib); 615 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 616 } 617 618 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 619 int 620 pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 621 { 622 struct pcib_softc *sc = device_get_softc(pcib); 623 device_t bus; 624 625 if (sc->flags & PCIB_DISABLE_MSI) 626 return (ENXIO); 627 bus = device_get_parent(pcib); 628 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 629 } 630 631 /* Pass request to release an MSI-X message up to the parent bridge. */ 632 int 633 pcib_release_msix(device_t pcib, device_t dev, int irq) 634 { 635 device_t bus; 636 637 bus = device_get_parent(pcib); 638 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 639 } 640 641 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 642 int 643 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 644 uint32_t *data) 645 { 646 device_t bus; 647 int error; 648 649 bus = device_get_parent(pcib); 650 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 651 if (error) 652 return (error); 653 654 pci_ht_map_msi(pcib, *addr); 655 return (0); 656 } 657 658 /* 659 * Try to read the bus number of a host-PCI bridge using appropriate config 660 * registers. 661 */ 662 int 663 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 664 uint8_t *busnum) 665 { 666 uint32_t id; 667 668 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 669 if (id == 0xffffffff) 670 return (0); 671 672 switch (id) { 673 case 0x12258086: 674 /* Intel 824?? */ 675 /* XXX This is a guess */ 676 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 677 *busnum = bus; 678 break; 679 case 0x84c48086: 680 /* Intel 82454KX/GX (Orion) */ 681 *busnum = read_config(bus, slot, func, 0x4a, 1); 682 break; 683 case 0x84ca8086: 684 /* 685 * For the 450nx chipset, there is a whole bundle of 686 * things pretending to be host bridges. The MIOC will 687 * be seen first and isn't really a pci bridge (the 688 * actual busses are attached to the PXB's). We need to 689 * read the registers of the MIOC to figure out the 690 * bus numbers for the PXB channels. 691 * 692 * Since the MIOC doesn't have a pci bus attached, we 693 * pretend it wasn't there. 694 */ 695 return (0); 696 case 0x84cb8086: 697 switch (slot) { 698 case 0x12: 699 /* Intel 82454NX PXB#0, Bus#A */ 700 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 701 break; 702 case 0x13: 703 /* Intel 82454NX PXB#0, Bus#B */ 704 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 705 break; 706 case 0x14: 707 /* Intel 82454NX PXB#1, Bus#A */ 708 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 709 break; 710 case 0x15: 711 /* Intel 82454NX PXB#1, Bus#B */ 712 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 713 break; 714 } 715 break; 716 717 /* ServerWorks -- vendor 0x1166 */ 718 case 0x00051166: 719 case 0x00061166: 720 case 0x00081166: 721 case 0x00091166: 722 case 0x00101166: 723 case 0x00111166: 724 case 0x00171166: 725 case 0x01011166: 726 case 0x010f1014: 727 case 0x02011166: 728 case 0x03021014: 729 *busnum = read_config(bus, slot, func, 0x44, 1); 730 break; 731 732 /* Compaq/HP -- vendor 0x0e11 */ 733 case 0x60100e11: 734 *busnum = read_config(bus, slot, func, 0xc8, 1); 735 break; 736 default: 737 /* Don't know how to read bus number. */ 738 return 0; 739 } 740 741 return 1; 742 } 743