1 /*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: src/sys/dev/pci/pci_pci.c,v 1.50.2.2.4.1 2009/04/15 03:14:26 kensmith Exp $ 31 */ 32 33 /* 34 * PCI:PCI bridge support. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/module.h> 41 #include <sys/bus.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 #include <machine_base/apic/ioapic.h> 45 46 #include <bus/pci/pcivar.h> 47 #include <bus/pci/pcireg.h> 48 #include <bus/pci/pcib_private.h> 49 50 #include "pcib_if.h" 51 52 static int pcib_probe(device_t dev); 53 54 static device_method_t pcib_methods[] = { 55 /* Device interface */ 56 DEVMETHOD(device_probe, pcib_probe), 57 DEVMETHOD(device_attach, pcib_attach), 58 DEVMETHOD(device_detach, bus_generic_detach), 59 DEVMETHOD(device_shutdown, bus_generic_shutdown), 60 DEVMETHOD(device_suspend, bus_generic_suspend), 61 DEVMETHOD(device_resume, bus_generic_resume), 62 63 /* Bus interface */ 64 DEVMETHOD(bus_print_child, bus_generic_print_child), 65 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 66 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 67 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 68 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 69 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 70 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 71 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 72 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 73 74 /* pcib interface */ 75 DEVMETHOD(pcib_maxslots, pcib_maxslots), 76 DEVMETHOD(pcib_read_config, pcib_read_config), 77 DEVMETHOD(pcib_write_config, pcib_write_config), 78 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 79 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 80 DEVMETHOD(pcib_release_msi, pcib_release_msi), 81 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 82 DEVMETHOD(pcib_release_msix, pcib_release_msix), 83 DEVMETHOD(pcib_map_msi, pcib_map_msi), 84 85 DEVMETHOD_END 86 }; 87 88 static devclass_t pcib_devclass; 89 90 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 91 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL); 92 93 /* 94 * Is the prefetch window open (eg, can we allocate memory in it?) 95 */ 96 static int 97 pcib_is_prefetch_open(struct pcib_softc *sc) 98 { 99 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 100 } 101 102 /* 103 * Is the nonprefetch window open (eg, can we allocate memory in it?) 104 */ 105 static int 106 pcib_is_nonprefetch_open(struct pcib_softc *sc) 107 { 108 return (sc->membase > 0 && sc->membase < sc->memlimit); 109 } 110 111 /* 112 * Is the io window open (eg, can we allocate ports in it?) 113 */ 114 static int 115 pcib_is_io_open(struct pcib_softc *sc) 116 { 117 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 118 } 119 120 /* 121 * Generic device interface 122 */ 123 static int 124 pcib_probe(device_t dev) 125 { 126 if ((pci_get_class(dev) == PCIC_BRIDGE) && 127 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 128 device_set_desc(dev, "PCI-PCI bridge"); 129 #if defined(__x86_64__) 130 /* PCIBIOS PCI-PCI bridge is -2000 */ 131 if (ioapic_enable) 132 return (-1000); 133 #endif 134 return (-10000); 135 } 136 return(ENXIO); 137 } 138 139 void 140 pcib_attach_common(device_t dev) 141 { 142 struct pcib_softc *sc; 143 uint8_t iolow; 144 145 sc = device_get_softc(dev); 146 sc->dev = dev; 147 148 /* 149 * Get current bridge configuration. 150 */ 151 sc->command = pci_read_config(dev, PCIR_COMMAND, 1); 152 sc->domain = pci_get_domain(dev); 153 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 154 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 155 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 156 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 157 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 158 159 /* 160 * Determine current I/O decode. 161 */ 162 if (sc->command & PCIM_CMD_PORTEN) { 163 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 164 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 165 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2), 166 pci_read_config(dev, PCIR_IOBASEL_1, 1)); 167 } else { 168 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1)); 169 } 170 171 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 172 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 173 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2), 174 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 175 } else { 176 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 177 } 178 } 179 180 /* 181 * Determine current memory decode. 182 */ 183 if (sc->command & PCIM_CMD_MEMEN) { 184 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2)); 185 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 186 iolow = pci_read_config(dev, PCIR_PMBASEL_1, 1); 187 if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 188 sc->pmembase = PCI_PPBMEMBASE( 189 pci_read_config(dev, PCIR_PMBASEH_1, 4), 190 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 191 else 192 sc->pmembase = PCI_PPBMEMBASE(0, 193 pci_read_config(dev, PCIR_PMBASEL_1, 2)); 194 iolow = pci_read_config(dev, PCIR_PMLIMITL_1, 1); 195 if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 196 sc->pmemlimit = PCI_PPBMEMLIMIT( 197 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 198 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 199 else 200 sc->pmemlimit = PCI_PPBMEMLIMIT(0, 201 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 202 } 203 204 /* 205 * Quirk handling. 206 */ 207 switch (pci_get_devid(dev)) { 208 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 209 { 210 uint8_t supbus; 211 212 supbus = pci_read_config(dev, 0x41, 1); 213 if (supbus != 0xff) { 214 sc->secbus = supbus + 1; 215 sc->subbus = supbus + 1; 216 } 217 break; 218 } 219 220 /* 221 * The i82380FB mobile docking controller is a PCI-PCI bridge, 222 * and it is a subtractive bridge. However, the ProgIf is wrong 223 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 224 * happen. There's also a Toshiba bridge that behaves this 225 * way. 226 */ 227 case 0x124b8086: /* Intel 82380FB Mobile */ 228 case 0x060513d7: /* Toshiba ???? */ 229 sc->flags |= PCIB_SUBTRACTIVE; 230 break; 231 232 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 233 case 0x00dd10de: 234 { 235 char *cp; 236 237 if ((cp = kgetenv("smbios.planar.maker")) == NULL) 238 break; 239 if (strncmp(cp, "Compal", 6) != 0) { 240 kfreeenv(cp); 241 break; 242 } 243 kfreeenv(cp); 244 if ((cp = kgetenv("smbios.planar.product")) == NULL) 245 break; 246 if (strncmp(cp, "08A0", 4) != 0) { 247 kfreeenv(cp); 248 break; 249 } 250 kfreeenv(cp); 251 if (sc->subbus < 0xa) { 252 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 253 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 254 } 255 break; 256 } 257 } 258 259 if (pci_msi_device_blacklisted(dev)) 260 sc->flags |= PCIB_DISABLE_MSI; 261 262 /* 263 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 264 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 265 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 266 * This means they act as if they were subtractively decoding 267 * bridges and pass all transactions. Mark them and real ProgIf 1 268 * parts as subtractive. 269 */ 270 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 271 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 272 sc->flags |= PCIB_SUBTRACTIVE; 273 274 if (bootverbose) { 275 device_printf(dev, " domain %d\n", sc->domain); 276 device_printf(dev, " secondary bus %d\n", sc->secbus); 277 device_printf(dev, " subordinate bus %d\n", sc->subbus); 278 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit); 279 if (pcib_is_nonprefetch_open(sc)) 280 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 281 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 282 if (pcib_is_prefetch_open(sc)) 283 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 284 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 285 else 286 device_printf(dev, " no prefetched decode\n"); 287 if (sc->flags & PCIB_SUBTRACTIVE) 288 device_printf(dev, " Subtractively decoded bridge.\n"); 289 } 290 291 if (pci_is_pcie(dev) && pcie_slot_implemented(dev)) { 292 uint16_t slot_ctrl; 293 uint8_t ptr; 294 295 /* 296 * XXX 297 * Before proper PCI Express hot-plug support is in place, 298 * disable all hot-plug interrupts on the PCI Express root 299 * port or down stream port for now. 300 */ 301 #define HPINTRS (PCIEM_SLOTCTL_HPINTR_MASK | PCIEM_SLOTCTL_HPINTR_EN) 302 303 ptr = pci_get_pciecap_ptr(dev); 304 slot_ctrl = pci_read_config(dev, ptr + PCIER_SLOTCTL, 2); 305 if (slot_ctrl & HPINTRS) { 306 device_printf(dev, "Disable PCI Express hot-plug " 307 "interrupts(0x%04x)\n", slot_ctrl & HPINTRS); 308 slot_ctrl &= ~HPINTRS; 309 pci_write_config(dev, ptr + PCIER_SLOTCTL, slot_ctrl, 2); 310 } 311 312 #undef HPINTRS 313 } 314 315 /* 316 * XXX If the secondary bus number is zero, we should assign a bus number 317 * since the BIOS hasn't, then initialise the bridge. 318 */ 319 320 /* 321 * XXX If the subordinate bus number is less than the secondary bus number, 322 * we should pick a better value. One sensible alternative would be to 323 * pick 255; the only tradeoff here is that configuration transactions 324 * would be more widely routed than absolutely necessary. 325 */ 326 327 /* 328 * Always enable busmastering on bridges so that transactions 329 * initiated on the secondary bus are passed through to the 330 * primary bus. 331 */ 332 pci_enable_busmaster(dev); 333 } 334 335 int 336 pcib_attach(device_t dev) 337 { 338 struct pcib_softc *sc; 339 device_t child; 340 341 pcib_attach_common(dev); 342 sc = device_get_softc(dev); 343 if (sc->secbus != 0) { 344 child = device_add_child(dev, "pci", sc->secbus); 345 if (child != NULL) 346 return(bus_generic_attach(dev)); 347 } 348 349 /* no secondary bus; we should have fixed this */ 350 return(0); 351 } 352 353 int 354 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 355 { 356 struct pcib_softc *sc = device_get_softc(dev); 357 358 switch (which) { 359 case PCIB_IVAR_DOMAIN: 360 *result = sc->domain; 361 return(0); 362 case PCIB_IVAR_BUS: 363 *result = sc->secbus; 364 return(0); 365 } 366 return(ENOENT); 367 } 368 369 int 370 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 371 { 372 struct pcib_softc *sc = device_get_softc(dev); 373 374 switch (which) { 375 case PCIB_IVAR_DOMAIN: 376 return(EINVAL); 377 case PCIB_IVAR_BUS: 378 sc->secbus = value; 379 return(0); 380 } 381 return(ENOENT); 382 } 383 384 /* 385 * We have to trap resource allocation requests and ensure that the bridge 386 * is set up to, or capable of handling them. 387 */ 388 struct resource * 389 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 390 u_long start, u_long end, u_long count, u_int flags, int cpuid) 391 { 392 struct pcib_softc *sc = device_get_softc(dev); 393 const char *name, *suffix; 394 int ok; 395 396 /* 397 * Fail the allocation for this range if it's not supported. 398 */ 399 name = device_get_nameunit(child); 400 if (name == NULL) { 401 name = ""; 402 suffix = ""; 403 } else 404 suffix = " "; 405 switch (type) { 406 case SYS_RES_IOPORT: 407 ok = 0; 408 if (!pcib_is_io_open(sc)) 409 break; 410 ok = (start >= sc->iobase && end <= sc->iolimit); 411 412 /* 413 * Make sure we allow access to VGA I/O addresses when the 414 * bridge has the "VGA Enable" bit set. 415 */ 416 if (!ok && pci_is_vga_ioport_range(start, end)) 417 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 418 419 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 420 if (!ok) { 421 if (start < sc->iobase) 422 start = sc->iobase; 423 if (end > sc->iolimit) 424 end = sc->iolimit; 425 if (start < end) 426 ok = 1; 427 } 428 } else { 429 ok = 1; 430 #if 1 431 if (start < sc->iobase && end > sc->iolimit) { 432 start = sc->iobase; 433 end = sc->iolimit; 434 } 435 #endif 436 } 437 if (end < start) { 438 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 439 end, start); 440 start = 0; 441 end = 0; 442 ok = 0; 443 } 444 if (!ok) { 445 device_printf(dev, "%s%srequested unsupported I/O " 446 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 447 name, suffix, start, end, sc->iobase, sc->iolimit); 448 return (NULL); 449 } 450 if (bootverbose) 451 device_printf(dev, 452 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 453 name, suffix, start, end); 454 break; 455 456 case SYS_RES_MEMORY: 457 ok = 0; 458 if (pcib_is_nonprefetch_open(sc)) 459 ok = ok || (start >= sc->membase && end <= sc->memlimit); 460 if (pcib_is_prefetch_open(sc)) 461 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 462 463 /* 464 * Make sure we allow access to VGA memory addresses when the 465 * bridge has the "VGA Enable" bit set. 466 */ 467 if (!ok && pci_is_vga_memory_range(start, end)) 468 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 469 470 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 471 if (!ok) { 472 ok = 1; 473 if (flags & RF_PREFETCHABLE) { 474 if (pcib_is_prefetch_open(sc)) { 475 if (start < sc->pmembase) 476 start = sc->pmembase; 477 if (end > sc->pmemlimit) 478 end = sc->pmemlimit; 479 } else { 480 ok = 0; 481 } 482 } else { /* non-prefetchable */ 483 if (pcib_is_nonprefetch_open(sc)) { 484 if (start < sc->membase) 485 start = sc->membase; 486 if (end > sc->memlimit) 487 end = sc->memlimit; 488 } else { 489 ok = 0; 490 } 491 } 492 } 493 } else if (!ok) { 494 ok = 1; /* subtractive bridge: always ok */ 495 #if 1 496 if (pcib_is_nonprefetch_open(sc)) { 497 if (start < sc->membase && end > sc->memlimit) { 498 start = sc->membase; 499 end = sc->memlimit; 500 } 501 } 502 if (pcib_is_prefetch_open(sc)) { 503 if (start < sc->pmembase && end > sc->pmemlimit) { 504 start = sc->pmembase; 505 end = sc->pmemlimit; 506 } 507 } 508 #endif 509 } 510 if (end < start) { 511 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 512 end, start); 513 start = 0; 514 end = 0; 515 ok = 0; 516 } 517 if (!ok && bootverbose) 518 device_printf(dev, 519 "%s%srequested unsupported memory range %#lx-%#lx " 520 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 521 name, suffix, start, end, 522 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 523 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 524 if (!ok) 525 return (NULL); 526 if (bootverbose) 527 device_printf(dev,"%s%srequested memory range " 528 "0x%lx-0x%lx: good\n", 529 name, suffix, start, end); 530 break; 531 532 default: 533 break; 534 } 535 /* 536 * Bridge is OK decoding this resource, so pass it up. 537 */ 538 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 539 count, flags, cpuid)); 540 } 541 542 /* 543 * PCIB interface. 544 */ 545 int 546 pcib_maxslots(device_t dev) 547 { 548 return(PCI_SLOTMAX); 549 } 550 551 /* 552 * Since we are a child of a PCI bus, its parent must support the pcib interface. 553 */ 554 uint32_t 555 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width) 556 { 557 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width)); 558 } 559 560 void 561 pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width) 562 { 563 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width); 564 } 565 566 /* 567 * Route an interrupt across a PCI bridge. 568 */ 569 int 570 pcib_route_interrupt(device_t pcib, device_t dev, int pin) 571 { 572 device_t bus; 573 int parent_intpin; 574 int intnum; 575 576 /* 577 * 578 * The PCI standard defines a swizzle of the child-side device/intpin to 579 * the parent-side intpin as follows. 580 * 581 * device = device on child bus 582 * child_intpin = intpin on child bus slot (0-3) 583 * parent_intpin = intpin on parent bus slot (0-3) 584 * 585 * parent_intpin = (device + child_intpin) % 4 586 */ 587 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 588 589 /* 590 * Our parent is a PCI bus. Its parent must export the pcib interface 591 * which includes the ability to route interrupts. 592 */ 593 bus = device_get_parent(pcib); 594 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 595 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 596 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 597 pci_get_slot(dev), 'A' + pin - 1, intnum); 598 } 599 return(intnum); 600 } 601 602 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 603 int 604 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, 605 int *irqs, int cpuid) 606 { 607 struct pcib_softc *sc = device_get_softc(pcib); 608 device_t bus; 609 610 if (sc->flags & PCIB_DISABLE_MSI) 611 return (ENXIO); 612 bus = device_get_parent(pcib); 613 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 614 irqs, cpuid)); 615 } 616 617 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 618 int 619 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs, int cpuid) 620 { 621 device_t bus; 622 623 bus = device_get_parent(pcib); 624 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs, 625 cpuid)); 626 } 627 628 /* Pass request to alloc an MSI-X message up to the parent bridge. */ 629 int 630 pcib_alloc_msix(device_t pcib, device_t dev, int *irq, int cpuid) 631 { 632 struct pcib_softc *sc = device_get_softc(pcib); 633 device_t bus; 634 635 if (sc->flags & PCIB_DISABLE_MSI) 636 return (ENXIO); 637 bus = device_get_parent(pcib); 638 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq, cpuid)); 639 } 640 641 /* Pass request to release an MSI-X message up to the parent bridge. */ 642 int 643 pcib_release_msix(device_t pcib, device_t dev, int irq, int cpuid) 644 { 645 device_t bus; 646 647 bus = device_get_parent(pcib); 648 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq, cpuid)); 649 } 650 651 /* Pass request to map MSI/MSI-X message up to parent bridge. */ 652 int 653 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 654 uint32_t *data, int cpuid) 655 { 656 device_t bus; 657 int error; 658 659 bus = device_get_parent(pcib); 660 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data, 661 cpuid); 662 if (error) 663 return (error); 664 665 pci_ht_map_msi(pcib, *addr); 666 return (0); 667 } 668 669 /* 670 * Try to read the bus number of a host-PCI bridge using appropriate config 671 * registers. 672 */ 673 int 674 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func, 675 uint8_t *busnum) 676 { 677 uint32_t id; 678 679 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4); 680 if (id == 0xffffffff) 681 return (0); 682 683 switch (id) { 684 case 0x12258086: 685 /* Intel 824?? */ 686 /* XXX This is a guess */ 687 /* *busnum = read_config(bus, slot, func, 0x41, 1); */ 688 *busnum = bus; 689 break; 690 case 0x84c48086: 691 /* Intel 82454KX/GX (Orion) */ 692 *busnum = read_config(bus, slot, func, 0x4a, 1); 693 break; 694 case 0x84ca8086: 695 /* 696 * For the 450nx chipset, there is a whole bundle of 697 * things pretending to be host bridges. The MIOC will 698 * be seen first and isn't really a pci bridge (the 699 * actual busses are attached to the PXB's). We need to 700 * read the registers of the MIOC to figure out the 701 * bus numbers for the PXB channels. 702 * 703 * Since the MIOC doesn't have a pci bus attached, we 704 * pretend it wasn't there. 705 */ 706 return (0); 707 case 0x84cb8086: 708 switch (slot) { 709 case 0x12: 710 /* Intel 82454NX PXB#0, Bus#A */ 711 *busnum = read_config(bus, 0x10, func, 0xd0, 1); 712 break; 713 case 0x13: 714 /* Intel 82454NX PXB#0, Bus#B */ 715 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1; 716 break; 717 case 0x14: 718 /* Intel 82454NX PXB#1, Bus#A */ 719 *busnum = read_config(bus, 0x10, func, 0xd3, 1); 720 break; 721 case 0x15: 722 /* Intel 82454NX PXB#1, Bus#B */ 723 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1; 724 break; 725 } 726 break; 727 728 /* ServerWorks -- vendor 0x1166 */ 729 case 0x00051166: 730 case 0x00061166: 731 case 0x00081166: 732 case 0x00091166: 733 case 0x00101166: 734 case 0x00111166: 735 case 0x00171166: 736 case 0x01011166: 737 case 0x010f1014: 738 case 0x02011166: 739 case 0x03021014: 740 *busnum = read_config(bus, slot, func, 0x44, 1); 741 break; 742 743 /* Compaq/HP -- vendor 0x0e11 */ 744 case 0x60100e11: 745 *busnum = read_config(bus, slot, func, 0xc8, 1); 746 break; 747 default: 748 /* Don't know how to read bus number. */ 749 return 0; 750 } 751 752 return 1; 753 } 754