1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/pci/pcivar.h,v 1.41.2.2 2002/01/10 12:08:22 mdodd Exp $ 27 * $DragonFly: src/sys/bus/pci/pcivar.h,v 1.2 2003/06/17 04:28:57 dillon Exp $ 28 * 29 */ 30 31 #ifndef _PCIVAR_H_ 32 #define _PCIVAR_H_ 33 34 #ifndef PCI_COMPAT 35 #define PCI_COMPAT 36 #endif 37 38 #include <sys/queue.h> 39 40 /* some PCI bus constants */ 41 42 #define PCI_BUSMAX 255 /* highest supported bus number */ 43 #define PCI_SLOTMAX 31 /* highest supported slot number */ 44 #define PCI_FUNCMAX 7 /* highest supported function number */ 45 #define PCI_REGMAX 255 /* highest supported config register addr. */ 46 47 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 48 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 49 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 50 51 /* pci_addr_t covers this system's PCI bus address space: 32 or 64 bit */ 52 53 #ifdef PCI_A64 54 typedef u_int64_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 55 #else 56 typedef u_int32_t pci_addr_t; /* u_int64_t for system with 64bit addresses */ 57 #endif 58 59 /* config header information common to all header types */ 60 61 typedef struct pcicfg { 62 struct device *dev; /* device which owns this */ 63 void *hdrspec; /* pointer to header type specific data */ 64 65 u_int16_t subvendor; /* card vendor ID */ 66 u_int16_t subdevice; /* card device ID, assigned by card vendor */ 67 u_int16_t vendor; /* chip vendor ID */ 68 u_int16_t device; /* chip device ID, assigned by chip vendor */ 69 70 u_int16_t cmdreg; /* disable/enable chip and PCI options */ 71 u_int16_t statreg; /* supported PCI features and error state */ 72 73 u_int8_t baseclass; /* chip PCI class */ 74 u_int8_t subclass; /* chip PCI subclass */ 75 u_int8_t progif; /* chip PCI programming interface */ 76 u_int8_t revid; /* chip revision ID */ 77 78 u_int8_t hdrtype; /* chip config header type */ 79 u_int8_t cachelnsz; /* cache line size in 4byte units */ 80 u_int8_t intpin; /* PCI interrupt pin */ 81 u_int8_t intline; /* interrupt line (IRQ for PC arch) */ 82 83 u_int8_t mingnt; /* min. useful bus grant time in 250ns units */ 84 u_int8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 85 u_int8_t lattimer; /* latency timer in units of 30ns bus cycles */ 86 87 u_int8_t mfdev; /* multi-function device (from hdrtype reg) */ 88 u_int8_t nummaps; /* actual number of PCI maps used */ 89 90 u_int8_t hose; /* hose which bus is attached to */ 91 u_int8_t bus; /* config space bus address */ 92 u_int8_t slot; /* config space slot address */ 93 u_int8_t func; /* config space function number */ 94 95 u_int8_t secondarybus; /* bus on secondary side of bridge, if any */ 96 u_int8_t subordinatebus; /* topmost bus number behind bridge, if any */ 97 98 u_int16_t pp_cap; /* PCI power management capabilities */ 99 u_int8_t pp_status; /* config space address of PCI power status reg */ 100 u_int8_t pp_pmcsr; /* config space address of PMCSR reg */ 101 u_int8_t pp_data; /* config space address of PCI power data reg */ 102 } pcicfgregs; 103 104 /* additional type 1 device config header information (PCI to PCI bridge) */ 105 106 #ifdef PCI_A64 107 #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 108 #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 109 #else 110 #define PCI_PPBMEMBASE(h,l) (((l)<<16) & ~0xfffff) 111 #define PCI_PPBMEMLIMIT(h,l) (((l)<<16) | 0xfffff) 112 #endif /* PCI_A64 */ 113 114 #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 115 #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 116 117 typedef struct { 118 pci_addr_t pmembase; /* base address of prefetchable memory */ 119 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 120 u_int32_t membase; /* base address of memory window */ 121 u_int32_t memlimit; /* topmost address of memory window */ 122 u_int32_t iobase; /* base address of port window */ 123 u_int32_t iolimit; /* topmost address of port window */ 124 u_int16_t secstat; /* secondary bus status register */ 125 u_int16_t bridgectl; /* bridge control register */ 126 u_int8_t seclat; /* CardBus latency timer */ 127 } pcih1cfgregs; 128 129 /* additional type 2 device config header information (CardBus bridge) */ 130 131 typedef struct { 132 u_int32_t membase0; /* base address of memory window */ 133 u_int32_t memlimit0; /* topmost address of memory window */ 134 u_int32_t membase1; /* base address of memory window */ 135 u_int32_t memlimit1; /* topmost address of memory window */ 136 u_int32_t iobase0; /* base address of port window */ 137 u_int32_t iolimit0; /* topmost address of port window */ 138 u_int32_t iobase1; /* base address of port window */ 139 u_int32_t iolimit1; /* topmost address of port window */ 140 u_int32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 141 u_int16_t secstat; /* secondary bus status register */ 142 u_int16_t bridgectl; /* bridge control register */ 143 u_int8_t seclat; /* CardBus latency timer */ 144 } pcih2cfgregs; 145 146 /* PCI bus attach definitions (there could be multiple PCI bus *trees* ... */ 147 148 typedef struct pciattach { 149 int unit; 150 int pcibushigh; 151 struct pciattach *next; 152 } pciattach; 153 154 extern u_int32_t pci_numdevs; 155 156 157 /* externally visible functions */ 158 159 const char *pci_ata_match(struct device *dev); 160 const char *pci_usb_match(struct device *dev); 161 const char *pci_vga_match(struct device *dev); 162 163 /* low level PCI config register functions provided by pcibus.c */ 164 165 int pci_cfgread (pcicfgregs *cfg, int reg, int bytes); 166 void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes); 167 #ifdef __alpha__ 168 vm_offset_t pci_cvt_to_dense (vm_offset_t); 169 vm_offset_t pci_cvt_to_bwx (vm_offset_t); 170 #endif /* __alpha__ */ 171 172 /* low level devlist operations for the 2.2 compatibility code in pci.c */ 173 pcicfgregs * pci_devlist_get_parent(pcicfgregs *cfg); 174 175 #ifdef _SYS_BUS_H_ 176 177 #include "pci_if.h" 178 179 /* 180 * Define pci-specific resource flags for accessing memory via dense 181 * or bwx memory spaces. These flags are ignored on i386. 182 */ 183 #define PCI_RF_DENSE 0x10000 184 #define PCI_RF_BWX 0x20000 185 186 enum pci_device_ivars { 187 PCI_IVAR_SUBVENDOR, 188 PCI_IVAR_SUBDEVICE, 189 PCI_IVAR_VENDOR, 190 PCI_IVAR_DEVICE, 191 PCI_IVAR_DEVID, 192 PCI_IVAR_CLASS, 193 PCI_IVAR_SUBCLASS, 194 PCI_IVAR_PROGIF, 195 PCI_IVAR_REVID, 196 PCI_IVAR_INTPIN, 197 PCI_IVAR_IRQ, 198 PCI_IVAR_BUS, 199 PCI_IVAR_SLOT, 200 PCI_IVAR_FUNCTION, 201 PCI_IVAR_SECONDARYBUS, 202 PCI_IVAR_SUBORDINATEBUS, 203 PCI_IVAR_HOSE, 204 }; 205 206 /* 207 * Simplified accessors for pci devices 208 */ 209 #define PCI_ACCESSOR(A, B, T) \ 210 \ 211 static __inline T pci_get_ ## A(device_t dev) \ 212 { \ 213 uintptr_t v; \ 214 BUS_READ_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, &v); \ 215 return (T) v; \ 216 } \ 217 \ 218 static __inline void pci_set_ ## A(device_t dev, T t) \ 219 { \ 220 u_long v = (u_long) t; \ 221 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCI_IVAR_ ## B, v); \ 222 } 223 224 PCI_ACCESSOR(subvendor, SUBVENDOR, u_int16_t) 225 PCI_ACCESSOR(subdevice, SUBDEVICE, u_int16_t) 226 PCI_ACCESSOR(vendor, VENDOR, u_int16_t) 227 PCI_ACCESSOR(device, DEVICE, u_int16_t) 228 PCI_ACCESSOR(devid, DEVID, u_int32_t) 229 PCI_ACCESSOR(class, CLASS, u_int8_t) 230 PCI_ACCESSOR(subclass, SUBCLASS, u_int8_t) 231 PCI_ACCESSOR(progif, PROGIF, u_int8_t) 232 PCI_ACCESSOR(revid, REVID, u_int8_t) 233 PCI_ACCESSOR(intpin, INTPIN, u_int8_t) 234 PCI_ACCESSOR(irq, IRQ, u_int8_t) 235 PCI_ACCESSOR(bus, BUS, u_int8_t) 236 PCI_ACCESSOR(slot, SLOT, u_int8_t) 237 PCI_ACCESSOR(function, FUNCTION, u_int8_t) 238 PCI_ACCESSOR(secondarybus, SECONDARYBUS, u_int8_t) 239 PCI_ACCESSOR(subordinatebus, SUBORDINATEBUS, u_int8_t) 240 PCI_ACCESSOR(hose, HOSE, u_int32_t) 241 242 static __inline u_int32_t 243 pci_read_config(device_t dev, int reg, int width) 244 { 245 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 246 } 247 248 static __inline void 249 pci_write_config(device_t dev, int reg, u_int32_t val, int width) 250 { 251 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 252 } 253 254 /* 255 * Convenience functions. 256 * 257 * These should be used in preference to manually manipulating 258 * configuration space. 259 */ 260 static __inline void 261 pci_enable_busmaster(device_t dev) 262 { 263 PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev); 264 } 265 266 static __inline void 267 pci_disable_busmaster(device_t dev) 268 { 269 PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev); 270 } 271 272 static __inline void 273 pci_enable_io(device_t dev, int space) 274 { 275 PCI_ENABLE_IO(device_get_parent(dev), dev, space); 276 } 277 278 static __inline void 279 pci_disable_io(device_t dev, int space) 280 { 281 PCI_DISABLE_IO(device_get_parent(dev), dev, space); 282 } 283 284 /* 285 * PCI power states are as defined by ACPI: 286 * 287 * D0 State in which device is on and running. It is receiving full 288 * power from the system and delivering full functionality to the user. 289 * D1 Class-specific low-power state in which device context may or may not 290 * be lost. Buses in D1 cannot do anything to the bus that would force 291 * devices on that bus to loose context. 292 * D2 Class-specific low-power state in which device context may or may 293 * not be lost. Attains greater power savings than D1. Buses in D2 294 * can cause devices on that bus to loose some context. Devices in D2 295 * must be prepared for the bus to be in D2 or higher. 296 * D3 State in which the device is off and not running. Device context is 297 * lost. Power can be removed from the device. 298 */ 299 #define PCI_POWERSTATE_D0 0 300 #define PCI_POWERSTATE_D1 1 301 #define PCI_POWERSTATE_D2 2 302 #define PCI_POWERSTATE_D3 3 303 #define PCI_POWERSTATE_UNKNOWN -1 304 305 static __inline int 306 pci_set_powerstate(device_t dev, int state) 307 { 308 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 309 } 310 311 static __inline int 312 pci_get_powerstate(device_t dev) 313 { 314 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 315 } 316 317 /* 318 * Ivars for pci bridges. 319 */ 320 321 /*typedef enum pci_device_ivars pcib_device_ivars;*/ 322 enum pcib_device_ivars { 323 PCIB_IVAR_HOSE, 324 }; 325 326 #define PCIB_ACCESSOR(A, B, T) \ 327 \ 328 static __inline T pcib_get_ ## A(device_t dev) \ 329 { \ 330 uintptr_t v; \ 331 BUS_READ_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, &v); \ 332 return (T) v; \ 333 } \ 334 \ 335 static __inline void pcib_set_ ## A(device_t dev, T t) \ 336 { \ 337 u_long v = (u_long) t; \ 338 BUS_WRITE_IVAR(device_get_parent(dev), dev, PCIB_IVAR_ ## B, v); \ 339 } 340 341 PCIB_ACCESSOR(hose, HOSE, u_int32_t) 342 343 device_t pci_find_bsf(u_int8_t, u_int8_t, u_int8_t); 344 device_t pci_find_device(u_int16_t, u_int16_t); 345 #endif 346 347 /* for compatibility to FreeBSD-2.2 version of PCI code */ 348 349 #ifdef PCI_COMPAT 350 351 typedef pcicfgregs *pcici_t; 352 typedef unsigned pcidi_t; 353 typedef void pci_inthand_t(void *arg); 354 355 #define pci_max_burst_len (3) 356 357 /* just copied from old PCI code for now ... */ 358 359 struct pci_device { 360 char* pd_name; 361 const char* (*pd_probe ) (pcici_t tag, pcidi_t type); 362 void (*pd_attach) (pcici_t tag, int unit); 363 u_long *pd_count; 364 int (*pd_shutdown) (int, int); 365 }; 366 367 #ifdef __i386__ 368 typedef u_short pci_port_t; 369 #else 370 typedef u_int pci_port_t; 371 #endif 372 373 u_long pci_conf_read (pcici_t tag, u_long reg); 374 void pci_conf_write (pcici_t tag, u_long reg, u_long data); 375 int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa); 376 int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa); 377 int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg, 378 intrmask_t *maskptr); 379 int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg, 380 intrmask_t *maskptr, u_int flags); 381 int pci_unmap_int (pcici_t tag); 382 383 pcici_t pci_get_parent_from_tag(pcici_t tag); 384 int pci_get_bus_from_tag(pcici_t tag); 385 386 struct module; 387 int compat_pci_handler (struct module *, int, void *); 388 #define COMPAT_PCI_DRIVER(name, pcidata) \ 389 static moduledata_t name##_mod = { \ 390 #name, \ 391 compat_pci_handler, \ 392 &pcidata \ 393 }; \ 394 DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY) 395 396 397 #endif /* PCI_COMPAT */ 398 #endif /* _PCIVAR_H_ */ 399