1 /* $FreeBSD: head/sys/dev/usb/controller/ehci.c 269569 2014-08-05 08:24:41Z n_hibma $ */ 2 /*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 5 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 6 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 32 * 33 * The EHCI 0.96 spec can be found at 34 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 35 * The EHCI 1.0 spec can be found at 36 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 37 * and the USB 2.0 spec at 38 * http://www.usb.org/developers/docs/usb_20.zip 39 * 40 */ 41 42 /* 43 * TODO: 44 * 1) command failures are not recovered correctly 45 */ 46 47 #include <sys/stdint.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/condvar.h> 57 #include <sys/sysctl.h> 58 #include <sys/unistd.h> 59 #include <sys/callout.h> 60 #include <sys/malloc.h> 61 #include <sys/caps.h> 62 63 #include <bus/u4b/usb.h> 64 #include <bus/u4b/usbdi.h> 65 66 #define USB_DEBUG_VAR ehcidebug 67 68 #include <bus/u4b/usb_core.h> 69 #include <bus/u4b/usb_debug.h> 70 #include <bus/u4b/usb_busdma.h> 71 #include <bus/u4b/usb_process.h> 72 #include <bus/u4b/usb_transfer.h> 73 #include <bus/u4b/usb_device.h> 74 #include <bus/u4b/usb_hub.h> 75 #include <bus/u4b/usb_util.h> 76 77 #include <bus/u4b/usb_controller.h> 78 #include <bus/u4b/usb_bus.h> 79 #include <bus/u4b/controller/ehci.h> 80 #include <bus/u4b/controller/ehcireg.h> 81 82 #define EHCI_BUS2SC(bus) \ 83 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 84 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 85 86 #ifdef USB_DEBUG 87 static int ehcidebug = 0; 88 static int ehcinohighspeed = 0; 89 static int ehciiaadbug = 0; 90 static int ehcilostintrbug = 0; 91 92 static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 93 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW, 94 &ehcidebug, 0, "Debug level"); 95 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW, 96 &ehcinohighspeed, 0, "Disable High Speed USB"); 97 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW, 98 &ehciiaadbug, 0, "Enable doorbell bug workaround"); 99 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW, 100 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround"); 101 102 TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug); 103 TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed); 104 TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug); 105 TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug); 106 107 static void ehci_dump_regs(ehci_softc_t *sc); 108 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 109 110 #endif 111 112 #define EHCI_INTR_ENDPT 1 113 114 static const struct usb_bus_methods ehci_bus_methods; 115 static const struct usb_pipe_methods ehci_device_bulk_methods; 116 static const struct usb_pipe_methods ehci_device_ctrl_methods; 117 static const struct usb_pipe_methods ehci_device_intr_methods; 118 static const struct usb_pipe_methods ehci_device_isoc_fs_methods; 119 static const struct usb_pipe_methods ehci_device_isoc_hs_methods; 120 121 static void ehci_do_poll(struct usb_bus *); 122 static void ehci_device_done(struct usb_xfer *, usb_error_t); 123 static uint8_t ehci_check_transfer(struct usb_xfer *); 124 static void ehci_timeout(void *); 125 static void ehci_poll_timeout(void *); 126 127 static void ehci_root_intr(ehci_softc_t *sc); 128 129 struct ehci_std_temp { 130 ehci_softc_t *sc; 131 struct usb_page_cache *pc; 132 ehci_qtd_t *td; 133 ehci_qtd_t *td_next; 134 uint32_t average; 135 uint32_t qtd_status; 136 uint32_t len; 137 uint16_t max_frame_size; 138 uint8_t shortpkt; 139 uint8_t auto_data_toggle; 140 uint8_t setup_alt_next; 141 uint8_t last_frame; 142 }; 143 144 void 145 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 146 { 147 ehci_softc_t *sc = EHCI_BUS2SC(bus); 148 uint32_t i; 149 150 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 151 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 152 153 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 154 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 155 156 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 157 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 158 159 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 160 cb(bus, sc->sc_hw.intr_start_pc + i, 161 sc->sc_hw.intr_start_pg + i, 162 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 163 } 164 165 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 166 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 167 sc->sc_hw.isoc_hs_start_pg + i, 168 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 169 } 170 171 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 172 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 173 sc->sc_hw.isoc_fs_start_pg + i, 174 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 175 } 176 } 177 178 usb_error_t 179 ehci_reset(ehci_softc_t *sc) 180 { 181 uint32_t hcr; 182 int i; 183 184 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 185 for (i = 0; i < 100; i++) { 186 usb_pause_mtx(NULL, hz / 128); 187 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 188 if (!hcr) { 189 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) { 190 /* 191 * Force USBMODE as requested. Controllers 192 * may have multiple operating modes. 193 */ 194 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE); 195 if (sc->sc_flags & EHCI_SCFLG_SETMODE) { 196 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST; 197 device_printf(sc->sc_bus.bdev, 198 "set host controller mode\n"); 199 } 200 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) { 201 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE; 202 device_printf(sc->sc_bus.bdev, 203 "set big-endian mode\n"); 204 } 205 EOWRITE4(sc, EHCI_USBMODE, usbmode); 206 } 207 return (0); 208 } 209 } 210 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 211 return (USB_ERR_IOERROR); 212 } 213 214 static usb_error_t 215 ehci_hcreset(ehci_softc_t *sc) 216 { 217 uint32_t hcr; 218 int i; 219 220 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 221 for (i = 0; i < 100; i++) { 222 usb_pause_mtx(NULL, hz / 128); 223 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 224 if (hcr) 225 break; 226 } 227 if (!hcr) 228 /* 229 * Fall through and try reset anyway even though 230 * Table 2-9 in the EHCI spec says this will result 231 * in undefined behavior. 232 */ 233 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 234 235 return (ehci_reset(sc)); 236 } 237 238 static int 239 ehci_init_sub(struct ehci_softc *sc) 240 { 241 struct usb_page_search buf_res; 242 uint32_t cparams; 243 uint32_t hcr; 244 uint8_t i; 245 246 cparams = EREAD4(sc, EHCI_HCCPARAMS); 247 248 DPRINTF("cparams=0x%x\n", cparams); 249 250 if (EHCI_HCC_64BIT(cparams)) { 251 DPRINTF("HCC uses 64-bit structures\n"); 252 253 /* MUST clear segment register if 64 bit capable */ 254 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 255 } 256 257 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 258 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 259 260 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 261 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 262 263 /* enable interrupts */ 264 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 265 266 /* turn on controller */ 267 EOWRITE4(sc, EHCI_USBCMD, 268 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 269 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 270 EHCI_CMD_ASE | 271 EHCI_CMD_PSE | 272 EHCI_CMD_RS); 273 274 /* Take over port ownership */ 275 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 276 277 for (i = 0; i < 100; i++) { 278 usb_pause_mtx(NULL, hz / 128); 279 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 280 if (!hcr) { 281 break; 282 } 283 } 284 if (hcr) { 285 device_printf(sc->sc_bus.bdev, "run timeout\n"); 286 return (USB_ERR_IOERROR); 287 } 288 return (USB_ERR_NORMAL_COMPLETION); 289 } 290 291 usb_error_t 292 ehci_init(ehci_softc_t *sc) 293 { 294 struct usb_page_search buf_res; 295 uint32_t version; 296 uint32_t sparams; 297 uint16_t i; 298 uint16_t x; 299 uint16_t y; 300 uint16_t bit; 301 usb_error_t err = 0; 302 303 DPRINTF("start\n"); 304 305 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_lock, 0); 306 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_lock, 0); 307 308 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 309 310 #ifdef USB_DEBUG 311 if (ehciiaadbug) 312 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 313 if (ehcilostintrbug) 314 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 315 if (ehcidebug > 2) { 316 ehci_dump_regs(sc); 317 } 318 #endif 319 320 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 321 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 322 version >> 8, version & 0xff); 323 324 sparams = EREAD4(sc, EHCI_HCSPARAMS); 325 DPRINTF("sparams=0x%x\n", sparams); 326 327 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 328 sc->sc_bus.usbrev = USB_REV_2_0; 329 330 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) { 331 /* Reset the controller */ 332 DPRINTF("%s: resetting\n", 333 device_get_nameunit(sc->sc_bus.bdev)); 334 335 err = ehci_hcreset(sc); 336 if (err) { 337 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 338 return (err); 339 } 340 } 341 342 /* 343 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 344 * bytes 2: 256*4 bytes 3: unknown 345 */ 346 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 347 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 348 return (USB_ERR_IOERROR); 349 } 350 /* set up the bus struct */ 351 sc->sc_bus.methods = &ehci_bus_methods; 352 353 sc->sc_eintrs = EHCI_NORMAL_INTRS; 354 355 if (1) { 356 struct ehci_qh_sub *qh; 357 358 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 359 360 qh = buf_res.buffer; 361 362 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 363 364 /* init terminate TD */ 365 qh->qtd_next = 366 htohc32(sc, EHCI_LINK_TERMINATE); 367 qh->qtd_altnext = 368 htohc32(sc, EHCI_LINK_TERMINATE); 369 qh->qtd_status = 370 htohc32(sc, EHCI_QTD_HALTED); 371 } 372 373 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 374 ehci_qh_t *qh; 375 376 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 377 378 qh = buf_res.buffer; 379 380 /* initialize page cache pointer */ 381 382 qh->page_cache = sc->sc_hw.intr_start_pc + i; 383 384 /* store a pointer to queue head */ 385 386 sc->sc_intr_p_last[i] = qh; 387 388 qh->qh_self = 389 htohc32(sc, buf_res.physaddr) | 390 htohc32(sc, EHCI_LINK_QH); 391 392 qh->qh_endp = 393 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 394 qh->qh_endphub = 395 htohc32(sc, EHCI_QH_SET_MULT(1)); 396 qh->qh_curqtd = 0; 397 398 qh->qh_qtd.qtd_next = 399 htohc32(sc, EHCI_LINK_TERMINATE); 400 qh->qh_qtd.qtd_altnext = 401 htohc32(sc, EHCI_LINK_TERMINATE); 402 qh->qh_qtd.qtd_status = 403 htohc32(sc, EHCI_QTD_HALTED); 404 } 405 406 /* 407 * the QHs are arranged to give poll intervals that are 408 * powers of 2 times 1ms 409 * 410 * e.g. 64-127, 32-63, 16-31, 8-15, 4-7, 2-3, 1-1, 0 411 * 1ms 2ms 4ms 8ms 16ms 32ms 64ms 128m 412 */ 413 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 414 while (bit) { 415 x = bit; 416 while (x & bit) { 417 ehci_qh_t *qh_x; 418 ehci_qh_t *qh_y; 419 420 y = (x ^ bit) | (bit / 2); 421 422 qh_x = sc->sc_intr_p_last[x]; 423 qh_y = sc->sc_intr_p_last[y]; 424 425 /* 426 * the next QH has half the poll interval 427 */ 428 qh_x->qh_link = qh_y->qh_self; 429 430 x++; 431 } 432 bit >>= 1; 433 } 434 435 if (1) { 436 ehci_qh_t *qh; 437 438 qh = sc->sc_intr_p_last[0]; 439 440 /* the last (1ms) QH terminates */ 441 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 442 } 443 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 444 ehci_sitd_t *sitd; 445 ehci_itd_t *itd; 446 447 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 448 449 sitd = buf_res.buffer; 450 451 /* initialize page cache pointer */ 452 453 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 454 455 /* store a pointer to the transfer descriptor */ 456 457 sc->sc_isoc_fs_p_last[i] = sitd; 458 459 /* initialize full speed isochronous */ 460 461 sitd->sitd_self = 462 htohc32(sc, buf_res.physaddr) | 463 htohc32(sc, EHCI_LINK_SITD); 464 465 sitd->sitd_back = 466 htohc32(sc, EHCI_LINK_TERMINATE); 467 468 /* 469 * Point to 1ms interrupt queue heads 1:1 470 */ 471 sitd->sitd_next = 472 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 473 474 475 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 476 477 itd = buf_res.buffer; 478 479 /* initialize page cache pointer */ 480 481 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 482 483 /* store a pointer to the transfer descriptor */ 484 485 sc->sc_isoc_hs_p_last[i] = itd; 486 487 /* initialize high speed isochronous */ 488 489 itd->itd_self = 490 htohc32(sc, buf_res.physaddr) | 491 htohc32(sc, EHCI_LINK_ITD); 492 493 /* 494 * 1:1 HS -> FS 495 */ 496 itd->itd_next = 497 sitd->sitd_self; 498 } 499 500 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 501 502 if (1) { 503 uint32_t *pframes; 504 505 pframes = buf_res.buffer; 506 507 /* 508 * execution order: 509 * pframes -> high speed isochronous -> 510 * full speed isochronous -> interrupt QH's 511 * 512 * Each pframe chains through 10 queue heads. 513 * HS FS IQ1ms IQ2ms IQ4ms ... IQ128ms -> term 514 */ 515 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 516 pframes[i] = sc->sc_isoc_hs_p_last 517 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 518 } 519 } 520 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 521 522 /* 523 * Asynchronous schedule requires a QH the points to itself initially. 524 * (it is not terminated with EHCI_LINK_TERMINATE). 525 */ 526 if (1) { 527 528 ehci_qh_t *qh; 529 530 qh = buf_res.buffer; 531 532 /* initialize page cache pointer */ 533 534 qh->page_cache = &sc->sc_hw.async_start_pc; 535 536 /* store a pointer to the queue head */ 537 538 sc->sc_async_p_last = qh; 539 540 /* init dummy QH that starts the async list */ 541 542 qh->qh_self = 543 htohc32(sc, buf_res.physaddr) | 544 htohc32(sc, EHCI_LINK_QH); 545 546 /* fill the QH */ 547 qh->qh_endp = 548 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 549 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 550 qh->qh_link = qh->qh_self; 551 qh->qh_curqtd = 0; 552 553 /* fill the overlay qTD */ 554 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 555 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 556 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 557 } 558 /* flush all cache into memory */ 559 560 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 561 562 #ifdef USB_DEBUG 563 if (ehcidebug) { 564 ehci_dump_sqh(sc, sc->sc_async_p_last); 565 } 566 #endif 567 568 /* finial setup */ 569 err = ehci_init_sub(sc); 570 571 if (!err) { 572 /* catch any lost interrupts */ 573 ehci_do_poll(&sc->sc_bus); 574 } 575 return (err); 576 } 577 578 /* 579 * shut down the controller when the system is going down 580 */ 581 void 582 ehci_detach(ehci_softc_t *sc) 583 { 584 USB_BUS_LOCK(&sc->sc_bus); 585 586 usb_callout_stop(&sc->sc_tmo_pcd); 587 usb_callout_stop(&sc->sc_tmo_poll); 588 589 EOWRITE4(sc, EHCI_USBINTR, 0); 590 USB_BUS_UNLOCK(&sc->sc_bus); 591 592 if (ehci_hcreset(sc)) { 593 DPRINTF("reset failed!\n"); 594 } 595 596 /* XXX let stray task complete */ 597 usb_pause_mtx(NULL, hz / 20); 598 599 usb_callout_drain(&sc->sc_tmo_pcd); 600 usb_callout_drain(&sc->sc_tmo_poll); 601 } 602 603 static void 604 ehci_suspend(ehci_softc_t *sc) 605 { 606 DPRINTF("stopping the HC\n"); 607 608 /* reset HC */ 609 ehci_hcreset(sc); 610 } 611 612 static void 613 ehci_resume(ehci_softc_t *sc) 614 { 615 /* reset HC */ 616 ehci_hcreset(sc); 617 618 /* setup HC */ 619 ehci_init_sub(sc); 620 621 /* catch any lost interrupts */ 622 ehci_do_poll(&sc->sc_bus); 623 } 624 625 #ifdef USB_DEBUG 626 static void 627 ehci_dump_regs(ehci_softc_t *sc) 628 { 629 uint32_t i; 630 631 i = EOREAD4(sc, EHCI_USBCMD); 632 kprintf("cmd=0x%08x\n", i); 633 634 if (i & EHCI_CMD_ITC_1) 635 kprintf(" EHCI_CMD_ITC_1\n"); 636 if (i & EHCI_CMD_ITC_2) 637 kprintf(" EHCI_CMD_ITC_2\n"); 638 if (i & EHCI_CMD_ITC_4) 639 kprintf(" EHCI_CMD_ITC_4\n"); 640 if (i & EHCI_CMD_ITC_8) 641 kprintf(" EHCI_CMD_ITC_8\n"); 642 if (i & EHCI_CMD_ITC_16) 643 kprintf(" EHCI_CMD_ITC_16\n"); 644 if (i & EHCI_CMD_ITC_32) 645 kprintf(" EHCI_CMD_ITC_32\n"); 646 if (i & EHCI_CMD_ITC_64) 647 kprintf(" EHCI_CMD_ITC_64\n"); 648 if (i & EHCI_CMD_ASPME) 649 kprintf(" EHCI_CMD_ASPME\n"); 650 if (i & EHCI_CMD_ASPMC) 651 kprintf(" EHCI_CMD_ASPMC\n"); 652 if (i & EHCI_CMD_LHCR) 653 kprintf(" EHCI_CMD_LHCR\n"); 654 if (i & EHCI_CMD_IAAD) 655 kprintf(" EHCI_CMD_IAAD\n"); 656 if (i & EHCI_CMD_ASE) 657 kprintf(" EHCI_CMD_ASE\n"); 658 if (i & EHCI_CMD_PSE) 659 kprintf(" EHCI_CMD_PSE\n"); 660 if (i & EHCI_CMD_FLS_M) 661 kprintf(" EHCI_CMD_FLS_M\n"); 662 if (i & EHCI_CMD_HCRESET) 663 kprintf(" EHCI_CMD_HCRESET\n"); 664 if (i & EHCI_CMD_RS) 665 kprintf(" EHCI_CMD_RS\n"); 666 667 i = EOREAD4(sc, EHCI_USBSTS); 668 669 kprintf("sts=0x%08x\n", i); 670 671 if (i & EHCI_STS_ASS) 672 kprintf(" EHCI_STS_ASS\n"); 673 if (i & EHCI_STS_PSS) 674 kprintf(" EHCI_STS_PSS\n"); 675 if (i & EHCI_STS_REC) 676 kprintf(" EHCI_STS_REC\n"); 677 if (i & EHCI_STS_HCH) 678 kprintf(" EHCI_STS_HCH\n"); 679 if (i & EHCI_STS_IAA) 680 kprintf(" EHCI_STS_IAA\n"); 681 if (i & EHCI_STS_HSE) 682 kprintf(" EHCI_STS_HSE\n"); 683 if (i & EHCI_STS_FLR) 684 kprintf(" EHCI_STS_FLR\n"); 685 if (i & EHCI_STS_PCD) 686 kprintf(" EHCI_STS_PCD\n"); 687 if (i & EHCI_STS_ERRINT) 688 kprintf(" EHCI_STS_ERRINT\n"); 689 if (i & EHCI_STS_INT) 690 kprintf(" EHCI_STS_INT\n"); 691 692 kprintf("ien=0x%08x\n", 693 EOREAD4(sc, EHCI_USBINTR)); 694 kprintf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 695 EOREAD4(sc, EHCI_FRINDEX), 696 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 697 EOREAD4(sc, EHCI_PERIODICLISTBASE), 698 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 699 for (i = 1; i <= sc->sc_noport; i++) { 700 kprintf("port %d status=0x%08x\n", i, 701 EOREAD4(sc, EHCI_PORTSC(i))); 702 } 703 } 704 705 static void 706 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 707 { 708 link = hc32toh(sc, link); 709 kprintf("0x%08x", link); 710 if (link & EHCI_LINK_TERMINATE) 711 kprintf("<T>"); 712 else { 713 kprintf("<"); 714 if (type) { 715 switch (EHCI_LINK_TYPE(link)) { 716 case EHCI_LINK_ITD: 717 kprintf("ITD"); 718 break; 719 case EHCI_LINK_QH: 720 kprintf("QH"); 721 break; 722 case EHCI_LINK_SITD: 723 kprintf("SITD"); 724 break; 725 case EHCI_LINK_FSTN: 726 kprintf("FSTN"); 727 break; 728 } 729 } 730 kprintf(">"); 731 } 732 } 733 734 static void 735 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 736 { 737 uint32_t s; 738 739 kprintf(" next="); 740 ehci_dump_link(sc, qtd->qtd_next, 0); 741 kprintf(" altnext="); 742 ehci_dump_link(sc, qtd->qtd_altnext, 0); 743 kprintf("\n"); 744 s = hc32toh(sc, qtd->qtd_status); 745 kprintf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 746 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 747 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 748 kprintf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 749 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 750 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 751 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 752 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 753 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 754 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 755 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 756 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 757 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 758 759 for (s = 0; s < 5; s++) { 760 kprintf(" buffer[%d]=0x%08x\n", s, 761 hc32toh(sc, qtd->qtd_buffer[s])); 762 } 763 for (s = 0; s < 5; s++) { 764 kprintf(" buffer_hi[%d]=0x%08x\n", s, 765 hc32toh(sc, qtd->qtd_buffer_hi[s])); 766 } 767 } 768 769 static uint8_t 770 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 771 { 772 uint8_t temp; 773 774 usb_pc_cpu_invalidate(sqtd->page_cache); 775 kprintf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 776 ehci_dump_qtd(sc, sqtd); 777 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 778 return (temp); 779 } 780 781 static void 782 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 783 { 784 uint16_t i; 785 uint8_t stop; 786 787 stop = 0; 788 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 789 stop = ehci_dump_sqtd(sc, sqtd); 790 } 791 if (sqtd) { 792 kprintf("dump aborted, too many TDs\n"); 793 } 794 } 795 796 static void 797 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 798 { 799 uint32_t endp; 800 uint32_t endphub; 801 802 usb_pc_cpu_invalidate(qh->page_cache); 803 kprintf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 804 kprintf(" link="); 805 ehci_dump_link(sc, qh->qh_link, 1); 806 kprintf("\n"); 807 endp = hc32toh(sc, qh->qh_endp); 808 kprintf(" endp=0x%08x\n", endp); 809 kprintf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 810 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 811 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 812 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 813 kprintf(" mpl=0x%x ctl=%d nrl=%d\n", 814 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 815 EHCI_QH_GET_NRL(endp)); 816 endphub = hc32toh(sc, qh->qh_endphub); 817 kprintf(" endphub=0x%08x\n", endphub); 818 kprintf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 819 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 820 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 821 EHCI_QH_GET_MULT(endphub)); 822 kprintf(" curqtd="); 823 ehci_dump_link(sc, qh->qh_curqtd, 0); 824 kprintf("\n"); 825 kprintf("Overlay qTD:\n"); 826 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 827 } 828 829 static void 830 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 831 { 832 usb_pc_cpu_invalidate(sitd->page_cache); 833 kprintf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 834 kprintf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 835 kprintf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 836 hc32toh(sc, sitd->sitd_portaddr), 837 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 838 ? "in" : "out", 839 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 840 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 841 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 842 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 843 kprintf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 844 kprintf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 845 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 846 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 847 kprintf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 848 hc32toh(sc, sitd->sitd_back), 849 hc32toh(sc, sitd->sitd_bp[0]), 850 hc32toh(sc, sitd->sitd_bp[1]), 851 hc32toh(sc, sitd->sitd_bp_hi[0]), 852 hc32toh(sc, sitd->sitd_bp_hi[1])); 853 } 854 855 static void 856 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 857 { 858 usb_pc_cpu_invalidate(itd->page_cache); 859 kprintf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 860 kprintf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 861 kprintf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 862 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 863 kprintf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 864 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 865 kprintf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 866 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 867 kprintf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 868 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 869 kprintf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 870 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 871 kprintf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 872 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 873 kprintf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 874 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 875 kprintf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 876 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 877 kprintf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 878 kprintf(" addr=0x%02x; endpt=0x%01x\n", 879 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 880 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 881 kprintf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 882 kprintf(" dir=%s; mpl=0x%02x\n", 883 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 884 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 885 kprintf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 886 hc32toh(sc, itd->itd_bp[2]), 887 hc32toh(sc, itd->itd_bp[3]), 888 hc32toh(sc, itd->itd_bp[4]), 889 hc32toh(sc, itd->itd_bp[5]), 890 hc32toh(sc, itd->itd_bp[6])); 891 kprintf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 892 " 0x%08x,0x%08x,0x%08x\n", 893 hc32toh(sc, itd->itd_bp_hi[0]), 894 hc32toh(sc, itd->itd_bp_hi[1]), 895 hc32toh(sc, itd->itd_bp_hi[2]), 896 hc32toh(sc, itd->itd_bp_hi[3]), 897 hc32toh(sc, itd->itd_bp_hi[4]), 898 hc32toh(sc, itd->itd_bp_hi[5]), 899 hc32toh(sc, itd->itd_bp_hi[6])); 900 } 901 902 static void 903 ehci_dump_isoc(ehci_softc_t *sc) 904 { 905 ehci_itd_t *itd; 906 ehci_sitd_t *sitd; 907 uint16_t max = 1000; 908 uint16_t pos; 909 910 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 911 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 912 913 kprintf("%s: isochronous dump from frame 0x%03x:\n", 914 __func__, pos); 915 916 itd = sc->sc_isoc_hs_p_last[pos]; 917 sitd = sc->sc_isoc_fs_p_last[pos]; 918 919 while (itd && max && max--) { 920 ehci_dump_itd(sc, itd); 921 itd = itd->prev; 922 } 923 924 while (sitd && max && max--) { 925 ehci_dump_sitd(sc, sitd); 926 sitd = sitd->prev; 927 } 928 } 929 930 #endif 931 932 static void 933 ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 934 { 935 /* check for early completion */ 936 if (ehci_check_transfer(xfer)) { 937 return; 938 } 939 /* put transfer on interrupt queue */ 940 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 941 942 /* start timeout, if any */ 943 if (xfer->timeout != 0) { 944 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 945 } 946 } 947 948 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 949 static ehci_sitd_t * 950 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 951 { 952 DPRINTFN(11, "%p to %p\n", std, last); 953 954 /* (sc->sc_bus.mtx) must be locked */ 955 956 std->next = last->next; 957 std->sitd_next = last->sitd_next; 958 959 std->prev = last; 960 961 usb_pc_cpu_flush(std->page_cache); 962 963 /* 964 * the last->next->prev is never followed: std->next->prev = std; 965 */ 966 last->next = std; 967 last->sitd_next = std->sitd_self; 968 969 usb_pc_cpu_flush(last->page_cache); 970 971 return (std); 972 } 973 974 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 975 static ehci_itd_t * 976 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 977 { 978 DPRINTFN(11, "%p to %p\n", std, last); 979 980 /* (sc->sc_bus.mtx) must be locked */ 981 982 std->next = last->next; 983 std->itd_next = last->itd_next; 984 985 std->prev = last; 986 987 usb_pc_cpu_flush(std->page_cache); 988 989 /* 990 * the last->next->prev is never followed: std->next->prev = std; 991 */ 992 last->next = std; 993 last->itd_next = std->itd_self; 994 995 usb_pc_cpu_flush(last->page_cache); 996 997 return (std); 998 } 999 1000 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 1001 static ehci_qh_t * 1002 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1003 { 1004 DPRINTFN(11, "%p to %p\n", sqh, last); 1005 1006 if (sqh->prev != NULL) { 1007 /* should not happen */ 1008 DPRINTFN(0, "QH already linked!\n"); 1009 return (last); 1010 } 1011 /* (sc->sc_bus.mtx) must be locked */ 1012 1013 sqh->next = last->next; 1014 sqh->qh_link = last->qh_link; 1015 1016 sqh->prev = last; 1017 1018 usb_pc_cpu_flush(sqh->page_cache); 1019 1020 /* 1021 * the last->next->prev is never followed: sqh->next->prev = sqh; 1022 */ 1023 1024 last->next = sqh; 1025 last->qh_link = sqh->qh_self; 1026 1027 usb_pc_cpu_flush(last->page_cache); 1028 1029 return (sqh); 1030 } 1031 1032 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1033 static ehci_sitd_t * 1034 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1035 { 1036 DPRINTFN(11, "%p from %p\n", std, last); 1037 1038 /* (sc->sc_bus.mtx) must be locked */ 1039 1040 std->prev->next = std->next; 1041 std->prev->sitd_next = std->sitd_next; 1042 1043 usb_pc_cpu_flush(std->prev->page_cache); 1044 1045 if (std->next) { 1046 std->next->prev = std->prev; 1047 usb_pc_cpu_flush(std->next->page_cache); 1048 } 1049 return ((last == std) ? std->prev : last); 1050 } 1051 1052 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1053 static ehci_itd_t * 1054 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1055 { 1056 DPRINTFN(11, "%p from %p\n", std, last); 1057 1058 /* (sc->sc_bus.mtx) must be locked */ 1059 1060 std->prev->next = std->next; 1061 std->prev->itd_next = std->itd_next; 1062 1063 usb_pc_cpu_flush(std->prev->page_cache); 1064 1065 if (std->next) { 1066 std->next->prev = std->prev; 1067 usb_pc_cpu_flush(std->next->page_cache); 1068 } 1069 return ((last == std) ? std->prev : last); 1070 } 1071 1072 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1073 static ehci_qh_t * 1074 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1075 { 1076 DPRINTFN(11, "%p from %p\n", sqh, last); 1077 1078 /* (sc->sc_bus.mtx) must be locked */ 1079 1080 /* only remove if not removed from a queue */ 1081 if (sqh->prev) { 1082 1083 sqh->prev->next = sqh->next; 1084 sqh->prev->qh_link = sqh->qh_link; 1085 1086 usb_pc_cpu_flush(sqh->prev->page_cache); 1087 1088 if (sqh->next) { 1089 sqh->next->prev = sqh->prev; 1090 usb_pc_cpu_flush(sqh->next->page_cache); 1091 } 1092 last = ((last == sqh) ? sqh->prev : last); 1093 1094 sqh->prev = 0; 1095 1096 usb_pc_cpu_flush(sqh->page_cache); 1097 } 1098 return (last); 1099 } 1100 1101 static void 1102 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1103 { 1104 uint16_t rem; 1105 uint8_t dt; 1106 1107 /* count number of full packets */ 1108 dt = (actlen / xfer->max_packet_size) & 1; 1109 1110 /* compute remainder */ 1111 rem = actlen % xfer->max_packet_size; 1112 1113 if (rem > 0) 1114 dt ^= 1; /* short packet at the end */ 1115 else if (actlen != xlen) 1116 dt ^= 1; /* zero length packet at the end */ 1117 else if (xlen == 0) 1118 dt ^= 1; /* zero length transfer */ 1119 1120 xfer->endpoint->toggle_next ^= dt; 1121 } 1122 1123 static usb_error_t 1124 ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1125 { 1126 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1127 ehci_qtd_t *td; 1128 ehci_qtd_t *td_alt_next; 1129 uint32_t status; 1130 uint16_t len; 1131 1132 td = xfer->td_transfer_cache; 1133 td_alt_next = td->alt_next; 1134 1135 if (xfer->aframes != xfer->nframes) { 1136 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1137 } 1138 while (1) { 1139 1140 usb_pc_cpu_invalidate(td->page_cache); 1141 status = hc32toh(sc, td->qtd_status); 1142 1143 len = EHCI_QTD_GET_BYTES(status); 1144 1145 /* 1146 * Verify the status length and 1147 * add the length to "frlengths[]": 1148 */ 1149 if (len > td->len) { 1150 /* should not happen */ 1151 DPRINTF("Invalid status length, " 1152 "0x%04x/0x%04x bytes\n", len, td->len); 1153 status |= EHCI_QTD_HALTED; 1154 } else if (xfer->aframes != xfer->nframes) { 1155 xfer->frlengths[xfer->aframes] += td->len - len; 1156 /* manually update data toggle */ 1157 ehci_data_toggle_update(xfer, td->len - len, td->len); 1158 } 1159 1160 /* Check for last transfer */ 1161 if (((void *)td) == xfer->td_transfer_last) { 1162 td = NULL; 1163 break; 1164 } 1165 /* Check for transfer error */ 1166 if (status & EHCI_QTD_HALTED) { 1167 /* the transfer is finished */ 1168 td = NULL; 1169 break; 1170 } 1171 /* Check for short transfer */ 1172 if (len > 0) { 1173 if (xfer->flags_int.short_frames_ok) { 1174 /* follow alt next */ 1175 td = td->alt_next; 1176 } else { 1177 /* the transfer is finished */ 1178 td = NULL; 1179 } 1180 break; 1181 } 1182 td = td->obj_next; 1183 1184 if (td->alt_next != td_alt_next) { 1185 /* this USB frame is complete */ 1186 break; 1187 } 1188 } 1189 1190 /* update transfer cache */ 1191 1192 xfer->td_transfer_cache = td; 1193 1194 #ifdef USB_DEBUG 1195 if (status & EHCI_QTD_STATERRS) { 1196 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1197 "status=%s%s%s%s%s%s%s%s\n", 1198 xfer->address, xfer->endpointno, xfer->aframes, 1199 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1200 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1201 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1202 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1203 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1204 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1205 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1206 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1207 } 1208 #endif 1209 if (status & EHCI_QTD_HALTED) { 1210 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1211 (xfer->xroot->udev->address != 0)) { 1212 /* try to separate I/O errors from STALL */ 1213 if (EHCI_QTD_GET_CERR(status) == 0) 1214 return (USB_ERR_IOERROR); 1215 } 1216 return (USB_ERR_STALLED); 1217 } 1218 return (USB_ERR_NORMAL_COMPLETION); 1219 } 1220 1221 static void 1222 ehci_non_isoc_done(struct usb_xfer *xfer) 1223 { 1224 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1225 ehci_qh_t *qh; 1226 uint32_t status; 1227 usb_error_t err = 0; 1228 1229 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1230 xfer, xfer->endpoint); 1231 1232 #ifdef USB_DEBUG 1233 if (ehcidebug > 10) { 1234 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1235 1236 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1237 } 1238 #endif 1239 1240 /* extract data toggle directly from the QH's overlay area */ 1241 1242 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1243 1244 usb_pc_cpu_invalidate(qh->page_cache); 1245 1246 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1247 1248 /* reset scanner */ 1249 1250 xfer->td_transfer_cache = xfer->td_transfer_first; 1251 1252 if (xfer->flags_int.control_xfr) { 1253 1254 if (xfer->flags_int.control_hdr) { 1255 1256 err = ehci_non_isoc_done_sub(xfer); 1257 } 1258 xfer->aframes = 1; 1259 1260 if (xfer->td_transfer_cache == NULL) { 1261 goto done; 1262 } 1263 } 1264 while (xfer->aframes != xfer->nframes) { 1265 1266 err = ehci_non_isoc_done_sub(xfer); 1267 xfer->aframes++; 1268 1269 if (xfer->td_transfer_cache == NULL) { 1270 goto done; 1271 } 1272 } 1273 1274 if (xfer->flags_int.control_xfr && 1275 !xfer->flags_int.control_act) { 1276 1277 err = ehci_non_isoc_done_sub(xfer); 1278 } 1279 done: 1280 ehci_device_done(xfer, err); 1281 } 1282 1283 /*------------------------------------------------------------------------* 1284 * ehci_check_transfer 1285 * 1286 * Return values: 1287 * 0: USB transfer is not finished 1288 * Else: USB transfer is finished 1289 *------------------------------------------------------------------------*/ 1290 static uint8_t 1291 ehci_check_transfer(struct usb_xfer *xfer) 1292 { 1293 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1294 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1295 1296 uint32_t status; 1297 1298 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1299 1300 if (methods == &ehci_device_isoc_fs_methods) { 1301 ehci_sitd_t *td; 1302 1303 /* isochronous full speed transfer */ 1304 1305 td = xfer->td_transfer_last; 1306 usb_pc_cpu_invalidate(td->page_cache); 1307 status = hc32toh(sc, td->sitd_status); 1308 1309 /* also check if first is complete */ 1310 1311 td = xfer->td_transfer_first; 1312 usb_pc_cpu_invalidate(td->page_cache); 1313 status |= hc32toh(sc, td->sitd_status); 1314 1315 if (!(status & EHCI_SITD_ACTIVE)) { 1316 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1317 goto transferred; 1318 } 1319 } else if (methods == &ehci_device_isoc_hs_methods) { 1320 ehci_itd_t *td; 1321 1322 /* isochronous high speed transfer */ 1323 1324 /* check last transfer */ 1325 td = xfer->td_transfer_last; 1326 usb_pc_cpu_invalidate(td->page_cache); 1327 status = td->itd_status[0]; 1328 status |= td->itd_status[1]; 1329 status |= td->itd_status[2]; 1330 status |= td->itd_status[3]; 1331 status |= td->itd_status[4]; 1332 status |= td->itd_status[5]; 1333 status |= td->itd_status[6]; 1334 status |= td->itd_status[7]; 1335 1336 /* also check first transfer */ 1337 td = xfer->td_transfer_first; 1338 usb_pc_cpu_invalidate(td->page_cache); 1339 status |= td->itd_status[0]; 1340 status |= td->itd_status[1]; 1341 status |= td->itd_status[2]; 1342 status |= td->itd_status[3]; 1343 status |= td->itd_status[4]; 1344 status |= td->itd_status[5]; 1345 status |= td->itd_status[6]; 1346 status |= td->itd_status[7]; 1347 1348 /* if no transactions are active we continue */ 1349 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1350 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1351 goto transferred; 1352 } 1353 } else { 1354 ehci_qtd_t *td; 1355 ehci_qh_t *qh; 1356 1357 /* non-isochronous transfer */ 1358 1359 /* 1360 * check whether there is an error somewhere in the middle, 1361 * or whether there was a short packet (SPD and not ACTIVE) 1362 */ 1363 td = xfer->td_transfer_cache; 1364 1365 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1366 1367 usb_pc_cpu_invalidate(qh->page_cache); 1368 1369 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1370 if (status & EHCI_QTD_ACTIVE) { 1371 /* transfer is pending */ 1372 goto done; 1373 } 1374 1375 while (1) { 1376 usb_pc_cpu_invalidate(td->page_cache); 1377 status = hc32toh(sc, td->qtd_status); 1378 1379 /* 1380 * Check if there is an active TD which 1381 * indicates that the transfer isn't done. 1382 */ 1383 if (status & EHCI_QTD_ACTIVE) { 1384 /* update cache */ 1385 xfer->td_transfer_cache = td; 1386 goto done; 1387 } 1388 /* 1389 * last transfer descriptor makes the transfer done 1390 */ 1391 if (((void *)td) == xfer->td_transfer_last) { 1392 break; 1393 } 1394 /* 1395 * any kind of error makes the transfer done 1396 */ 1397 if (status & EHCI_QTD_HALTED) { 1398 break; 1399 } 1400 /* 1401 * if there is no alternate next transfer, a short 1402 * packet also makes the transfer done 1403 */ 1404 if (EHCI_QTD_GET_BYTES(status)) { 1405 if (xfer->flags_int.short_frames_ok) { 1406 /* follow alt next */ 1407 if (td->alt_next) { 1408 td = td->alt_next; 1409 continue; 1410 } 1411 } 1412 /* transfer is done */ 1413 break; 1414 } 1415 td = td->obj_next; 1416 } 1417 ehci_non_isoc_done(xfer); 1418 goto transferred; 1419 } 1420 1421 done: 1422 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1423 return (0); 1424 1425 transferred: 1426 return (1); 1427 } 1428 1429 static void 1430 ehci_pcd_enable(ehci_softc_t *sc) 1431 { 1432 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 1433 1434 sc->sc_eintrs |= EHCI_STS_PCD; 1435 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1436 1437 /* acknowledge any PCD interrupt */ 1438 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1439 1440 ehci_root_intr(sc); 1441 } 1442 1443 static void 1444 ehci_interrupt_poll(ehci_softc_t *sc) 1445 { 1446 struct usb_xfer *xfer; 1447 1448 repeat: 1449 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1450 /* 1451 * check if transfer is transferred 1452 */ 1453 if (ehci_check_transfer(xfer)) { 1454 /* queue has been modified */ 1455 goto repeat; 1456 } 1457 } 1458 } 1459 1460 /* 1461 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1462 * writing back the qTD status, or miss signalling occasionally under 1463 * heavy load. If the host machine is too fast, we can miss 1464 * transaction completion - when we scan the active list the 1465 * transaction still seems to be active. This generally exhibits 1466 * itself as a umass stall that never recovers. 1467 * 1468 * We work around this behaviour by setting up this callback after any 1469 * softintr that completes with transactions still pending, giving us 1470 * another chance to check for completion after the writeback has 1471 * taken place. 1472 */ 1473 static void 1474 ehci_poll_timeout(void *arg) 1475 { 1476 ehci_softc_t *sc = arg; 1477 1478 DPRINTFN(3, "\n"); 1479 ehci_interrupt_poll(sc); 1480 } 1481 1482 /*------------------------------------------------------------------------* 1483 * ehci_interrupt - EHCI interrupt handler 1484 * 1485 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1486 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1487 * is present ! 1488 *------------------------------------------------------------------------*/ 1489 void 1490 ehci_interrupt(ehci_softc_t *sc) 1491 { 1492 uint32_t status; 1493 1494 USB_BUS_LOCK(&sc->sc_bus); 1495 1496 DPRINTFN(16, "real interrupt\n"); 1497 1498 #ifdef USB_DEBUG 1499 if (ehcidebug > 15) { 1500 ehci_dump_regs(sc); 1501 } 1502 #endif 1503 1504 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1505 if (status == 0) { 1506 /* the interrupt was not for us */ 1507 goto done; 1508 } 1509 if (!(status & sc->sc_eintrs)) { 1510 goto done; 1511 } 1512 1513 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1514 1515 status &= sc->sc_eintrs; 1516 1517 if (status & EHCI_STS_HSE) { 1518 kprintf("%s: unrecoverable error, " 1519 "controller halted\n", __FUNCTION__); 1520 #ifdef USB_DEBUG 1521 ehci_dump_regs(sc); 1522 ehci_dump_isoc(sc); 1523 #endif 1524 } 1525 if (status & EHCI_STS_PCD) { 1526 /* 1527 * Disable PCD interrupt for now, because it will be 1528 * on until the port has been reset. 1529 */ 1530 sc->sc_eintrs &= ~EHCI_STS_PCD; 1531 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1532 1533 ehci_root_intr(sc); 1534 1535 /* do not allow RHSC interrupts > 1 per second */ 1536 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1537 (void *)&ehci_pcd_enable, sc); 1538 } 1539 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1540 1541 if (status != 0) { 1542 /* block unprocessed interrupts */ 1543 sc->sc_eintrs &= ~status; 1544 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1545 kprintf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1546 } 1547 /* poll all the USB transfers */ 1548 ehci_interrupt_poll(sc); 1549 1550 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1551 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1552 (void *)&ehci_poll_timeout, sc); 1553 } 1554 1555 done: 1556 USB_BUS_UNLOCK(&sc->sc_bus); 1557 } 1558 1559 /* 1560 * called when a request does not complete 1561 */ 1562 static void 1563 ehci_timeout(void *arg) 1564 { 1565 struct usb_xfer *xfer = arg; 1566 1567 DPRINTF("xfer=%p\n", xfer); 1568 1569 USB_BUS_LOCK_ASSERT(xfer->xroot->bus); 1570 1571 /* transfer is transferred */ 1572 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1573 } 1574 1575 static void 1576 ehci_do_poll(struct usb_bus *bus) 1577 { 1578 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1579 1580 USB_BUS_LOCK(&sc->sc_bus); 1581 ehci_interrupt_poll(sc); 1582 USB_BUS_UNLOCK(&sc->sc_bus); 1583 } 1584 1585 static void 1586 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1587 { 1588 struct usb_page_search buf_res; 1589 ehci_qtd_t *td; 1590 ehci_qtd_t *td_next; 1591 ehci_qtd_t *td_alt_next; 1592 uint32_t buf_offset; 1593 uint32_t average; 1594 uint32_t len_old; 1595 uint32_t terminate; 1596 uint32_t qtd_altnext; 1597 uint8_t shortpkt_old; 1598 uint8_t precompute; 1599 1600 terminate = temp->sc->sc_terminate_self; 1601 qtd_altnext = temp->sc->sc_terminate_self; 1602 td_alt_next = NULL; 1603 buf_offset = 0; 1604 shortpkt_old = temp->shortpkt; 1605 len_old = temp->len; 1606 precompute = 1; 1607 1608 restart: 1609 1610 td = temp->td; /* starts out NULL */ 1611 td_next = temp->td_next; /* starts with first td */ 1612 1613 while (1) { 1614 1615 if (temp->len == 0) { 1616 1617 if (temp->shortpkt) { 1618 break; 1619 } 1620 /* send a Zero Length Packet, ZLP, last */ 1621 1622 temp->shortpkt = 1; 1623 average = 0; 1624 1625 } else { 1626 1627 average = temp->average; 1628 1629 if (temp->len < average) { 1630 if (temp->len % temp->max_frame_size) { 1631 temp->shortpkt = 1; 1632 } 1633 average = temp->len; 1634 } 1635 } 1636 1637 if (td_next == NULL) { 1638 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1639 } 1640 /* get next TD */ 1641 1642 td = td_next; 1643 td_next = td->obj_next; 1644 1645 /* check if we are pre-computing */ 1646 1647 if (precompute) { 1648 1649 /* update remaining length */ 1650 1651 temp->len -= average; 1652 1653 continue; 1654 } 1655 /* fill out current TD */ 1656 1657 td->qtd_status = 1658 temp->qtd_status | 1659 htohc32(temp->sc, EHCI_QTD_IOC | 1660 EHCI_QTD_SET_BYTES(average)); 1661 1662 if (average == 0) { 1663 1664 if (temp->auto_data_toggle == 0) { 1665 1666 /* update data toggle, ZLP case */ 1667 1668 temp->qtd_status ^= 1669 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1670 } 1671 td->len = 0; 1672 1673 /* properly reset reserved fields */ 1674 td->qtd_buffer[0] = 0; 1675 td->qtd_buffer[1] = 0; 1676 td->qtd_buffer[2] = 0; 1677 td->qtd_buffer[3] = 0; 1678 td->qtd_buffer[4] = 0; 1679 td->qtd_buffer_hi[0] = 0; 1680 td->qtd_buffer_hi[1] = 0; 1681 td->qtd_buffer_hi[2] = 0; 1682 td->qtd_buffer_hi[3] = 0; 1683 td->qtd_buffer_hi[4] = 0; 1684 } else { 1685 1686 uint8_t x; 1687 1688 if (temp->auto_data_toggle == 0) { 1689 1690 /* update data toggle */ 1691 1692 if (((average + temp->max_frame_size - 1) / 1693 temp->max_frame_size) & 1) { 1694 temp->qtd_status ^= 1695 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1696 } 1697 } 1698 td->len = average; 1699 1700 /* update remaining length */ 1701 1702 temp->len -= average; 1703 1704 /* fill out buffer pointers */ 1705 1706 usbd_get_page(temp->pc, buf_offset, &buf_res); 1707 td->qtd_buffer[0] = 1708 htohc32(temp->sc, buf_res.physaddr); 1709 td->qtd_buffer_hi[0] = 0; 1710 1711 x = 1; 1712 1713 while (average > EHCI_PAGE_SIZE) { 1714 average -= EHCI_PAGE_SIZE; 1715 buf_offset += EHCI_PAGE_SIZE; 1716 usbd_get_page(temp->pc, buf_offset, &buf_res); 1717 td->qtd_buffer[x] = 1718 htohc32(temp->sc, 1719 buf_res.physaddr & (~0xFFF)); 1720 td->qtd_buffer_hi[x] = 0; 1721 x++; 1722 } 1723 1724 /* 1725 * NOTE: The "average" variable is never zero after 1726 * exiting the loop above ! 1727 * 1728 * NOTE: We have to subtract one from the offset to 1729 * ensure that we are computing the physical address 1730 * of a valid page ! 1731 */ 1732 buf_offset += average; 1733 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1734 td->qtd_buffer[x] = 1735 htohc32(temp->sc, 1736 buf_res.physaddr & (~0xFFF)); 1737 td->qtd_buffer_hi[x] = 0; 1738 1739 /* properly reset reserved fields */ 1740 while (++x < EHCI_QTD_NBUFFERS) { 1741 td->qtd_buffer[x] = 0; 1742 td->qtd_buffer_hi[x] = 0; 1743 } 1744 } 1745 1746 if (td_next) { 1747 /* link the current TD with the next one */ 1748 td->qtd_next = td_next->qtd_self; 1749 } 1750 td->qtd_altnext = qtd_altnext; 1751 td->alt_next = td_alt_next; 1752 1753 usb_pc_cpu_flush(td->page_cache); 1754 } 1755 1756 if (precompute) { 1757 precompute = 0; 1758 1759 /* setup alt next pointer, if any */ 1760 if (temp->last_frame) { 1761 td_alt_next = NULL; 1762 qtd_altnext = terminate; 1763 } else { 1764 /* we use this field internally */ 1765 td_alt_next = td_next; 1766 if (temp->setup_alt_next) { 1767 qtd_altnext = td_next->qtd_self; 1768 } else { 1769 qtd_altnext = terminate; 1770 } 1771 } 1772 1773 /* restore */ 1774 temp->shortpkt = shortpkt_old; 1775 temp->len = len_old; 1776 goto restart; 1777 } 1778 temp->td = td; 1779 temp->td_next = td_next; 1780 } 1781 1782 static void 1783 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1784 { 1785 struct ehci_std_temp temp; 1786 const struct usb_pipe_methods *methods; 1787 ehci_qh_t *qh; 1788 ehci_qtd_t *td; 1789 uint32_t qh_endp; 1790 uint32_t qh_endphub; 1791 uint32_t x; 1792 1793 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1794 xfer->address, UE_GET_ADDR(xfer->endpointno), 1795 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1796 1797 temp.average = xfer->max_hc_frame_size; 1798 temp.max_frame_size = xfer->max_frame_size; 1799 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1800 1801 /* toggle the DMA set we are using */ 1802 xfer->flags_int.curr_dma_set ^= 1; 1803 1804 /* get next DMA set */ 1805 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1806 1807 xfer->td_transfer_first = td; 1808 xfer->td_transfer_cache = td; 1809 1810 temp.td = NULL; 1811 temp.td_next = td; 1812 temp.qtd_status = 0; 1813 temp.last_frame = 0; 1814 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1815 1816 if (xfer->flags_int.control_xfr) { 1817 if (xfer->endpoint->toggle_next) { 1818 /* DATA1 is next */ 1819 temp.qtd_status |= 1820 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1821 } 1822 temp.auto_data_toggle = 0; 1823 } else { 1824 temp.auto_data_toggle = 1; 1825 } 1826 1827 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1828 (xfer->xroot->udev->address != 0)) { 1829 /* max 3 retries */ 1830 temp.qtd_status |= 1831 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1832 } 1833 /* check if we should prepend a setup message */ 1834 1835 if (xfer->flags_int.control_xfr) { 1836 if (xfer->flags_int.control_hdr) { 1837 1838 xfer->endpoint->toggle_next = 0; 1839 1840 temp.qtd_status &= 1841 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1842 temp.qtd_status |= htohc32(temp.sc, 1843 EHCI_QTD_ACTIVE | 1844 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1845 EHCI_QTD_SET_TOGGLE(0)); 1846 1847 temp.len = xfer->frlengths[0]; 1848 temp.pc = xfer->frbuffers + 0; 1849 temp.shortpkt = temp.len ? 1 : 0; 1850 /* check for last frame */ 1851 if (xfer->nframes == 1) { 1852 /* no STATUS stage yet, SETUP is last */ 1853 if (xfer->flags_int.control_act) { 1854 temp.last_frame = 1; 1855 temp.setup_alt_next = 0; 1856 } 1857 } 1858 ehci_setup_standard_chain_sub(&temp); 1859 } 1860 x = 1; 1861 } else { 1862 x = 0; 1863 } 1864 1865 while (x != xfer->nframes) { 1866 1867 /* DATA0 / DATA1 message */ 1868 1869 temp.len = xfer->frlengths[x]; 1870 temp.pc = xfer->frbuffers + x; 1871 1872 x++; 1873 1874 if (x == xfer->nframes) { 1875 if (xfer->flags_int.control_xfr) { 1876 /* no STATUS stage yet, DATA is last */ 1877 if (xfer->flags_int.control_act) { 1878 temp.last_frame = 1; 1879 temp.setup_alt_next = 0; 1880 } 1881 } else { 1882 temp.last_frame = 1; 1883 temp.setup_alt_next = 0; 1884 } 1885 } 1886 /* keep previous data toggle and error count */ 1887 1888 temp.qtd_status &= 1889 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1890 EHCI_QTD_SET_TOGGLE(1)); 1891 1892 if (temp.len == 0) { 1893 1894 /* make sure that we send an USB packet */ 1895 1896 temp.shortpkt = 0; 1897 1898 } else { 1899 1900 /* regular data transfer */ 1901 1902 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1903 } 1904 1905 /* set endpoint direction */ 1906 1907 temp.qtd_status |= 1908 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1909 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1910 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1911 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1912 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1913 1914 ehci_setup_standard_chain_sub(&temp); 1915 } 1916 1917 /* check if we should append a status stage */ 1918 1919 if (xfer->flags_int.control_xfr && 1920 !xfer->flags_int.control_act) { 1921 1922 /* 1923 * Send a DATA1 message and invert the current endpoint 1924 * direction. 1925 */ 1926 1927 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1928 EHCI_QTD_SET_TOGGLE(1)); 1929 temp.qtd_status |= 1930 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1931 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1932 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1933 EHCI_QTD_SET_TOGGLE(1)) : 1934 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1935 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1936 EHCI_QTD_SET_TOGGLE(1)); 1937 1938 temp.len = 0; 1939 temp.pc = NULL; 1940 temp.shortpkt = 0; 1941 temp.last_frame = 1; 1942 temp.setup_alt_next = 0; 1943 1944 ehci_setup_standard_chain_sub(&temp); 1945 } 1946 td = temp.td; 1947 1948 /* the last TD terminates the transfer: */ 1949 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1950 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1951 1952 usb_pc_cpu_flush(td->page_cache); 1953 1954 /* must have at least one frame! */ 1955 1956 xfer->td_transfer_last = td; 1957 1958 #ifdef USB_DEBUG 1959 if (ehcidebug > 8) { 1960 DPRINTF("nexttog=%d; data before transfer:\n", 1961 xfer->endpoint->toggle_next); 1962 ehci_dump_sqtds(temp.sc, 1963 xfer->td_transfer_first); 1964 } 1965 #endif 1966 1967 methods = xfer->endpoint->methods; 1968 1969 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1970 1971 /* the "qh_link" field is filled when the QH is added */ 1972 1973 qh_endp = 1974 (EHCI_QH_SET_ADDR(xfer->address) | 1975 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 1976 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1977 1978 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1979 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 1980 if (methods != &ehci_device_intr_methods) 1981 qh_endp |= EHCI_QH_SET_NRL(8); 1982 } else { 1983 1984 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1985 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 1986 } else { 1987 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 1988 } 1989 1990 if (methods == &ehci_device_ctrl_methods) { 1991 qh_endp |= EHCI_QH_CTL; 1992 } 1993 if (methods != &ehci_device_intr_methods) { 1994 /* Only try one time per microframe! */ 1995 qh_endp |= EHCI_QH_SET_NRL(1); 1996 } 1997 } 1998 1999 if (temp.auto_data_toggle == 0) { 2000 /* software computes the data toggle */ 2001 qh_endp |= EHCI_QH_DTC; 2002 } 2003 2004 qh->qh_endp = htohc32(temp.sc, qh_endp); 2005 2006 qh_endphub = 2007 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 2008 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 2009 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 2010 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2011 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 2012 2013 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 2014 qh->qh_curqtd = 0; 2015 2016 /* fill the overlay qTD */ 2017 2018 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 2019 /* DATA1 is next */ 2020 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 2021 } else { 2022 qh->qh_qtd.qtd_status = 0; 2023 } 2024 2025 td = xfer->td_transfer_first; 2026 2027 qh->qh_qtd.qtd_next = td->qtd_self; 2028 qh->qh_qtd.qtd_altnext = 2029 htohc32(temp.sc, EHCI_LINK_TERMINATE); 2030 2031 /* properly reset reserved fields */ 2032 qh->qh_qtd.qtd_buffer[0] = 0; 2033 qh->qh_qtd.qtd_buffer[1] = 0; 2034 qh->qh_qtd.qtd_buffer[2] = 0; 2035 qh->qh_qtd.qtd_buffer[3] = 0; 2036 qh->qh_qtd.qtd_buffer[4] = 0; 2037 qh->qh_qtd.qtd_buffer_hi[0] = 0; 2038 qh->qh_qtd.qtd_buffer_hi[1] = 0; 2039 qh->qh_qtd.qtd_buffer_hi[2] = 0; 2040 qh->qh_qtd.qtd_buffer_hi[3] = 0; 2041 qh->qh_qtd.qtd_buffer_hi[4] = 0; 2042 2043 usb_pc_cpu_flush(qh->page_cache); 2044 2045 if (xfer->xroot->udev->flags.self_suspended == 0) { 2046 EHCI_APPEND_QH(qh, *qh_last); 2047 } 2048 } 2049 2050 static void 2051 ehci_root_intr(ehci_softc_t *sc) 2052 { 2053 uint16_t i; 2054 uint16_t m; 2055 2056 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2057 2058 /* clear any old interrupt data */ 2059 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2060 2061 /* set bits */ 2062 m = (sc->sc_noport + 1); 2063 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2064 m = (8 * sizeof(sc->sc_hub_idata)); 2065 } 2066 for (i = 1; i < m; i++) { 2067 /* pick out CHANGE bits from the status register */ 2068 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2069 setbit(sc->sc_hub_idata, i); 2070 DPRINTF("port %d changed\n", i); 2071 } 2072 } 2073 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2074 sizeof(sc->sc_hub_idata)); 2075 } 2076 2077 static void 2078 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2079 { 2080 uint32_t nframes = xfer->nframes; 2081 uint32_t status; 2082 uint32_t *plen = xfer->frlengths; 2083 uint16_t len = 0; 2084 ehci_sitd_t *td = xfer->td_transfer_first; 2085 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2086 2087 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2088 xfer, xfer->endpoint); 2089 2090 while (nframes--) { 2091 if (td == NULL) { 2092 panic("%s:%d: out of TD's\n", 2093 __FUNCTION__, __LINE__); 2094 } 2095 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2096 pp_last = &sc->sc_isoc_fs_p_last[0]; 2097 } 2098 #ifdef USB_DEBUG 2099 if (ehcidebug > 15) { 2100 DPRINTF("isoc FS-TD\n"); 2101 ehci_dump_sitd(sc, td); 2102 } 2103 #endif 2104 usb_pc_cpu_invalidate(td->page_cache); 2105 status = hc32toh(sc, td->sitd_status); 2106 2107 len = EHCI_SITD_GET_LEN(status); 2108 2109 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2110 2111 if (*plen >= len) { 2112 len = *plen - len; 2113 } else { 2114 len = 0; 2115 } 2116 2117 *plen = len; 2118 2119 /* remove FS-TD from schedule */ 2120 EHCI_REMOVE_FS_TD(td, *pp_last); 2121 2122 pp_last++; 2123 plen++; 2124 td = td->obj_next; 2125 } 2126 2127 xfer->aframes = xfer->nframes; 2128 } 2129 2130 static void 2131 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2132 { 2133 uint32_t nframes = xfer->nframes; 2134 uint32_t status; 2135 uint32_t *plen = xfer->frlengths; 2136 uint16_t len = 0; 2137 uint8_t td_no = 0; 2138 ehci_itd_t *td = xfer->td_transfer_first; 2139 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2140 2141 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2142 xfer, xfer->endpoint); 2143 2144 while (nframes) { 2145 if (td == NULL) { 2146 panic("%s:%d: out of TD's\n", 2147 __FUNCTION__, __LINE__); 2148 } 2149 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2150 pp_last = &sc->sc_isoc_hs_p_last[0]; 2151 } 2152 #ifdef USB_DEBUG 2153 if (ehcidebug > 15) { 2154 DPRINTF("isoc HS-TD\n"); 2155 ehci_dump_itd(sc, td); 2156 } 2157 #endif 2158 2159 usb_pc_cpu_invalidate(td->page_cache); 2160 status = hc32toh(sc, td->itd_status[td_no]); 2161 2162 len = EHCI_ITD_GET_LEN(status); 2163 2164 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2165 2166 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2167 2168 if (*plen >= len) { 2169 /* 2170 * The length is valid. NOTE: The 2171 * complete length is written back 2172 * into the status field, and not the 2173 * remainder like with other transfer 2174 * descriptor types. 2175 */ 2176 } else { 2177 /* Invalid length - truncate */ 2178 len = 0; 2179 } 2180 2181 *plen = len; 2182 plen++; 2183 nframes--; 2184 } 2185 2186 td_no++; 2187 2188 if ((td_no == 8) || (nframes == 0)) { 2189 /* remove HS-TD from schedule */ 2190 EHCI_REMOVE_HS_TD(td, *pp_last); 2191 pp_last++; 2192 2193 td_no = 0; 2194 td = td->obj_next; 2195 } 2196 } 2197 xfer->aframes = xfer->nframes; 2198 } 2199 2200 /* NOTE: "done" can be run two times in a row, 2201 * from close and from interrupt 2202 */ 2203 static void 2204 ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2205 { 2206 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 2207 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2208 2209 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2210 2211 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2212 xfer, xfer->endpoint, error); 2213 2214 if ((methods == &ehci_device_bulk_methods) || 2215 (methods == &ehci_device_ctrl_methods)) { 2216 #ifdef USB_DEBUG 2217 if (ehcidebug > 8) { 2218 DPRINTF("nexttog=%d; data after transfer:\n", 2219 xfer->endpoint->toggle_next); 2220 ehci_dump_sqtds(sc, 2221 xfer->td_transfer_first); 2222 } 2223 #endif 2224 2225 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2226 sc->sc_async_p_last); 2227 } 2228 if (methods == &ehci_device_intr_methods) { 2229 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2230 sc->sc_intr_p_last[xfer->qh_pos]); 2231 } 2232 /* 2233 * Only finish isochronous transfers once which will update 2234 * "xfer->frlengths". 2235 */ 2236 if (xfer->td_transfer_first && 2237 xfer->td_transfer_last) { 2238 if (methods == &ehci_device_isoc_fs_methods) { 2239 ehci_isoc_fs_done(sc, xfer); 2240 } 2241 if (methods == &ehci_device_isoc_hs_methods) { 2242 ehci_isoc_hs_done(sc, xfer); 2243 } 2244 xfer->td_transfer_first = NULL; 2245 xfer->td_transfer_last = NULL; 2246 } 2247 /* dequeue transfer and start next transfer */ 2248 usbd_transfer_done(xfer, error); 2249 } 2250 2251 /*------------------------------------------------------------------------* 2252 * ehci bulk support 2253 *------------------------------------------------------------------------*/ 2254 static void 2255 ehci_device_bulk_open(struct usb_xfer *xfer) 2256 { 2257 return; 2258 } 2259 2260 static void 2261 ehci_device_bulk_close(struct usb_xfer *xfer) 2262 { 2263 ehci_device_done(xfer, USB_ERR_CANCELLED); 2264 } 2265 2266 static void 2267 ehci_device_bulk_enter(struct usb_xfer *xfer) 2268 { 2269 return; 2270 } 2271 2272 static void 2273 ehci_doorbell_async(struct ehci_softc *sc) 2274 { 2275 uint32_t temp; 2276 2277 /* 2278 * XXX Performance quirk: Some Host Controllers have a too low 2279 * interrupt rate. Issue an IAAD to stimulate the Host 2280 * Controller after queueing the BULK transfer. 2281 * 2282 * XXX Force the host controller to refresh any QH caches. 2283 */ 2284 temp = EOREAD4(sc, EHCI_USBCMD); 2285 if (!(temp & EHCI_CMD_IAAD)) 2286 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2287 } 2288 2289 static void 2290 ehci_device_bulk_start(struct usb_xfer *xfer) 2291 { 2292 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2293 2294 /* setup TD's and QH */ 2295 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2296 2297 /* put transfer on interrupt queue */ 2298 ehci_transfer_intr_enqueue(xfer); 2299 2300 /* 2301 * XXX Certain nVidia chipsets choke when using the IAAD 2302 * feature too frequently. 2303 */ 2304 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2305 return; 2306 2307 ehci_doorbell_async(sc); 2308 } 2309 2310 static const struct usb_pipe_methods ehci_device_bulk_methods = 2311 { 2312 .open = ehci_device_bulk_open, 2313 .close = ehci_device_bulk_close, 2314 .enter = ehci_device_bulk_enter, 2315 .start = ehci_device_bulk_start, 2316 }; 2317 2318 /*------------------------------------------------------------------------* 2319 * ehci control support 2320 *------------------------------------------------------------------------*/ 2321 static void 2322 ehci_device_ctrl_open(struct usb_xfer *xfer) 2323 { 2324 return; 2325 } 2326 2327 static void 2328 ehci_device_ctrl_close(struct usb_xfer *xfer) 2329 { 2330 ehci_device_done(xfer, USB_ERR_CANCELLED); 2331 } 2332 2333 static void 2334 ehci_device_ctrl_enter(struct usb_xfer *xfer) 2335 { 2336 return; 2337 } 2338 2339 static void 2340 ehci_device_ctrl_start(struct usb_xfer *xfer) 2341 { 2342 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2343 2344 /* setup TD's and QH */ 2345 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2346 2347 /* put transfer on interrupt queue */ 2348 ehci_transfer_intr_enqueue(xfer); 2349 } 2350 2351 static const struct usb_pipe_methods ehci_device_ctrl_methods = 2352 { 2353 .open = ehci_device_ctrl_open, 2354 .close = ehci_device_ctrl_close, 2355 .enter = ehci_device_ctrl_enter, 2356 .start = ehci_device_ctrl_start, 2357 }; 2358 2359 /*------------------------------------------------------------------------* 2360 * ehci interrupt support 2361 *------------------------------------------------------------------------*/ 2362 static void 2363 ehci_device_intr_open(struct usb_xfer *xfer) 2364 { 2365 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2366 uint16_t best; 2367 uint16_t bit; 2368 uint16_t x; 2369 2370 usb_hs_bandwidth_alloc(xfer); 2371 2372 /* 2373 * Find the best QH position corresponding to the given interval: 2374 */ 2375 2376 best = 0; 2377 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2378 while (bit) { 2379 if (xfer->interval >= bit) { 2380 x = bit; 2381 best = bit; 2382 while (x & bit) { 2383 if (sc->sc_intr_stat[x] < 2384 sc->sc_intr_stat[best]) { 2385 best = x; 2386 } 2387 x++; 2388 } 2389 break; 2390 } 2391 bit >>= 1; 2392 } 2393 2394 sc->sc_intr_stat[best]++; 2395 xfer->qh_pos = best; 2396 2397 DPRINTFN(3, "best=%d interval=%d\n", 2398 best, xfer->interval); 2399 } 2400 2401 static void 2402 ehci_device_intr_close(struct usb_xfer *xfer) 2403 { 2404 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2405 2406 sc->sc_intr_stat[xfer->qh_pos]--; 2407 2408 ehci_device_done(xfer, USB_ERR_CANCELLED); 2409 2410 /* bandwidth must be freed after device done */ 2411 usb_hs_bandwidth_free(xfer); 2412 } 2413 2414 static void 2415 ehci_device_intr_enter(struct usb_xfer *xfer) 2416 { 2417 return; 2418 } 2419 2420 static void 2421 ehci_device_intr_start(struct usb_xfer *xfer) 2422 { 2423 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2424 2425 /* setup TD's and QH */ 2426 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2427 2428 /* put transfer on interrupt queue */ 2429 ehci_transfer_intr_enqueue(xfer); 2430 } 2431 2432 static const struct usb_pipe_methods ehci_device_intr_methods = 2433 { 2434 .open = ehci_device_intr_open, 2435 .close = ehci_device_intr_close, 2436 .enter = ehci_device_intr_enter, 2437 .start = ehci_device_intr_start, 2438 }; 2439 2440 /*------------------------------------------------------------------------* 2441 * ehci full speed isochronous support 2442 *------------------------------------------------------------------------*/ 2443 static void 2444 ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2445 { 2446 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2447 ehci_sitd_t *td; 2448 uint32_t sitd_portaddr; 2449 uint8_t ds; 2450 2451 sitd_portaddr = 2452 EHCI_SITD_SET_ADDR(xfer->address) | 2453 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2454 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2455 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2456 2457 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2458 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2459 2460 sitd_portaddr = htohc32(sc, sitd_portaddr); 2461 2462 /* initialize all TD's */ 2463 2464 for (ds = 0; ds != 2; ds++) { 2465 2466 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2467 2468 td->sitd_portaddr = sitd_portaddr; 2469 2470 /* 2471 * TODO: make some kind of automatic 2472 * SMASK/CMASK selection based on micro-frame 2473 * usage 2474 * 2475 * micro-frame usage (8 microframes per 1ms) 2476 */ 2477 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2478 2479 usb_pc_cpu_flush(td->page_cache); 2480 } 2481 } 2482 } 2483 2484 static void 2485 ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2486 { 2487 ehci_device_done(xfer, USB_ERR_CANCELLED); 2488 } 2489 2490 static void 2491 ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2492 { 2493 struct usb_page_search buf_res; 2494 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2495 ehci_sitd_t *td; 2496 ehci_sitd_t *td_last = NULL; 2497 ehci_sitd_t **pp_last; 2498 uint32_t *plen; 2499 uint32_t buf_offset; 2500 uint32_t nframes; 2501 uint32_t temp; 2502 uint32_t sitd_mask; 2503 uint16_t tlen; 2504 uint8_t sa; 2505 uint8_t sb; 2506 2507 #ifdef USB_DEBUG 2508 uint8_t once = 1; 2509 2510 #endif 2511 2512 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2513 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2514 2515 /* get the current frame index */ 2516 2517 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2518 2519 /* 2520 * check if the frame index is within the window where the frames 2521 * will be inserted 2522 */ 2523 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2524 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2525 2526 if ((xfer->endpoint->is_synced == 0) || 2527 (buf_offset < xfer->nframes)) { 2528 /* 2529 * If there is data underflow or the pipe queue is empty we 2530 * schedule the transfer a few frames ahead of the current 2531 * frame position. Else two isochronous transfers might 2532 * overlap. 2533 */ 2534 xfer->endpoint->isoc_next = (nframes + 3) & 2535 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2536 xfer->endpoint->is_synced = 1; 2537 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2538 } 2539 /* 2540 * compute how many milliseconds the insertion is ahead of the 2541 * current frame position: 2542 */ 2543 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2544 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2545 2546 /* 2547 * pre-compute when the isochronous transfer will be finished: 2548 */ 2549 xfer->isoc_time_complete = 2550 usb_isoc_time_expand(&sc->sc_bus, nframes) + 2551 buf_offset + xfer->nframes; 2552 2553 /* get the real number of frames */ 2554 2555 nframes = xfer->nframes; 2556 2557 buf_offset = 0; 2558 2559 plen = xfer->frlengths; 2560 2561 /* toggle the DMA set we are using */ 2562 xfer->flags_int.curr_dma_set ^= 1; 2563 2564 /* get next DMA set */ 2565 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2566 xfer->td_transfer_first = td; 2567 2568 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2569 2570 /* store starting position */ 2571 2572 xfer->qh_pos = xfer->endpoint->isoc_next; 2573 2574 while (nframes--) { 2575 if (td == NULL) { 2576 panic("%s:%d: out of TD's\n", 2577 __FUNCTION__, __LINE__); 2578 } 2579 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) 2580 pp_last = &sc->sc_isoc_fs_p_last[0]; 2581 2582 /* reuse sitd_portaddr and sitd_back from last transfer */ 2583 2584 if (*plen > xfer->max_frame_size) { 2585 #ifdef USB_DEBUG 2586 if (once) { 2587 once = 0; 2588 kprintf("%s: frame length(%d) exceeds %d " 2589 "bytes (frame truncated)\n", 2590 __FUNCTION__, *plen, 2591 xfer->max_frame_size); 2592 } 2593 #endif 2594 *plen = xfer->max_frame_size; 2595 } 2596 2597 /* allocate a slot */ 2598 2599 sa = usbd_fs_isoc_schedule_alloc_slot(xfer, 2600 xfer->isoc_time_complete - nframes - 1); 2601 2602 if (sa == 255) { 2603 /* 2604 * Schedule is FULL, set length to zero: 2605 */ 2606 2607 *plen = 0; 2608 sa = USB_FS_ISOC_UFRAME_MAX - 1; 2609 } 2610 if (*plen) { 2611 /* 2612 * only call "usbd_get_page()" when we have a 2613 * non-zero length 2614 */ 2615 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2616 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2617 buf_offset += *plen; 2618 /* 2619 * NOTE: We need to subtract one from the offset so 2620 * that we are on a valid page! 2621 */ 2622 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2623 &buf_res); 2624 temp = buf_res.physaddr & ~0xFFF; 2625 } else { 2626 td->sitd_bp[0] = 0; 2627 temp = 0; 2628 } 2629 2630 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2631 tlen = *plen; 2632 if (tlen <= 188) { 2633 temp |= 1; /* T-count = 1, TP = ALL */ 2634 tlen = 1; 2635 } else { 2636 tlen += 187; 2637 tlen /= 188; 2638 temp |= tlen; /* T-count = [1..6] */ 2639 temp |= 8; /* TP = Begin */ 2640 } 2641 2642 tlen += sa; 2643 2644 if (tlen >= 8) { 2645 sb = 0; 2646 } else { 2647 sb = (1 << tlen); 2648 } 2649 2650 sa = (1 << sa); 2651 sa = (sb - sa) & 0x3F; 2652 sb = 0; 2653 } else { 2654 sb = (-(4 << sa)) & 0xFE; 2655 sa = (1 << sa) & 0x3F; 2656 } 2657 2658 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2659 EHCI_SITD_SET_CMASK(sb)); 2660 2661 td->sitd_bp[1] = htohc32(sc, temp); 2662 2663 td->sitd_mask = htohc32(sc, sitd_mask); 2664 2665 if (nframes == 0) { 2666 td->sitd_status = htohc32(sc, 2667 EHCI_SITD_IOC | 2668 EHCI_SITD_ACTIVE | 2669 EHCI_SITD_SET_LEN(*plen)); 2670 } else { 2671 td->sitd_status = htohc32(sc, 2672 EHCI_SITD_ACTIVE | 2673 EHCI_SITD_SET_LEN(*plen)); 2674 } 2675 usb_pc_cpu_flush(td->page_cache); 2676 2677 #ifdef USB_DEBUG 2678 if (ehcidebug > 15) { 2679 DPRINTF("FS-TD %d\n", nframes); 2680 ehci_dump_sitd(sc, td); 2681 } 2682 #endif 2683 /* insert TD into schedule */ 2684 EHCI_APPEND_FS_TD(td, *pp_last); 2685 pp_last++; 2686 2687 plen++; 2688 td_last = td; 2689 td = td->obj_next; 2690 } 2691 2692 xfer->td_transfer_last = td_last; 2693 2694 /* update isoc_next */ 2695 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2696 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2697 2698 /* 2699 * We don't allow cancelling of the SPLIT transaction USB FULL 2700 * speed transfer, because it disturbs the bandwidth 2701 * computation algorithm. 2702 */ 2703 xfer->flags_int.can_cancel_immed = 0; 2704 } 2705 2706 static void 2707 ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2708 { 2709 /* 2710 * We don't allow cancelling of the SPLIT transaction USB FULL 2711 * speed transfer, because it disturbs the bandwidth 2712 * computation algorithm. 2713 */ 2714 xfer->flags_int.can_cancel_immed = 0; 2715 2716 /* set a default timeout */ 2717 if (xfer->timeout == 0) 2718 xfer->timeout = 500; /* ms */ 2719 2720 /* put transfer on interrupt queue */ 2721 ehci_transfer_intr_enqueue(xfer); 2722 } 2723 2724 static const struct usb_pipe_methods ehci_device_isoc_fs_methods = 2725 { 2726 .open = ehci_device_isoc_fs_open, 2727 .close = ehci_device_isoc_fs_close, 2728 .enter = ehci_device_isoc_fs_enter, 2729 .start = ehci_device_isoc_fs_start, 2730 }; 2731 2732 /*------------------------------------------------------------------------* 2733 * ehci high speed isochronous support 2734 *------------------------------------------------------------------------*/ 2735 static void 2736 ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2737 { 2738 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2739 ehci_itd_t *td; 2740 uint32_t temp; 2741 uint8_t ds; 2742 2743 usb_hs_bandwidth_alloc(xfer); 2744 2745 /* initialize all TD's */ 2746 2747 for (ds = 0; ds != 2; ds++) { 2748 2749 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2750 2751 /* set TD inactive */ 2752 td->itd_status[0] = 0; 2753 td->itd_status[1] = 0; 2754 td->itd_status[2] = 0; 2755 td->itd_status[3] = 0; 2756 td->itd_status[4] = 0; 2757 td->itd_status[5] = 0; 2758 td->itd_status[6] = 0; 2759 td->itd_status[7] = 0; 2760 2761 /* set endpoint and address */ 2762 td->itd_bp[0] = htohc32(sc, 2763 EHCI_ITD_SET_ADDR(xfer->address) | 2764 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2765 2766 temp = 2767 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2768 2769 /* set direction */ 2770 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2771 temp |= EHCI_ITD_SET_DIR_IN; 2772 } 2773 /* set maximum packet size */ 2774 td->itd_bp[1] = htohc32(sc, temp); 2775 2776 /* set transfer multiplier */ 2777 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2778 2779 usb_pc_cpu_flush(td->page_cache); 2780 } 2781 } 2782 } 2783 2784 static void 2785 ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2786 { 2787 ehci_device_done(xfer, USB_ERR_CANCELLED); 2788 2789 /* bandwidth must be freed after device done */ 2790 usb_hs_bandwidth_free(xfer); 2791 } 2792 2793 static void 2794 ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2795 { 2796 struct usb_page_search buf_res; 2797 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2798 ehci_itd_t *td; 2799 ehci_itd_t *td_last = NULL; 2800 ehci_itd_t **pp_last; 2801 bus_size_t page_addr; 2802 uint32_t *plen; 2803 uint32_t status; 2804 uint32_t buf_offset; 2805 uint32_t nframes; 2806 uint32_t itd_offset[8 + 1]; 2807 uint8_t x; 2808 uint8_t td_no; 2809 uint8_t page_no; 2810 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 2811 2812 #ifdef USB_DEBUG 2813 uint8_t once = 1; 2814 2815 #endif 2816 2817 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2818 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift); 2819 2820 /* get the current frame index */ 2821 2822 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2823 2824 /* 2825 * check if the frame index is within the window where the frames 2826 * will be inserted 2827 */ 2828 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2829 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2830 2831 if ((xfer->endpoint->is_synced == 0) || 2832 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2833 /* 2834 * If there is data underflow or the pipe queue is empty we 2835 * schedule the transfer a few frames ahead of the current 2836 * frame position. Else two isochronous transfers might 2837 * overlap. 2838 */ 2839 xfer->endpoint->isoc_next = (nframes + 3) & 2840 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2841 xfer->endpoint->is_synced = 1; 2842 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2843 } 2844 /* 2845 * compute how many milliseconds the insertion is ahead of the 2846 * current frame position: 2847 */ 2848 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2849 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2850 2851 /* 2852 * pre-compute when the isochronous transfer will be finished: 2853 */ 2854 xfer->isoc_time_complete = 2855 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2856 (((xfer->nframes << shift) + 7) / 8); 2857 2858 /* get the real number of frames */ 2859 2860 nframes = xfer->nframes; 2861 2862 buf_offset = 0; 2863 td_no = 0; 2864 2865 plen = xfer->frlengths; 2866 2867 /* toggle the DMA set we are using */ 2868 xfer->flags_int.curr_dma_set ^= 1; 2869 2870 /* get next DMA set */ 2871 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2872 xfer->td_transfer_first = td; 2873 2874 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2875 2876 /* store starting position */ 2877 2878 xfer->qh_pos = xfer->endpoint->isoc_next; 2879 2880 while (nframes) { 2881 if (td == NULL) { 2882 panic("%s:%d: out of TD's\n", 2883 __FUNCTION__, __LINE__); 2884 } 2885 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2886 pp_last = &sc->sc_isoc_hs_p_last[0]; 2887 } 2888 /* range check */ 2889 if (*plen > xfer->max_frame_size) { 2890 #ifdef USB_DEBUG 2891 if (once) { 2892 once = 0; 2893 kprintf("%s: frame length(%d) exceeds %d bytes " 2894 "(frame truncated)\n", 2895 __FUNCTION__, *plen, xfer->max_frame_size); 2896 } 2897 #endif 2898 *plen = xfer->max_frame_size; 2899 } 2900 2901 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2902 status = (EHCI_ITD_SET_LEN(*plen) | 2903 EHCI_ITD_ACTIVE | 2904 EHCI_ITD_SET_PG(0)); 2905 td->itd_status[td_no] = htohc32(sc, status); 2906 itd_offset[td_no] = buf_offset; 2907 buf_offset += *plen; 2908 plen++; 2909 nframes --; 2910 } else { 2911 td->itd_status[td_no] = 0; /* not active */ 2912 itd_offset[td_no] = buf_offset; 2913 } 2914 2915 td_no++; 2916 2917 if ((td_no == 8) || (nframes == 0)) { 2918 2919 /* the rest of the transfers are not active, if any */ 2920 for (x = td_no; x != 8; x++) { 2921 td->itd_status[x] = 0; /* not active */ 2922 } 2923 2924 /* check if there is any data to be transferred */ 2925 if (itd_offset[0] != buf_offset) { 2926 page_no = 0; 2927 itd_offset[td_no] = buf_offset; 2928 2929 /* get first page offset */ 2930 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2931 /* get page address */ 2932 page_addr = buf_res.physaddr & ~0xFFF; 2933 /* update page address */ 2934 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2935 td->itd_bp[0] |= htohc32(sc, page_addr); 2936 2937 for (x = 0; x != td_no; x++) { 2938 /* set page number and page offset */ 2939 status = (EHCI_ITD_SET_PG(page_no) | 2940 (buf_res.physaddr & 0xFFF)); 2941 td->itd_status[x] |= htohc32(sc, status); 2942 2943 /* get next page offset */ 2944 if (itd_offset[x + 1] == buf_offset) { 2945 /* 2946 * We subtract one so that 2947 * we don't go off the last 2948 * page! 2949 */ 2950 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2951 } else { 2952 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2953 } 2954 2955 /* check if we need a new page */ 2956 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2957 /* new page needed */ 2958 page_addr = buf_res.physaddr & ~0xFFF; 2959 if (page_no == 6) { 2960 panic("%s: too many pages\n", __FUNCTION__); 2961 } 2962 page_no++; 2963 /* update page address */ 2964 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2965 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2966 } 2967 } 2968 } 2969 /* set IOC bit if we are complete */ 2970 if (nframes == 0) { 2971 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2972 } 2973 usb_pc_cpu_flush(td->page_cache); 2974 #ifdef USB_DEBUG 2975 if (ehcidebug > 15) { 2976 DPRINTF("HS-TD %d\n", nframes); 2977 ehci_dump_itd(sc, td); 2978 } 2979 #endif 2980 /* insert TD into schedule */ 2981 EHCI_APPEND_HS_TD(td, *pp_last); 2982 pp_last++; 2983 2984 td_no = 0; 2985 td_last = td; 2986 td = td->obj_next; 2987 } 2988 } 2989 2990 xfer->td_transfer_last = td_last; 2991 2992 /* update isoc_next */ 2993 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2994 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2995 } 2996 2997 static void 2998 ehci_device_isoc_hs_start(struct usb_xfer *xfer) 2999 { 3000 /* put transfer on interrupt queue */ 3001 ehci_transfer_intr_enqueue(xfer); 3002 } 3003 3004 static const struct usb_pipe_methods ehci_device_isoc_hs_methods = 3005 { 3006 .open = ehci_device_isoc_hs_open, 3007 .close = ehci_device_isoc_hs_close, 3008 .enter = ehci_device_isoc_hs_enter, 3009 .start = ehci_device_isoc_hs_start, 3010 }; 3011 3012 /*------------------------------------------------------------------------* 3013 * ehci root control support 3014 *------------------------------------------------------------------------* 3015 * Simulate a hardware hub by handling all the necessary requests. 3016 *------------------------------------------------------------------------*/ 3017 3018 static const 3019 struct usb_device_descriptor ehci_devd = 3020 { 3021 sizeof(struct usb_device_descriptor), 3022 UDESC_DEVICE, /* type */ 3023 {0x00, 0x02}, /* USB version */ 3024 UDCLASS_HUB, /* class */ 3025 UDSUBCLASS_HUB, /* subclass */ 3026 UDPROTO_HSHUBSTT, /* protocol */ 3027 64, /* max packet */ 3028 {0}, {0}, {0x00, 0x01}, /* device id */ 3029 1, 2, 0, /* string indicies */ 3030 1 /* # of configurations */ 3031 }; 3032 3033 static const 3034 struct usb_device_qualifier ehci_odevd = 3035 { 3036 sizeof(struct usb_device_qualifier), 3037 UDESC_DEVICE_QUALIFIER, /* type */ 3038 {0x00, 0x02}, /* USB version */ 3039 UDCLASS_HUB, /* class */ 3040 UDSUBCLASS_HUB, /* subclass */ 3041 UDPROTO_FSHUB, /* protocol */ 3042 0, /* max packet */ 3043 0, /* # of configurations */ 3044 0 3045 }; 3046 3047 static const struct ehci_config_desc ehci_confd = { 3048 .confd = { 3049 .bLength = sizeof(struct usb_config_descriptor), 3050 .bDescriptorType = UDESC_CONFIG, 3051 .wTotalLength[0] = sizeof(ehci_confd), 3052 .bNumInterface = 1, 3053 .bConfigurationValue = 1, 3054 .iConfiguration = 0, 3055 .bmAttributes = UC_SELF_POWERED, 3056 .bMaxPower = 0 /* max power */ 3057 }, 3058 .ifcd = { 3059 .bLength = sizeof(struct usb_interface_descriptor), 3060 .bDescriptorType = UDESC_INTERFACE, 3061 .bNumEndpoints = 1, 3062 .bInterfaceClass = UICLASS_HUB, 3063 .bInterfaceSubClass = UISUBCLASS_HUB, 3064 .bInterfaceProtocol = 0, 3065 }, 3066 .endpd = { 3067 .bLength = sizeof(struct usb_endpoint_descriptor), 3068 .bDescriptorType = UDESC_ENDPOINT, 3069 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3070 .bmAttributes = UE_INTERRUPT, 3071 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3072 .bInterval = 255, 3073 }, 3074 }; 3075 3076 static const 3077 struct usb_hub_descriptor ehci_hubd = 3078 { 3079 .bDescLength = 0, /* dynamic length */ 3080 .bDescriptorType = UDESC_HUB, 3081 }; 3082 3083 static void 3084 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3085 { 3086 uint32_t port; 3087 uint32_t v; 3088 3089 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3090 3091 port = EHCI_PORTSC(index); 3092 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3093 EOWRITE4(sc, port, v | EHCI_PS_PO); 3094 } 3095 3096 static usb_error_t 3097 ehci_roothub_exec(struct usb_device *udev, 3098 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3099 { 3100 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3101 const char *str_ptr; 3102 const void *ptr; 3103 uint32_t port; 3104 uint32_t v; 3105 uint16_t len; 3106 uint16_t i; 3107 uint16_t value; 3108 uint16_t index; 3109 usb_error_t err; 3110 3111 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 3112 3113 /* buffer reset */ 3114 ptr = (const void *)&sc->sc_hub_desc; 3115 len = 0; 3116 err = 0; 3117 3118 value = UGETW(req->wValue); 3119 index = UGETW(req->wIndex); 3120 3121 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3122 "wValue=0x%04x wIndex=0x%04x\n", 3123 req->bmRequestType, req->bRequest, 3124 UGETW(req->wLength), value, index); 3125 3126 #define C(x,y) ((x) | ((y) << 8)) 3127 switch (C(req->bRequest, req->bmRequestType)) { 3128 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3129 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3130 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3131 /* 3132 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3133 * for the integrated root hub. 3134 */ 3135 break; 3136 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3137 len = 1; 3138 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3139 break; 3140 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3141 switch (value >> 8) { 3142 case UDESC_DEVICE: 3143 if ((value & 0xff) != 0) { 3144 err = USB_ERR_IOERROR; 3145 goto done; 3146 } 3147 len = sizeof(ehci_devd); 3148 ptr = (const void *)&ehci_devd; 3149 break; 3150 /* 3151 * We can't really operate at another speed, 3152 * but the specification says we need this 3153 * descriptor: 3154 */ 3155 case UDESC_DEVICE_QUALIFIER: 3156 if ((value & 0xff) != 0) { 3157 err = USB_ERR_IOERROR; 3158 goto done; 3159 } 3160 len = sizeof(ehci_odevd); 3161 ptr = (const void *)&ehci_odevd; 3162 break; 3163 3164 case UDESC_CONFIG: 3165 if ((value & 0xff) != 0) { 3166 err = USB_ERR_IOERROR; 3167 goto done; 3168 } 3169 len = sizeof(ehci_confd); 3170 ptr = (const void *)&ehci_confd; 3171 break; 3172 3173 case UDESC_STRING: 3174 switch (value & 0xff) { 3175 case 0: /* Language table */ 3176 str_ptr = "\001"; 3177 break; 3178 3179 case 1: /* Vendor */ 3180 str_ptr = sc->sc_vendor; 3181 break; 3182 3183 case 2: /* Product */ 3184 str_ptr = "EHCI root HUB"; 3185 break; 3186 3187 default: 3188 str_ptr = ""; 3189 break; 3190 } 3191 3192 len = usb_make_str_desc( 3193 sc->sc_hub_desc.temp, 3194 sizeof(sc->sc_hub_desc.temp), 3195 str_ptr); 3196 break; 3197 default: 3198 err = USB_ERR_IOERROR; 3199 goto done; 3200 } 3201 break; 3202 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3203 len = 1; 3204 sc->sc_hub_desc.temp[0] = 0; 3205 break; 3206 case C(UR_GET_STATUS, UT_READ_DEVICE): 3207 len = 2; 3208 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3209 break; 3210 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3211 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3212 len = 2; 3213 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3214 break; 3215 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3216 if (value >= EHCI_MAX_DEVICES) { 3217 err = USB_ERR_IOERROR; 3218 goto done; 3219 } 3220 sc->sc_addr = value; 3221 break; 3222 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3223 if ((value != 0) && (value != 1)) { 3224 err = USB_ERR_IOERROR; 3225 goto done; 3226 } 3227 sc->sc_conf = value; 3228 break; 3229 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3230 break; 3231 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3232 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3233 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3234 err = USB_ERR_IOERROR; 3235 goto done; 3236 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3237 break; 3238 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3239 break; 3240 /* Hub requests */ 3241 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3242 break; 3243 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3244 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3245 3246 if ((index < 1) || 3247 (index > sc->sc_noport)) { 3248 err = USB_ERR_IOERROR; 3249 goto done; 3250 } 3251 port = EHCI_PORTSC(index); 3252 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3253 switch (value) { 3254 case UHF_PORT_ENABLE: 3255 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3256 break; 3257 case UHF_PORT_SUSPEND: 3258 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3259 3260 /* 3261 * waking up a High Speed device is rather 3262 * complicated if 3263 */ 3264 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3265 } 3266 /* wait 20ms for resume sequence to complete */ 3267 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 50); 3268 3269 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3270 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3271 3272 /* 4ms settle time */ 3273 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 250); 3274 break; 3275 case UHF_PORT_POWER: 3276 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3277 break; 3278 case UHF_PORT_TEST: 3279 DPRINTFN(3, "clear port test " 3280 "%d\n", index); 3281 break; 3282 case UHF_PORT_INDICATOR: 3283 DPRINTFN(3, "clear port ind " 3284 "%d\n", index); 3285 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3286 break; 3287 case UHF_C_PORT_CONNECTION: 3288 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3289 break; 3290 case UHF_C_PORT_ENABLE: 3291 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3292 break; 3293 case UHF_C_PORT_SUSPEND: 3294 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3295 break; 3296 case UHF_C_PORT_OVER_CURRENT: 3297 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3298 break; 3299 case UHF_C_PORT_RESET: 3300 sc->sc_isreset = 0; 3301 break; 3302 default: 3303 err = USB_ERR_IOERROR; 3304 goto done; 3305 } 3306 break; 3307 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3308 if ((value & 0xff) != 0) { 3309 err = USB_ERR_IOERROR; 3310 goto done; 3311 } 3312 v = EREAD4(sc, EHCI_HCSPARAMS); 3313 3314 sc->sc_hub_desc.hubd = ehci_hubd; 3315 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3316 3317 if (EHCI_HCS_PPC(v)) 3318 i = UHD_PWR_INDIVIDUAL; 3319 else 3320 i = UHD_PWR_NO_SWITCH; 3321 3322 if (EHCI_HCS_P_INDICATOR(v)) 3323 i |= UHD_PORT_IND; 3324 3325 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3326 /* XXX can't find out? */ 3327 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3328 /* XXX don't know if ports are removable or not */ 3329 sc->sc_hub_desc.hubd.bDescLength = 3330 8 + ((sc->sc_noport + 7) / 8); 3331 len = sc->sc_hub_desc.hubd.bDescLength; 3332 break; 3333 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3334 len = 16; 3335 memset(sc->sc_hub_desc.temp, 0, 16); 3336 break; 3337 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3338 DPRINTFN(9, "get port status i=%d\n", 3339 index); 3340 if ((index < 1) || 3341 (index > sc->sc_noport)) { 3342 err = USB_ERR_IOERROR; 3343 goto done; 3344 } 3345 v = EOREAD4(sc, EHCI_PORTSC(index)); 3346 DPRINTFN(9, "port status=0x%04x\n", v); 3347 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) { 3348 if ((v & 0xc000000) == 0x8000000) 3349 i = UPS_HIGH_SPEED; 3350 else if ((v & 0xc000000) == 0x4000000) 3351 i = UPS_LOW_SPEED; 3352 else 3353 i = 0; 3354 } else { 3355 i = UPS_HIGH_SPEED; 3356 } 3357 if (v & EHCI_PS_CS) 3358 i |= UPS_CURRENT_CONNECT_STATUS; 3359 if (v & EHCI_PS_PE) 3360 i |= UPS_PORT_ENABLED; 3361 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3362 i |= UPS_SUSPEND; 3363 if (v & EHCI_PS_OCA) 3364 i |= UPS_OVERCURRENT_INDICATOR; 3365 if (v & EHCI_PS_PR) 3366 i |= UPS_RESET; 3367 if (v & EHCI_PS_PP) 3368 i |= UPS_PORT_POWER; 3369 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3370 i = 0; 3371 if (v & EHCI_PS_CSC) 3372 i |= UPS_C_CONNECT_STATUS; 3373 if (v & EHCI_PS_PEC) 3374 i |= UPS_C_PORT_ENABLED; 3375 if (v & EHCI_PS_OCC) 3376 i |= UPS_C_OVERCURRENT_INDICATOR; 3377 if (v & EHCI_PS_FPR) 3378 i |= UPS_C_SUSPEND; 3379 if (sc->sc_isreset) 3380 i |= UPS_C_PORT_RESET; 3381 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3382 len = sizeof(sc->sc_hub_desc.ps); 3383 break; 3384 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3385 err = USB_ERR_IOERROR; 3386 goto done; 3387 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3388 break; 3389 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3390 if ((index < 1) || 3391 (index > sc->sc_noport)) { 3392 err = USB_ERR_IOERROR; 3393 goto done; 3394 } 3395 port = EHCI_PORTSC(index); 3396 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3397 switch (value) { 3398 case UHF_PORT_ENABLE: 3399 EOWRITE4(sc, port, v | EHCI_PS_PE); 3400 break; 3401 case UHF_PORT_SUSPEND: 3402 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3403 break; 3404 case UHF_PORT_RESET: 3405 DPRINTFN(6, "reset port %d\n", index); 3406 #ifdef USB_DEBUG 3407 if (ehcinohighspeed) { 3408 /* 3409 * Connect USB device to companion 3410 * controller. 3411 */ 3412 ehci_disown(sc, index, 1); 3413 break; 3414 } 3415 #endif 3416 if (EHCI_PS_IS_LOWSPEED(v) && 3417 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3418 /* Low speed device, give up ownership. */ 3419 ehci_disown(sc, index, 1); 3420 break; 3421 } 3422 /* Start reset sequence. */ 3423 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3424 EOWRITE4(sc, port, v | EHCI_PS_PR); 3425 3426 /* Wait for reset to complete. */ 3427 usb_pause_mtx(&sc->sc_bus.bus_lock, 3428 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 3429 3430 /* Terminate reset sequence. */ 3431 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3432 EOWRITE4(sc, port, v); 3433 3434 /* Wait for HC to complete reset. */ 3435 usb_pause_mtx(&sc->sc_bus.bus_lock, 3436 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3437 3438 v = EOREAD4(sc, port); 3439 DPRINTF("ehci after reset, status=0x%08x\n", v); 3440 if (v & EHCI_PS_PR) { 3441 device_printf(sc->sc_bus.bdev, 3442 "port reset timeout\n"); 3443 err = USB_ERR_TIMEOUT; 3444 goto done; 3445 } 3446 if (!(v & EHCI_PS_PE) && 3447 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3448 /* Not a high speed device, give up ownership.*/ 3449 ehci_disown(sc, index, 0); 3450 break; 3451 } 3452 sc->sc_isreset = 1; 3453 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3454 index, v); 3455 break; 3456 3457 case UHF_PORT_POWER: 3458 DPRINTFN(3, "set port power %d\n", index); 3459 EOWRITE4(sc, port, v | EHCI_PS_PP); 3460 break; 3461 3462 case UHF_PORT_TEST: 3463 DPRINTFN(3, "set port test %d\n", index); 3464 break; 3465 3466 case UHF_PORT_INDICATOR: 3467 DPRINTFN(3, "set port ind %d\n", index); 3468 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3469 break; 3470 3471 default: 3472 err = USB_ERR_IOERROR; 3473 goto done; 3474 } 3475 break; 3476 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3477 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3478 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3479 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3480 break; 3481 default: 3482 err = USB_ERR_IOERROR; 3483 goto done; 3484 } 3485 done: 3486 *plength = len; 3487 *pptr = ptr; 3488 return (err); 3489 } 3490 3491 static void 3492 ehci_xfer_setup(struct usb_setup_params *parm) 3493 { 3494 struct usb_page_search page_info; 3495 struct usb_page_cache *pc; 3496 ehci_softc_t *sc; 3497 struct usb_xfer *xfer; 3498 void *last_obj; 3499 uint32_t nqtd; 3500 uint32_t nqh; 3501 uint32_t nsitd; 3502 uint32_t nitd; 3503 uint32_t n; 3504 3505 sc = EHCI_BUS2SC(parm->udev->bus); 3506 xfer = parm->curr_xfer; 3507 3508 nqtd = 0; 3509 nqh = 0; 3510 nsitd = 0; 3511 nitd = 0; 3512 3513 /* 3514 * compute maximum number of some structures 3515 */ 3516 if (parm->methods == &ehci_device_ctrl_methods) { 3517 3518 /* 3519 * The proof for the "nqtd" formula is illustrated like 3520 * this: 3521 * 3522 * +------------------------------------+ 3523 * | | 3524 * | |remainder -> | 3525 * | +-----+---+ | 3526 * | | xxx | x | frm 0 | 3527 * | +-----+---++ | 3528 * | | xxx | xx | frm 1 | 3529 * | +-----+----+ | 3530 * | ... | 3531 * +------------------------------------+ 3532 * 3533 * "xxx" means a completely full USB transfer descriptor 3534 * 3535 * "x" and "xx" means a short USB packet 3536 * 3537 * For the remainder of an USB transfer modulo 3538 * "max_data_length" we need two USB transfer descriptors. 3539 * One to transfer the remaining data and one to finalise 3540 * with a zero length packet in case the "force_short_xfer" 3541 * flag is set. We only need two USB transfer descriptors in 3542 * the case where the transfer length of the first one is a 3543 * factor of "max_frame_size". The rest of the needed USB 3544 * transfer descriptors is given by the buffer size divided 3545 * by the maximum data payload. 3546 */ 3547 parm->hc_max_packet_size = 0x400; 3548 parm->hc_max_packet_count = 1; 3549 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3550 xfer->flags_int.bdma_enable = 1; 3551 3552 usbd_transfer_setup_sub(parm); 3553 3554 nqh = 1; 3555 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3556 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3557 3558 } else if (parm->methods == &ehci_device_bulk_methods) { 3559 3560 parm->hc_max_packet_size = 0x400; 3561 parm->hc_max_packet_count = 1; 3562 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3563 xfer->flags_int.bdma_enable = 1; 3564 3565 usbd_transfer_setup_sub(parm); 3566 3567 nqh = 1; 3568 nqtd = ((2 * xfer->nframes) 3569 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3570 3571 } else if (parm->methods == &ehci_device_intr_methods) { 3572 3573 if (parm->speed == USB_SPEED_HIGH) { 3574 parm->hc_max_packet_size = 0x400; 3575 parm->hc_max_packet_count = 3; 3576 } else if (parm->speed == USB_SPEED_FULL) { 3577 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3578 parm->hc_max_packet_count = 1; 3579 } else { 3580 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3581 parm->hc_max_packet_count = 1; 3582 } 3583 3584 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3585 xfer->flags_int.bdma_enable = 1; 3586 3587 usbd_transfer_setup_sub(parm); 3588 3589 nqh = 1; 3590 nqtd = ((2 * xfer->nframes) 3591 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3592 3593 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3594 3595 parm->hc_max_packet_size = 0x3FF; 3596 parm->hc_max_packet_count = 1; 3597 parm->hc_max_frame_size = 0x3FF; 3598 xfer->flags_int.bdma_enable = 1; 3599 3600 usbd_transfer_setup_sub(parm); 3601 3602 nsitd = xfer->nframes; 3603 3604 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3605 3606 parm->hc_max_packet_size = 0x400; 3607 parm->hc_max_packet_count = 3; 3608 parm->hc_max_frame_size = 0xC00; 3609 xfer->flags_int.bdma_enable = 1; 3610 3611 usbd_transfer_setup_sub(parm); 3612 3613 nitd = ((xfer->nframes + 7) / 8) << 3614 usbd_xfer_get_fps_shift(xfer); 3615 3616 } else { 3617 3618 parm->hc_max_packet_size = 0x400; 3619 parm->hc_max_packet_count = 1; 3620 parm->hc_max_frame_size = 0x400; 3621 3622 usbd_transfer_setup_sub(parm); 3623 } 3624 3625 alloc_dma_set: 3626 3627 if (parm->err) { 3628 return; 3629 } 3630 /* 3631 * Allocate queue heads and transfer descriptors 3632 */ 3633 last_obj = NULL; 3634 3635 if (usbd_transfer_setup_sub_malloc( 3636 parm, &pc, sizeof(ehci_itd_t), 3637 EHCI_ITD_ALIGN, nitd)) { 3638 parm->err = USB_ERR_NOMEM; 3639 return; 3640 } 3641 if (parm->buf) { 3642 for (n = 0; n != nitd; n++) { 3643 ehci_itd_t *td; 3644 3645 usbd_get_page(pc + n, 0, &page_info); 3646 3647 td = page_info.buffer; 3648 3649 /* init TD */ 3650 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3651 td->obj_next = last_obj; 3652 td->page_cache = pc + n; 3653 3654 last_obj = td; 3655 3656 usb_pc_cpu_flush(pc + n); 3657 } 3658 } 3659 if (usbd_transfer_setup_sub_malloc( 3660 parm, &pc, sizeof(ehci_sitd_t), 3661 EHCI_SITD_ALIGN, nsitd)) { 3662 parm->err = USB_ERR_NOMEM; 3663 return; 3664 } 3665 if (parm->buf) { 3666 for (n = 0; n != nsitd; n++) { 3667 ehci_sitd_t *td; 3668 3669 usbd_get_page(pc + n, 0, &page_info); 3670 3671 td = page_info.buffer; 3672 3673 /* init TD */ 3674 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3675 td->obj_next = last_obj; 3676 td->page_cache = pc + n; 3677 3678 last_obj = td; 3679 3680 usb_pc_cpu_flush(pc + n); 3681 } 3682 } 3683 if (usbd_transfer_setup_sub_malloc( 3684 parm, &pc, sizeof(ehci_qtd_t), 3685 EHCI_QTD_ALIGN, nqtd)) { 3686 parm->err = USB_ERR_NOMEM; 3687 return; 3688 } 3689 if (parm->buf) { 3690 for (n = 0; n != nqtd; n++) { 3691 ehci_qtd_t *qtd; 3692 3693 usbd_get_page(pc + n, 0, &page_info); 3694 3695 qtd = page_info.buffer; 3696 3697 /* init TD */ 3698 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3699 qtd->obj_next = last_obj; 3700 qtd->page_cache = pc + n; 3701 3702 last_obj = qtd; 3703 3704 usb_pc_cpu_flush(pc + n); 3705 } 3706 } 3707 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3708 3709 last_obj = NULL; 3710 3711 if (usbd_transfer_setup_sub_malloc( 3712 parm, &pc, sizeof(ehci_qh_t), 3713 EHCI_QH_ALIGN, nqh)) { 3714 parm->err = USB_ERR_NOMEM; 3715 return; 3716 } 3717 if (parm->buf) { 3718 for (n = 0; n != nqh; n++) { 3719 ehci_qh_t *qh; 3720 3721 usbd_get_page(pc + n, 0, &page_info); 3722 3723 qh = page_info.buffer; 3724 3725 /* init QH */ 3726 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3727 qh->obj_next = last_obj; 3728 qh->page_cache = pc + n; 3729 3730 last_obj = qh; 3731 3732 usb_pc_cpu_flush(pc + n); 3733 } 3734 } 3735 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3736 3737 if (!xfer->flags_int.curr_dma_set) { 3738 xfer->flags_int.curr_dma_set = 1; 3739 goto alloc_dma_set; 3740 } 3741 } 3742 3743 static void 3744 ehci_xfer_unsetup(struct usb_xfer *xfer) 3745 { 3746 return; 3747 } 3748 3749 static void 3750 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3751 struct usb_endpoint *ep) 3752 { 3753 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3754 3755 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3756 ep, udev->address, 3757 edesc->bEndpointAddress, udev->flags.usb_mode, 3758 sc->sc_addr); 3759 3760 if (udev->device_index != sc->sc_addr) { 3761 3762 if ((udev->speed != USB_SPEED_HIGH) && 3763 ((udev->hs_hub_addr == 0) || 3764 (udev->hs_port_no == 0) || 3765 (udev->parent_hs_hub == NULL) || 3766 (udev->parent_hs_hub->hub == NULL))) { 3767 /* We need a transaction translator */ 3768 goto done; 3769 } 3770 switch (edesc->bmAttributes & UE_XFERTYPE) { 3771 case UE_CONTROL: 3772 ep->methods = &ehci_device_ctrl_methods; 3773 break; 3774 case UE_INTERRUPT: 3775 ep->methods = &ehci_device_intr_methods; 3776 break; 3777 case UE_ISOCHRONOUS: 3778 if (udev->speed == USB_SPEED_HIGH) { 3779 ep->methods = &ehci_device_isoc_hs_methods; 3780 } else if (udev->speed == USB_SPEED_FULL) { 3781 ep->methods = &ehci_device_isoc_fs_methods; 3782 } 3783 break; 3784 case UE_BULK: 3785 ep->methods = &ehci_device_bulk_methods; 3786 break; 3787 default: 3788 /* do nothing */ 3789 break; 3790 } 3791 } 3792 done: 3793 return; 3794 } 3795 3796 static void 3797 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3798 { 3799 /* 3800 * Wait until the hardware has finished any possible use of 3801 * the transfer descriptor(s) and QH 3802 */ 3803 *pus = (1125); /* microseconds */ 3804 } 3805 3806 static void 3807 ehci_device_resume(struct usb_device *udev) 3808 { 3809 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3810 struct usb_xfer *xfer; 3811 const struct usb_pipe_methods *methods; 3812 3813 DPRINTF("\n"); 3814 3815 USB_BUS_LOCK(udev->bus); 3816 3817 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3818 3819 if (xfer->xroot->udev == udev) { 3820 3821 methods = xfer->endpoint->methods; 3822 3823 if ((methods == &ehci_device_bulk_methods) || 3824 (methods == &ehci_device_ctrl_methods)) { 3825 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3826 sc->sc_async_p_last); 3827 } 3828 if (methods == &ehci_device_intr_methods) { 3829 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3830 sc->sc_intr_p_last[xfer->qh_pos]); 3831 } 3832 } 3833 } 3834 3835 USB_BUS_UNLOCK(udev->bus); 3836 3837 return; 3838 } 3839 3840 static void 3841 ehci_device_suspend(struct usb_device *udev) 3842 { 3843 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3844 struct usb_xfer *xfer; 3845 const struct usb_pipe_methods *methods; 3846 3847 DPRINTF("\n"); 3848 3849 USB_BUS_LOCK(udev->bus); 3850 3851 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3852 3853 if (xfer->xroot->udev == udev) { 3854 3855 methods = xfer->endpoint->methods; 3856 3857 if ((methods == &ehci_device_bulk_methods) || 3858 (methods == &ehci_device_ctrl_methods)) { 3859 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3860 sc->sc_async_p_last); 3861 } 3862 if (methods == &ehci_device_intr_methods) { 3863 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3864 sc->sc_intr_p_last[xfer->qh_pos]); 3865 } 3866 } 3867 } 3868 3869 USB_BUS_UNLOCK(udev->bus); 3870 } 3871 3872 static void 3873 ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3874 { 3875 struct ehci_softc *sc = EHCI_BUS2SC(bus); 3876 3877 switch (state) { 3878 case USB_HW_POWER_SUSPEND: 3879 case USB_HW_POWER_SHUTDOWN: 3880 ehci_suspend(sc); 3881 break; 3882 case USB_HW_POWER_RESUME: 3883 ehci_resume(sc); 3884 break; 3885 default: 3886 break; 3887 } 3888 } 3889 3890 static void 3891 ehci_set_hw_power(struct usb_bus *bus) 3892 { 3893 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3894 uint32_t temp; 3895 uint32_t flags; 3896 3897 DPRINTF("\n"); 3898 3899 USB_BUS_LOCK(bus); 3900 3901 flags = bus->hw_power_state; 3902 3903 temp = EOREAD4(sc, EHCI_USBCMD); 3904 3905 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3906 3907 if (flags & (USB_HW_POWER_CONTROL | 3908 USB_HW_POWER_BULK)) { 3909 DPRINTF("Async is active\n"); 3910 temp |= EHCI_CMD_ASE; 3911 } 3912 if (flags & (USB_HW_POWER_INTERRUPT | 3913 USB_HW_POWER_ISOC)) { 3914 DPRINTF("Periodic is active\n"); 3915 temp |= EHCI_CMD_PSE; 3916 } 3917 EOWRITE4(sc, EHCI_USBCMD, temp); 3918 3919 USB_BUS_UNLOCK(bus); 3920 3921 return; 3922 } 3923 3924 static void 3925 ehci_start_dma_delay_second(struct usb_xfer *xfer) 3926 { 3927 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3928 3929 DPRINTF("\n"); 3930 3931 /* trigger doorbell */ 3932 ehci_doorbell_async(sc); 3933 3934 /* give the doorbell 4ms */ 3935 usbd_transfer_timeout_ms(xfer, 3936 (void (*)(void *))&usb_dma_delay_done_cb, 4); 3937 } 3938 3939 /* 3940 * Ring the doorbell twice before freeing any DMA descriptors. Some host 3941 * controllers apparently cache the QH descriptors and need a message 3942 * that the cache needs to be discarded. 3943 */ 3944 static void 3945 ehci_start_dma_delay(struct usb_xfer *xfer) 3946 { 3947 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3948 3949 DPRINTF("\n"); 3950 3951 /* trigger doorbell */ 3952 ehci_doorbell_async(sc); 3953 3954 /* give the doorbell 4ms */ 3955 usbd_transfer_timeout_ms(xfer, 3956 (void (*)(void *))&ehci_start_dma_delay_second, 4); 3957 } 3958 3959 static const struct usb_bus_methods ehci_bus_methods = 3960 { 3961 .endpoint_init = ehci_ep_init, 3962 .xfer_setup = ehci_xfer_setup, 3963 .xfer_unsetup = ehci_xfer_unsetup, 3964 .get_dma_delay = ehci_get_dma_delay, 3965 .device_resume = ehci_device_resume, 3966 .device_suspend = ehci_device_suspend, 3967 .set_hw_power = ehci_set_hw_power, 3968 .set_hw_power_sleep = ehci_set_hw_power_sleep, 3969 .roothub_exec = ehci_roothub_exec, 3970 .xfer_poll = ehci_do_poll, 3971 .start_dma_delay = ehci_start_dma_delay, 3972 }; 3973