1 /* $FreeBSD: head/sys/dev/usb/controller/uhci.c 278883 2015-02-17 07:52:50Z hselasky $ */ 2 /*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 5 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB Universal Host Controller driver. 31 * Handles e.g. PIIX3 and PIIX4. 32 * 33 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 34 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 35 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 36 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 37 */ 38 39 #include <sys/stdint.h> 40 #include <sys/param.h> 41 #include <sys/queue.h> 42 #include <sys/types.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/bus.h> 46 #include <sys/module.h> 47 #include <sys/lock.h> 48 #include <sys/condvar.h> 49 #include <sys/sysctl.h> 50 #include <sys/unistd.h> 51 #include <sys/callout.h> 52 #include <sys/malloc.h> 53 #include <sys/priv.h> 54 55 #include <bus/u4b/usb.h> 56 #include <bus/u4b/usbdi.h> 57 58 #define USB_DEBUG_VAR uhcidebug 59 60 #include <bus/u4b/usb_core.h> 61 #include <bus/u4b/usb_debug.h> 62 #include <bus/u4b/usb_busdma.h> 63 #include <bus/u4b/usb_process.h> 64 #include <bus/u4b/usb_transfer.h> 65 #include <bus/u4b/usb_device.h> 66 #include <bus/u4b/usb_hub.h> 67 #include <bus/u4b/usb_util.h> 68 69 #include <bus/u4b/usb_controller.h> 70 #include <bus/u4b/usb_bus.h> 71 #include <bus/u4b/controller/uhci.h> 72 #include <bus/u4b/controller/uhcireg.h> 73 74 #define alt_next next 75 #define UHCI_BUS2SC(bus) \ 76 ((uhci_softc_t *)(((uint8_t *)(bus)) - \ 77 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus)))) 78 79 #ifdef USB_DEBUG 80 static int uhcidebug = 0; 81 static int uhcinoloop = 0; 82 83 static SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci"); 84 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RW, 85 &uhcidebug, 0, "uhci debug level"); 86 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RW, 87 &uhcinoloop, 0, "uhci noloop"); 88 89 TUNABLE_INT("hw.usb.uhci.debug", &uhcidebug); 90 TUNABLE_INT("hw.usb.uhci.loop", &uhcinoloop); 91 92 static void uhci_dumpregs(uhci_softc_t *sc); 93 static void uhci_dump_tds(uhci_td_t *td); 94 95 #endif 96 97 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 98 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 99 #define UWRITE1(sc, r, x) \ 100 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 101 } while (/*CONSTCOND*/0) 102 #define UWRITE2(sc, r, x) \ 103 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 104 } while (/*CONSTCOND*/0) 105 #define UWRITE4(sc, r, x) \ 106 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 107 } while (/*CONSTCOND*/0) 108 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 109 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 110 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 111 112 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 113 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 114 115 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 116 117 #define UHCI_INTR_ENDPT 1 118 119 struct uhci_mem_layout { 120 121 struct usb_page_search buf_res; 122 struct usb_page_search fix_res; 123 124 struct usb_page_cache *buf_pc; 125 struct usb_page_cache *fix_pc; 126 127 uint32_t buf_offset; 128 129 uint16_t max_frame_size; 130 }; 131 132 struct uhci_std_temp { 133 134 struct uhci_mem_layout ml; 135 uhci_td_t *td; 136 uhci_td_t *td_next; 137 uint32_t average; 138 uint32_t td_status; 139 uint32_t td_token; 140 uint32_t len; 141 uint16_t max_frame_size; 142 uint8_t shortpkt; 143 uint8_t setup_alt_next; 144 uint8_t last_frame; 145 }; 146 147 static const struct usb_bus_methods uhci_bus_methods; 148 static const struct usb_pipe_methods uhci_device_bulk_methods; 149 static const struct usb_pipe_methods uhci_device_ctrl_methods; 150 static const struct usb_pipe_methods uhci_device_intr_methods; 151 static const struct usb_pipe_methods uhci_device_isoc_methods; 152 153 static uint8_t uhci_restart(uhci_softc_t *sc); 154 static void uhci_do_poll(struct usb_bus *); 155 static void uhci_device_done(struct usb_xfer *, usb_error_t); 156 static void uhci_transfer_intr_enqueue(struct usb_xfer *); 157 static void uhci_timeout(void *); 158 static uint8_t uhci_check_transfer(struct usb_xfer *); 159 static void uhci_root_intr(uhci_softc_t *sc); 160 161 void 162 uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 163 { 164 struct uhci_softc *sc = UHCI_BUS2SC(bus); 165 uint32_t i; 166 167 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 168 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 169 170 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 171 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 172 173 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 174 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 175 176 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 177 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 178 179 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 180 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 181 182 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 183 sizeof(uhci_td_t), UHCI_TD_ALIGN); 184 185 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 186 cb(bus, sc->sc_hw.isoc_start_pc + i, 187 sc->sc_hw.isoc_start_pg + i, 188 sizeof(uhci_td_t), UHCI_TD_ALIGN); 189 } 190 191 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 192 cb(bus, sc->sc_hw.intr_start_pc + i, 193 sc->sc_hw.intr_start_pg + i, 194 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 195 } 196 } 197 198 static void 199 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer) 200 { 201 ml->buf_pc = xfer->frbuffers + 0; 202 ml->fix_pc = xfer->buf_fixup; 203 204 ml->buf_offset = 0; 205 206 ml->max_frame_size = xfer->max_frame_size; 207 } 208 209 static void 210 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 211 { 212 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 213 214 if (ml->buf_res.length < td->len) { 215 216 /* need to do a fixup */ 217 218 usbd_get_page(ml->fix_pc, 0, &ml->fix_res); 219 220 td->td_buffer = htole32(ml->fix_res.physaddr); 221 222 /* 223 * The UHCI driver cannot handle 224 * page crossings, so a fixup is 225 * needed: 226 * 227 * +----+----+ - - - 228 * | YYY|Y | 229 * +----+----+ - - - 230 * \ \ 231 * \ \ 232 * +----+ 233 * |YYYY| (fixup) 234 * +----+ 235 */ 236 237 if ((td->td_token & htole32(UHCI_TD_PID)) == 238 htole32(UHCI_TD_PID_IN)) { 239 td->fix_pc = ml->fix_pc; 240 usb_pc_cpu_invalidate(ml->fix_pc); 241 242 } else { 243 td->fix_pc = NULL; 244 245 /* copy data to fixup location */ 246 247 usbd_copy_out(ml->buf_pc, ml->buf_offset, 248 ml->fix_res.buffer, td->len); 249 250 usb_pc_cpu_flush(ml->fix_pc); 251 } 252 253 /* prepare next fixup */ 254 255 ml->fix_pc++; 256 257 } else { 258 259 td->td_buffer = htole32(ml->buf_res.physaddr); 260 td->fix_pc = NULL; 261 } 262 263 /* prepare next data location */ 264 265 ml->buf_offset += td->len; 266 } 267 268 /* 269 * Return values: 270 * 0: Success 271 * Else: Failure 272 */ 273 static uint8_t 274 uhci_restart(uhci_softc_t *sc) 275 { 276 struct usb_page_search buf_res; 277 278 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 279 280 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) { 281 DPRINTFN(2, "Already started\n"); 282 return (0); 283 } 284 285 DPRINTFN(2, "Restarting\n"); 286 287 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 288 289 /* Reload fresh base address */ 290 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 291 292 /* 293 * Assume 64 byte packets at frame end and start HC controller: 294 */ 295 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 296 297 /* wait 10 milliseconds */ 298 299 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 100); 300 301 /* check that controller has started */ 302 303 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 304 DPRINTFN(2, "Failed\n"); 305 return (1); 306 } 307 return (0); 308 } 309 310 void 311 uhci_reset(uhci_softc_t *sc) 312 { 313 uint16_t n; 314 315 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 316 317 DPRINTF("resetting the HC\n"); 318 319 /* disable interrupts */ 320 321 UWRITE2(sc, UHCI_INTR, 0); 322 323 /* global reset */ 324 325 UHCICMD(sc, UHCI_CMD_GRESET); 326 327 /* wait */ 328 329 usb_pause_mtx(&sc->sc_bus.bus_lock, 330 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 331 332 /* terminate all transfers */ 333 334 UHCICMD(sc, UHCI_CMD_HCRESET); 335 336 /* the reset bit goes low when the controller is done */ 337 338 n = UHCI_RESET_TIMEOUT; 339 while (n--) { 340 /* wait one millisecond */ 341 342 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 1000); 343 344 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 345 goto done_1; 346 } 347 } 348 349 device_printf(sc->sc_bus.bdev, 350 "controller did not reset\n"); 351 352 done_1: 353 354 n = 10; 355 while (n--) { 356 /* wait one millisecond */ 357 358 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 1000); 359 360 /* check if HC is stopped */ 361 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 362 goto done_2; 363 } 364 } 365 366 device_printf(sc->sc_bus.bdev, 367 "controller did not stop\n"); 368 369 done_2: 370 371 /* reset frame number */ 372 UWRITE2(sc, UHCI_FRNUM, 0); 373 /* set default SOF value */ 374 UWRITE1(sc, UHCI_SOF, 0x40); 375 376 USB_BUS_UNLOCK(&sc->sc_bus); 377 378 /* stop root interrupt */ 379 if (sc->sc_didinit) 380 usb_callout_drain(&sc->sc_root_intr); 381 382 USB_BUS_LOCK(&sc->sc_bus); 383 } 384 385 static void 386 uhci_start(uhci_softc_t *sc) 387 { 388 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 389 390 DPRINTFN(2, "enabling\n"); 391 392 /* enable interrupts */ 393 394 UWRITE2(sc, UHCI_INTR, 395 (UHCI_INTR_TOCRCIE | 396 UHCI_INTR_RIE | 397 UHCI_INTR_IOCE | 398 UHCI_INTR_SPIE)); 399 400 if (uhci_restart(sc)) { 401 device_printf(sc->sc_bus.bdev, 402 "cannot start HC controller\n"); 403 } 404 405 /* start root interrupt */ 406 uhci_root_intr(sc); 407 } 408 409 static struct uhci_qh * 410 uhci_init_qh(struct usb_page_cache *pc) 411 { 412 struct usb_page_search buf_res; 413 struct uhci_qh *qh; 414 415 usbd_get_page(pc, 0, &buf_res); 416 417 qh = buf_res.buffer; 418 419 qh->qh_self = 420 htole32(buf_res.physaddr) | 421 htole32(UHCI_PTR_QH); 422 423 qh->page_cache = pc; 424 425 return (qh); 426 } 427 428 static struct uhci_td * 429 uhci_init_td(struct usb_page_cache *pc) 430 { 431 struct usb_page_search buf_res; 432 struct uhci_td *td; 433 434 usbd_get_page(pc, 0, &buf_res); 435 436 td = buf_res.buffer; 437 438 td->td_self = 439 htole32(buf_res.physaddr) | 440 htole32(UHCI_PTR_TD); 441 442 td->page_cache = pc; 443 444 return (td); 445 } 446 447 usb_error_t 448 uhci_init(uhci_softc_t *sc) 449 { 450 uint16_t bit; 451 uint16_t x; 452 uint16_t y; 453 454 DPRINTF("start\n"); 455 456 sc->sc_didinit = 1; 457 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_lock, 0); 458 459 #ifdef USB_DEBUG 460 if (uhcidebug > 2) { 461 uhci_dumpregs(sc); 462 } 463 #endif 464 /* 465 * Setup QH's 466 */ 467 sc->sc_ls_ctl_p_last = 468 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 469 470 sc->sc_fs_ctl_p_last = 471 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 472 473 sc->sc_bulk_p_last = 474 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 475 #if 0 476 sc->sc_reclaim_qh_p = 477 sc->sc_fs_ctl_p_last; 478 #else 479 /* setup reclaim looping point */ 480 sc->sc_reclaim_qh_p = 481 sc->sc_bulk_p_last; 482 #endif 483 484 sc->sc_last_qh_p = 485 uhci_init_qh(&sc->sc_hw.last_qh_pc); 486 487 sc->sc_last_td_p = 488 uhci_init_td(&sc->sc_hw.last_td_pc); 489 490 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 491 sc->sc_isoc_p_last[x] = 492 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 493 } 494 495 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 496 sc->sc_intr_p_last[x] = 497 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 498 } 499 500 /* 501 * the QHs are arranged to give poll intervals that are 502 * powers of 2 times 1ms 503 */ 504 bit = UHCI_IFRAMELIST_COUNT / 2; 505 while (bit) { 506 x = bit; 507 while (x & bit) { 508 uhci_qh_t *qh_x; 509 uhci_qh_t *qh_y; 510 511 y = (x ^ bit) | (bit / 2); 512 513 /* 514 * the next QH has half the poll interval 515 */ 516 qh_x = sc->sc_intr_p_last[x]; 517 qh_y = sc->sc_intr_p_last[y]; 518 519 qh_x->h_next = NULL; 520 qh_x->qh_h_next = qh_y->qh_self; 521 qh_x->e_next = NULL; 522 qh_x->qh_e_next = htole32(UHCI_PTR_T); 523 x++; 524 } 525 bit >>= 1; 526 } 527 528 if (1) { 529 uhci_qh_t *qh_ls; 530 uhci_qh_t *qh_intr; 531 532 qh_ls = sc->sc_ls_ctl_p_last; 533 qh_intr = sc->sc_intr_p_last[0]; 534 535 /* start QH for interrupt traffic */ 536 qh_intr->h_next = qh_ls; 537 qh_intr->qh_h_next = qh_ls->qh_self; 538 qh_intr->e_next = 0; 539 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 540 } 541 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 542 543 uhci_td_t *td_x; 544 uhci_qh_t *qh_intr; 545 546 td_x = sc->sc_isoc_p_last[x]; 547 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 548 549 /* start TD for isochronous traffic */ 550 td_x->next = NULL; 551 td_x->td_next = qh_intr->qh_self; 552 td_x->td_status = htole32(UHCI_TD_IOS); 553 td_x->td_token = htole32(0); 554 td_x->td_buffer = htole32(0); 555 } 556 557 if (1) { 558 uhci_qh_t *qh_ls; 559 uhci_qh_t *qh_fs; 560 561 qh_ls = sc->sc_ls_ctl_p_last; 562 qh_fs = sc->sc_fs_ctl_p_last; 563 564 /* start QH where low speed control traffic will be queued */ 565 qh_ls->h_next = qh_fs; 566 qh_ls->qh_h_next = qh_fs->qh_self; 567 qh_ls->e_next = 0; 568 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 569 } 570 if (1) { 571 uhci_qh_t *qh_ctl; 572 uhci_qh_t *qh_blk; 573 uhci_qh_t *qh_lst; 574 uhci_td_t *td_lst; 575 576 qh_ctl = sc->sc_fs_ctl_p_last; 577 qh_blk = sc->sc_bulk_p_last; 578 579 /* start QH where full speed control traffic will be queued */ 580 qh_ctl->h_next = qh_blk; 581 qh_ctl->qh_h_next = qh_blk->qh_self; 582 qh_ctl->e_next = 0; 583 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 584 585 qh_lst = sc->sc_last_qh_p; 586 587 /* start QH where bulk traffic will be queued */ 588 qh_blk->h_next = qh_lst; 589 qh_blk->qh_h_next = qh_lst->qh_self; 590 qh_blk->e_next = 0; 591 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 592 593 td_lst = sc->sc_last_td_p; 594 595 /* end QH which is used for looping the QHs */ 596 qh_lst->h_next = 0; 597 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 598 qh_lst->e_next = td_lst; 599 qh_lst->qh_e_next = td_lst->td_self; 600 601 /* 602 * end TD which hangs from the last QH, to avoid a bug in the PIIX 603 * that makes it run berserk otherwise 604 */ 605 td_lst->next = 0; 606 td_lst->td_next = htole32(UHCI_PTR_T); 607 td_lst->td_status = htole32(0); /* inactive */ 608 td_lst->td_token = htole32(0); 609 td_lst->td_buffer = htole32(0); 610 } 611 if (1) { 612 struct usb_page_search buf_res; 613 uint32_t *pframes; 614 615 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 616 617 pframes = buf_res.buffer; 618 619 620 /* 621 * Setup UHCI framelist 622 * 623 * Execution order: 624 * 625 * pframes -> full speed isochronous -> interrupt QH's -> low 626 * speed control -> full speed control -> bulk transfers 627 * 628 */ 629 630 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 631 pframes[x] = 632 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 633 } 634 } 635 /* flush all cache into memory */ 636 637 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 638 639 /* set up the bus struct */ 640 sc->sc_bus.methods = &uhci_bus_methods; 641 642 USB_BUS_LOCK(&sc->sc_bus); 643 /* reset the controller */ 644 uhci_reset(sc); 645 646 /* start the controller */ 647 uhci_start(sc); 648 USB_BUS_UNLOCK(&sc->sc_bus); 649 650 /* catch lost interrupts */ 651 uhci_do_poll(&sc->sc_bus); 652 653 return (0); 654 } 655 656 static void 657 uhci_suspend(uhci_softc_t *sc) 658 { 659 #ifdef USB_DEBUG 660 if (uhcidebug > 2) { 661 uhci_dumpregs(sc); 662 } 663 #endif 664 665 USB_BUS_LOCK(&sc->sc_bus); 666 667 /* stop the controller */ 668 669 uhci_reset(sc); 670 671 /* enter global suspend */ 672 673 UHCICMD(sc, UHCI_CMD_EGSM); 674 675 USB_BUS_UNLOCK(&sc->sc_bus); 676 } 677 678 static void 679 uhci_resume(uhci_softc_t *sc) 680 { 681 USB_BUS_LOCK(&sc->sc_bus); 682 683 /* reset the controller */ 684 685 uhci_reset(sc); 686 687 /* force global resume */ 688 689 UHCICMD(sc, UHCI_CMD_FGR); 690 691 /* and start traffic again */ 692 693 uhci_start(sc); 694 695 USB_BUS_UNLOCK(&sc->sc_bus); 696 697 #ifdef USB_DEBUG 698 if (uhcidebug > 2) 699 uhci_dumpregs(sc); 700 #endif 701 702 /* catch lost interrupts */ 703 uhci_do_poll(&sc->sc_bus); 704 } 705 706 #ifdef USB_DEBUG 707 static void 708 uhci_dumpregs(uhci_softc_t *sc) 709 { 710 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 711 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 712 device_get_nameunit(sc->sc_bus.bdev), 713 UREAD2(sc, UHCI_CMD), 714 UREAD2(sc, UHCI_STS), 715 UREAD2(sc, UHCI_INTR), 716 UREAD2(sc, UHCI_FRNUM), 717 UREAD4(sc, UHCI_FLBASEADDR), 718 UREAD1(sc, UHCI_SOF), 719 UREAD2(sc, UHCI_PORTSC1), 720 UREAD2(sc, UHCI_PORTSC2)); 721 } 722 723 static uint8_t 724 uhci_dump_td(uhci_td_t *p) 725 { 726 uint32_t td_next; 727 uint32_t td_status; 728 uint32_t td_token; 729 uint8_t temp; 730 731 usb_pc_cpu_invalidate(p->page_cache); 732 733 td_next = le32toh(p->td_next); 734 td_status = le32toh(p->td_status); 735 td_token = le32toh(p->td_token); 736 737 /* 738 * Check whether the link pointer in this TD marks the link pointer 739 * as end of queue: 740 */ 741 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 742 743 kprintf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 744 "token=0x%08x buffer=0x%08x\n", 745 p, 746 le32toh(p->td_self), 747 td_next, 748 td_status, 749 td_token, 750 le32toh(p->td_buffer)); 751 752 kprintf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 753 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 754 p, 755 (td_next & 1) ? "-T" : "", 756 (td_next & 2) ? "-Q" : "", 757 (td_next & 4) ? "-VF" : "", 758 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 759 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 760 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 761 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 762 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 763 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 764 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 765 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 766 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 767 (td_status & UHCI_TD_LS) ? "-LS" : "", 768 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 769 UHCI_TD_GET_ERRCNT(td_status), 770 UHCI_TD_GET_ACTLEN(td_status), 771 UHCI_TD_GET_PID(td_token), 772 UHCI_TD_GET_DEVADDR(td_token), 773 UHCI_TD_GET_ENDPT(td_token), 774 UHCI_TD_GET_DT(td_token), 775 UHCI_TD_GET_MAXLEN(td_token)); 776 777 return (temp); 778 } 779 780 static uint8_t 781 uhci_dump_qh(uhci_qh_t *sqh) 782 { 783 uint8_t temp; 784 uint32_t qh_h_next; 785 uint32_t qh_e_next; 786 787 usb_pc_cpu_invalidate(sqh->page_cache); 788 789 qh_h_next = le32toh(sqh->qh_h_next); 790 qh_e_next = le32toh(sqh->qh_e_next); 791 792 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 793 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 794 795 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 796 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 797 798 return (temp); 799 } 800 801 static void 802 uhci_dump_all(uhci_softc_t *sc) 803 { 804 uhci_dumpregs(sc); 805 uhci_dump_qh(sc->sc_ls_ctl_p_last); 806 uhci_dump_qh(sc->sc_fs_ctl_p_last); 807 uhci_dump_qh(sc->sc_bulk_p_last); 808 uhci_dump_qh(sc->sc_last_qh_p); 809 } 810 811 static void 812 uhci_dump_tds(uhci_td_t *td) 813 { 814 for (; 815 td != NULL; 816 td = td->obj_next) { 817 if (uhci_dump_td(td)) { 818 break; 819 } 820 } 821 } 822 823 #endif 824 825 /* 826 * Let the last QH loop back to the full speed control transfer QH. 827 * This is what intel calls "bandwidth reclamation" and improves 828 * USB performance a lot for some devices. 829 * If we are already looping, just count it. 830 */ 831 static void 832 uhci_add_loop(uhci_softc_t *sc) 833 { 834 struct uhci_qh *qh_lst; 835 struct uhci_qh *qh_rec; 836 837 #ifdef USB_DEBUG 838 if (uhcinoloop) { 839 return; 840 } 841 #endif 842 if (++(sc->sc_loops) == 1) { 843 DPRINTFN(6, "add\n"); 844 845 qh_lst = sc->sc_last_qh_p; 846 qh_rec = sc->sc_reclaim_qh_p; 847 848 /* NOTE: we don't loop back the soft pointer */ 849 850 qh_lst->qh_h_next = qh_rec->qh_self; 851 usb_pc_cpu_flush(qh_lst->page_cache); 852 } 853 } 854 855 static void 856 uhci_rem_loop(uhci_softc_t *sc) 857 { 858 struct uhci_qh *qh_lst; 859 860 #ifdef USB_DEBUG 861 if (uhcinoloop) { 862 return; 863 } 864 #endif 865 if (--(sc->sc_loops) == 0) { 866 DPRINTFN(6, "remove\n"); 867 868 qh_lst = sc->sc_last_qh_p; 869 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 870 usb_pc_cpu_flush(qh_lst->page_cache); 871 } 872 } 873 874 static void 875 uhci_transfer_intr_enqueue(struct usb_xfer *xfer) 876 { 877 /* check for early completion */ 878 if (uhci_check_transfer(xfer)) { 879 return; 880 } 881 /* put transfer on interrupt queue */ 882 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 883 884 /* start timeout, if any */ 885 if (xfer->timeout != 0) { 886 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 887 } 888 } 889 890 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 891 static uhci_td_t * 892 _uhci_append_td(uhci_td_t *std, uhci_td_t *last) 893 { 894 DPRINTFN(11, "%p to %p\n", std, last); 895 896 /* (sc->sc_bus.lock) must be locked */ 897 898 std->next = last->next; 899 std->td_next = last->td_next; 900 901 std->prev = last; 902 903 usb_pc_cpu_flush(std->page_cache); 904 905 /* 906 * the last->next->prev is never followed: std->next->prev = std; 907 */ 908 last->next = std; 909 last->td_next = std->td_self; 910 911 usb_pc_cpu_flush(last->page_cache); 912 913 return (std); 914 } 915 916 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last) 917 static uhci_qh_t * 918 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last) 919 { 920 DPRINTFN(11, "%p to %p\n", sqh, last); 921 922 if (sqh->h_prev != NULL) { 923 /* should not happen */ 924 DPRINTFN(0, "QH already linked!\n"); 925 return (last); 926 } 927 /* (sc->sc_bus.lock) must be locked */ 928 929 sqh->h_next = last->h_next; 930 sqh->qh_h_next = last->qh_h_next; 931 932 sqh->h_prev = last; 933 934 usb_pc_cpu_flush(sqh->page_cache); 935 936 /* 937 * The "last->h_next->h_prev" is never followed: 938 * 939 * "sqh->h_next->h_prev" = sqh; 940 */ 941 942 last->h_next = sqh; 943 last->qh_h_next = sqh->qh_self; 944 945 usb_pc_cpu_flush(last->page_cache); 946 947 return (sqh); 948 } 949 950 /**/ 951 952 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 953 static uhci_td_t * 954 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 955 { 956 DPRINTFN(11, "%p from %p\n", std, last); 957 958 /* (sc->sc_bus.lock) must be locked */ 959 960 std->prev->next = std->next; 961 std->prev->td_next = std->td_next; 962 963 usb_pc_cpu_flush(std->prev->page_cache); 964 965 if (std->next) { 966 std->next->prev = std->prev; 967 usb_pc_cpu_flush(std->next->page_cache); 968 } 969 return ((last == std) ? std->prev : last); 970 } 971 972 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 973 static uhci_qh_t * 974 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 975 { 976 DPRINTFN(11, "%p from %p\n", sqh, last); 977 978 /* (sc->sc_bus.lock) must be locked */ 979 980 /* only remove if not removed from a queue */ 981 if (sqh->h_prev) { 982 983 sqh->h_prev->h_next = sqh->h_next; 984 sqh->h_prev->qh_h_next = sqh->qh_h_next; 985 986 usb_pc_cpu_flush(sqh->h_prev->page_cache); 987 988 if (sqh->h_next) { 989 sqh->h_next->h_prev = sqh->h_prev; 990 usb_pc_cpu_flush(sqh->h_next->page_cache); 991 } 992 last = ((last == sqh) ? sqh->h_prev : last); 993 994 sqh->h_prev = 0; 995 996 usb_pc_cpu_flush(sqh->page_cache); 997 } 998 return (last); 999 } 1000 1001 static void 1002 uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer) 1003 { 1004 struct usb_page_search res; 1005 uint32_t nframes = xfer->nframes; 1006 uint32_t status; 1007 uint32_t offset = 0; 1008 uint32_t *plen = xfer->frlengths; 1009 uint16_t len = 0; 1010 uhci_td_t *td = xfer->td_transfer_first; 1011 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1012 1013 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1014 xfer, xfer->endpoint); 1015 1016 /* sync any DMA memory before doing fixups */ 1017 1018 usb_bdma_post_sync(xfer); 1019 1020 while (nframes--) { 1021 if (td == NULL) { 1022 panic("%s:%d: out of TD's\n", 1023 __func__, __LINE__); 1024 } 1025 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1026 pp_last = &sc->sc_isoc_p_last[0]; 1027 } 1028 #ifdef USB_DEBUG 1029 if (uhcidebug > 5) { 1030 DPRINTF("isoc TD\n"); 1031 uhci_dump_td(td); 1032 } 1033 #endif 1034 usb_pc_cpu_invalidate(td->page_cache); 1035 status = le32toh(td->td_status); 1036 1037 len = UHCI_TD_GET_ACTLEN(status); 1038 1039 if (len > *plen) { 1040 len = *plen; 1041 } 1042 if (td->fix_pc) { 1043 1044 usbd_get_page(td->fix_pc, 0, &res); 1045 1046 /* copy data from fixup location to real location */ 1047 1048 usb_pc_cpu_invalidate(td->fix_pc); 1049 1050 usbd_copy_in(xfer->frbuffers, offset, 1051 res.buffer, len); 1052 } 1053 offset += *plen; 1054 1055 *plen = len; 1056 1057 /* remove TD from schedule */ 1058 UHCI_REMOVE_TD(td, *pp_last); 1059 1060 pp_last++; 1061 plen++; 1062 td = td->obj_next; 1063 } 1064 1065 xfer->aframes = xfer->nframes; 1066 } 1067 1068 static usb_error_t 1069 uhci_non_isoc_done_sub(struct usb_xfer *xfer) 1070 { 1071 struct usb_page_search res; 1072 uhci_td_t *td; 1073 uhci_td_t *td_alt_next; 1074 uint32_t status; 1075 uint32_t token; 1076 uint16_t len; 1077 1078 td = xfer->td_transfer_cache; 1079 td_alt_next = td->alt_next; 1080 1081 if (xfer->aframes != xfer->nframes) { 1082 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1083 } 1084 while (1) { 1085 1086 usb_pc_cpu_invalidate(td->page_cache); 1087 status = le32toh(td->td_status); 1088 token = le32toh(td->td_token); 1089 1090 /* 1091 * Verify the status and add 1092 * up the actual length: 1093 */ 1094 1095 len = UHCI_TD_GET_ACTLEN(status); 1096 if (len > td->len) { 1097 /* should not happen */ 1098 DPRINTF("Invalid status length, " 1099 "0x%04x/0x%04x bytes\n", len, td->len); 1100 status |= UHCI_TD_STALLED; 1101 1102 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1103 1104 if (td->fix_pc) { 1105 1106 usbd_get_page(td->fix_pc, 0, &res); 1107 1108 /* 1109 * copy data from fixup location to real 1110 * location 1111 */ 1112 1113 usb_pc_cpu_invalidate(td->fix_pc); 1114 1115 usbd_copy_in(xfer->frbuffers + xfer->aframes, 1116 xfer->frlengths[xfer->aframes], res.buffer, len); 1117 } 1118 /* update actual length */ 1119 1120 xfer->frlengths[xfer->aframes] += len; 1121 } 1122 /* Check for last transfer */ 1123 if (((void *)td) == xfer->td_transfer_last) { 1124 td = NULL; 1125 break; 1126 } 1127 if (status & UHCI_TD_STALLED) { 1128 /* the transfer is finished */ 1129 td = NULL; 1130 break; 1131 } 1132 /* Check for short transfer */ 1133 if (len != td->len) { 1134 if (xfer->flags_int.short_frames_ok) { 1135 /* follow alt next */ 1136 td = td->alt_next; 1137 } else { 1138 /* the transfer is finished */ 1139 td = NULL; 1140 } 1141 break; 1142 } 1143 td = td->obj_next; 1144 1145 if (td->alt_next != td_alt_next) { 1146 /* this USB frame is complete */ 1147 break; 1148 } 1149 } 1150 1151 /* update transfer cache */ 1152 1153 xfer->td_transfer_cache = td; 1154 1155 /* update data toggle */ 1156 1157 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1158 1159 #ifdef USB_DEBUG 1160 if (status & UHCI_TD_ERROR) { 1161 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1162 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1163 xfer->address, xfer->endpointno, xfer->aframes, 1164 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1165 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1166 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1167 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1168 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1169 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1170 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1171 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1172 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1173 (status & UHCI_TD_LS) ? "[LS]" : "", 1174 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1175 } 1176 #endif 1177 if (status & UHCI_TD_STALLED) { 1178 /* try to separate I/O errors from STALL */ 1179 if (UHCI_TD_GET_ERRCNT(status) == 0) 1180 return (USB_ERR_IOERROR); 1181 return (USB_ERR_STALLED); 1182 } 1183 return (USB_ERR_NORMAL_COMPLETION); 1184 } 1185 1186 static void 1187 uhci_non_isoc_done(struct usb_xfer *xfer) 1188 { 1189 usb_error_t err = 0; 1190 1191 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1192 xfer, xfer->endpoint); 1193 1194 #ifdef USB_DEBUG 1195 if (uhcidebug > 10) { 1196 uhci_dump_tds(xfer->td_transfer_first); 1197 } 1198 #endif 1199 1200 /* sync any DMA memory before doing fixups */ 1201 1202 usb_bdma_post_sync(xfer); 1203 1204 /* reset scanner */ 1205 1206 xfer->td_transfer_cache = xfer->td_transfer_first; 1207 1208 if (xfer->flags_int.control_xfr) { 1209 if (xfer->flags_int.control_hdr) { 1210 1211 err = uhci_non_isoc_done_sub(xfer); 1212 } 1213 xfer->aframes = 1; 1214 1215 if (xfer->td_transfer_cache == NULL) { 1216 goto done; 1217 } 1218 } 1219 while (xfer->aframes != xfer->nframes) { 1220 1221 err = uhci_non_isoc_done_sub(xfer); 1222 xfer->aframes++; 1223 1224 if (xfer->td_transfer_cache == NULL) { 1225 goto done; 1226 } 1227 } 1228 1229 if (xfer->flags_int.control_xfr && 1230 !xfer->flags_int.control_act) { 1231 1232 err = uhci_non_isoc_done_sub(xfer); 1233 } 1234 done: 1235 uhci_device_done(xfer, err); 1236 } 1237 1238 /*------------------------------------------------------------------------* 1239 * uhci_check_transfer_sub 1240 * 1241 * The main purpose of this function is to update the data-toggle 1242 * in case it is wrong. 1243 *------------------------------------------------------------------------*/ 1244 static void 1245 uhci_check_transfer_sub(struct usb_xfer *xfer) 1246 { 1247 uhci_qh_t *qh; 1248 uhci_td_t *td; 1249 uhci_td_t *td_alt_next; 1250 1251 uint32_t td_token; 1252 uint32_t td_self; 1253 1254 td = xfer->td_transfer_cache; 1255 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1256 1257 td_token = td->obj_next->td_token; 1258 td = td->alt_next; 1259 xfer->td_transfer_cache = td; 1260 td_self = td->td_self; 1261 td_alt_next = td->alt_next; 1262 1263 if (xfer->flags_int.control_xfr) 1264 goto skip; /* don't touch the DT value! */ 1265 1266 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1)))) 1267 goto skip; /* data toggle has correct value */ 1268 1269 /* 1270 * The data toggle is wrong and we need to toggle it ! 1271 */ 1272 while (1) { 1273 1274 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1275 usb_pc_cpu_flush(td->page_cache); 1276 1277 if (td == xfer->td_transfer_last) { 1278 /* last transfer */ 1279 break; 1280 } 1281 td = td->obj_next; 1282 1283 if (td->alt_next != td_alt_next) { 1284 /* next frame */ 1285 break; 1286 } 1287 } 1288 skip: 1289 1290 /* update the QH */ 1291 qh->qh_e_next = td_self; 1292 usb_pc_cpu_flush(qh->page_cache); 1293 1294 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1295 } 1296 1297 /*------------------------------------------------------------------------* 1298 * uhci_check_transfer 1299 * 1300 * Return values: 1301 * 0: USB transfer is not finished 1302 * Else: USB transfer is finished 1303 *------------------------------------------------------------------------*/ 1304 static uint8_t 1305 uhci_check_transfer(struct usb_xfer *xfer) 1306 { 1307 uint32_t status; 1308 uint32_t token; 1309 uhci_td_t *td; 1310 1311 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1312 1313 if (xfer->endpoint->methods == &uhci_device_isoc_methods) { 1314 /* isochronous transfer */ 1315 1316 td = xfer->td_transfer_last; 1317 1318 usb_pc_cpu_invalidate(td->page_cache); 1319 status = le32toh(td->td_status); 1320 1321 /* check also if the first is complete */ 1322 1323 td = xfer->td_transfer_first; 1324 1325 usb_pc_cpu_invalidate(td->page_cache); 1326 status |= le32toh(td->td_status); 1327 1328 if (!(status & UHCI_TD_ACTIVE)) { 1329 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1330 goto transferred; 1331 } 1332 } else { 1333 /* non-isochronous transfer */ 1334 1335 /* 1336 * check whether there is an error somewhere 1337 * in the middle, or whether there was a short 1338 * packet (SPD and not ACTIVE) 1339 */ 1340 td = xfer->td_transfer_cache; 1341 1342 while (1) { 1343 usb_pc_cpu_invalidate(td->page_cache); 1344 status = le32toh(td->td_status); 1345 token = le32toh(td->td_token); 1346 1347 /* 1348 * if there is an active TD the transfer isn't done 1349 */ 1350 if (status & UHCI_TD_ACTIVE) { 1351 /* update cache */ 1352 xfer->td_transfer_cache = td; 1353 goto done; 1354 } 1355 /* 1356 * last transfer descriptor makes the transfer done 1357 */ 1358 if (((void *)td) == xfer->td_transfer_last) { 1359 break; 1360 } 1361 /* 1362 * any kind of error makes the transfer done 1363 */ 1364 if (status & UHCI_TD_STALLED) { 1365 break; 1366 } 1367 /* 1368 * check if we reached the last packet 1369 * or if there is a short packet: 1370 */ 1371 if ((td->td_next == htole32(UHCI_PTR_T)) || 1372 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1373 1374 if (xfer->flags_int.short_frames_ok) { 1375 /* follow alt next */ 1376 if (td->alt_next) { 1377 /* update cache */ 1378 xfer->td_transfer_cache = td; 1379 uhci_check_transfer_sub(xfer); 1380 goto done; 1381 } 1382 } 1383 /* transfer is done */ 1384 break; 1385 } 1386 td = td->obj_next; 1387 } 1388 uhci_non_isoc_done(xfer); 1389 goto transferred; 1390 } 1391 1392 done: 1393 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1394 return (0); 1395 1396 transferred: 1397 return (1); 1398 } 1399 1400 static void 1401 uhci_interrupt_poll(uhci_softc_t *sc) 1402 { 1403 struct usb_xfer *xfer; 1404 1405 repeat: 1406 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1407 /* 1408 * check if transfer is transferred 1409 */ 1410 if (uhci_check_transfer(xfer)) { 1411 /* queue has been modified */ 1412 goto repeat; 1413 } 1414 } 1415 } 1416 1417 /*------------------------------------------------------------------------* 1418 * uhci_interrupt - UHCI interrupt handler 1419 * 1420 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1421 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1422 * is present ! 1423 *------------------------------------------------------------------------*/ 1424 void 1425 uhci_interrupt(uhci_softc_t *sc) 1426 { 1427 uint32_t status; 1428 1429 USB_BUS_LOCK(&sc->sc_bus); 1430 1431 DPRINTFN(16, "real interrupt\n"); 1432 1433 #ifdef USB_DEBUG 1434 if (uhcidebug > 15) { 1435 uhci_dumpregs(sc); 1436 } 1437 #endif 1438 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1439 if (status == 0) { 1440 /* the interrupt was not for us */ 1441 goto done; 1442 } 1443 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1444 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1445 1446 if (status & UHCI_STS_RD) { 1447 #ifdef USB_DEBUG 1448 kprintf("%s: resume detect\n", 1449 __func__); 1450 #endif 1451 } 1452 if (status & UHCI_STS_HSE) { 1453 kprintf("%s: host system error\n", 1454 __func__); 1455 } 1456 if (status & UHCI_STS_HCPE) { 1457 kprintf("%s: host controller process error\n", 1458 __func__); 1459 } 1460 if (status & UHCI_STS_HCH) { 1461 /* no acknowledge needed */ 1462 DPRINTF("%s: host controller halted\n", 1463 __func__); 1464 #ifdef USB_DEBUG 1465 if (uhcidebug > 0) { 1466 uhci_dump_all(sc); 1467 } 1468 #endif 1469 } 1470 } 1471 /* get acknowledge bits */ 1472 status &= (UHCI_STS_USBINT | 1473 UHCI_STS_USBEI | 1474 UHCI_STS_RD | 1475 UHCI_STS_HSE | 1476 UHCI_STS_HCPE | 1477 UHCI_STS_HCH); 1478 1479 if (status == 0) { 1480 /* nothing to acknowledge */ 1481 goto done; 1482 } 1483 /* acknowledge interrupts */ 1484 UWRITE2(sc, UHCI_STS, status); 1485 1486 /* poll all the USB transfers */ 1487 uhci_interrupt_poll(sc); 1488 1489 done: 1490 USB_BUS_UNLOCK(&sc->sc_bus); 1491 } 1492 1493 /* 1494 * called when a request does not complete 1495 */ 1496 static void 1497 uhci_timeout(void *arg) 1498 { 1499 struct usb_xfer *xfer = arg; 1500 1501 DPRINTF("xfer=%p\n", xfer); 1502 1503 USB_BUS_LOCK_ASSERT(xfer->xroot->bus); 1504 1505 /* transfer is transferred */ 1506 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1507 } 1508 1509 static void 1510 uhci_do_poll(struct usb_bus *bus) 1511 { 1512 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1513 1514 USB_BUS_LOCK(&sc->sc_bus); 1515 uhci_interrupt_poll(sc); 1516 USB_BUS_UNLOCK(&sc->sc_bus); 1517 } 1518 1519 static void 1520 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1521 { 1522 uhci_td_t *td; 1523 uhci_td_t *td_next; 1524 uhci_td_t *td_alt_next; 1525 uint32_t average; 1526 uint32_t len_old; 1527 uint8_t shortpkt_old; 1528 uint8_t precompute; 1529 1530 td_alt_next = NULL; 1531 shortpkt_old = temp->shortpkt; 1532 len_old = temp->len; 1533 precompute = 1; 1534 1535 /* software is used to detect short incoming transfers */ 1536 1537 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1538 temp->td_status |= htole32(UHCI_TD_SPD); 1539 } else { 1540 temp->td_status &= ~htole32(UHCI_TD_SPD); 1541 } 1542 1543 temp->ml.buf_offset = 0; 1544 1545 restart: 1546 1547 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1548 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1549 1550 td = temp->td; 1551 td_next = temp->td_next; 1552 1553 while (1) { 1554 1555 if (temp->len == 0) { 1556 1557 if (temp->shortpkt) { 1558 break; 1559 } 1560 /* send a Zero Length Packet, ZLP, last */ 1561 1562 temp->shortpkt = 1; 1563 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1564 average = 0; 1565 1566 } else { 1567 1568 average = temp->average; 1569 1570 if (temp->len < average) { 1571 temp->shortpkt = 1; 1572 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1573 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1574 average = temp->len; 1575 } 1576 } 1577 1578 if (td_next == NULL) { 1579 panic("%s: out of UHCI transfer descriptors!", __func__); 1580 } 1581 /* get next TD */ 1582 1583 td = td_next; 1584 td_next = td->obj_next; 1585 1586 /* check if we are pre-computing */ 1587 1588 if (precompute) { 1589 1590 /* update remaining length */ 1591 1592 temp->len -= average; 1593 1594 continue; 1595 } 1596 /* fill out current TD */ 1597 1598 td->td_status = temp->td_status; 1599 td->td_token = temp->td_token; 1600 1601 /* update data toggle */ 1602 1603 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1604 1605 if (average == 0) { 1606 1607 td->len = 0; 1608 td->td_buffer = 0; 1609 td->fix_pc = NULL; 1610 1611 } else { 1612 1613 /* update remaining length */ 1614 1615 temp->len -= average; 1616 1617 td->len = average; 1618 1619 /* fill out buffer pointer and do fixup, if any */ 1620 1621 uhci_mem_layout_fixup(&temp->ml, td); 1622 } 1623 1624 td->alt_next = td_alt_next; 1625 1626 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1627 /* we need to receive these frames one by one ! */ 1628 td->td_status |= htole32(UHCI_TD_IOC); 1629 td->td_next = htole32(UHCI_PTR_T); 1630 } else { 1631 if (td_next) { 1632 /* link the current TD with the next one */ 1633 td->td_next = td_next->td_self; 1634 } 1635 } 1636 1637 usb_pc_cpu_flush(td->page_cache); 1638 } 1639 1640 if (precompute) { 1641 precompute = 0; 1642 1643 /* setup alt next pointer, if any */ 1644 if (temp->last_frame) { 1645 td_alt_next = NULL; 1646 } else { 1647 /* we use this field internally */ 1648 td_alt_next = td_next; 1649 } 1650 1651 /* restore */ 1652 temp->shortpkt = shortpkt_old; 1653 temp->len = len_old; 1654 goto restart; 1655 } 1656 temp->td = td; 1657 temp->td_next = td_next; 1658 } 1659 1660 static uhci_td_t * 1661 uhci_setup_standard_chain(struct usb_xfer *xfer) 1662 { 1663 struct uhci_std_temp temp; 1664 uhci_td_t *td; 1665 uint32_t x; 1666 1667 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1668 xfer->address, UE_GET_ADDR(xfer->endpointno), 1669 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1670 1671 temp.average = xfer->max_frame_size; 1672 temp.max_frame_size = xfer->max_frame_size; 1673 1674 /* toggle the DMA set we are using */ 1675 xfer->flags_int.curr_dma_set ^= 1; 1676 1677 /* get next DMA set */ 1678 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1679 xfer->td_transfer_first = td; 1680 xfer->td_transfer_cache = td; 1681 1682 temp.td = NULL; 1683 temp.td_next = td; 1684 temp.last_frame = 0; 1685 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1686 1687 uhci_mem_layout_init(&temp.ml, xfer); 1688 1689 temp.td_status = 1690 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1691 UHCI_TD_ACTIVE)); 1692 1693 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1694 temp.td_status |= htole32(UHCI_TD_LS); 1695 } 1696 temp.td_token = 1697 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) | 1698 UHCI_TD_SET_DEVADDR(xfer->address)); 1699 1700 if (xfer->endpoint->toggle_next) { 1701 /* DATA1 is next */ 1702 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1703 } 1704 /* check if we should prepend a setup message */ 1705 1706 if (xfer->flags_int.control_xfr) { 1707 1708 if (xfer->flags_int.control_hdr) { 1709 1710 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1711 UHCI_TD_SET_ENDPT(0xF)); 1712 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1713 UHCI_TD_SET_DT(0)); 1714 1715 temp.len = xfer->frlengths[0]; 1716 temp.ml.buf_pc = xfer->frbuffers + 0; 1717 temp.shortpkt = temp.len ? 1 : 0; 1718 /* check for last frame */ 1719 if (xfer->nframes == 1) { 1720 /* no STATUS stage yet, SETUP is last */ 1721 if (xfer->flags_int.control_act) { 1722 temp.last_frame = 1; 1723 temp.setup_alt_next = 0; 1724 } 1725 } 1726 uhci_setup_standard_chain_sub(&temp); 1727 } 1728 x = 1; 1729 } else { 1730 x = 0; 1731 } 1732 1733 while (x != xfer->nframes) { 1734 1735 /* DATA0 / DATA1 message */ 1736 1737 temp.len = xfer->frlengths[x]; 1738 temp.ml.buf_pc = xfer->frbuffers + x; 1739 1740 x++; 1741 1742 if (x == xfer->nframes) { 1743 if (xfer->flags_int.control_xfr) { 1744 /* no STATUS stage yet, DATA is last */ 1745 if (xfer->flags_int.control_act) { 1746 temp.last_frame = 1; 1747 temp.setup_alt_next = 0; 1748 } 1749 } else { 1750 temp.last_frame = 1; 1751 temp.setup_alt_next = 0; 1752 } 1753 } 1754 /* 1755 * Keep previous data toggle, 1756 * device address and endpoint number: 1757 */ 1758 1759 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1760 UHCI_TD_SET_ENDPT(0xF) | 1761 UHCI_TD_SET_DT(1)); 1762 1763 if (temp.len == 0) { 1764 1765 /* make sure that we send an USB packet */ 1766 1767 temp.shortpkt = 0; 1768 1769 } else { 1770 1771 /* regular data transfer */ 1772 1773 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1774 } 1775 1776 /* set endpoint direction */ 1777 1778 temp.td_token |= 1779 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1780 htole32(UHCI_TD_PID_IN) : 1781 htole32(UHCI_TD_PID_OUT); 1782 1783 uhci_setup_standard_chain_sub(&temp); 1784 } 1785 1786 /* check if we should append a status stage */ 1787 1788 if (xfer->flags_int.control_xfr && 1789 !xfer->flags_int.control_act) { 1790 1791 /* 1792 * send a DATA1 message and reverse the current endpoint 1793 * direction 1794 */ 1795 1796 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1797 UHCI_TD_SET_ENDPT(0xF) | 1798 UHCI_TD_SET_DT(1)); 1799 temp.td_token |= 1800 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1801 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1802 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1803 1804 temp.len = 0; 1805 temp.ml.buf_pc = NULL; 1806 temp.shortpkt = 0; 1807 temp.last_frame = 1; 1808 temp.setup_alt_next = 0; 1809 1810 uhci_setup_standard_chain_sub(&temp); 1811 } 1812 td = temp.td; 1813 1814 /* Ensure that last TD is terminating: */ 1815 td->td_next = htole32(UHCI_PTR_T); 1816 1817 /* set interrupt bit */ 1818 1819 td->td_status |= htole32(UHCI_TD_IOC); 1820 1821 usb_pc_cpu_flush(td->page_cache); 1822 1823 /* must have at least one frame! */ 1824 1825 xfer->td_transfer_last = td; 1826 1827 #ifdef USB_DEBUG 1828 if (uhcidebug > 8) { 1829 DPRINTF("nexttog=%d; data before transfer:\n", 1830 xfer->endpoint->toggle_next); 1831 uhci_dump_tds(xfer->td_transfer_first); 1832 } 1833 #endif 1834 return (xfer->td_transfer_first); 1835 } 1836 1837 /* NOTE: "done" can be run two times in a row, 1838 * from close and from interrupt 1839 */ 1840 1841 static void 1842 uhci_device_done(struct usb_xfer *xfer, usb_error_t error) 1843 { 1844 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1845 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1846 uhci_qh_t *qh; 1847 1848 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 1849 1850 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1851 xfer, xfer->endpoint, error); 1852 1853 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1854 if (qh) { 1855 usb_pc_cpu_invalidate(qh->page_cache); 1856 } 1857 if (xfer->flags_int.bandwidth_reclaimed) { 1858 xfer->flags_int.bandwidth_reclaimed = 0; 1859 uhci_rem_loop(sc); 1860 } 1861 if (methods == &uhci_device_bulk_methods) { 1862 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1863 } 1864 if (methods == &uhci_device_ctrl_methods) { 1865 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1866 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1867 } else { 1868 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1869 } 1870 } 1871 if (methods == &uhci_device_intr_methods) { 1872 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1873 } 1874 /* 1875 * Only finish isochronous transfers once 1876 * which will update "xfer->frlengths". 1877 */ 1878 if (xfer->td_transfer_first && 1879 xfer->td_transfer_last) { 1880 if (methods == &uhci_device_isoc_methods) { 1881 uhci_isoc_done(sc, xfer); 1882 } 1883 xfer->td_transfer_first = NULL; 1884 xfer->td_transfer_last = NULL; 1885 } 1886 /* dequeue transfer and start next transfer */ 1887 usbd_transfer_done(xfer, error); 1888 } 1889 1890 /*------------------------------------------------------------------------* 1891 * uhci bulk support 1892 *------------------------------------------------------------------------*/ 1893 static void 1894 uhci_device_bulk_open(struct usb_xfer *xfer) 1895 { 1896 return; 1897 } 1898 1899 static void 1900 uhci_device_bulk_close(struct usb_xfer *xfer) 1901 { 1902 uhci_device_done(xfer, USB_ERR_CANCELLED); 1903 } 1904 1905 static void 1906 uhci_device_bulk_enter(struct usb_xfer *xfer) 1907 { 1908 return; 1909 } 1910 1911 static void 1912 uhci_device_bulk_start(struct usb_xfer *xfer) 1913 { 1914 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1915 uhci_td_t *td; 1916 uhci_qh_t *qh; 1917 1918 /* setup TD's */ 1919 td = uhci_setup_standard_chain(xfer); 1920 1921 /* setup QH */ 1922 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1923 1924 qh->e_next = td; 1925 qh->qh_e_next = td->td_self; 1926 1927 if (xfer->xroot->udev->flags.self_suspended == 0) { 1928 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 1929 uhci_add_loop(sc); 1930 xfer->flags_int.bandwidth_reclaimed = 1; 1931 } else { 1932 usb_pc_cpu_flush(qh->page_cache); 1933 } 1934 1935 /* put transfer on interrupt queue */ 1936 uhci_transfer_intr_enqueue(xfer); 1937 } 1938 1939 static const struct usb_pipe_methods uhci_device_bulk_methods = 1940 { 1941 .open = uhci_device_bulk_open, 1942 .close = uhci_device_bulk_close, 1943 .enter = uhci_device_bulk_enter, 1944 .start = uhci_device_bulk_start, 1945 }; 1946 1947 /*------------------------------------------------------------------------* 1948 * uhci control support 1949 *------------------------------------------------------------------------*/ 1950 static void 1951 uhci_device_ctrl_open(struct usb_xfer *xfer) 1952 { 1953 return; 1954 } 1955 1956 static void 1957 uhci_device_ctrl_close(struct usb_xfer *xfer) 1958 { 1959 uhci_device_done(xfer, USB_ERR_CANCELLED); 1960 } 1961 1962 static void 1963 uhci_device_ctrl_enter(struct usb_xfer *xfer) 1964 { 1965 return; 1966 } 1967 1968 static void 1969 uhci_device_ctrl_start(struct usb_xfer *xfer) 1970 { 1971 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1972 uhci_qh_t *qh; 1973 uhci_td_t *td; 1974 1975 /* setup TD's */ 1976 td = uhci_setup_standard_chain(xfer); 1977 1978 /* setup QH */ 1979 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1980 1981 qh->e_next = td; 1982 qh->qh_e_next = td->td_self; 1983 1984 /* 1985 * NOTE: some devices choke on bandwidth- reclamation for control 1986 * transfers 1987 */ 1988 if (xfer->xroot->udev->flags.self_suspended == 0) { 1989 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1990 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 1991 } else { 1992 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 1993 } 1994 } else { 1995 usb_pc_cpu_flush(qh->page_cache); 1996 } 1997 /* put transfer on interrupt queue */ 1998 uhci_transfer_intr_enqueue(xfer); 1999 } 2000 2001 static const struct usb_pipe_methods uhci_device_ctrl_methods = 2002 { 2003 .open = uhci_device_ctrl_open, 2004 .close = uhci_device_ctrl_close, 2005 .enter = uhci_device_ctrl_enter, 2006 .start = uhci_device_ctrl_start, 2007 }; 2008 2009 /*------------------------------------------------------------------------* 2010 * uhci interrupt support 2011 *------------------------------------------------------------------------*/ 2012 static void 2013 uhci_device_intr_open(struct usb_xfer *xfer) 2014 { 2015 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2016 uint16_t best; 2017 uint16_t bit; 2018 uint16_t x; 2019 2020 best = 0; 2021 bit = UHCI_IFRAMELIST_COUNT / 2; 2022 while (bit) { 2023 if (xfer->interval >= bit) { 2024 x = bit; 2025 best = bit; 2026 while (x & bit) { 2027 if (sc->sc_intr_stat[x] < 2028 sc->sc_intr_stat[best]) { 2029 best = x; 2030 } 2031 x++; 2032 } 2033 break; 2034 } 2035 bit >>= 1; 2036 } 2037 2038 sc->sc_intr_stat[best]++; 2039 xfer->qh_pos = best; 2040 2041 DPRINTFN(3, "best=%d interval=%d\n", 2042 best, xfer->interval); 2043 } 2044 2045 static void 2046 uhci_device_intr_close(struct usb_xfer *xfer) 2047 { 2048 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2049 2050 sc->sc_intr_stat[xfer->qh_pos]--; 2051 2052 uhci_device_done(xfer, USB_ERR_CANCELLED); 2053 } 2054 2055 static void 2056 uhci_device_intr_enter(struct usb_xfer *xfer) 2057 { 2058 return; 2059 } 2060 2061 static void 2062 uhci_device_intr_start(struct usb_xfer *xfer) 2063 { 2064 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2065 uhci_qh_t *qh; 2066 uhci_td_t *td; 2067 2068 /* setup TD's */ 2069 td = uhci_setup_standard_chain(xfer); 2070 2071 /* setup QH */ 2072 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2073 2074 qh->e_next = td; 2075 qh->qh_e_next = td->td_self; 2076 2077 if (xfer->xroot->udev->flags.self_suspended == 0) { 2078 /* enter QHs into the controller data structures */ 2079 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 2080 } else { 2081 usb_pc_cpu_flush(qh->page_cache); 2082 } 2083 2084 /* put transfer on interrupt queue */ 2085 uhci_transfer_intr_enqueue(xfer); 2086 } 2087 2088 static const struct usb_pipe_methods uhci_device_intr_methods = 2089 { 2090 .open = uhci_device_intr_open, 2091 .close = uhci_device_intr_close, 2092 .enter = uhci_device_intr_enter, 2093 .start = uhci_device_intr_start, 2094 }; 2095 2096 /*------------------------------------------------------------------------* 2097 * uhci isochronous support 2098 *------------------------------------------------------------------------*/ 2099 static void 2100 uhci_device_isoc_open(struct usb_xfer *xfer) 2101 { 2102 uhci_td_t *td; 2103 uint32_t td_token; 2104 uint8_t ds; 2105 2106 td_token = 2107 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 2108 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) : 2109 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0); 2110 2111 td_token = htole32(td_token); 2112 2113 /* initialize all TD's */ 2114 2115 for (ds = 0; ds != 2; ds++) { 2116 2117 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2118 2119 /* mark TD as inactive */ 2120 td->td_status = htole32(UHCI_TD_IOS); 2121 td->td_token = td_token; 2122 2123 usb_pc_cpu_flush(td->page_cache); 2124 } 2125 } 2126 } 2127 2128 static void 2129 uhci_device_isoc_close(struct usb_xfer *xfer) 2130 { 2131 uhci_device_done(xfer, USB_ERR_CANCELLED); 2132 } 2133 2134 static void 2135 uhci_device_isoc_enter(struct usb_xfer *xfer) 2136 { 2137 struct uhci_mem_layout ml; 2138 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2139 uint32_t nframes; 2140 uint32_t temp; 2141 uint32_t *plen; 2142 2143 #ifdef USB_DEBUG 2144 uint8_t once = 1; 2145 2146 #endif 2147 uhci_td_t *td; 2148 uhci_td_t *td_last = NULL; 2149 uhci_td_t **pp_last; 2150 2151 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2152 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2153 2154 nframes = UREAD2(sc, UHCI_FRNUM); 2155 2156 temp = (nframes - xfer->endpoint->isoc_next) & 2157 (UHCI_VFRAMELIST_COUNT - 1); 2158 2159 if ((xfer->endpoint->is_synced == 0) || 2160 (temp < xfer->nframes)) { 2161 /* 2162 * If there is data underflow or the pipe queue is empty we 2163 * schedule the transfer a few frames ahead of the current 2164 * frame position. Else two isochronous transfers might 2165 * overlap. 2166 */ 2167 xfer->endpoint->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1); 2168 xfer->endpoint->is_synced = 1; 2169 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2170 } 2171 /* 2172 * compute how many milliseconds the insertion is ahead of the 2173 * current frame position: 2174 */ 2175 temp = (xfer->endpoint->isoc_next - nframes) & 2176 (UHCI_VFRAMELIST_COUNT - 1); 2177 2178 /* 2179 * pre-compute when the isochronous transfer will be finished: 2180 */ 2181 xfer->isoc_time_complete = 2182 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2183 xfer->nframes; 2184 2185 /* get the real number of frames */ 2186 2187 nframes = xfer->nframes; 2188 2189 uhci_mem_layout_init(&ml, xfer); 2190 2191 plen = xfer->frlengths; 2192 2193 /* toggle the DMA set we are using */ 2194 xfer->flags_int.curr_dma_set ^= 1; 2195 2196 /* get next DMA set */ 2197 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2198 xfer->td_transfer_first = td; 2199 2200 pp_last = &sc->sc_isoc_p_last[xfer->endpoint->isoc_next]; 2201 2202 /* store starting position */ 2203 2204 xfer->qh_pos = xfer->endpoint->isoc_next; 2205 2206 while (nframes--) { 2207 if (td == NULL) { 2208 panic("%s:%d: out of TD's\n", 2209 __func__, __LINE__); 2210 } 2211 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2212 pp_last = &sc->sc_isoc_p_last[0]; 2213 } 2214 if (*plen > xfer->max_frame_size) { 2215 #ifdef USB_DEBUG 2216 if (once) { 2217 once = 0; 2218 kprintf("%s: frame length(%d) exceeds %d " 2219 "bytes (frame truncated)\n", 2220 __func__, *plen, 2221 xfer->max_frame_size); 2222 } 2223 #endif 2224 *plen = xfer->max_frame_size; 2225 } 2226 /* reuse td_token from last transfer */ 2227 2228 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2229 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2230 2231 td->len = *plen; 2232 2233 if (td->len == 0) { 2234 /* 2235 * Do not call "uhci_mem_layout_fixup()" when the 2236 * length is zero! 2237 */ 2238 td->td_buffer = 0; 2239 td->fix_pc = NULL; 2240 2241 } else { 2242 2243 /* fill out buffer pointer and do fixup, if any */ 2244 2245 uhci_mem_layout_fixup(&ml, td); 2246 2247 } 2248 2249 /* update status */ 2250 if (nframes == 0) { 2251 td->td_status = htole32 2252 (UHCI_TD_ZERO_ACTLEN 2253 (UHCI_TD_SET_ERRCNT(0) | 2254 UHCI_TD_ACTIVE | 2255 UHCI_TD_IOS | 2256 UHCI_TD_IOC)); 2257 } else { 2258 td->td_status = htole32 2259 (UHCI_TD_ZERO_ACTLEN 2260 (UHCI_TD_SET_ERRCNT(0) | 2261 UHCI_TD_ACTIVE | 2262 UHCI_TD_IOS)); 2263 } 2264 2265 usb_pc_cpu_flush(td->page_cache); 2266 2267 #ifdef USB_DEBUG 2268 if (uhcidebug > 5) { 2269 DPRINTF("TD %d\n", nframes); 2270 uhci_dump_td(td); 2271 } 2272 #endif 2273 /* insert TD into schedule */ 2274 UHCI_APPEND_TD(td, *pp_last); 2275 pp_last++; 2276 2277 plen++; 2278 td_last = td; 2279 td = td->obj_next; 2280 } 2281 2282 xfer->td_transfer_last = td_last; 2283 2284 /* update isoc_next */ 2285 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) & 2286 (UHCI_VFRAMELIST_COUNT - 1); 2287 } 2288 2289 static void 2290 uhci_device_isoc_start(struct usb_xfer *xfer) 2291 { 2292 /* put transfer on interrupt queue */ 2293 uhci_transfer_intr_enqueue(xfer); 2294 } 2295 2296 static const struct usb_pipe_methods uhci_device_isoc_methods = 2297 { 2298 .open = uhci_device_isoc_open, 2299 .close = uhci_device_isoc_close, 2300 .enter = uhci_device_isoc_enter, 2301 .start = uhci_device_isoc_start, 2302 }; 2303 2304 /*------------------------------------------------------------------------* 2305 * uhci root control support 2306 *------------------------------------------------------------------------* 2307 * Simulate a hardware hub by handling all the necessary requests. 2308 *------------------------------------------------------------------------*/ 2309 2310 static const 2311 struct usb_device_descriptor uhci_devd = 2312 { 2313 sizeof(struct usb_device_descriptor), 2314 UDESC_DEVICE, /* type */ 2315 {0x00, 0x01}, /* USB version */ 2316 UDCLASS_HUB, /* class */ 2317 UDSUBCLASS_HUB, /* subclass */ 2318 UDPROTO_FSHUB, /* protocol */ 2319 64, /* max packet */ 2320 {0}, {0}, {0x00, 0x01}, /* device id */ 2321 1, 2, 0, /* string indicies */ 2322 1 /* # of configurations */ 2323 }; 2324 2325 static const struct uhci_config_desc uhci_confd = { 2326 .confd = { 2327 .bLength = sizeof(struct usb_config_descriptor), 2328 .bDescriptorType = UDESC_CONFIG, 2329 .wTotalLength[0] = sizeof(uhci_confd), 2330 .bNumInterface = 1, 2331 .bConfigurationValue = 1, 2332 .iConfiguration = 0, 2333 .bmAttributes = UC_SELF_POWERED, 2334 .bMaxPower = 0 /* max power */ 2335 }, 2336 .ifcd = { 2337 .bLength = sizeof(struct usb_interface_descriptor), 2338 .bDescriptorType = UDESC_INTERFACE, 2339 .bNumEndpoints = 1, 2340 .bInterfaceClass = UICLASS_HUB, 2341 .bInterfaceSubClass = UISUBCLASS_HUB, 2342 .bInterfaceProtocol = UIPROTO_FSHUB, 2343 }, 2344 .endpd = { 2345 .bLength = sizeof(struct usb_endpoint_descriptor), 2346 .bDescriptorType = UDESC_ENDPOINT, 2347 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2348 .bmAttributes = UE_INTERRUPT, 2349 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2350 .bInterval = 255, 2351 }, 2352 }; 2353 2354 static const 2355 struct usb_hub_descriptor_min uhci_hubd_piix = 2356 { 2357 .bDescLength = sizeof(uhci_hubd_piix), 2358 .bDescriptorType = UDESC_HUB, 2359 .bNbrPorts = 2, 2360 .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2361 .bPwrOn2PwrGood = 50, 2362 }; 2363 2364 /* 2365 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2366 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2367 * should not be used by the USB subsystem. As we cannot issue a 2368 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2369 * will be enabled as part of the reset. 2370 * 2371 * On the VT83C572, the port cannot be successfully enabled until the 2372 * outstanding "port enable change" and "connection status change" 2373 * events have been reset. 2374 */ 2375 static usb_error_t 2376 uhci_portreset(uhci_softc_t *sc, uint16_t index) 2377 { 2378 uint16_t port; 2379 uint16_t x; 2380 uint8_t lim; 2381 2382 if (index == 1) 2383 port = UHCI_PORTSC1; 2384 else if (index == 2) 2385 port = UHCI_PORTSC2; 2386 else 2387 return (USB_ERR_IOERROR); 2388 2389 /* 2390 * Before we do anything, turn on SOF messages on the USB 2391 * BUS. Some USB devices do not cope without them! 2392 */ 2393 uhci_restart(sc); 2394 2395 x = URWMASK(UREAD2(sc, port)); 2396 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2397 2398 usb_pause_mtx(&sc->sc_bus.bus_lock, 2399 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 2400 2401 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2402 index, UREAD2(sc, port)); 2403 2404 x = URWMASK(UREAD2(sc, port)); 2405 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2406 2407 2408 lockmgr(&sc->sc_bus.bus_lock, LK_RELEASE); 2409 2410 /* 2411 * This delay needs to be exactly 100us, else some USB devices 2412 * fail to attach! 2413 */ 2414 DELAY(100); 2415 2416 lockmgr(&sc->sc_bus.bus_lock, LK_EXCLUSIVE); 2417 2418 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2419 index, UREAD2(sc, port)); 2420 2421 x = URWMASK(UREAD2(sc, port)); 2422 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2423 2424 for (lim = 0; lim < 12; lim++) { 2425 2426 usb_pause_mtx(&sc->sc_bus.bus_lock, 2427 USB_MS_TO_TICKS(usb_port_reset_delay)); 2428 2429 x = UREAD2(sc, port); 2430 2431 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2432 index, lim, x); 2433 2434 if (!(x & UHCI_PORTSC_CCS)) { 2435 /* 2436 * No device is connected (or was disconnected 2437 * during reset). Consider the port reset. 2438 * The delay must be long enough to ensure on 2439 * the initial iteration that the device 2440 * connection will have been registered. 50ms 2441 * appears to be sufficient, but 20ms is not. 2442 */ 2443 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2444 index, lim); 2445 goto done; 2446 } 2447 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2448 /* 2449 * Port enabled changed and/or connection 2450 * status changed were set. Reset either or 2451 * both raised flags (by writing a 1 to that 2452 * bit), and wait again for state to settle. 2453 */ 2454 UWRITE2(sc, port, URWMASK(x) | 2455 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2456 continue; 2457 } 2458 if (x & UHCI_PORTSC_PE) { 2459 /* port is enabled */ 2460 goto done; 2461 } 2462 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2463 } 2464 2465 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2466 return (USB_ERR_TIMEOUT); 2467 2468 done: 2469 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2470 index, UREAD2(sc, port)); 2471 2472 sc->sc_isreset = 1; 2473 return (USB_ERR_NORMAL_COMPLETION); 2474 } 2475 2476 static usb_error_t 2477 uhci_roothub_exec(struct usb_device *udev, 2478 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2479 { 2480 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 2481 const void *ptr; 2482 const char *str_ptr; 2483 uint16_t x; 2484 uint16_t port; 2485 uint16_t value; 2486 uint16_t index; 2487 uint16_t status; 2488 uint16_t change; 2489 uint16_t len; 2490 usb_error_t err; 2491 2492 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2493 2494 /* buffer reset */ 2495 ptr = (const void *)&sc->sc_hub_desc.temp; 2496 len = 0; 2497 err = 0; 2498 2499 value = UGETW(req->wValue); 2500 index = UGETW(req->wIndex); 2501 2502 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2503 "wValue=0x%04x wIndex=0x%04x\n", 2504 req->bmRequestType, req->bRequest, 2505 UGETW(req->wLength), value, index); 2506 2507 #define C(x,y) ((x) | ((y) << 8)) 2508 switch (C(req->bRequest, req->bmRequestType)) { 2509 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2510 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2511 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2512 /* 2513 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2514 * for the integrated root hub. 2515 */ 2516 break; 2517 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2518 len = 1; 2519 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2520 break; 2521 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2522 switch (value >> 8) { 2523 case UDESC_DEVICE: 2524 if ((value & 0xff) != 0) { 2525 err = USB_ERR_IOERROR; 2526 goto done; 2527 } 2528 len = sizeof(uhci_devd); 2529 ptr = (const void *)&uhci_devd; 2530 break; 2531 2532 case UDESC_CONFIG: 2533 if ((value & 0xff) != 0) { 2534 err = USB_ERR_IOERROR; 2535 goto done; 2536 } 2537 len = sizeof(uhci_confd); 2538 ptr = (const void *)&uhci_confd; 2539 break; 2540 2541 case UDESC_STRING: 2542 switch (value & 0xff) { 2543 case 0: /* Language table */ 2544 str_ptr = "\001"; 2545 break; 2546 2547 case 1: /* Vendor */ 2548 str_ptr = sc->sc_vendor; 2549 break; 2550 2551 case 2: /* Product */ 2552 str_ptr = "UHCI root HUB"; 2553 break; 2554 2555 default: 2556 str_ptr = ""; 2557 break; 2558 } 2559 2560 len = usb_make_str_desc 2561 (sc->sc_hub_desc.temp, 2562 sizeof(sc->sc_hub_desc.temp), 2563 str_ptr); 2564 break; 2565 2566 default: 2567 err = USB_ERR_IOERROR; 2568 goto done; 2569 } 2570 break; 2571 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2572 len = 1; 2573 sc->sc_hub_desc.temp[0] = 0; 2574 break; 2575 case C(UR_GET_STATUS, UT_READ_DEVICE): 2576 len = 2; 2577 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2578 break; 2579 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2580 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2581 len = 2; 2582 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2583 break; 2584 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2585 if (value >= UHCI_MAX_DEVICES) { 2586 err = USB_ERR_IOERROR; 2587 goto done; 2588 } 2589 sc->sc_addr = value; 2590 break; 2591 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2592 if ((value != 0) && (value != 1)) { 2593 err = USB_ERR_IOERROR; 2594 goto done; 2595 } 2596 sc->sc_conf = value; 2597 break; 2598 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2599 break; 2600 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2601 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2602 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2603 err = USB_ERR_IOERROR; 2604 goto done; 2605 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2606 break; 2607 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2608 break; 2609 /* Hub requests */ 2610 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2611 break; 2612 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2613 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2614 "port=%d feature=%d\n", 2615 index, value); 2616 if (index == 1) 2617 port = UHCI_PORTSC1; 2618 else if (index == 2) 2619 port = UHCI_PORTSC2; 2620 else { 2621 err = USB_ERR_IOERROR; 2622 goto done; 2623 } 2624 switch (value) { 2625 case UHF_PORT_ENABLE: 2626 x = URWMASK(UREAD2(sc, port)); 2627 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2628 break; 2629 case UHF_PORT_SUSPEND: 2630 x = URWMASK(UREAD2(sc, port)); 2631 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP)); 2632 break; 2633 case UHF_PORT_RESET: 2634 x = URWMASK(UREAD2(sc, port)); 2635 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2636 break; 2637 case UHF_C_PORT_CONNECTION: 2638 x = URWMASK(UREAD2(sc, port)); 2639 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2640 break; 2641 case UHF_C_PORT_ENABLE: 2642 x = URWMASK(UREAD2(sc, port)); 2643 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2644 break; 2645 case UHF_C_PORT_OVER_CURRENT: 2646 x = URWMASK(UREAD2(sc, port)); 2647 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2648 break; 2649 case UHF_C_PORT_RESET: 2650 sc->sc_isreset = 0; 2651 err = USB_ERR_NORMAL_COMPLETION; 2652 goto done; 2653 case UHF_C_PORT_SUSPEND: 2654 sc->sc_isresumed &= ~(1 << index); 2655 break; 2656 case UHF_PORT_CONNECTION: 2657 case UHF_PORT_OVER_CURRENT: 2658 case UHF_PORT_POWER: 2659 case UHF_PORT_LOW_SPEED: 2660 default: 2661 err = USB_ERR_IOERROR; 2662 goto done; 2663 } 2664 break; 2665 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2666 if (index == 1) 2667 port = UHCI_PORTSC1; 2668 else if (index == 2) 2669 port = UHCI_PORTSC2; 2670 else { 2671 err = USB_ERR_IOERROR; 2672 goto done; 2673 } 2674 len = 1; 2675 sc->sc_hub_desc.temp[0] = 2676 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2677 UHCI_PORTSC_LS_SHIFT); 2678 break; 2679 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2680 if ((value & 0xff) != 0) { 2681 err = USB_ERR_IOERROR; 2682 goto done; 2683 } 2684 len = sizeof(uhci_hubd_piix); 2685 ptr = (const void *)&uhci_hubd_piix; 2686 break; 2687 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2688 len = 16; 2689 memset(sc->sc_hub_desc.temp, 0, 16); 2690 break; 2691 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2692 if (index == 1) 2693 port = UHCI_PORTSC1; 2694 else if (index == 2) 2695 port = UHCI_PORTSC2; 2696 else { 2697 err = USB_ERR_IOERROR; 2698 goto done; 2699 } 2700 x = UREAD2(sc, port); 2701 status = change = 0; 2702 if (x & UHCI_PORTSC_CCS) 2703 status |= UPS_CURRENT_CONNECT_STATUS; 2704 if (x & UHCI_PORTSC_CSC) 2705 change |= UPS_C_CONNECT_STATUS; 2706 if (x & UHCI_PORTSC_PE) 2707 status |= UPS_PORT_ENABLED; 2708 if (x & UHCI_PORTSC_POEDC) 2709 change |= UPS_C_PORT_ENABLED; 2710 if (x & UHCI_PORTSC_OCI) 2711 status |= UPS_OVERCURRENT_INDICATOR; 2712 if (x & UHCI_PORTSC_OCIC) 2713 change |= UPS_C_OVERCURRENT_INDICATOR; 2714 if (x & UHCI_PORTSC_LSDA) 2715 status |= UPS_LOW_SPEED; 2716 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) { 2717 /* need to do a write back */ 2718 UWRITE2(sc, port, URWMASK(x)); 2719 2720 /* wait 20ms for resume sequence to complete */ 2721 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 50); 2722 2723 /* clear suspend and resume detect */ 2724 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD | 2725 UHCI_PORTSC_SUSP)); 2726 2727 /* wait a little bit */ 2728 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 500); 2729 2730 sc->sc_isresumed |= (1 << index); 2731 2732 } else if (x & UHCI_PORTSC_SUSP) { 2733 status |= UPS_SUSPEND; 2734 } 2735 status |= UPS_PORT_POWER; 2736 if (sc->sc_isresumed & (1 << index)) 2737 change |= UPS_C_SUSPEND; 2738 if (sc->sc_isreset) 2739 change |= UPS_C_PORT_RESET; 2740 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2741 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2742 len = sizeof(sc->sc_hub_desc.ps); 2743 break; 2744 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2745 err = USB_ERR_IOERROR; 2746 goto done; 2747 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2748 break; 2749 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2750 if (index == 1) 2751 port = UHCI_PORTSC1; 2752 else if (index == 2) 2753 port = UHCI_PORTSC2; 2754 else { 2755 err = USB_ERR_IOERROR; 2756 goto done; 2757 } 2758 switch (value) { 2759 case UHF_PORT_ENABLE: 2760 x = URWMASK(UREAD2(sc, port)); 2761 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2762 break; 2763 case UHF_PORT_SUSPEND: 2764 x = URWMASK(UREAD2(sc, port)); 2765 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2766 break; 2767 case UHF_PORT_RESET: 2768 err = uhci_portreset(sc, index); 2769 goto done; 2770 case UHF_PORT_POWER: 2771 /* pretend we turned on power */ 2772 err = USB_ERR_NORMAL_COMPLETION; 2773 goto done; 2774 case UHF_C_PORT_CONNECTION: 2775 case UHF_C_PORT_ENABLE: 2776 case UHF_C_PORT_OVER_CURRENT: 2777 case UHF_PORT_CONNECTION: 2778 case UHF_PORT_OVER_CURRENT: 2779 case UHF_PORT_LOW_SPEED: 2780 case UHF_C_PORT_SUSPEND: 2781 case UHF_C_PORT_RESET: 2782 default: 2783 err = USB_ERR_IOERROR; 2784 goto done; 2785 } 2786 break; 2787 default: 2788 err = USB_ERR_IOERROR; 2789 goto done; 2790 } 2791 done: 2792 *plength = len; 2793 *pptr = ptr; 2794 return (err); 2795 } 2796 2797 /* 2798 * This routine is executed periodically and simulates interrupts from 2799 * the root controller interrupt pipe for port status change: 2800 */ 2801 static void 2802 uhci_root_intr(uhci_softc_t *sc) 2803 { 2804 DPRINTFN(21, "\n"); 2805 2806 USB_BUS_LOCK_ASSERT(&sc->sc_bus); 2807 2808 sc->sc_hub_idata[0] = 0; 2809 2810 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | 2811 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2812 sc->sc_hub_idata[0] |= 1 << 1; 2813 } 2814 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | 2815 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2816 sc->sc_hub_idata[0] |= 1 << 2; 2817 } 2818 2819 /* restart timer */ 2820 usb_callout_reset(&sc->sc_root_intr, hz, 2821 (void *)&uhci_root_intr, sc); 2822 2823 if (sc->sc_hub_idata[0] != 0) { 2824 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2825 sizeof(sc->sc_hub_idata)); 2826 } 2827 } 2828 2829 static void 2830 uhci_xfer_setup(struct usb_setup_params *parm) 2831 { 2832 struct usb_page_search page_info; 2833 struct usb_page_cache *pc; 2834 uhci_softc_t *sc; 2835 struct usb_xfer *xfer; 2836 void *last_obj; 2837 uint32_t ntd; 2838 uint32_t nqh; 2839 uint32_t nfixup; 2840 uint32_t n; 2841 uint16_t align; 2842 2843 sc = UHCI_BUS2SC(parm->udev->bus); 2844 xfer = parm->curr_xfer; 2845 2846 parm->hc_max_packet_size = 0x500; 2847 parm->hc_max_packet_count = 1; 2848 parm->hc_max_frame_size = 0x500; 2849 2850 /* 2851 * compute ntd and nqh 2852 */ 2853 if (parm->methods == &uhci_device_ctrl_methods) { 2854 xfer->flags_int.bdma_enable = 1; 2855 xfer->flags_int.bdma_no_post_sync = 1; 2856 2857 usbd_transfer_setup_sub(parm); 2858 2859 /* see EHCI HC driver for proof of "ntd" formula */ 2860 2861 nqh = 1; 2862 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2863 + (xfer->max_data_length / xfer->max_frame_size)); 2864 2865 } else if (parm->methods == &uhci_device_bulk_methods) { 2866 xfer->flags_int.bdma_enable = 1; 2867 xfer->flags_int.bdma_no_post_sync = 1; 2868 2869 usbd_transfer_setup_sub(parm); 2870 2871 nqh = 1; 2872 ntd = ((2 * xfer->nframes) 2873 + (xfer->max_data_length / xfer->max_frame_size)); 2874 2875 } else if (parm->methods == &uhci_device_intr_methods) { 2876 xfer->flags_int.bdma_enable = 1; 2877 xfer->flags_int.bdma_no_post_sync = 1; 2878 2879 usbd_transfer_setup_sub(parm); 2880 2881 nqh = 1; 2882 ntd = ((2 * xfer->nframes) 2883 + (xfer->max_data_length / xfer->max_frame_size)); 2884 2885 } else if (parm->methods == &uhci_device_isoc_methods) { 2886 xfer->flags_int.bdma_enable = 1; 2887 xfer->flags_int.bdma_no_post_sync = 1; 2888 2889 usbd_transfer_setup_sub(parm); 2890 2891 nqh = 0; 2892 ntd = xfer->nframes; 2893 2894 } else { 2895 2896 usbd_transfer_setup_sub(parm); 2897 2898 nqh = 0; 2899 ntd = 0; 2900 } 2901 2902 if (parm->err) { 2903 return; 2904 } 2905 /* 2906 * NOTE: the UHCI controller requires that 2907 * every packet must be contiguous on 2908 * the same USB memory page ! 2909 */ 2910 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 2911 2912 /* 2913 * Compute a suitable power of two alignment 2914 * for our "max_frame_size" fixup buffer(s): 2915 */ 2916 align = xfer->max_frame_size; 2917 n = 0; 2918 while (align) { 2919 align >>= 1; 2920 n++; 2921 } 2922 2923 /* check for power of two */ 2924 if (powerof2(xfer->max_frame_size)) { 2925 n--; 2926 } 2927 /* 2928 * We don't allow alignments of 2929 * less than 8 bytes: 2930 * 2931 * NOTE: Allocating using an aligment 2932 * of 1 byte has special meaning! 2933 */ 2934 if (n < 3) { 2935 n = 3; 2936 } 2937 align = (1 << n); 2938 2939 if (usbd_transfer_setup_sub_malloc( 2940 parm, &pc, xfer->max_frame_size, 2941 align, nfixup)) { 2942 parm->err = USB_ERR_NOMEM; 2943 return; 2944 } 2945 xfer->buf_fixup = pc; 2946 2947 alloc_dma_set: 2948 2949 if (parm->err) { 2950 return; 2951 } 2952 last_obj = NULL; 2953 2954 if (usbd_transfer_setup_sub_malloc( 2955 parm, &pc, sizeof(uhci_td_t), 2956 UHCI_TD_ALIGN, ntd)) { 2957 parm->err = USB_ERR_NOMEM; 2958 return; 2959 } 2960 if (parm->buf) { 2961 for (n = 0; n != ntd; n++) { 2962 uhci_td_t *td; 2963 2964 usbd_get_page(pc + n, 0, &page_info); 2965 2966 td = page_info.buffer; 2967 2968 /* init TD */ 2969 if ((parm->methods == &uhci_device_bulk_methods) || 2970 (parm->methods == &uhci_device_ctrl_methods) || 2971 (parm->methods == &uhci_device_intr_methods)) { 2972 /* set depth first bit */ 2973 td->td_self = htole32(page_info.physaddr | 2974 UHCI_PTR_TD | UHCI_PTR_VF); 2975 } else { 2976 td->td_self = htole32(page_info.physaddr | 2977 UHCI_PTR_TD); 2978 } 2979 2980 td->obj_next = last_obj; 2981 td->page_cache = pc + n; 2982 2983 last_obj = td; 2984 2985 usb_pc_cpu_flush(pc + n); 2986 } 2987 } 2988 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2989 2990 last_obj = NULL; 2991 2992 if (usbd_transfer_setup_sub_malloc( 2993 parm, &pc, sizeof(uhci_qh_t), 2994 UHCI_QH_ALIGN, nqh)) { 2995 parm->err = USB_ERR_NOMEM; 2996 return; 2997 } 2998 if (parm->buf) { 2999 for (n = 0; n != nqh; n++) { 3000 uhci_qh_t *qh; 3001 3002 usbd_get_page(pc + n, 0, &page_info); 3003 3004 qh = page_info.buffer; 3005 3006 /* init QH */ 3007 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 3008 qh->obj_next = last_obj; 3009 qh->page_cache = pc + n; 3010 3011 last_obj = qh; 3012 3013 usb_pc_cpu_flush(pc + n); 3014 } 3015 } 3016 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3017 3018 if (!xfer->flags_int.curr_dma_set) { 3019 xfer->flags_int.curr_dma_set = 1; 3020 goto alloc_dma_set; 3021 } 3022 } 3023 3024 static void 3025 uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3026 struct usb_endpoint *ep) 3027 { 3028 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 3029 3030 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3031 ep, udev->address, 3032 edesc->bEndpointAddress, udev->flags.usb_mode, 3033 sc->sc_addr); 3034 3035 if (udev->device_index != sc->sc_addr) { 3036 switch (edesc->bmAttributes & UE_XFERTYPE) { 3037 case UE_CONTROL: 3038 ep->methods = &uhci_device_ctrl_methods; 3039 break; 3040 case UE_INTERRUPT: 3041 ep->methods = &uhci_device_intr_methods; 3042 break; 3043 case UE_ISOCHRONOUS: 3044 if (udev->speed == USB_SPEED_FULL) { 3045 ep->methods = &uhci_device_isoc_methods; 3046 } 3047 break; 3048 case UE_BULK: 3049 ep->methods = &uhci_device_bulk_methods; 3050 break; 3051 default: 3052 /* do nothing */ 3053 break; 3054 } 3055 } 3056 } 3057 3058 static void 3059 uhci_xfer_unsetup(struct usb_xfer *xfer) 3060 { 3061 return; 3062 } 3063 3064 static void 3065 uhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3066 { 3067 /* 3068 * Wait until hardware has finished any possible use of the 3069 * transfer descriptor(s) and QH 3070 */ 3071 *pus = (1125); /* microseconds */ 3072 } 3073 3074 static void 3075 uhci_device_resume(struct usb_device *udev) 3076 { 3077 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3078 struct usb_xfer *xfer; 3079 const struct usb_pipe_methods *methods; 3080 uhci_qh_t *qh; 3081 3082 DPRINTF("\n"); 3083 3084 USB_BUS_LOCK(udev->bus); 3085 3086 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3087 3088 if (xfer->xroot->udev == udev) { 3089 3090 methods = xfer->endpoint->methods; 3091 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3092 3093 if (methods == &uhci_device_bulk_methods) { 3094 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 3095 uhci_add_loop(sc); 3096 xfer->flags_int.bandwidth_reclaimed = 1; 3097 } 3098 if (methods == &uhci_device_ctrl_methods) { 3099 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3100 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 3101 } else { 3102 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 3103 } 3104 } 3105 if (methods == &uhci_device_intr_methods) { 3106 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3107 } 3108 } 3109 } 3110 3111 USB_BUS_UNLOCK(udev->bus); 3112 3113 return; 3114 } 3115 3116 static void 3117 uhci_device_suspend(struct usb_device *udev) 3118 { 3119 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3120 struct usb_xfer *xfer; 3121 const struct usb_pipe_methods *methods; 3122 uhci_qh_t *qh; 3123 3124 DPRINTF("\n"); 3125 3126 USB_BUS_LOCK(udev->bus); 3127 3128 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3129 3130 if (xfer->xroot->udev == udev) { 3131 3132 methods = xfer->endpoint->methods; 3133 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3134 3135 if (xfer->flags_int.bandwidth_reclaimed) { 3136 xfer->flags_int.bandwidth_reclaimed = 0; 3137 uhci_rem_loop(sc); 3138 } 3139 if (methods == &uhci_device_bulk_methods) { 3140 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 3141 } 3142 if (methods == &uhci_device_ctrl_methods) { 3143 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3144 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 3145 } else { 3146 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 3147 } 3148 } 3149 if (methods == &uhci_device_intr_methods) { 3150 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3151 } 3152 } 3153 } 3154 3155 USB_BUS_UNLOCK(udev->bus); 3156 3157 return; 3158 } 3159 3160 static void 3161 uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3162 { 3163 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3164 3165 switch (state) { 3166 case USB_HW_POWER_SUSPEND: 3167 case USB_HW_POWER_SHUTDOWN: 3168 uhci_suspend(sc); 3169 break; 3170 case USB_HW_POWER_RESUME: 3171 uhci_resume(sc); 3172 break; 3173 default: 3174 break; 3175 } 3176 } 3177 3178 static void 3179 uhci_set_hw_power(struct usb_bus *bus) 3180 { 3181 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3182 uint32_t flags; 3183 3184 DPRINTF("\n"); 3185 3186 USB_BUS_LOCK(bus); 3187 3188 flags = bus->hw_power_state; 3189 3190 /* 3191 * WARNING: Some FULL speed USB devices require periodic SOF 3192 * messages! If any USB devices are connected through the 3193 * UHCI, power save will be disabled! 3194 */ 3195 if (flags & (USB_HW_POWER_CONTROL | 3196 USB_HW_POWER_NON_ROOT_HUB | 3197 USB_HW_POWER_BULK | 3198 USB_HW_POWER_INTERRUPT | 3199 USB_HW_POWER_ISOC)) { 3200 DPRINTF("Some USB transfer is " 3201 "active on unit %u.\n", 3202 device_get_unit(sc->sc_bus.bdev)); 3203 uhci_restart(sc); 3204 } else { 3205 DPRINTF("Power save on unit %u.\n", 3206 device_get_unit(sc->sc_bus.bdev)); 3207 UHCICMD(sc, UHCI_CMD_MAXP); 3208 } 3209 3210 USB_BUS_UNLOCK(bus); 3211 3212 return; 3213 } 3214 3215 3216 static const struct usb_bus_methods uhci_bus_methods = 3217 { 3218 .endpoint_init = uhci_ep_init, 3219 .xfer_setup = uhci_xfer_setup, 3220 .xfer_unsetup = uhci_xfer_unsetup, 3221 .get_dma_delay = uhci_get_dma_delay, 3222 .device_resume = uhci_device_resume, 3223 .device_suspend = uhci_device_suspend, 3224 .set_hw_power = uhci_set_hw_power, 3225 .set_hw_power_sleep = uhci_set_hw_power_sleep, 3226 .roothub_exec = uhci_roothub_exec, 3227 .xfer_poll = uhci_do_poll, 3228 }; 3229