1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* $FreeBSD: head/sys/dev/usb/controller/xhci_pci.c 276717 2015-01-05 20:22:18Z hselasky $ */ 27 28 #include <sys/stdint.h> 29 #include <sys/param.h> 30 #include <sys/queue.h> 31 #include <sys/types.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/module.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/condvar.h> 39 #include <sys/sysctl.h> 40 #include <sys/unistd.h> 41 #include <sys/callout.h> 42 #include <sys/malloc.h> 43 #include <sys/priv.h> 44 45 #include <bus/u4b/usb.h> 46 #include <bus/u4b/usbdi.h> 47 48 #include <bus/u4b/usb_core.h> 49 #include <bus/u4b/usb_busdma.h> 50 #include <bus/u4b/usb_process.h> 51 #include <bus/u4b/usb_util.h> 52 53 #include <bus/u4b/usb_controller.h> 54 #include <bus/u4b/usb_bus.h> 55 #include <bus/u4b/usb_pci.h> 56 #include <bus/u4b/controller/xhci.h> 57 #include <bus/u4b/controller/xhcireg.h> 58 #include "usb_if.h" 59 60 static device_probe_t xhci_pci_probe; 61 static device_attach_t xhci_pci_attach; 62 static device_detach_t xhci_pci_detach; 63 static usb_take_controller_t xhci_pci_take_controller; 64 65 static device_method_t xhci_device_methods[] = { 66 /* device interface */ 67 DEVMETHOD(device_probe, xhci_pci_probe), 68 DEVMETHOD(device_attach, xhci_pci_attach), 69 DEVMETHOD(device_detach, xhci_pci_detach), 70 DEVMETHOD(device_suspend, bus_generic_suspend), 71 DEVMETHOD(device_resume, bus_generic_resume), 72 DEVMETHOD(device_shutdown, bus_generic_shutdown), 73 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 74 75 DEVMETHOD_END 76 }; 77 78 static driver_t xhci_driver = { 79 .name = "xhci", 80 .methods = xhci_device_methods, 81 .size = sizeof(struct xhci_softc), 82 }; 83 84 static devclass_t xhci_devclass; 85 86 DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL); 87 MODULE_DEPEND(xhci, usb, 1, 1, 1); 88 89 static const char * 90 xhci_pci_match(device_t self) 91 { 92 uint32_t device_id = pci_get_devid(self); 93 94 switch (device_id) { 95 case 0x01941033: 96 return ("NEC uPD720200 USB 3.0 controller"); 97 98 case 0x10421b21: 99 return ("ASMedia ASM1042 USB 3.0 controller"); 100 101 case 0x0f358086: 102 return ("Intel BayTrail USB 3.0 controller"); 103 case 0x9c318086: 104 case 0x1e318086: 105 return ("Intel Panther Point USB 3.0 controller"); 106 case 0x8c318086: 107 return ("Intel Lynx Point USB 3.0 controller"); 108 case 0x8cb18086: 109 return ("Intel Wildcat Point USB 3.0 controller"); 110 case 0x8d318086: 111 return ("Intel Wellsburg USB 3.0 controller"); 112 case 0x9cb18086: 113 return ("Intel Wildcat Point-LP USB 3.0 controller"); 114 115 default: 116 break; 117 } 118 119 if ((pci_get_class(self) == PCIC_SERIALBUS) 120 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 121 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 122 return ("XHCI (generic) USB 3.0 controller"); 123 } 124 return (NULL); /* dunno */ 125 } 126 127 static int 128 xhci_pci_probe(device_t self) 129 { 130 const char *desc = xhci_pci_match(self); 131 132 if (desc) { 133 device_set_desc(self, desc); 134 return (0); 135 } else { 136 return (ENXIO); 137 } 138 } 139 140 static int xhci_use_msi = 1; 141 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); 142 143 static void 144 xhci_interrupt_poll(void *_sc) 145 { 146 struct xhci_softc *sc = _sc; 147 148 USB_BUS_UNLOCK(&sc->sc_bus); 149 xhci_interrupt(sc); 150 USB_BUS_LOCK(&sc->sc_bus); 151 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 152 } 153 154 static int 155 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) 156 { 157 uint32_t temp; 158 uint32_t usb3_mask; 159 uint32_t usb2_mask; 160 161 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | 162 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); 163 164 temp |= set; 165 temp &= ~clear; 166 167 /* Don't set bits which the hardware doesn't support */ 168 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); 169 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4); 170 171 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4); 172 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4); 173 174 device_printf(self, "Port routing mask set to 0x%08x\n", temp); 175 176 return (0); 177 } 178 179 static int 180 xhci_pci_attach(device_t self) 181 { 182 struct xhci_softc *sc = device_get_softc(self); 183 int err, rid; 184 uint8_t usedma32; 185 #if defined(__DragonFly__) 186 int irq_flags; 187 #else 188 int count; 189 #endif 190 191 rid = PCI_XHCI_CBMEM; 192 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 193 RF_ACTIVE); 194 if (!sc->sc_io_res) { 195 device_printf(self, "Could not map memory\n"); 196 return (ENOMEM); 197 } 198 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 199 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 200 sc->sc_io_size = rman_get_size(sc->sc_io_res); 201 202 /* check for USB 3.0 controllers which don't support 64-bit DMA */ 203 switch (pci_get_devid(self)) { 204 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */ 205 case 0x00141912: /* NEC uPD720201 USB 3.0 controller */ 206 case 0x78141022: /* AMD A10-7300, tested does not work w/64-bit DMA */ 207 usedma32 = 1; 208 break; 209 default: 210 usedma32 = 0; 211 break; 212 } 213 214 if (xhci_init(sc, self, usedma32)) { 215 device_printf(self, "Could not initialize softc\n"); 216 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 217 sc->sc_io_res); 218 return (ENXIO); 219 } 220 221 pci_enable_busmaster(self); 222 223 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_lock, 0); 224 USB_BUS_LOCK(&sc->sc_bus); 225 226 rid = 0; 227 #if defined(__DragonFly__) 228 pci_alloc_1intr(self, xhci_use_msi, &rid, &irq_flags); 229 sc->sc_irq_rid = rid; 230 #else 231 if (xhci_use_msi) { 232 count = pci_msi_count(self); 233 if (count >= 1) { 234 count = 1; 235 if (pci_alloc_msi(self, &rid, 1, count) == 0) { 236 if (bootverbose) 237 device_printf(self, "MSI enabled\n"); 238 sc->sc_irq_rid = 1; 239 } 240 } 241 } 242 #endif 243 244 /* 245 * hw.usb.xhci.use_polling=1 to force polling. 246 */ 247 if (xhci_use_polling() == 0) { 248 #if defined(__DragonFly__) 249 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, 250 &rid, irq_flags); 251 #else 252 sc->sc_irq_res = bus_alloc_resource_any( 253 self, SYS_RES_IRQ, 254 &sc->sc_irq_rid, 255 RF_SHAREABLE | RF_ACTIVE); 256 #endif 257 if (sc->sc_irq_res == NULL) { 258 pci_release_msi(self); 259 device_printf(self, "Could not allocate IRQ\n"); 260 /* goto error; FALLTHROUGH - use polling */ 261 } 262 } 263 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 264 if (sc->sc_bus.bdev == NULL) { 265 device_printf(self, "Could not add USB device\n"); 266 goto error; 267 } 268 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 269 270 ksprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self)); 271 272 if (sc->sc_irq_res != NULL) { 273 err = bus_setup_intr(self, sc->sc_irq_res, INTR_MPSAFE, 274 (driver_intr_t *)xhci_interrupt, sc, 275 &sc->sc_intr_hdl, NULL); 276 if (err != 0) { 277 bus_release_resource(self, SYS_RES_IRQ, 278 rman_get_rid(sc->sc_irq_res), 279 sc->sc_irq_res); 280 sc->sc_irq_res = NULL; 281 pci_release_msi(self); 282 device_printf(self, 283 "Could not setup IRQ, err=%d\n", 284 err); 285 sc->sc_intr_hdl = NULL; 286 } 287 } 288 289 /* On Intel chipsets reroute ports from EHCI to XHCI controller. */ 290 switch (pci_get_devid(self)) { 291 case 0x0f358086: /* BayTrail */ 292 case 0x9c318086: /* Panther Point */ 293 case 0x1e318086: /* Panther Point */ 294 case 0x8c318086: /* Lynx Point */ 295 case 0x8cb18086: /* Wildcat Point */ 296 case 0x9cb18086: /* Wildcat Point-LP */ 297 sc->sc_port_route = &xhci_pci_port_route; 298 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP; 299 break; 300 default: 301 break; 302 } 303 304 xhci_pci_take_controller(self); 305 306 err = xhci_halt_controller(sc); 307 308 if (err == 0) 309 err = xhci_start_controller(sc); 310 311 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) { 312 if (xhci_use_polling() != 0) { 313 device_printf(self, "Interrupt polling at %dHz\n", hz); 314 xhci_interrupt_poll(sc); 315 } else { 316 goto error; 317 } 318 } 319 USB_BUS_UNLOCK(&sc->sc_bus); 320 321 if (err == 0) { 322 err = device_probe_and_attach(sc->sc_bus.bdev); 323 } 324 325 if (err) { 326 device_printf(self, 327 "XHCI halt/start/probe failed err=%d\n", 328 err); 329 goto error; 330 } 331 return (0); 332 333 error: 334 USB_BUS_UNLOCK(&sc->sc_bus); 335 xhci_pci_detach(self); 336 return (ENXIO); 337 } 338 339 static int 340 xhci_pci_detach(device_t self) 341 { 342 struct xhci_softc *sc = device_get_softc(self); 343 device_t bdev; 344 345 if (sc->sc_bus.bdev != NULL) { 346 bdev = sc->sc_bus.bdev; 347 device_detach(bdev); 348 device_delete_child(self, bdev); 349 } 350 /* during module unload there are lots of children leftover */ 351 device_delete_children(self); 352 353 usb_callout_drain(&sc->sc_callout); 354 xhci_halt_controller(sc); 355 356 pci_disable_busmaster(self); 357 358 if (sc->sc_irq_res && sc->sc_intr_hdl) { 359 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 360 sc->sc_intr_hdl = NULL; 361 } 362 if (sc->sc_irq_res) { 363 bus_release_resource(self, SYS_RES_IRQ, 364 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 365 sc->sc_irq_res = NULL; 366 pci_release_msi(self); 367 } 368 if (sc->sc_io_res) { 369 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 370 sc->sc_io_res); 371 sc->sc_io_res = NULL; 372 } 373 374 xhci_uninit(sc); 375 376 return (0); 377 } 378 379 static int 380 xhci_pci_take_controller(device_t self) 381 { 382 struct xhci_softc *sc = device_get_softc(self); 383 uint32_t cparams; 384 uint32_t eecp; 385 uint32_t eec; 386 uint16_t to; 387 uint8_t bios_sem; 388 389 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 390 391 eec = -1; 392 393 /* Synchronise with the BIOS if it owns the controller. */ 394 for (eecp = XHCI_HCS0_XECP(cparams) << 2; 395 eecp != 0 && XHCI_XECP_NEXT(eec); 396 eecp += XHCI_XECP_NEXT(eec) << 2) { 397 eec = XREAD4(sc, capa, eecp); 398 399 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 400 continue; 401 bios_sem = XREAD1(sc, capa, eecp + XHCI_XECP_BIOS_SEM); 402 if (bios_sem == 0) 403 continue; 404 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 405 "to give up control\n"); 406 XWRITE1(sc, capa, eecp + XHCI_XECP_OS_SEM, 1); 407 to = 500; 408 while (1) { 409 bios_sem = XREAD1(sc, capa, eecp + XHCI_XECP_BIOS_SEM); 410 if (bios_sem == 0) 411 break; 412 413 if (--to == 0) { 414 device_printf(sc->sc_bus.bdev, 415 "timed out waiting for BIOS\n"); 416 break; 417 } 418 usb_pause_mtx(NULL, hz / 100 + 1); /* wait 10ms */ 419 } 420 } 421 return (0); 422 } 423