1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* $FreeBSD: head/sys/dev/usb/controller/xhci_pci.c 276717 2015-01-05 20:22:18Z hselasky $ */ 27 28 #include <sys/stdint.h> 29 #include <sys/param.h> 30 #include <sys/queue.h> 31 #include <sys/types.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/module.h> 36 #include <sys/lock.h> 37 #include <sys/condvar.h> 38 #include <sys/sysctl.h> 39 #include <sys/unistd.h> 40 #include <sys/callout.h> 41 #include <sys/malloc.h> 42 #include <sys/caps.h> 43 44 #include <bus/u4b/usb.h> 45 #include <bus/u4b/usbdi.h> 46 47 #include <bus/u4b/usb_core.h> 48 #include <bus/u4b/usb_busdma.h> 49 #include <bus/u4b/usb_process.h> 50 #include <bus/u4b/usb_util.h> 51 52 #include <bus/u4b/usb_controller.h> 53 #include <bus/u4b/usb_bus.h> 54 #include <bus/u4b/usb_pci.h> 55 #include <bus/u4b/controller/xhci.h> 56 #include <bus/u4b/controller/xhcireg.h> 57 #include "usb_if.h" 58 59 static device_probe_t xhci_pci_probe; 60 static device_attach_t xhci_pci_attach; 61 static device_detach_t xhci_pci_detach; 62 static usb_take_controller_t xhci_pci_take_controller; 63 64 static device_method_t xhci_device_methods[] = { 65 /* device interface */ 66 DEVMETHOD(device_probe, xhci_pci_probe), 67 DEVMETHOD(device_attach, xhci_pci_attach), 68 DEVMETHOD(device_detach, xhci_pci_detach), 69 DEVMETHOD(device_suspend, bus_generic_suspend), 70 DEVMETHOD(device_resume, bus_generic_resume), 71 DEVMETHOD(device_shutdown, bus_generic_shutdown), 72 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 73 74 DEVMETHOD_END 75 }; 76 77 static driver_t xhci_driver = { 78 .name = "xhci", 79 .methods = xhci_device_methods, 80 .size = sizeof(struct xhci_softc), 81 }; 82 83 static devclass_t xhci_devclass; 84 85 DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL); 86 MODULE_DEPEND(xhci, usb, 1, 1, 1); 87 88 static const char * 89 xhci_pci_match(device_t self) 90 { 91 uint32_t device_id = pci_get_devid(self); 92 93 switch (device_id) { 94 case 0x01941033: 95 return ("NEC uPD720200 USB 3.0 controller"); 96 97 case 0x10421b21: 98 return ("ASMedia ASM1042 USB 3.0 controller"); 99 100 case 0x0f358086: 101 return ("Intel BayTrail USB 3.0 controller"); 102 case 0x9c318086: 103 case 0x1e318086: 104 return ("Intel Panther Point USB 3.0 controller"); 105 case 0x8c318086: 106 return ("Intel Lynx Point USB 3.0 controller"); 107 case 0x8cb18086: 108 return ("Intel Wildcat Point USB 3.0 controller"); 109 case 0x8d318086: 110 return ("Intel Wellsburg USB 3.0 controller"); 111 case 0x9cb18086: 112 return ("Intel Wildcat Point-LP USB 3.0 controller"); 113 case 0x9d2f8086: 114 return ("Intel Sunrise Point-LP USB 3.0 controller"); 115 case 0xa12f8086: 116 return ("Intel Sunrise Point USB 3.0 controller"); 117 case 0xa1af8086: 118 return ("Intel Lewisburg USB 3.0 controller"); 119 case 0xa2af8086: 120 return ("Intel Union Point USB 3.0 controller"); 121 case 0xa01b177d: 122 return ("Cavium ThunderX USB 3.0 controller"); 123 default: 124 break; 125 } 126 127 if ((pci_get_class(self) == PCIC_SERIALBUS) 128 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 129 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 130 return ("XHCI (generic) USB 3.0 controller"); 131 } 132 return (NULL); /* dunno */ 133 } 134 135 static int 136 xhci_pci_probe(device_t self) 137 { 138 const char *desc = xhci_pci_match(self); 139 140 if (desc) { 141 device_set_desc(self, desc); 142 return (0); 143 } else { 144 return (ENXIO); 145 } 146 } 147 148 static int xhci_use_msi = 1; 149 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); 150 151 static void 152 xhci_interrupt_poll(void *_sc) 153 { 154 struct xhci_softc *sc = _sc; 155 156 USB_BUS_UNLOCK(&sc->sc_bus); 157 xhci_interrupt(sc); 158 USB_BUS_LOCK(&sc->sc_bus); 159 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 160 } 161 162 static int 163 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) 164 { 165 uint32_t temp; 166 uint32_t usb3_mask; 167 uint32_t usb2_mask; 168 169 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | 170 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); 171 172 temp |= set; 173 temp &= ~clear; 174 175 /* Don't set bits which the hardware doesn't support */ 176 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); 177 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4); 178 179 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4); 180 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4); 181 182 device_printf(self, "Port routing mask set to 0x%08x\n", temp); 183 184 return (0); 185 } 186 187 static int 188 xhci_pci_attach(device_t self) 189 { 190 struct xhci_softc *sc = device_get_softc(self); 191 int err, rid; 192 uint8_t usedma32; 193 #if defined(__DragonFly__) 194 int irq_flags; 195 #else 196 int count; 197 #endif 198 199 rid = PCI_XHCI_CBMEM; 200 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 201 RF_ACTIVE); 202 if (!sc->sc_io_res) { 203 device_printf(self, "Could not map memory\n"); 204 return (ENOMEM); 205 } 206 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 207 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 208 sc->sc_io_size = rman_get_size(sc->sc_io_res); 209 210 /* check for USB 3.0 controllers which don't support 64-bit DMA */ 211 switch (pci_get_devid(self)) { 212 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */ 213 case 0x00141912: /* NEC uPD720201 USB 3.0 controller */ 214 case 0x78141022: /* AMD A10-7300, tested does not work w/64-bit DMA */ 215 usedma32 = 1; 216 break; 217 default: 218 usedma32 = 0; 219 break; 220 } 221 222 if (xhci_init(sc, self, usedma32)) { 223 device_printf(self, "Could not initialize softc\n"); 224 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 225 sc->sc_io_res); 226 return (ENXIO); 227 } 228 229 pci_enable_busmaster(self); 230 231 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_lock, 0); 232 USB_BUS_LOCK(&sc->sc_bus); 233 234 rid = 0; 235 #if defined(__DragonFly__) 236 pci_alloc_1intr(self, xhci_use_msi, &rid, &irq_flags); 237 sc->sc_irq_rid = rid; 238 #else 239 if (xhci_use_msi) { 240 count = pci_msi_count(self); 241 if (count >= 1) { 242 count = 1; 243 if (pci_alloc_msi(self, &rid, 1, count) == 0) { 244 if (bootverbose) 245 device_printf(self, "MSI enabled\n"); 246 sc->sc_irq_rid = 1; 247 } 248 } 249 } 250 #endif 251 252 /* 253 * hw.usb.xhci.use_polling=1 to force polling. 254 */ 255 if (xhci_use_polling() == 0) { 256 #if defined(__DragonFly__) 257 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, 258 &rid, irq_flags); 259 #else 260 sc->sc_irq_res = bus_alloc_resource_any( 261 self, SYS_RES_IRQ, 262 &sc->sc_irq_rid, 263 RF_SHAREABLE | RF_ACTIVE); 264 #endif 265 if (sc->sc_irq_res == NULL) { 266 pci_release_msi(self); 267 device_printf(self, "Could not allocate IRQ\n"); 268 /* goto error; FALLTHROUGH - use polling */ 269 } 270 } 271 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 272 if (sc->sc_bus.bdev == NULL) { 273 device_printf(self, "Could not add USB device\n"); 274 goto error; 275 } 276 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 277 278 ksprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self)); 279 280 if (sc->sc_irq_res != NULL) { 281 err = bus_setup_intr(self, sc->sc_irq_res, INTR_MPSAFE, 282 (driver_intr_t *)xhci_interrupt, sc, 283 &sc->sc_intr_hdl, NULL); 284 if (err != 0) { 285 bus_release_resource(self, SYS_RES_IRQ, 286 rman_get_rid(sc->sc_irq_res), 287 sc->sc_irq_res); 288 sc->sc_irq_res = NULL; 289 pci_release_msi(self); 290 device_printf(self, 291 "Could not setup IRQ, err=%d\n", 292 err); 293 sc->sc_intr_hdl = NULL; 294 } 295 } 296 297 /* On Intel chipsets reroute ports from EHCI to XHCI controller. */ 298 switch (pci_get_devid(self)) { 299 case 0x0f358086: /* BayTrail */ 300 case 0x9c318086: /* Panther Point */ 301 case 0x1e318086: /* Panther Point */ 302 case 0x8c318086: /* Lynx Point */ 303 case 0x8cb18086: /* Wildcat Point */ 304 case 0x9cb18086: /* Wildcat Point-LP */ 305 sc->sc_port_route = &xhci_pci_port_route; 306 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP; 307 break; 308 default: 309 break; 310 } 311 312 xhci_pci_take_controller(self); 313 314 err = xhci_halt_controller(sc); 315 316 if (err == 0) 317 err = xhci_start_controller(sc); 318 319 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) { 320 if (xhci_use_polling() != 0) { 321 device_printf(self, "Interrupt polling at %dHz\n", hz); 322 xhci_interrupt_poll(sc); 323 } else { 324 goto error; 325 } 326 } 327 USB_BUS_UNLOCK(&sc->sc_bus); 328 329 if (err == 0) { 330 err = device_probe_and_attach(sc->sc_bus.bdev); 331 } 332 333 if (err) { 334 device_printf(self, 335 "XHCI halt/start/probe failed err=%d\n", 336 err); 337 goto error; 338 } 339 return (0); 340 341 error: 342 USB_BUS_UNLOCK(&sc->sc_bus); 343 xhci_pci_detach(self); 344 return (ENXIO); 345 } 346 347 static int 348 xhci_pci_detach(device_t self) 349 { 350 struct xhci_softc *sc = device_get_softc(self); 351 device_t bdev; 352 353 if (sc->sc_bus.bdev != NULL) { 354 bdev = sc->sc_bus.bdev; 355 device_detach(bdev); 356 device_delete_child(self, bdev); 357 } 358 /* during module unload there are lots of children leftover */ 359 device_delete_children(self); 360 361 usb_callout_drain(&sc->sc_callout); 362 xhci_halt_controller(sc); 363 364 pci_disable_busmaster(self); 365 366 if (sc->sc_irq_res && sc->sc_intr_hdl) { 367 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 368 sc->sc_intr_hdl = NULL; 369 } 370 if (sc->sc_irq_res) { 371 bus_release_resource(self, SYS_RES_IRQ, 372 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 373 sc->sc_irq_res = NULL; 374 pci_release_msi(self); 375 } 376 if (sc->sc_io_res) { 377 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 378 sc->sc_io_res); 379 sc->sc_io_res = NULL; 380 } 381 382 xhci_uninit(sc); 383 384 return (0); 385 } 386 387 static int 388 xhci_pci_take_controller(device_t self) 389 { 390 struct xhci_softc *sc = device_get_softc(self); 391 uint32_t cparams; 392 uint32_t eecp; 393 uint32_t eec; 394 uint16_t to; 395 uint8_t bios_sem; 396 397 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 398 399 eec = -1; 400 401 /* Synchronise with the BIOS if it owns the controller. */ 402 for (eecp = XHCI_HCS0_XECP(cparams) << 2; 403 eecp != 0 && XHCI_XECP_NEXT(eec); 404 eecp += XHCI_XECP_NEXT(eec) << 2) { 405 eec = XREAD4(sc, capa, eecp); 406 407 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 408 continue; 409 bios_sem = XREAD1(sc, capa, eecp + XHCI_XECP_BIOS_SEM); 410 if (bios_sem == 0) 411 continue; 412 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 413 "to give up control\n"); 414 XWRITE1(sc, capa, eecp + XHCI_XECP_OS_SEM, 1); 415 to = 500; 416 while (1) { 417 bios_sem = XREAD1(sc, capa, eecp + XHCI_XECP_BIOS_SEM); 418 if (bios_sem == 0) 419 break; 420 421 if (--to == 0) { 422 device_printf(sc->sc_bus.bdev, 423 "timed out waiting for BIOS\n"); 424 break; 425 } 426 usb_pause_mtx(NULL, hz / 100 + 1); /* wait 10ms */ 427 } 428 } 429 return (0); 430 } 431