1 /*- 2 * Copyright (c) 1997, 1998, 1999, 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Copyright (c) 2006 6 * Alfred Perlstein <alfred@FreeBSD.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * ADMtek AN986 Pegasus and AN8511 Pegasus II USB to ethernet driver. 41 * Datasheet is available from http://www.admtek.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ee.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 * 47 * SMP locking by Alfred Perlstein <alfred@FreeBSD.org>. 48 * RED Inc. 49 */ 50 51 /* 52 * The Pegasus chip uses four USB "endpoints" to provide 10/100 ethernet 53 * support: the control endpoint for reading/writing registers, burst 54 * read endpoint for packet reception, burst write for packet transmission 55 * and one for "interrupts." The chip uses the same RX filter scheme 56 * as the other ADMtek ethernet parts: one perfect filter entry for the 57 * the station address and a 64-bit multicast hash table. The chip supports 58 * both MII and HomePNA attachments. 59 * 60 * Since the maximum data transfer speed of USB is supposed to be 12Mbps, 61 * you're never really going to get 100Mbps speeds from this device. I 62 * think the idea is to allow the device to connect to 10 or 100Mbps 63 * networks, not necessarily to provide 100Mbps performance. Also, since 64 * the controller uses an external PHY chip, it's possible that board 65 * designers might simply choose a 10Mbps PHY. 66 * 67 * Registers are accessed using uether_do_request(). Packet 68 * transfers are done using usbd_transfer() and friends. 69 */ 70 71 #include <sys/stdint.h> 72 #include <sys/stddef.h> 73 #include <sys/param.h> 74 #include <sys/queue.h> 75 #include <sys/types.h> 76 #include <sys/systm.h> 77 #include <sys/kernel.h> 78 #include <sys/bus.h> 79 #include <sys/module.h> 80 #include <sys/lock.h> 81 #include <sys/mutex.h> 82 #include <sys/condvar.h> 83 #include <sys/sysctl.h> 84 #include <sys/sx.h> 85 #include <sys/unistd.h> 86 #include <sys/callout.h> 87 #include <sys/malloc.h> 88 #include <sys/priv.h> 89 90 #include <dev/usb/usb.h> 91 #include <dev/usb/usbdi.h> 92 #include <dev/usb/usbdi_util.h> 93 #include "usbdevs.h" 94 95 #define USB_DEBUG_VAR aue_debug 96 #include <dev/usb/usb_debug.h> 97 #include <dev/usb/usb_process.h> 98 99 #include <dev/usb/net/usb_ethernet.h> 100 #include <dev/usb/net/if_auereg.h> 101 102 #ifdef USB_DEBUG 103 static int aue_debug = 0; 104 105 static SYSCTL_NODE(_hw_usb, OID_AUTO, aue, CTLFLAG_RW, 0, "USB aue"); 106 SYSCTL_INT(_hw_usb_aue, OID_AUTO, debug, CTLFLAG_RW, &aue_debug, 0, 107 "Debug level"); 108 #endif 109 110 /* 111 * Various supported device vendors/products. 112 */ 113 static const STRUCT_USB_HOST_ID aue_devs[] = { 114 #define AUE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 115 AUE_DEV(3COM, 3C460B, AUE_FLAG_PII), 116 AUE_DEV(ABOCOM, DSB650TX_PNA, 0), 117 AUE_DEV(ABOCOM, UFE1000, AUE_FLAG_LSYS), 118 AUE_DEV(ABOCOM, XX10, 0), 119 AUE_DEV(ABOCOM, XX1, AUE_FLAG_PNA | AUE_FLAG_PII), 120 AUE_DEV(ABOCOM, XX2, AUE_FLAG_PII), 121 AUE_DEV(ABOCOM, XX4, AUE_FLAG_PNA), 122 AUE_DEV(ABOCOM, XX5, AUE_FLAG_PNA), 123 AUE_DEV(ABOCOM, XX6, AUE_FLAG_PII), 124 AUE_DEV(ABOCOM, XX7, AUE_FLAG_PII), 125 AUE_DEV(ABOCOM, XX8, AUE_FLAG_PII), 126 AUE_DEV(ABOCOM, XX9, AUE_FLAG_PNA), 127 AUE_DEV(ACCTON, SS1001, AUE_FLAG_PII), 128 AUE_DEV(ACCTON, USB320_EC, 0), 129 AUE_DEV(ADMTEK, PEGASUSII_2, AUE_FLAG_PII), 130 AUE_DEV(ADMTEK, PEGASUSII_3, AUE_FLAG_PII), 131 AUE_DEV(ADMTEK, PEGASUSII_4, AUE_FLAG_PII), 132 AUE_DEV(ADMTEK, PEGASUSII, AUE_FLAG_PII), 133 AUE_DEV(ADMTEK, PEGASUS, AUE_FLAG_PNA | AUE_FLAG_DUAL_PHY), 134 AUE_DEV(AEI, FASTETHERNET, AUE_FLAG_PII), 135 AUE_DEV(ALLIEDTELESYN, ATUSB100, AUE_FLAG_PII), 136 AUE_DEV(ATEN, UC110T, AUE_FLAG_PII), 137 AUE_DEV(BELKIN, USB2LAN, AUE_FLAG_PII), 138 AUE_DEV(BILLIONTON, USB100, 0), 139 AUE_DEV(BILLIONTON, USBE100, AUE_FLAG_PII), 140 AUE_DEV(BILLIONTON, USBEL100, 0), 141 AUE_DEV(BILLIONTON, USBLP100, AUE_FLAG_PNA), 142 AUE_DEV(COREGA, FETHER_USB_TXS, AUE_FLAG_PII), 143 AUE_DEV(COREGA, FETHER_USB_TX, 0), 144 AUE_DEV(DLINK, DSB650TX1, AUE_FLAG_LSYS), 145 AUE_DEV(DLINK, DSB650TX2, AUE_FLAG_LSYS | AUE_FLAG_PII), 146 AUE_DEV(DLINK, DSB650TX3, AUE_FLAG_LSYS | AUE_FLAG_PII), 147 AUE_DEV(DLINK, DSB650TX4, AUE_FLAG_LSYS | AUE_FLAG_PII), 148 AUE_DEV(DLINK, DSB650TX_PNA, AUE_FLAG_PNA), 149 AUE_DEV(DLINK, DSB650TX, AUE_FLAG_LSYS), 150 AUE_DEV(DLINK, DSB650, AUE_FLAG_LSYS), 151 AUE_DEV(ELCON, PLAN, AUE_FLAG_PNA | AUE_FLAG_PII), 152 AUE_DEV(ELECOM, LDUSB20, AUE_FLAG_PII), 153 AUE_DEV(ELECOM, LDUSBLTX, AUE_FLAG_PII), 154 AUE_DEV(ELECOM, LDUSBTX0, 0), 155 AUE_DEV(ELECOM, LDUSBTX1, AUE_FLAG_LSYS), 156 AUE_DEV(ELECOM, LDUSBTX2, 0), 157 AUE_DEV(ELECOM, LDUSBTX3, AUE_FLAG_LSYS), 158 AUE_DEV(ELSA, USB2ETHERNET, 0), 159 AUE_DEV(GIGABYTE, GNBR402W, 0), 160 AUE_DEV(HAWKING, UF100, AUE_FLAG_PII), 161 AUE_DEV(HP, HN210E, AUE_FLAG_PII), 162 AUE_DEV(IODATA, USBETTXS, AUE_FLAG_PII), 163 AUE_DEV(IODATA, USBETTX, 0), 164 AUE_DEV(KINGSTON, KNU101TX, 0), 165 AUE_DEV(LINKSYS, USB100H1, AUE_FLAG_LSYS | AUE_FLAG_PNA), 166 AUE_DEV(LINKSYS, USB100TX, AUE_FLAG_LSYS), 167 AUE_DEV(LINKSYS, USB10TA, AUE_FLAG_LSYS), 168 AUE_DEV(LINKSYS, USB10TX1, AUE_FLAG_LSYS | AUE_FLAG_PII), 169 AUE_DEV(LINKSYS, USB10TX2, AUE_FLAG_LSYS | AUE_FLAG_PII), 170 AUE_DEV(LINKSYS, USB10T, AUE_FLAG_LSYS), 171 AUE_DEV(MELCO, LUA2TX5, AUE_FLAG_PII), 172 AUE_DEV(MELCO, LUATX1, 0), 173 AUE_DEV(MELCO, LUATX5, 0), 174 AUE_DEV(MICROSOFT, MN110, AUE_FLAG_PII), 175 AUE_DEV(NETGEAR, FA101, AUE_FLAG_PII), 176 AUE_DEV(SIEMENS, SPEEDSTREAM, AUE_FLAG_PII), 177 AUE_DEV(SIIG2, USBTOETHER, AUE_FLAG_PII), 178 AUE_DEV(SMARTBRIDGES, SMARTNIC, AUE_FLAG_PII), 179 AUE_DEV(SMC, 2202USB, 0), 180 AUE_DEV(SMC, 2206USB, AUE_FLAG_PII), 181 AUE_DEV(SOHOWARE, NUB100, 0), 182 AUE_DEV(SOHOWARE, NUB110, AUE_FLAG_PII), 183 #undef AUE_DEV 184 }; 185 186 /* prototypes */ 187 188 static device_probe_t aue_probe; 189 static device_attach_t aue_attach; 190 static device_detach_t aue_detach; 191 static miibus_readreg_t aue_miibus_readreg; 192 static miibus_writereg_t aue_miibus_writereg; 193 static miibus_statchg_t aue_miibus_statchg; 194 195 static usb_callback_t aue_intr_callback; 196 static usb_callback_t aue_bulk_read_callback; 197 static usb_callback_t aue_bulk_write_callback; 198 199 static uether_fn_t aue_attach_post; 200 static uether_fn_t aue_init; 201 static uether_fn_t aue_stop; 202 static uether_fn_t aue_start; 203 static uether_fn_t aue_tick; 204 static uether_fn_t aue_setmulti; 205 static uether_fn_t aue_setpromisc; 206 207 static uint8_t aue_csr_read_1(struct aue_softc *, uint16_t); 208 static uint16_t aue_csr_read_2(struct aue_softc *, uint16_t); 209 static void aue_csr_write_1(struct aue_softc *, uint16_t, uint8_t); 210 static void aue_csr_write_2(struct aue_softc *, uint16_t, uint16_t); 211 static void aue_eeprom_getword(struct aue_softc *, int, uint16_t *); 212 static void aue_read_eeprom(struct aue_softc *, uint8_t *, uint16_t, 213 uint16_t); 214 static void aue_reset(struct aue_softc *); 215 static void aue_reset_pegasus_II(struct aue_softc *); 216 217 static int aue_ifmedia_upd(struct ifnet *); 218 static void aue_ifmedia_sts(struct ifnet *, struct ifmediareq *); 219 220 static const struct usb_config aue_config[AUE_N_TRANSFER] = { 221 222 [AUE_BULK_DT_WR] = { 223 .type = UE_BULK, 224 .endpoint = UE_ADDR_ANY, 225 .direction = UE_DIR_OUT, 226 .bufsize = (MCLBYTES + 2), 227 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 228 .callback = aue_bulk_write_callback, 229 .timeout = 10000, /* 10 seconds */ 230 }, 231 232 [AUE_BULK_DT_RD] = { 233 .type = UE_BULK, 234 .endpoint = UE_ADDR_ANY, 235 .direction = UE_DIR_IN, 236 .bufsize = (MCLBYTES + 4 + ETHER_CRC_LEN), 237 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 238 .callback = aue_bulk_read_callback, 239 }, 240 241 [AUE_INTR_DT_RD] = { 242 .type = UE_INTERRUPT, 243 .endpoint = UE_ADDR_ANY, 244 .direction = UE_DIR_IN, 245 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 246 .bufsize = 0, /* use wMaxPacketSize */ 247 .callback = aue_intr_callback, 248 }, 249 }; 250 251 static device_method_t aue_methods[] = { 252 /* Device interface */ 253 DEVMETHOD(device_probe, aue_probe), 254 DEVMETHOD(device_attach, aue_attach), 255 DEVMETHOD(device_detach, aue_detach), 256 257 /* MII interface */ 258 DEVMETHOD(miibus_readreg, aue_miibus_readreg), 259 DEVMETHOD(miibus_writereg, aue_miibus_writereg), 260 DEVMETHOD(miibus_statchg, aue_miibus_statchg), 261 262 DEVMETHOD_END 263 }; 264 265 static driver_t aue_driver = { 266 .name = "aue", 267 .methods = aue_methods, 268 .size = sizeof(struct aue_softc) 269 }; 270 271 static devclass_t aue_devclass; 272 273 DRIVER_MODULE(aue, uhub, aue_driver, aue_devclass, NULL, 0); 274 DRIVER_MODULE(miibus, aue, miibus_driver, miibus_devclass, 0, 0); 275 MODULE_DEPEND(aue, uether, 1, 1, 1); 276 MODULE_DEPEND(aue, usb, 1, 1, 1); 277 MODULE_DEPEND(aue, ether, 1, 1, 1); 278 MODULE_DEPEND(aue, miibus, 1, 1, 1); 279 MODULE_VERSION(aue, 1); 280 281 static const struct usb_ether_methods aue_ue_methods = { 282 .ue_attach_post = aue_attach_post, 283 .ue_start = aue_start, 284 .ue_init = aue_init, 285 .ue_stop = aue_stop, 286 .ue_tick = aue_tick, 287 .ue_setmulti = aue_setmulti, 288 .ue_setpromisc = aue_setpromisc, 289 .ue_mii_upd = aue_ifmedia_upd, 290 .ue_mii_sts = aue_ifmedia_sts, 291 }; 292 293 #define AUE_SETBIT(sc, reg, x) \ 294 aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) | (x)) 295 296 #define AUE_CLRBIT(sc, reg, x) \ 297 aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) & ~(x)) 298 299 static uint8_t 300 aue_csr_read_1(struct aue_softc *sc, uint16_t reg) 301 { 302 struct usb_device_request req; 303 usb_error_t err; 304 uint8_t val; 305 306 req.bmRequestType = UT_READ_VENDOR_DEVICE; 307 req.bRequest = AUE_UR_READREG; 308 USETW(req.wValue, 0); 309 USETW(req.wIndex, reg); 310 USETW(req.wLength, 1); 311 312 err = uether_do_request(&sc->sc_ue, &req, &val, 1000); 313 if (err) 314 return (0); 315 return (val); 316 } 317 318 static uint16_t 319 aue_csr_read_2(struct aue_softc *sc, uint16_t reg) 320 { 321 struct usb_device_request req; 322 usb_error_t err; 323 uint16_t val; 324 325 req.bmRequestType = UT_READ_VENDOR_DEVICE; 326 req.bRequest = AUE_UR_READREG; 327 USETW(req.wValue, 0); 328 USETW(req.wIndex, reg); 329 USETW(req.wLength, 2); 330 331 err = uether_do_request(&sc->sc_ue, &req, &val, 1000); 332 if (err) 333 return (0); 334 return (le16toh(val)); 335 } 336 337 static void 338 aue_csr_write_1(struct aue_softc *sc, uint16_t reg, uint8_t val) 339 { 340 struct usb_device_request req; 341 342 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 343 req.bRequest = AUE_UR_WRITEREG; 344 req.wValue[0] = val; 345 req.wValue[1] = 0; 346 USETW(req.wIndex, reg); 347 USETW(req.wLength, 1); 348 349 if (uether_do_request(&sc->sc_ue, &req, &val, 1000)) { 350 /* error ignored */ 351 } 352 } 353 354 static void 355 aue_csr_write_2(struct aue_softc *sc, uint16_t reg, uint16_t val) 356 { 357 struct usb_device_request req; 358 359 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 360 req.bRequest = AUE_UR_WRITEREG; 361 USETW(req.wValue, val); 362 USETW(req.wIndex, reg); 363 USETW(req.wLength, 2); 364 365 val = htole16(val); 366 367 if (uether_do_request(&sc->sc_ue, &req, &val, 1000)) { 368 /* error ignored */ 369 } 370 } 371 372 /* 373 * Read a word of data stored in the EEPROM at address 'addr.' 374 */ 375 static void 376 aue_eeprom_getword(struct aue_softc *sc, int addr, uint16_t *dest) 377 { 378 int i; 379 uint16_t word = 0; 380 381 aue_csr_write_1(sc, AUE_EE_REG, addr); 382 aue_csr_write_1(sc, AUE_EE_CTL, AUE_EECTL_READ); 383 384 for (i = 0; i != AUE_TIMEOUT; i++) { 385 if (aue_csr_read_1(sc, AUE_EE_CTL) & AUE_EECTL_DONE) 386 break; 387 if (uether_pause(&sc->sc_ue, hz / 100)) 388 break; 389 } 390 391 if (i == AUE_TIMEOUT) 392 device_printf(sc->sc_ue.ue_dev, "EEPROM read timed out\n"); 393 394 word = aue_csr_read_2(sc, AUE_EE_DATA); 395 *dest = word; 396 } 397 398 /* 399 * Read a sequence of words from the EEPROM. 400 */ 401 static void 402 aue_read_eeprom(struct aue_softc *sc, uint8_t *dest, 403 uint16_t off, uint16_t len) 404 { 405 uint16_t *ptr = (uint16_t *)dest; 406 int i; 407 408 for (i = 0; i != len; i++, ptr++) 409 aue_eeprom_getword(sc, off + i, ptr); 410 } 411 412 static int 413 aue_miibus_readreg(device_t dev, int phy, int reg) 414 { 415 struct aue_softc *sc = device_get_softc(dev); 416 int i, locked; 417 uint16_t val = 0; 418 419 locked = mtx_owned(&sc->sc_mtx); 420 if (!locked) 421 AUE_LOCK(sc); 422 423 /* 424 * The Am79C901 HomePNA PHY actually contains two transceivers: a 1Mbps 425 * HomePNA PHY and a 10Mbps full/half duplex ethernet PHY with NWAY 426 * autoneg. However in the ADMtek adapter, only the 1Mbps PHY is 427 * actually connected to anything, so we ignore the 10Mbps one. It 428 * happens to be configured for MII address 3, so we filter that out. 429 */ 430 if (sc->sc_flags & AUE_FLAG_DUAL_PHY) { 431 if (phy == 3) 432 goto done; 433 #if 0 434 if (phy != 1) 435 goto done; 436 #endif 437 } 438 aue_csr_write_1(sc, AUE_PHY_ADDR, phy); 439 aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_READ); 440 441 for (i = 0; i != AUE_TIMEOUT; i++) { 442 if (aue_csr_read_1(sc, AUE_PHY_CTL) & AUE_PHYCTL_DONE) 443 break; 444 if (uether_pause(&sc->sc_ue, hz / 100)) 445 break; 446 } 447 448 if (i == AUE_TIMEOUT) 449 device_printf(sc->sc_ue.ue_dev, "MII read timed out\n"); 450 451 val = aue_csr_read_2(sc, AUE_PHY_DATA); 452 453 done: 454 if (!locked) 455 AUE_UNLOCK(sc); 456 return (val); 457 } 458 459 static int 460 aue_miibus_writereg(device_t dev, int phy, int reg, int data) 461 { 462 struct aue_softc *sc = device_get_softc(dev); 463 int i; 464 int locked; 465 466 if (phy == 3) 467 return (0); 468 469 locked = mtx_owned(&sc->sc_mtx); 470 if (!locked) 471 AUE_LOCK(sc); 472 473 aue_csr_write_2(sc, AUE_PHY_DATA, data); 474 aue_csr_write_1(sc, AUE_PHY_ADDR, phy); 475 aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_WRITE); 476 477 for (i = 0; i != AUE_TIMEOUT; i++) { 478 if (aue_csr_read_1(sc, AUE_PHY_CTL) & AUE_PHYCTL_DONE) 479 break; 480 if (uether_pause(&sc->sc_ue, hz / 100)) 481 break; 482 } 483 484 if (i == AUE_TIMEOUT) 485 device_printf(sc->sc_ue.ue_dev, "MII write timed out\n"); 486 487 if (!locked) 488 AUE_UNLOCK(sc); 489 return (0); 490 } 491 492 static void 493 aue_miibus_statchg(device_t dev) 494 { 495 struct aue_softc *sc = device_get_softc(dev); 496 struct mii_data *mii = GET_MII(sc); 497 int locked; 498 499 locked = mtx_owned(&sc->sc_mtx); 500 if (!locked) 501 AUE_LOCK(sc); 502 503 AUE_CLRBIT(sc, AUE_CTL0, AUE_CTL0_RX_ENB | AUE_CTL0_TX_ENB); 504 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 505 AUE_SETBIT(sc, AUE_CTL1, AUE_CTL1_SPEEDSEL); 506 else 507 AUE_CLRBIT(sc, AUE_CTL1, AUE_CTL1_SPEEDSEL); 508 509 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 510 AUE_SETBIT(sc, AUE_CTL1, AUE_CTL1_DUPLEX); 511 else 512 AUE_CLRBIT(sc, AUE_CTL1, AUE_CTL1_DUPLEX); 513 514 AUE_SETBIT(sc, AUE_CTL0, AUE_CTL0_RX_ENB | AUE_CTL0_TX_ENB); 515 516 /* 517 * Set the LED modes on the LinkSys adapter. 518 * This turns on the 'dual link LED' bin in the auxmode 519 * register of the Broadcom PHY. 520 */ 521 if (sc->sc_flags & AUE_FLAG_LSYS) { 522 uint16_t auxmode; 523 524 auxmode = aue_miibus_readreg(dev, 0, 0x1b); 525 aue_miibus_writereg(dev, 0, 0x1b, auxmode | 0x04); 526 } 527 if (!locked) 528 AUE_UNLOCK(sc); 529 } 530 531 #define AUE_BITS 6 532 static void 533 aue_setmulti(struct usb_ether *ue) 534 { 535 struct aue_softc *sc = uether_getsc(ue); 536 struct ifnet *ifp = uether_getifp(ue); 537 struct ifmultiaddr *ifma; 538 uint32_t h = 0; 539 uint32_t i; 540 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 541 542 AUE_LOCK_ASSERT(sc, MA_OWNED); 543 544 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 545 AUE_SETBIT(sc, AUE_CTL0, AUE_CTL0_ALLMULTI); 546 return; 547 } 548 549 AUE_CLRBIT(sc, AUE_CTL0, AUE_CTL0_ALLMULTI); 550 551 /* now program new ones */ 552 if_maddr_rlock(ifp); 553 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 554 if (ifma->ifma_addr->sa_family != AF_LINK) 555 continue; 556 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 557 ifma->ifma_addr), ETHER_ADDR_LEN) & ((1 << AUE_BITS) - 1); 558 hashtbl[(h >> 3)] |= 1 << (h & 0x7); 559 } 560 if_maddr_runlock(ifp); 561 562 /* write the hashtable */ 563 for (i = 0; i != 8; i++) 564 aue_csr_write_1(sc, AUE_MAR0 + i, hashtbl[i]); 565 } 566 567 static void 568 aue_reset_pegasus_II(struct aue_softc *sc) 569 { 570 /* Magic constants taken from Linux driver. */ 571 aue_csr_write_1(sc, AUE_REG_1D, 0); 572 aue_csr_write_1(sc, AUE_REG_7B, 2); 573 #if 0 574 if ((sc->sc_flags & HAS_HOME_PNA) && mii_mode) 575 aue_csr_write_1(sc, AUE_REG_81, 6); 576 else 577 #endif 578 aue_csr_write_1(sc, AUE_REG_81, 2); 579 } 580 581 static void 582 aue_reset(struct aue_softc *sc) 583 { 584 int i; 585 586 AUE_SETBIT(sc, AUE_CTL1, AUE_CTL1_RESETMAC); 587 588 for (i = 0; i != AUE_TIMEOUT; i++) { 589 if (!(aue_csr_read_1(sc, AUE_CTL1) & AUE_CTL1_RESETMAC)) 590 break; 591 if (uether_pause(&sc->sc_ue, hz / 100)) 592 break; 593 } 594 595 if (i == AUE_TIMEOUT) 596 device_printf(sc->sc_ue.ue_dev, "reset failed\n"); 597 598 /* 599 * The PHY(s) attached to the Pegasus chip may be held 600 * in reset until we flip on the GPIO outputs. Make sure 601 * to set the GPIO pins high so that the PHY(s) will 602 * be enabled. 603 * 604 * NOTE: We used to force all of the GPIO pins low first and then 605 * enable the ones we want. This has been changed to better 606 * match the ADMtek's reference design to avoid setting the 607 * power-down configuration line of the PHY at the same time 608 * it is reset. 609 */ 610 aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1); 611 aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1|AUE_GPIO_OUT0); 612 613 if (sc->sc_flags & AUE_FLAG_LSYS) { 614 /* Grrr. LinkSys has to be different from everyone else. */ 615 aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1); 616 aue_csr_write_1(sc, AUE_GPIO0, 617 AUE_GPIO_SEL0|AUE_GPIO_SEL1|AUE_GPIO_OUT0); 618 } 619 if (sc->sc_flags & AUE_FLAG_PII) 620 aue_reset_pegasus_II(sc); 621 622 /* Wait a little while for the chip to get its brains in order: */ 623 uether_pause(&sc->sc_ue, hz / 100); 624 } 625 626 static void 627 aue_attach_post(struct usb_ether *ue) 628 { 629 struct aue_softc *sc = uether_getsc(ue); 630 631 /* reset the adapter */ 632 aue_reset(sc); 633 634 /* get station address from the EEPROM */ 635 aue_read_eeprom(sc, ue->ue_eaddr, 0, 3); 636 } 637 638 /* 639 * Probe for a Pegasus chip. 640 */ 641 static int 642 aue_probe(device_t dev) 643 { 644 struct usb_attach_arg *uaa = device_get_ivars(dev); 645 646 if (uaa->usb_mode != USB_MODE_HOST) 647 return (ENXIO); 648 if (uaa->info.bConfigIndex != AUE_CONFIG_INDEX) 649 return (ENXIO); 650 if (uaa->info.bIfaceIndex != AUE_IFACE_IDX) 651 return (ENXIO); 652 /* 653 * Belkin USB Bluetooth dongles of the F8T012xx1 model series conflict 654 * with older Belkin USB2LAN adapters. Skip if_aue if we detect one of 655 * the devices that look like Bluetooth adapters. 656 */ 657 if (uaa->info.idVendor == USB_VENDOR_BELKIN && 658 uaa->info.idProduct == USB_PRODUCT_BELKIN_F8T012 && 659 uaa->info.bcdDevice == 0x0413) 660 return (ENXIO); 661 662 return (usbd_lookup_id_by_uaa(aue_devs, sizeof(aue_devs), uaa)); 663 } 664 665 /* 666 * Attach the interface. Allocate softc structures, do ifmedia 667 * setup and ethernet/BPF attach. 668 */ 669 static int 670 aue_attach(device_t dev) 671 { 672 struct usb_attach_arg *uaa = device_get_ivars(dev); 673 struct aue_softc *sc = device_get_softc(dev); 674 struct usb_ether *ue = &sc->sc_ue; 675 uint8_t iface_index; 676 int error; 677 678 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 679 680 if (uaa->info.bcdDevice >= 0x0201) { 681 /* XXX currently undocumented */ 682 sc->sc_flags |= AUE_FLAG_VER_2; 683 } 684 685 device_set_usb_desc(dev); 686 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 687 688 iface_index = AUE_IFACE_IDX; 689 error = usbd_transfer_setup(uaa->device, &iface_index, 690 sc->sc_xfer, aue_config, AUE_N_TRANSFER, 691 sc, &sc->sc_mtx); 692 if (error) { 693 device_printf(dev, "allocating USB transfers failed\n"); 694 goto detach; 695 } 696 697 ue->ue_sc = sc; 698 ue->ue_dev = dev; 699 ue->ue_udev = uaa->device; 700 ue->ue_mtx = &sc->sc_mtx; 701 ue->ue_methods = &aue_ue_methods; 702 703 error = uether_ifattach(ue); 704 if (error) { 705 device_printf(dev, "could not attach interface\n"); 706 goto detach; 707 } 708 return (0); /* success */ 709 710 detach: 711 aue_detach(dev); 712 return (ENXIO); /* failure */ 713 } 714 715 static int 716 aue_detach(device_t dev) 717 { 718 struct aue_softc *sc = device_get_softc(dev); 719 struct usb_ether *ue = &sc->sc_ue; 720 721 usbd_transfer_unsetup(sc->sc_xfer, AUE_N_TRANSFER); 722 uether_ifdetach(ue); 723 mtx_destroy(&sc->sc_mtx); 724 725 return (0); 726 } 727 728 static void 729 aue_intr_callback(struct usb_xfer *xfer, usb_error_t error) 730 { 731 struct aue_softc *sc = usbd_xfer_softc(xfer); 732 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 733 struct aue_intrpkt pkt; 734 struct usb_page_cache *pc; 735 int actlen; 736 737 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 738 739 switch (USB_GET_STATE(xfer)) { 740 case USB_ST_TRANSFERRED: 741 742 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && 743 actlen >= sizeof(pkt)) { 744 745 pc = usbd_xfer_get_frame(xfer, 0); 746 usbd_copy_out(pc, 0, &pkt, sizeof(pkt)); 747 748 if (pkt.aue_txstat0) 749 ifp->if_oerrors++; 750 if (pkt.aue_txstat0 & (AUE_TXSTAT0_LATECOLL & 751 AUE_TXSTAT0_EXCESSCOLL)) 752 ifp->if_collisions++; 753 } 754 /* FALLTHROUGH */ 755 case USB_ST_SETUP: 756 tr_setup: 757 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 758 usbd_transfer_submit(xfer); 759 return; 760 761 default: /* Error */ 762 if (error != USB_ERR_CANCELLED) { 763 /* try to clear stall first */ 764 usbd_xfer_set_stall(xfer); 765 goto tr_setup; 766 } 767 return; 768 } 769 } 770 771 static void 772 aue_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 773 { 774 struct aue_softc *sc = usbd_xfer_softc(xfer); 775 struct usb_ether *ue = &sc->sc_ue; 776 struct ifnet *ifp = uether_getifp(ue); 777 struct aue_rxpkt stat; 778 struct usb_page_cache *pc; 779 int actlen; 780 781 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 782 pc = usbd_xfer_get_frame(xfer, 0); 783 784 switch (USB_GET_STATE(xfer)) { 785 case USB_ST_TRANSFERRED: 786 DPRINTFN(11, "received %d bytes\n", actlen); 787 788 if (sc->sc_flags & AUE_FLAG_VER_2) { 789 790 if (actlen == 0) { 791 ifp->if_ierrors++; 792 goto tr_setup; 793 } 794 } else { 795 796 if (actlen <= sizeof(stat) + ETHER_CRC_LEN) { 797 ifp->if_ierrors++; 798 goto tr_setup; 799 } 800 usbd_copy_out(pc, actlen - sizeof(stat), &stat, 801 sizeof(stat)); 802 803 /* 804 * turn off all the non-error bits in the rx status 805 * word: 806 */ 807 stat.aue_rxstat &= AUE_RXSTAT_MASK; 808 if (stat.aue_rxstat) { 809 ifp->if_ierrors++; 810 goto tr_setup; 811 } 812 /* No errors; receive the packet. */ 813 actlen -= (sizeof(stat) + ETHER_CRC_LEN); 814 } 815 uether_rxbuf(ue, pc, 0, actlen); 816 817 /* FALLTHROUGH */ 818 case USB_ST_SETUP: 819 tr_setup: 820 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 821 usbd_transfer_submit(xfer); 822 uether_rxflush(ue); 823 return; 824 825 default: /* Error */ 826 DPRINTF("bulk read error, %s\n", 827 usbd_errstr(error)); 828 829 if (error != USB_ERR_CANCELLED) { 830 /* try to clear stall first */ 831 usbd_xfer_set_stall(xfer); 832 goto tr_setup; 833 } 834 return; 835 } 836 } 837 838 static void 839 aue_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 840 { 841 struct aue_softc *sc = usbd_xfer_softc(xfer); 842 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 843 struct usb_page_cache *pc; 844 struct mbuf *m; 845 uint8_t buf[2]; 846 int actlen; 847 848 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 849 pc = usbd_xfer_get_frame(xfer, 0); 850 851 switch (USB_GET_STATE(xfer)) { 852 case USB_ST_TRANSFERRED: 853 DPRINTFN(11, "transfer of %d bytes complete\n", actlen); 854 ifp->if_opackets++; 855 856 /* FALLTHROUGH */ 857 case USB_ST_SETUP: 858 tr_setup: 859 if ((sc->sc_flags & AUE_FLAG_LINK) == 0) { 860 /* 861 * don't send anything if there is no link ! 862 */ 863 return; 864 } 865 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 866 867 if (m == NULL) 868 return; 869 if (m->m_pkthdr.len > MCLBYTES) 870 m->m_pkthdr.len = MCLBYTES; 871 if (sc->sc_flags & AUE_FLAG_VER_2) { 872 873 usbd_xfer_set_frame_len(xfer, 0, m->m_pkthdr.len); 874 875 usbd_m_copy_in(pc, 0, m, 0, m->m_pkthdr.len); 876 877 } else { 878 879 usbd_xfer_set_frame_len(xfer, 0, (m->m_pkthdr.len + 2)); 880 881 /* 882 * The ADMtek documentation says that the 883 * packet length is supposed to be specified 884 * in the first two bytes of the transfer, 885 * however it actually seems to ignore this 886 * info and base the frame size on the bulk 887 * transfer length. 888 */ 889 buf[0] = (uint8_t)(m->m_pkthdr.len); 890 buf[1] = (uint8_t)(m->m_pkthdr.len >> 8); 891 892 usbd_copy_in(pc, 0, buf, 2); 893 usbd_m_copy_in(pc, 2, m, 0, m->m_pkthdr.len); 894 } 895 896 /* 897 * if there's a BPF listener, bounce a copy 898 * of this frame to him: 899 */ 900 BPF_MTAP(ifp, m); 901 902 m_freem(m); 903 904 usbd_transfer_submit(xfer); 905 return; 906 907 default: /* Error */ 908 DPRINTFN(11, "transfer error, %s\n", 909 usbd_errstr(error)); 910 911 ifp->if_oerrors++; 912 913 if (error != USB_ERR_CANCELLED) { 914 /* try to clear stall first */ 915 usbd_xfer_set_stall(xfer); 916 goto tr_setup; 917 } 918 return; 919 } 920 } 921 922 static void 923 aue_tick(struct usb_ether *ue) 924 { 925 struct aue_softc *sc = uether_getsc(ue); 926 struct mii_data *mii = GET_MII(sc); 927 928 AUE_LOCK_ASSERT(sc, MA_OWNED); 929 930 mii_tick(mii); 931 if ((sc->sc_flags & AUE_FLAG_LINK) == 0 932 && mii->mii_media_status & IFM_ACTIVE && 933 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 934 sc->sc_flags |= AUE_FLAG_LINK; 935 aue_start(ue); 936 } 937 } 938 939 static void 940 aue_start(struct usb_ether *ue) 941 { 942 struct aue_softc *sc = uether_getsc(ue); 943 944 /* 945 * start the USB transfers, if not already started: 946 */ 947 usbd_transfer_start(sc->sc_xfer[AUE_INTR_DT_RD]); 948 usbd_transfer_start(sc->sc_xfer[AUE_BULK_DT_RD]); 949 usbd_transfer_start(sc->sc_xfer[AUE_BULK_DT_WR]); 950 } 951 952 static void 953 aue_init(struct usb_ether *ue) 954 { 955 struct aue_softc *sc = uether_getsc(ue); 956 struct ifnet *ifp = uether_getifp(ue); 957 int i; 958 959 AUE_LOCK_ASSERT(sc, MA_OWNED); 960 961 /* 962 * Cancel pending I/O 963 */ 964 aue_reset(sc); 965 966 /* Set MAC address */ 967 for (i = 0; i != ETHER_ADDR_LEN; i++) 968 aue_csr_write_1(sc, AUE_PAR0 + i, IF_LLADDR(ifp)[i]); 969 970 /* update promiscuous setting */ 971 aue_setpromisc(ue); 972 973 /* Load the multicast filter. */ 974 aue_setmulti(ue); 975 976 /* Enable RX and TX */ 977 aue_csr_write_1(sc, AUE_CTL0, AUE_CTL0_RXSTAT_APPEND | AUE_CTL0_RX_ENB); 978 AUE_SETBIT(sc, AUE_CTL0, AUE_CTL0_TX_ENB); 979 AUE_SETBIT(sc, AUE_CTL2, AUE_CTL2_EP3_CLR); 980 981 usbd_xfer_set_stall(sc->sc_xfer[AUE_BULK_DT_WR]); 982 983 ifp->if_drv_flags |= IFF_DRV_RUNNING; 984 aue_start(ue); 985 } 986 987 static void 988 aue_setpromisc(struct usb_ether *ue) 989 { 990 struct aue_softc *sc = uether_getsc(ue); 991 struct ifnet *ifp = uether_getifp(ue); 992 993 AUE_LOCK_ASSERT(sc, MA_OWNED); 994 995 /* if we want promiscuous mode, set the allframes bit: */ 996 if (ifp->if_flags & IFF_PROMISC) 997 AUE_SETBIT(sc, AUE_CTL2, AUE_CTL2_RX_PROMISC); 998 else 999 AUE_CLRBIT(sc, AUE_CTL2, AUE_CTL2_RX_PROMISC); 1000 } 1001 1002 /* 1003 * Set media options. 1004 */ 1005 static int 1006 aue_ifmedia_upd(struct ifnet *ifp) 1007 { 1008 struct aue_softc *sc = ifp->if_softc; 1009 struct mii_data *mii = GET_MII(sc); 1010 struct mii_softc *miisc; 1011 1012 AUE_LOCK_ASSERT(sc, MA_OWNED); 1013 1014 sc->sc_flags &= ~AUE_FLAG_LINK; 1015 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1016 PHY_RESET(miisc); 1017 mii_mediachg(mii); 1018 return (0); 1019 } 1020 1021 /* 1022 * Report current media status. 1023 */ 1024 static void 1025 aue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1026 { 1027 struct aue_softc *sc = ifp->if_softc; 1028 struct mii_data *mii = GET_MII(sc); 1029 1030 AUE_LOCK(sc); 1031 mii_pollstat(mii); 1032 ifmr->ifm_active = mii->mii_media_active; 1033 ifmr->ifm_status = mii->mii_media_status; 1034 AUE_UNLOCK(sc); 1035 } 1036 1037 /* 1038 * Stop the adapter and free any mbufs allocated to the 1039 * RX and TX lists. 1040 */ 1041 static void 1042 aue_stop(struct usb_ether *ue) 1043 { 1044 struct aue_softc *sc = uether_getsc(ue); 1045 struct ifnet *ifp = uether_getifp(ue); 1046 1047 AUE_LOCK_ASSERT(sc, MA_OWNED); 1048 1049 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1050 sc->sc_flags &= ~AUE_FLAG_LINK; 1051 1052 /* 1053 * stop all the transfers, if not already stopped: 1054 */ 1055 usbd_transfer_stop(sc->sc_xfer[AUE_BULK_DT_WR]); 1056 usbd_transfer_stop(sc->sc_xfer[AUE_BULK_DT_RD]); 1057 usbd_transfer_stop(sc->sc_xfer[AUE_INTR_DT_RD]); 1058 1059 aue_csr_write_1(sc, AUE_CTL0, 0); 1060 aue_csr_write_1(sc, AUE_CTL1, 0); 1061 aue_reset(sc); 1062 } 1063