1b7d5e03cSMatthew Dillon /*
2b7d5e03cSMatthew Dillon * Copyright (c) 2013 Qualcomm Atheros, Inc.
3b7d5e03cSMatthew Dillon *
4b7d5e03cSMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
5b7d5e03cSMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
6b7d5e03cSMatthew Dillon * copyright notice and this permission notice appear in all copies.
7b7d5e03cSMatthew Dillon *
8b7d5e03cSMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9b7d5e03cSMatthew Dillon * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10b7d5e03cSMatthew Dillon * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11b7d5e03cSMatthew Dillon * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12b7d5e03cSMatthew Dillon * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13b7d5e03cSMatthew Dillon * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14b7d5e03cSMatthew Dillon * PERFORMANCE OF THIS SOFTWARE.
15b7d5e03cSMatthew Dillon */
16b7d5e03cSMatthew Dillon
17b7d5e03cSMatthew Dillon #include "opt_ah.h"
18b7d5e03cSMatthew Dillon
19b7d5e03cSMatthew Dillon #include "ah.h"
20b7d5e03cSMatthew Dillon #include "ah_internal.h"
21b7d5e03cSMatthew Dillon #include "ah_devid.h"
22b7d5e03cSMatthew Dillon #ifdef AH_DEBUG
23b7d5e03cSMatthew Dillon #include "ah_desc.h" /* NB: for HAL_PHYERR* */
24b7d5e03cSMatthew Dillon #endif
25b7d5e03cSMatthew Dillon
26b7d5e03cSMatthew Dillon #include "ar9300/ar9300.h"
27b7d5e03cSMatthew Dillon #include "ar9300/ar9300reg.h"
28b7d5e03cSMatthew Dillon #include "ar9300/ar9300phy.h"
29b7d5e03cSMatthew Dillon
30b7d5e03cSMatthew Dillon
31b7d5e03cSMatthew Dillon void
ar9300_get_hw_hangs(struct ath_hal * ah,hal_hw_hangs_t * hangs)32b7d5e03cSMatthew Dillon ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs)
33b7d5e03cSMatthew Dillon {
34b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
35b7d5e03cSMatthew Dillon *hangs = 0;
36b7d5e03cSMatthew Dillon
37b7d5e03cSMatthew Dillon if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) {
38b7d5e03cSMatthew Dillon *hangs |= HAL_RIFS_BB_HANG_WAR;
39b7d5e03cSMatthew Dillon }
40b7d5e03cSMatthew Dillon if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) {
41b7d5e03cSMatthew Dillon *hangs |= HAL_DFS_BB_HANG_WAR;
42b7d5e03cSMatthew Dillon }
43b7d5e03cSMatthew Dillon if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL)
44b7d5e03cSMatthew Dillon == HAL_OK)
45b7d5e03cSMatthew Dillon {
46b7d5e03cSMatthew Dillon *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR;
47b7d5e03cSMatthew Dillon }
48b7d5e03cSMatthew Dillon if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) {
49b7d5e03cSMatthew Dillon *hangs |= HAL_MAC_HANG_WAR;
50b7d5e03cSMatthew Dillon }
51b7d5e03cSMatthew Dillon if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL)
52b7d5e03cSMatthew Dillon == HAL_OK)
53b7d5e03cSMatthew Dillon {
54b7d5e03cSMatthew Dillon *hangs |= HAL_PHYRESTART_CLR_WAR;
55b7d5e03cSMatthew Dillon }
56b7d5e03cSMatthew Dillon
57b7d5e03cSMatthew Dillon ahp->ah_hang_wars = *hangs;
58b7d5e03cSMatthew Dillon }
59b7d5e03cSMatthew Dillon
60b7d5e03cSMatthew Dillon /*
61b7d5e03cSMatthew Dillon * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about
62b7d5e03cSMatthew Dillon * HT20, HT40, fast-clock, turbo mode, etc.
63b7d5e03cSMatthew Dillon */
64b7d5e03cSMatthew Dillon static u_int
ar9300_mac_to_usec(struct ath_hal * ah,u_int clks)65b7d5e03cSMatthew Dillon ar9300_mac_to_usec(struct ath_hal *ah, u_int clks)
66b7d5e03cSMatthew Dillon {
67b7d5e03cSMatthew Dillon #if 0
68b7d5e03cSMatthew Dillon const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
69b7d5e03cSMatthew Dillon
70b7d5e03cSMatthew Dillon if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
71b7d5e03cSMatthew Dillon return (ath_hal_mac_usec(ah, clks) / 2);
72b7d5e03cSMatthew Dillon } else {
73b7d5e03cSMatthew Dillon return (ath_hal_mac_usec(ah, clks));
74b7d5e03cSMatthew Dillon }
75b7d5e03cSMatthew Dillon #endif
76b7d5e03cSMatthew Dillon return (ath_hal_mac_usec(ah, clks));
77b7d5e03cSMatthew Dillon }
78b7d5e03cSMatthew Dillon
79b7d5e03cSMatthew Dillon u_int
ar9300_mac_to_clks(struct ath_hal * ah,u_int usecs)80b7d5e03cSMatthew Dillon ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs)
81b7d5e03cSMatthew Dillon {
82b7d5e03cSMatthew Dillon #if 0
83b7d5e03cSMatthew Dillon const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
84b7d5e03cSMatthew Dillon
85b7d5e03cSMatthew Dillon if (chan && IEEE80211_IS_CHAN_HT40(chan)) {
86b7d5e03cSMatthew Dillon return (ath_hal_mac_clks(ah, usecs) * 2);
87b7d5e03cSMatthew Dillon } else {
88b7d5e03cSMatthew Dillon return (ath_hal_mac_clks(ah, usecs));
89b7d5e03cSMatthew Dillon }
90b7d5e03cSMatthew Dillon #endif
91b7d5e03cSMatthew Dillon return (ath_hal_mac_clks(ah, usecs));
92b7d5e03cSMatthew Dillon }
93b7d5e03cSMatthew Dillon
94b7d5e03cSMatthew Dillon void
ar9300_get_mac_address(struct ath_hal * ah,u_int8_t * mac)95b7d5e03cSMatthew Dillon ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac)
96b7d5e03cSMatthew Dillon {
97b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
98b7d5e03cSMatthew Dillon
99b7d5e03cSMatthew Dillon OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
100b7d5e03cSMatthew Dillon }
101b7d5e03cSMatthew Dillon
102b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_set_mac_address(struct ath_hal * ah,const u_int8_t * mac)103b7d5e03cSMatthew Dillon ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac)
104b7d5e03cSMatthew Dillon {
105b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
106b7d5e03cSMatthew Dillon
107b7d5e03cSMatthew Dillon OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
108b7d5e03cSMatthew Dillon return AH_TRUE;
109b7d5e03cSMatthew Dillon }
110b7d5e03cSMatthew Dillon
111b7d5e03cSMatthew Dillon void
ar9300_get_bss_id_mask(struct ath_hal * ah,u_int8_t * mask)112b7d5e03cSMatthew Dillon ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask)
113b7d5e03cSMatthew Dillon {
114b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
115b7d5e03cSMatthew Dillon
116b7d5e03cSMatthew Dillon OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN);
117b7d5e03cSMatthew Dillon }
118b7d5e03cSMatthew Dillon
119b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_set_bss_id_mask(struct ath_hal * ah,const u_int8_t * mask)120b7d5e03cSMatthew Dillon ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask)
121b7d5e03cSMatthew Dillon {
122b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
123b7d5e03cSMatthew Dillon
124b7d5e03cSMatthew Dillon /* save it since it must be rewritten on reset */
125b7d5e03cSMatthew Dillon OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN);
126b7d5e03cSMatthew Dillon
127b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask));
128b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4));
129b7d5e03cSMatthew Dillon return AH_TRUE;
130b7d5e03cSMatthew Dillon }
131b7d5e03cSMatthew Dillon
132b7d5e03cSMatthew Dillon /*
133b7d5e03cSMatthew Dillon * Attempt to change the cards operating regulatory domain to the given value
134b7d5e03cSMatthew Dillon * Returns: A_EINVAL for an unsupported regulatory domain.
135b7d5e03cSMatthew Dillon * A_HARDWARE for an unwritable EEPROM or bad EEPROM version
136b7d5e03cSMatthew Dillon */
137b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_set_regulatory_domain(struct ath_hal * ah,u_int16_t reg_domain,HAL_STATUS * status)138b7d5e03cSMatthew Dillon ar9300_set_regulatory_domain(struct ath_hal *ah,
139b7d5e03cSMatthew Dillon u_int16_t reg_domain, HAL_STATUS *status)
140b7d5e03cSMatthew Dillon {
141b7d5e03cSMatthew Dillon HAL_STATUS ecode;
142b7d5e03cSMatthew Dillon
143b7d5e03cSMatthew Dillon if (AH_PRIVATE(ah)->ah_currentRD == 0) {
144b7d5e03cSMatthew Dillon AH_PRIVATE(ah)->ah_currentRD = reg_domain;
145b7d5e03cSMatthew Dillon return AH_TRUE;
146b7d5e03cSMatthew Dillon }
147b7d5e03cSMatthew Dillon ecode = HAL_EIO;
148b7d5e03cSMatthew Dillon
149b7d5e03cSMatthew Dillon #if 0
150b7d5e03cSMatthew Dillon bad:
151b7d5e03cSMatthew Dillon #endif
152b7d5e03cSMatthew Dillon if (status) {
153b7d5e03cSMatthew Dillon *status = ecode;
154b7d5e03cSMatthew Dillon }
155b7d5e03cSMatthew Dillon return AH_FALSE;
156b7d5e03cSMatthew Dillon }
157b7d5e03cSMatthew Dillon
158b7d5e03cSMatthew Dillon /*
159b7d5e03cSMatthew Dillon * Return the wireless modes (a,b,g,t) supported by hardware.
160b7d5e03cSMatthew Dillon *
161b7d5e03cSMatthew Dillon * This value is what is actually supported by the hardware
162b7d5e03cSMatthew Dillon * and is unaffected by regulatory/country code settings.
163b7d5e03cSMatthew Dillon *
164b7d5e03cSMatthew Dillon */
165b7d5e03cSMatthew Dillon u_int
ar9300_get_wireless_modes(struct ath_hal * ah)166b7d5e03cSMatthew Dillon ar9300_get_wireless_modes(struct ath_hal *ah)
167b7d5e03cSMatthew Dillon {
168b7d5e03cSMatthew Dillon return AH_PRIVATE(ah)->ah_caps.halWirelessModes;
169b7d5e03cSMatthew Dillon }
170b7d5e03cSMatthew Dillon
171b7d5e03cSMatthew Dillon /*
172b7d5e03cSMatthew Dillon * Set the interrupt and GPIO values so the ISR can disable RF
173b7d5e03cSMatthew Dillon * on a switch signal. Assumes GPIO port and interrupt polarity
174b7d5e03cSMatthew Dillon * are set prior to call.
175b7d5e03cSMatthew Dillon */
176b7d5e03cSMatthew Dillon void
ar9300_enable_rf_kill(struct ath_hal * ah)177b7d5e03cSMatthew Dillon ar9300_enable_rf_kill(struct ath_hal *ah)
178b7d5e03cSMatthew Dillon {
179b7d5e03cSMatthew Dillon /* TODO - can this really be above the hal on the GPIO interface for
180b7d5e03cSMatthew Dillon * TODO - the client only?
181b7d5e03cSMatthew Dillon */
182b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
183b7d5e03cSMatthew Dillon
184b7d5e03cSMatthew Dillon if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
185b7d5e03cSMatthew Dillon /* Check RF kill GPIO before set/clear RFSILENT bits. */
186b7d5e03cSMatthew Dillon if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) {
187b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT),
188b7d5e03cSMatthew Dillon AR_RFSILENT_FORCE);
189b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
190b7d5e03cSMatthew Dillon }
191b7d5e03cSMatthew Dillon else {
192b7d5e03cSMatthew Dillon OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT),
193b7d5e03cSMatthew Dillon AR_RFSILENT_FORCE);
194b7d5e03cSMatthew Dillon OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
195b7d5e03cSMatthew Dillon }
196b7d5e03cSMatthew Dillon }
197b7d5e03cSMatthew Dillon else {
198b7d5e03cSMatthew Dillon /* Connect rfsilent_bb_l to baseband */
199b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
200b7d5e03cSMatthew Dillon AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
201b7d5e03cSMatthew Dillon
202b7d5e03cSMatthew Dillon /* Set input mux for rfsilent_bb_l to GPIO #0 */
203b7d5e03cSMatthew Dillon OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
204b7d5e03cSMatthew Dillon AR_GPIO_INPUT_MUX2_RFSILENT);
205b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2),
206b7d5e03cSMatthew Dillon (ahp->ah_gpio_select & 0x0f) << 4);
207b7d5e03cSMatthew Dillon
208b7d5e03cSMatthew Dillon /*
209b7d5e03cSMatthew Dillon * Configure the desired GPIO port for input and
210b7d5e03cSMatthew Dillon * enable baseband rf silence
211b7d5e03cSMatthew Dillon */
212b7d5e03cSMatthew Dillon ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select);
213b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
214b7d5e03cSMatthew Dillon }
215b7d5e03cSMatthew Dillon
216b7d5e03cSMatthew Dillon /*
217b7d5e03cSMatthew Dillon * If radio disable switch connection to GPIO bit x is enabled
218b7d5e03cSMatthew Dillon * program GPIO interrupt.
219b7d5e03cSMatthew Dillon * If rfkill bit on eeprom is 1, setupeeprommap routine has already
220b7d5e03cSMatthew Dillon * verified that it is a later version of eeprom, it has a place for
221b7d5e03cSMatthew Dillon * rfkill bit and it is set to 1, indicating that GPIO bit x hardware
222b7d5e03cSMatthew Dillon * connection is present.
223b7d5e03cSMatthew Dillon */
224b7d5e03cSMatthew Dillon /*
225b7d5e03cSMatthew Dillon * RFKill uses polling not interrupt,
226b7d5e03cSMatthew Dillon * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue
227b7d5e03cSMatthew Dillon */
228b7d5e03cSMatthew Dillon if (ath_hal_hasrfkill_int(ah)) {
229b7d5e03cSMatthew Dillon if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) {
230b7d5e03cSMatthew Dillon /* switch already closed, set to interrupt upon open */
231b7d5e03cSMatthew Dillon ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit);
232b7d5e03cSMatthew Dillon } else {
233b7d5e03cSMatthew Dillon ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit);
234b7d5e03cSMatthew Dillon }
235b7d5e03cSMatthew Dillon }
236b7d5e03cSMatthew Dillon }
237b7d5e03cSMatthew Dillon
238b7d5e03cSMatthew Dillon /*
239b7d5e03cSMatthew Dillon * Change the LED blinking pattern to correspond to the connectivity
240b7d5e03cSMatthew Dillon */
241b7d5e03cSMatthew Dillon void
ar9300_set_led_state(struct ath_hal * ah,HAL_LED_STATE state)242b7d5e03cSMatthew Dillon ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state)
243b7d5e03cSMatthew Dillon {
244b7d5e03cSMatthew Dillon static const u_int32_t ledbits[8] = {
245b7d5e03cSMatthew Dillon AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */
246b7d5e03cSMatthew Dillon AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */
247b7d5e03cSMatthew Dillon AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */
248b7d5e03cSMatthew Dillon AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */
249b7d5e03cSMatthew Dillon AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */
250b7d5e03cSMatthew Dillon AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */
251b7d5e03cSMatthew Dillon AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */
252b7d5e03cSMatthew Dillon AR_CFG_LED_ASSOC_NONE,
253b7d5e03cSMatthew Dillon };
254b7d5e03cSMatthew Dillon
255b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]);
256b7d5e03cSMatthew Dillon }
257b7d5e03cSMatthew Dillon
258b7d5e03cSMatthew Dillon /*
259b7d5e03cSMatthew Dillon * Sets the Power LED on the cardbus without affecting the Network LED.
260b7d5e03cSMatthew Dillon */
261b7d5e03cSMatthew Dillon void
ar9300_set_power_led_state(struct ath_hal * ah,u_int8_t enabled)262b7d5e03cSMatthew Dillon ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled)
263b7d5e03cSMatthew Dillon {
264b7d5e03cSMatthew Dillon u_int32_t val;
265b7d5e03cSMatthew Dillon
266b7d5e03cSMatthew Dillon val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF;
267b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val);
268b7d5e03cSMatthew Dillon }
269b7d5e03cSMatthew Dillon
270b7d5e03cSMatthew Dillon /*
271b7d5e03cSMatthew Dillon * Sets the Network LED on the cardbus without affecting the Power LED.
272b7d5e03cSMatthew Dillon */
273b7d5e03cSMatthew Dillon void
ar9300_set_network_led_state(struct ath_hal * ah,u_int8_t enabled)274b7d5e03cSMatthew Dillon ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled)
275b7d5e03cSMatthew Dillon {
276b7d5e03cSMatthew Dillon u_int32_t val;
277b7d5e03cSMatthew Dillon
278b7d5e03cSMatthew Dillon val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF;
279b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val);
280b7d5e03cSMatthew Dillon }
281b7d5e03cSMatthew Dillon
282b7d5e03cSMatthew Dillon /*
283b7d5e03cSMatthew Dillon * Change association related fields programmed into the hardware.
284b7d5e03cSMatthew Dillon * Writing a valid BSSID to the hardware effectively enables the hardware
285b7d5e03cSMatthew Dillon * to synchronize its TSF to the correct beacons and receive frames coming
286b7d5e03cSMatthew Dillon * from that BSSID. It is called by the SME JOIN operation.
287b7d5e03cSMatthew Dillon */
288b7d5e03cSMatthew Dillon void
ar9300_write_associd(struct ath_hal * ah,const u_int8_t * bssid,u_int16_t assoc_id)289b7d5e03cSMatthew Dillon ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
290b7d5e03cSMatthew Dillon u_int16_t assoc_id)
291b7d5e03cSMatthew Dillon {
292b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
293b7d5e03cSMatthew Dillon
294b7d5e03cSMatthew Dillon /* save bssid and assoc_id for restore on reset */
295b7d5e03cSMatthew Dillon OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
296b7d5e03cSMatthew Dillon ahp->ah_assoc_id = assoc_id;
297b7d5e03cSMatthew Dillon
298b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
299b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) |
300b7d5e03cSMatthew Dillon ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S));
301b7d5e03cSMatthew Dillon }
302b7d5e03cSMatthew Dillon
303b7d5e03cSMatthew Dillon /*
304b7d5e03cSMatthew Dillon * Get the current hardware tsf for stamlme
305b7d5e03cSMatthew Dillon */
306b7d5e03cSMatthew Dillon u_int64_t
ar9300_get_tsf64(struct ath_hal * ah)307b7d5e03cSMatthew Dillon ar9300_get_tsf64(struct ath_hal *ah)
308b7d5e03cSMatthew Dillon {
309b7d5e03cSMatthew Dillon u_int64_t tsf;
310b7d5e03cSMatthew Dillon
311b7d5e03cSMatthew Dillon /* XXX sync multi-word read? */
312b7d5e03cSMatthew Dillon tsf = OS_REG_READ(ah, AR_TSF_U32);
313b7d5e03cSMatthew Dillon tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
314b7d5e03cSMatthew Dillon return tsf;
315b7d5e03cSMatthew Dillon }
316b7d5e03cSMatthew Dillon
317b7d5e03cSMatthew Dillon void
ar9300_set_tsf64(struct ath_hal * ah,u_int64_t tsf)318b7d5e03cSMatthew Dillon ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf)
319b7d5e03cSMatthew Dillon {
320b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff));
321b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff));
322b7d5e03cSMatthew Dillon }
323b7d5e03cSMatthew Dillon
324b7d5e03cSMatthew Dillon /*
325b7d5e03cSMatthew Dillon * Get the current hardware tsf for stamlme
326b7d5e03cSMatthew Dillon */
327b7d5e03cSMatthew Dillon u_int32_t
ar9300_get_tsf32(struct ath_hal * ah)328b7d5e03cSMatthew Dillon ar9300_get_tsf32(struct ath_hal *ah)
329b7d5e03cSMatthew Dillon {
330b7d5e03cSMatthew Dillon return OS_REG_READ(ah, AR_TSF_L32);
331b7d5e03cSMatthew Dillon }
332b7d5e03cSMatthew Dillon
333b7d5e03cSMatthew Dillon u_int32_t
ar9300_get_tsf2_32(struct ath_hal * ah)334b7d5e03cSMatthew Dillon ar9300_get_tsf2_32(struct ath_hal *ah)
335b7d5e03cSMatthew Dillon {
336b7d5e03cSMatthew Dillon return OS_REG_READ(ah, AR_TSF2_L32);
337b7d5e03cSMatthew Dillon }
338b7d5e03cSMatthew Dillon
339b7d5e03cSMatthew Dillon /*
340b7d5e03cSMatthew Dillon * Reset the current hardware tsf for stamlme.
341b7d5e03cSMatthew Dillon */
342b7d5e03cSMatthew Dillon void
ar9300_reset_tsf(struct ath_hal * ah)343b7d5e03cSMatthew Dillon ar9300_reset_tsf(struct ath_hal *ah)
344b7d5e03cSMatthew Dillon {
345b7d5e03cSMatthew Dillon int count;
346b7d5e03cSMatthew Dillon
347b7d5e03cSMatthew Dillon count = 0;
348b7d5e03cSMatthew Dillon while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
349b7d5e03cSMatthew Dillon count++;
350b7d5e03cSMatthew Dillon if (count > 10) {
351b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RESET,
352b7d5e03cSMatthew Dillon "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__);
353b7d5e03cSMatthew Dillon break;
354b7d5e03cSMatthew Dillon }
355b7d5e03cSMatthew Dillon OS_DELAY(10);
356b7d5e03cSMatthew Dillon }
357b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
358b7d5e03cSMatthew Dillon }
359b7d5e03cSMatthew Dillon
360b7d5e03cSMatthew Dillon /*
361b7d5e03cSMatthew Dillon * Set or clear hardware basic rate bit
362b7d5e03cSMatthew Dillon * Set hardware basic rate set if basic rate is found
363b7d5e03cSMatthew Dillon * and basic rate is equal or less than 2Mbps
364b7d5e03cSMatthew Dillon */
365b7d5e03cSMatthew Dillon void
ar9300_set_basic_rate(struct ath_hal * ah,HAL_RATE_SET * rs)366b7d5e03cSMatthew Dillon ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs)
367b7d5e03cSMatthew Dillon {
368b7d5e03cSMatthew Dillon const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
369b7d5e03cSMatthew Dillon u_int32_t reg;
370b7d5e03cSMatthew Dillon u_int8_t xset;
371b7d5e03cSMatthew Dillon int i;
372b7d5e03cSMatthew Dillon
373b7d5e03cSMatthew Dillon if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) {
374b7d5e03cSMatthew Dillon return;
375b7d5e03cSMatthew Dillon }
376b7d5e03cSMatthew Dillon xset = 0;
377b7d5e03cSMatthew Dillon for (i = 0; i < rs->rs_count; i++) {
378b7d5e03cSMatthew Dillon u_int8_t rset = rs->rs_rates[i];
379b7d5e03cSMatthew Dillon /* Basic rate defined? */
380b7d5e03cSMatthew Dillon if ((rset & 0x80) && (rset &= 0x7f) >= xset) {
381b7d5e03cSMatthew Dillon xset = rset;
382b7d5e03cSMatthew Dillon }
383b7d5e03cSMatthew Dillon }
384b7d5e03cSMatthew Dillon /*
385b7d5e03cSMatthew Dillon * Set the h/w bit to reflect whether or not the basic
386b7d5e03cSMatthew Dillon * rate is found to be equal or less than 2Mbps.
387b7d5e03cSMatthew Dillon */
388b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, AR_STA_ID1);
389b7d5e03cSMatthew Dillon if (xset && xset / 2 <= 2) {
390b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
391b7d5e03cSMatthew Dillon } else {
392b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
393b7d5e03cSMatthew Dillon }
394b7d5e03cSMatthew Dillon }
395b7d5e03cSMatthew Dillon
396b7d5e03cSMatthew Dillon /*
397b7d5e03cSMatthew Dillon * Grab a semi-random value from hardware registers - may not
398b7d5e03cSMatthew Dillon * change often
399b7d5e03cSMatthew Dillon */
400b7d5e03cSMatthew Dillon u_int32_t
ar9300_get_random_seed(struct ath_hal * ah)401b7d5e03cSMatthew Dillon ar9300_get_random_seed(struct ath_hal *ah)
402b7d5e03cSMatthew Dillon {
403b7d5e03cSMatthew Dillon u_int32_t nf;
404b7d5e03cSMatthew Dillon
405b7d5e03cSMatthew Dillon nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
406b7d5e03cSMatthew Dillon if (nf & 0x100) {
407b7d5e03cSMatthew Dillon nf = 0 - ((nf ^ 0x1ff) + 1);
408b7d5e03cSMatthew Dillon }
409b7d5e03cSMatthew Dillon return (OS_REG_READ(ah, AR_TSF_U32) ^
410b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_TSF_L32) ^ nf);
411b7d5e03cSMatthew Dillon }
412b7d5e03cSMatthew Dillon
413b7d5e03cSMatthew Dillon /*
414b7d5e03cSMatthew Dillon * Detect if our card is present
415b7d5e03cSMatthew Dillon */
416b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_detect_card_present(struct ath_hal * ah)417b7d5e03cSMatthew Dillon ar9300_detect_card_present(struct ath_hal *ah)
418b7d5e03cSMatthew Dillon {
419b7d5e03cSMatthew Dillon u_int16_t mac_version, mac_rev;
420b7d5e03cSMatthew Dillon u_int32_t v;
421b7d5e03cSMatthew Dillon
422b7d5e03cSMatthew Dillon /*
423b7d5e03cSMatthew Dillon * Read the Silicon Revision register and compare that
424b7d5e03cSMatthew Dillon * to what we read at attach time. If the same, we say
425b7d5e03cSMatthew Dillon * a card/device is present.
426b7d5e03cSMatthew Dillon */
427b7d5e03cSMatthew Dillon v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID;
428b7d5e03cSMatthew Dillon if (v == 0xFF) {
429b7d5e03cSMatthew Dillon /* new SREV format */
430b7d5e03cSMatthew Dillon v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV));
431b7d5e03cSMatthew Dillon /*
432b7d5e03cSMatthew Dillon * Include 6-bit Chip Type (masked to 0) to differentiate
433b7d5e03cSMatthew Dillon * from pre-Sowl versions
434b7d5e03cSMatthew Dillon */
435b7d5e03cSMatthew Dillon mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
436b7d5e03cSMatthew Dillon mac_rev = MS(v, AR_SREV_REVISION2);
437b7d5e03cSMatthew Dillon } else {
438b7d5e03cSMatthew Dillon mac_version = MS(v, AR_SREV_VERSION);
439b7d5e03cSMatthew Dillon mac_rev = v & AR_SREV_REVISION;
440b7d5e03cSMatthew Dillon }
441b7d5e03cSMatthew Dillon return (AH_PRIVATE(ah)->ah_macVersion == mac_version &&
442b7d5e03cSMatthew Dillon AH_PRIVATE(ah)->ah_macRev == mac_rev);
443b7d5e03cSMatthew Dillon }
444b7d5e03cSMatthew Dillon
445b7d5e03cSMatthew Dillon /*
446b7d5e03cSMatthew Dillon * Update MIB Counters
447b7d5e03cSMatthew Dillon */
448b7d5e03cSMatthew Dillon void
ar9300_update_mib_mac_stats(struct ath_hal * ah)449b7d5e03cSMatthew Dillon ar9300_update_mib_mac_stats(struct ath_hal *ah)
450b7d5e03cSMatthew Dillon {
451b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
452b7d5e03cSMatthew Dillon HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats;
453b7d5e03cSMatthew Dillon
454b7d5e03cSMatthew Dillon stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
455b7d5e03cSMatthew Dillon stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
456b7d5e03cSMatthew Dillon stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
457b7d5e03cSMatthew Dillon stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
458b7d5e03cSMatthew Dillon stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
459b7d5e03cSMatthew Dillon }
460b7d5e03cSMatthew Dillon
461b7d5e03cSMatthew Dillon void
ar9300_get_mib_mac_stats(struct ath_hal * ah,HAL_MIB_STATS * stats)462b7d5e03cSMatthew Dillon ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats)
463b7d5e03cSMatthew Dillon {
464b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
465b7d5e03cSMatthew Dillon HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats;
466b7d5e03cSMatthew Dillon
467b7d5e03cSMatthew Dillon stats->ackrcv_bad = istats->ackrcv_bad;
468b7d5e03cSMatthew Dillon stats->rts_bad = istats->rts_bad;
469b7d5e03cSMatthew Dillon stats->fcs_bad = istats->fcs_bad;
470b7d5e03cSMatthew Dillon stats->rts_good = istats->rts_good;
471b7d5e03cSMatthew Dillon stats->beacons = istats->beacons;
472b7d5e03cSMatthew Dillon }
473b7d5e03cSMatthew Dillon
474b7d5e03cSMatthew Dillon /*
475b7d5e03cSMatthew Dillon * Detect if the HW supports spreading a CCK signal on channel 14
476b7d5e03cSMatthew Dillon */
477b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_is_japan_channel_spread_supported(struct ath_hal * ah)478b7d5e03cSMatthew Dillon ar9300_is_japan_channel_spread_supported(struct ath_hal *ah)
479b7d5e03cSMatthew Dillon {
480b7d5e03cSMatthew Dillon return AH_TRUE;
481b7d5e03cSMatthew Dillon }
482b7d5e03cSMatthew Dillon
483b7d5e03cSMatthew Dillon /*
484b7d5e03cSMatthew Dillon * Get the rssi of frame curently being received.
485b7d5e03cSMatthew Dillon */
486b7d5e03cSMatthew Dillon u_int32_t
ar9300_get_cur_rssi(struct ath_hal * ah)487b7d5e03cSMatthew Dillon ar9300_get_cur_rssi(struct ath_hal *ah)
488b7d5e03cSMatthew Dillon {
489b7d5e03cSMatthew Dillon /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */
490b7d5e03cSMatthew Dillon /* get combined RSSI */
491b7d5e03cSMatthew Dillon return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff);
492b7d5e03cSMatthew Dillon }
493b7d5e03cSMatthew Dillon
494b7d5e03cSMatthew Dillon #if ATH_GEN_RANDOMNESS
495b7d5e03cSMatthew Dillon /*
496b7d5e03cSMatthew Dillon * Get the rssi value from BB on ctl chain0.
497b7d5e03cSMatthew Dillon */
498b7d5e03cSMatthew Dillon u_int32_t
ar9300_get_rssi_chain0(struct ath_hal * ah)499b7d5e03cSMatthew Dillon ar9300_get_rssi_chain0(struct ath_hal *ah)
500b7d5e03cSMatthew Dillon {
501b7d5e03cSMatthew Dillon /* get ctl chain0 RSSI */
502b7d5e03cSMatthew Dillon return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff;
503b7d5e03cSMatthew Dillon }
504b7d5e03cSMatthew Dillon #endif
505b7d5e03cSMatthew Dillon
506b7d5e03cSMatthew Dillon u_int
ar9300_get_def_antenna(struct ath_hal * ah)507b7d5e03cSMatthew Dillon ar9300_get_def_antenna(struct ath_hal *ah)
508b7d5e03cSMatthew Dillon {
509b7d5e03cSMatthew Dillon return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
510b7d5e03cSMatthew Dillon }
511b7d5e03cSMatthew Dillon
512b7d5e03cSMatthew Dillon /* Setup coverage class */
513b7d5e03cSMatthew Dillon void
ar9300_set_coverage_class(struct ath_hal * ah,u_int8_t coverageclass,int now)514b7d5e03cSMatthew Dillon ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now)
515b7d5e03cSMatthew Dillon {
516b7d5e03cSMatthew Dillon }
517b7d5e03cSMatthew Dillon
518b7d5e03cSMatthew Dillon void
ar9300_set_def_antenna(struct ath_hal * ah,u_int antenna)519b7d5e03cSMatthew Dillon ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna)
520b7d5e03cSMatthew Dillon {
521b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
522b7d5e03cSMatthew Dillon }
523b7d5e03cSMatthew Dillon
524b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_set_antenna_switch(struct ath_hal * ah,HAL_ANT_SETTING settings,const struct ieee80211_channel * chan,u_int8_t * tx_chainmask,u_int8_t * rx_chainmask,u_int8_t * antenna_cfgd)525b7d5e03cSMatthew Dillon ar9300_set_antenna_switch(struct ath_hal *ah,
526b7d5e03cSMatthew Dillon HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
527b7d5e03cSMatthew Dillon u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd)
528b7d5e03cSMatthew Dillon {
529b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
530b7d5e03cSMatthew Dillon
531b7d5e03cSMatthew Dillon /*
532b7d5e03cSMatthew Dillon * Owl does not support diversity or changing antennas.
533b7d5e03cSMatthew Dillon *
534b7d5e03cSMatthew Dillon * Instead this API and function are defined differently for AR9300.
535b7d5e03cSMatthew Dillon * To support Tablet PC's, this interface allows the system
536b7d5e03cSMatthew Dillon * to dramatically reduce the TX power on a particular chain.
537b7d5e03cSMatthew Dillon *
538b7d5e03cSMatthew Dillon * Based on the value of (redefined) diversity_control, the
539b7d5e03cSMatthew Dillon * reset code will decrease power on chain 0 or chain 1/2.
540b7d5e03cSMatthew Dillon *
541b7d5e03cSMatthew Dillon * Based on the value of bit 0 of antenna_switch_swap,
542b7d5e03cSMatthew Dillon * the mapping between OID call and chain is defined as:
543b7d5e03cSMatthew Dillon * 0: map A -> 0, B -> 1;
544b7d5e03cSMatthew Dillon * 1: map A -> 1, B -> 0;
545b7d5e03cSMatthew Dillon *
546b7d5e03cSMatthew Dillon * NOTE:
547b7d5e03cSMatthew Dillon * The devices that use this OID should use a tx_chain_mask and
548b7d5e03cSMatthew Dillon * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is
549b7d5e03cSMatthew Dillon * used in order to ensure an active transmit antenna. This
550b7d5e03cSMatthew Dillon * API will allow the host to turn off the only transmitting
551b7d5e03cSMatthew Dillon * antenna to ensure the antenna closest to the user's body is
552b7d5e03cSMatthew Dillon * powered-down.
553b7d5e03cSMatthew Dillon */
554b7d5e03cSMatthew Dillon /*
555b7d5e03cSMatthew Dillon * Set antenna control for use during reset sequence by
556b7d5e03cSMatthew Dillon * ar9300_decrease_chain_power()
557b7d5e03cSMatthew Dillon */
558b7d5e03cSMatthew Dillon ahp->ah_diversity_control = settings;
559b7d5e03cSMatthew Dillon
560b7d5e03cSMatthew Dillon return AH_TRUE;
561b7d5e03cSMatthew Dillon }
562b7d5e03cSMatthew Dillon
563b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_is_sleep_after_beacon_broken(struct ath_hal * ah)564b7d5e03cSMatthew Dillon ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah)
565b7d5e03cSMatthew Dillon {
566b7d5e03cSMatthew Dillon return AH_TRUE;
567b7d5e03cSMatthew Dillon }
568b7d5e03cSMatthew Dillon
569b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_set_slot_time(struct ath_hal * ah,u_int us)570b7d5e03cSMatthew Dillon ar9300_set_slot_time(struct ath_hal *ah, u_int us)
571b7d5e03cSMatthew Dillon {
572b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
573b7d5e03cSMatthew Dillon if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) {
574b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us);
575b7d5e03cSMatthew Dillon ahp->ah_slot_time = (u_int) -1; /* restore default handling */
576b7d5e03cSMatthew Dillon return AH_FALSE;
577b7d5e03cSMatthew Dillon } else {
578b7d5e03cSMatthew Dillon /* convert to system clocks */
579b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us));
580b7d5e03cSMatthew Dillon ahp->ah_slot_time = us;
581b7d5e03cSMatthew Dillon return AH_TRUE;
582b7d5e03cSMatthew Dillon }
583b7d5e03cSMatthew Dillon }
584b7d5e03cSMatthew Dillon
585b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_set_ack_timeout(struct ath_hal * ah,u_int us)586b7d5e03cSMatthew Dillon ar9300_set_ack_timeout(struct ath_hal *ah, u_int us)
587b7d5e03cSMatthew Dillon {
588b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
589b7d5e03cSMatthew Dillon
590b7d5e03cSMatthew Dillon if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
591b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us);
592b7d5e03cSMatthew Dillon ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */
593b7d5e03cSMatthew Dillon return AH_FALSE;
594b7d5e03cSMatthew Dillon } else {
595b7d5e03cSMatthew Dillon /* convert to system clocks */
596b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah,
597b7d5e03cSMatthew Dillon AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us));
598b7d5e03cSMatthew Dillon ahp->ah_ack_timeout = us;
599b7d5e03cSMatthew Dillon return AH_TRUE;
600b7d5e03cSMatthew Dillon }
601b7d5e03cSMatthew Dillon }
602b7d5e03cSMatthew Dillon
603b7d5e03cSMatthew Dillon u_int
ar9300_get_ack_timeout(struct ath_hal * ah)604b7d5e03cSMatthew Dillon ar9300_get_ack_timeout(struct ath_hal *ah)
605b7d5e03cSMatthew Dillon {
606b7d5e03cSMatthew Dillon u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
607b7d5e03cSMatthew Dillon return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */
608b7d5e03cSMatthew Dillon }
609b7d5e03cSMatthew Dillon
610b7d5e03cSMatthew Dillon HAL_STATUS
ar9300_set_quiet(struct ath_hal * ah,u_int32_t period,u_int32_t duration,u_int32_t next_start,HAL_QUIET_FLAG flag)611b7d5e03cSMatthew Dillon ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
612b7d5e03cSMatthew Dillon u_int32_t next_start, HAL_QUIET_FLAG flag)
613b7d5e03cSMatthew Dillon {
614b7d5e03cSMatthew Dillon #define TU_TO_USEC(_tu) ((_tu) << 10)
615b7d5e03cSMatthew Dillon HAL_STATUS status = HAL_EIO;
616b7d5e03cSMatthew Dillon u_int32_t tsf = 0, j, next_start_us = 0;
617b7d5e03cSMatthew Dillon if (flag & HAL_QUIET_ENABLE) {
618b7d5e03cSMatthew Dillon for (j = 0; j < 2; j++) {
619b7d5e03cSMatthew Dillon next_start_us = TU_TO_USEC(next_start);
620b7d5e03cSMatthew Dillon tsf = OS_REG_READ(ah, AR_TSF_L32);
621b7d5e03cSMatthew Dillon if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) {
622b7d5e03cSMatthew Dillon next_start_us += tsf;
623b7d5e03cSMatthew Dillon }
624b7d5e03cSMatthew Dillon if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) {
625b7d5e03cSMatthew Dillon next_start_us +=
626b7d5e03cSMatthew Dillon ah->ah_config.ah_sw_beacon_response_time;
627b7d5e03cSMatthew Dillon }
628b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
629b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR));
630b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period));
631b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us);
632b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
633b7d5e03cSMatthew Dillon if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) {
634b7d5e03cSMatthew Dillon status = HAL_OK;
635b7d5e03cSMatthew Dillon break;
636b7d5e03cSMatthew Dillon }
637b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved "
638b7d5e03cSMatthew Dillon "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf);
639b7d5e03cSMatthew Dillon /* TSF shouldn't count twice or reg access is taking forever */
640b7d5e03cSMatthew Dillon HALASSERT(j < 1);
641b7d5e03cSMatthew Dillon }
642b7d5e03cSMatthew Dillon } else {
643b7d5e03cSMatthew Dillon OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
644b7d5e03cSMatthew Dillon status = HAL_OK;
645b7d5e03cSMatthew Dillon }
646b7d5e03cSMatthew Dillon
647b7d5e03cSMatthew Dillon return status;
648b7d5e03cSMatthew Dillon #undef TU_TO_USEC
649b7d5e03cSMatthew Dillon }
650b7d5e03cSMatthew Dillon #ifdef ATH_SUPPORT_DFS
651b7d5e03cSMatthew Dillon void
ar9300_cac_tx_quiet(struct ath_hal * ah,HAL_BOOL enable)652b7d5e03cSMatthew Dillon ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable)
653b7d5e03cSMatthew Dillon {
654b7d5e03cSMatthew Dillon u32 reg1, reg2;
655b7d5e03cSMatthew Dillon
656b7d5e03cSMatthew Dillon reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE));
657b7d5e03cSMatthew Dillon reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1));
658b7d5e03cSMatthew Dillon AH9300(ah)->ah_cac_quiet_enabled = enable;
659b7d5e03cSMatthew Dillon
660b7d5e03cSMatthew Dillon if (enable) {
661b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE),
662b7d5e03cSMatthew Dillon reg1 | AR_PCU_FORCE_QUIET_COLL);
663b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1),
664b7d5e03cSMatthew Dillon reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE);
665b7d5e03cSMatthew Dillon } else {
666b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE),
667b7d5e03cSMatthew Dillon reg1 & ~AR_PCU_FORCE_QUIET_COLL);
668b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1),
669b7d5e03cSMatthew Dillon reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE);
670b7d5e03cSMatthew Dillon }
671b7d5e03cSMatthew Dillon }
672b7d5e03cSMatthew Dillon #endif /* ATH_SUPPORT_DFS */
673b7d5e03cSMatthew Dillon
674b7d5e03cSMatthew Dillon void
ar9300_set_pcu_config(struct ath_hal * ah)675b7d5e03cSMatthew Dillon ar9300_set_pcu_config(struct ath_hal *ah)
676b7d5e03cSMatthew Dillon {
677b7d5e03cSMatthew Dillon ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode);
678b7d5e03cSMatthew Dillon }
679b7d5e03cSMatthew Dillon
680b7d5e03cSMatthew Dillon HAL_STATUS
ar9300_get_capability(struct ath_hal * ah,HAL_CAPABILITY_TYPE type,u_int32_t capability,u_int32_t * result)681b7d5e03cSMatthew Dillon ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
682b7d5e03cSMatthew Dillon u_int32_t capability, u_int32_t *result)
683b7d5e03cSMatthew Dillon {
684b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
685b7d5e03cSMatthew Dillon const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
686a20e5e51SMatthew Dillon struct ar9300_ani_state *ani;
687b7d5e03cSMatthew Dillon
688b7d5e03cSMatthew Dillon switch (type) {
689b7d5e03cSMatthew Dillon case HAL_CAP_CIPHER: /* cipher handled in hardware */
690b7d5e03cSMatthew Dillon switch (capability) {
691b7d5e03cSMatthew Dillon case HAL_CIPHER_AES_CCM:
692b7d5e03cSMatthew Dillon case HAL_CIPHER_AES_OCB:
693b7d5e03cSMatthew Dillon case HAL_CIPHER_TKIP:
694b7d5e03cSMatthew Dillon case HAL_CIPHER_WEP:
695b7d5e03cSMatthew Dillon case HAL_CIPHER_MIC:
696b7d5e03cSMatthew Dillon case HAL_CIPHER_CLR:
697b7d5e03cSMatthew Dillon return HAL_OK;
698b7d5e03cSMatthew Dillon default:
699b7d5e03cSMatthew Dillon return HAL_ENOTSUPP;
700b7d5e03cSMatthew Dillon }
701b7d5e03cSMatthew Dillon case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
702b7d5e03cSMatthew Dillon switch (capability) {
703b7d5e03cSMatthew Dillon case 0: /* hardware capability */
704b7d5e03cSMatthew Dillon return HAL_OK;
705b7d5e03cSMatthew Dillon case 1:
706b7d5e03cSMatthew Dillon return (ahp->ah_sta_id1_defaults &
707b7d5e03cSMatthew Dillon AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
708b7d5e03cSMatthew Dillon default:
709b7d5e03cSMatthew Dillon return HAL_ENOTSUPP;
710b7d5e03cSMatthew Dillon }
711b7d5e03cSMatthew Dillon case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
712b7d5e03cSMatthew Dillon switch (capability) {
713b7d5e03cSMatthew Dillon case 0: /* hardware capability */
714b7d5e03cSMatthew Dillon return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
715b7d5e03cSMatthew Dillon case 1: /* current setting */
716b7d5e03cSMatthew Dillon return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
717b7d5e03cSMatthew Dillon HAL_ENXIO : HAL_OK;
718b7d5e03cSMatthew Dillon default:
719b7d5e03cSMatthew Dillon return HAL_ENOTSUPP;
720b7d5e03cSMatthew Dillon }
721b7d5e03cSMatthew Dillon case HAL_CAP_WME_TKIPMIC:
722b7d5e03cSMatthew Dillon /* hardware can do TKIP MIC when WMM is turned on */
723b7d5e03cSMatthew Dillon return HAL_OK;
724b7d5e03cSMatthew Dillon case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */
725b7d5e03cSMatthew Dillon return HAL_OK;
726b7d5e03cSMatthew Dillon case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
727b7d5e03cSMatthew Dillon switch (capability) {
728b7d5e03cSMatthew Dillon case 0: /* hardware capability */
729b7d5e03cSMatthew Dillon return HAL_OK;
730b7d5e03cSMatthew Dillon case 1: /* current setting */
731b7d5e03cSMatthew Dillon return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) &
732b7d5e03cSMatthew Dillon AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
733b7d5e03cSMatthew Dillon HAL_OK : HAL_ENXIO;
734b7d5e03cSMatthew Dillon }
735b7d5e03cSMatthew Dillon return HAL_EINVAL;
736b7d5e03cSMatthew Dillon case HAL_CAP_TPC:
737b7d5e03cSMatthew Dillon switch (capability) {
738b7d5e03cSMatthew Dillon case 0: /* hardware capability */
739b7d5e03cSMatthew Dillon return HAL_OK;
740b7d5e03cSMatthew Dillon case 1:
741b7d5e03cSMatthew Dillon return ah->ah_config.ath_hal_desc_tpc ?
742b7d5e03cSMatthew Dillon HAL_OK : HAL_ENXIO;
743b7d5e03cSMatthew Dillon }
744b7d5e03cSMatthew Dillon return HAL_OK;
745b7d5e03cSMatthew Dillon case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
746b7d5e03cSMatthew Dillon return HAL_OK;
747b7d5e03cSMatthew Dillon case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
748b7d5e03cSMatthew Dillon switch (capability) {
749b7d5e03cSMatthew Dillon case 0: /* hardware capability */
750b7d5e03cSMatthew Dillon return HAL_OK;
751b7d5e03cSMatthew Dillon case 1:
752b7d5e03cSMatthew Dillon if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
753b7d5e03cSMatthew Dillon /*
754b7d5e03cSMatthew Dillon * Owl and Merlin have problems in mcast key search.
755b7d5e03cSMatthew Dillon * Disable this cap. in Ad-hoc mode. see Bug 25776 and
756b7d5e03cSMatthew Dillon * 26802
757b7d5e03cSMatthew Dillon */
758b7d5e03cSMatthew Dillon return HAL_ENXIO;
759b7d5e03cSMatthew Dillon } else {
760b7d5e03cSMatthew Dillon return (ahp->ah_sta_id1_defaults &
761b7d5e03cSMatthew Dillon AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
762b7d5e03cSMatthew Dillon }
763b7d5e03cSMatthew Dillon }
764b7d5e03cSMatthew Dillon return HAL_EINVAL;
765b7d5e03cSMatthew Dillon case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
766b7d5e03cSMatthew Dillon switch (capability) {
767b7d5e03cSMatthew Dillon case 0: /* hardware capability */
768b7d5e03cSMatthew Dillon return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
769b7d5e03cSMatthew Dillon case 1:
770b7d5e03cSMatthew Dillon return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ?
771b7d5e03cSMatthew Dillon HAL_OK : HAL_ENXIO;
772b7d5e03cSMatthew Dillon }
773b7d5e03cSMatthew Dillon return HAL_EINVAL;
774b7d5e03cSMatthew Dillon case HAL_CAP_RFSILENT: /* rfsilent support */
775b7d5e03cSMatthew Dillon if (capability == 3) { /* rfkill interrupt */
776b7d5e03cSMatthew Dillon /*
777b7d5e03cSMatthew Dillon * XXX: Interrupt-based notification of RF Kill state
778b7d5e03cSMatthew Dillon * changes not working yet. Report that this feature
779b7d5e03cSMatthew Dillon * is not supported so that polling is used instead.
780b7d5e03cSMatthew Dillon */
781b7d5e03cSMatthew Dillon return (HAL_ENOTSUPP);
782b7d5e03cSMatthew Dillon }
783b7d5e03cSMatthew Dillon return ath_hal_getcapability(ah, type, capability, result);
784b7d5e03cSMatthew Dillon case HAL_CAP_4ADDR_AGGR:
785b7d5e03cSMatthew Dillon return HAL_OK;
786b7d5e03cSMatthew Dillon case HAL_CAP_BB_RIFS_HANG:
787b7d5e03cSMatthew Dillon return HAL_ENOTSUPP;
788b7d5e03cSMatthew Dillon case HAL_CAP_BB_DFS_HANG:
789b7d5e03cSMatthew Dillon return HAL_ENOTSUPP;
790b7d5e03cSMatthew Dillon case HAL_CAP_BB_RX_CLEAR_STUCK_HANG:
791b7d5e03cSMatthew Dillon /* Track chips that are known to have BB hangs related
792b7d5e03cSMatthew Dillon * to rx_clear stuck low.
793b7d5e03cSMatthew Dillon */
794b7d5e03cSMatthew Dillon return HAL_ENOTSUPP;
795b7d5e03cSMatthew Dillon case HAL_CAP_MAC_HANG:
796b7d5e03cSMatthew Dillon /* Track chips that are known to have MAC hangs.
797b7d5e03cSMatthew Dillon */
798b7d5e03cSMatthew Dillon return HAL_OK;
799b7d5e03cSMatthew Dillon case HAL_CAP_RIFS_RX_ENABLED:
800b7d5e03cSMatthew Dillon /* Is RIFS RX currently enabled */
801b7d5e03cSMatthew Dillon return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
802b7d5e03cSMatthew Dillon #if 0
803b7d5e03cSMatthew Dillon case HAL_CAP_ANT_CFG_2GHZ:
804b7d5e03cSMatthew Dillon *result = p_cap->halNumAntCfg2Ghz;
805b7d5e03cSMatthew Dillon return HAL_OK;
806b7d5e03cSMatthew Dillon case HAL_CAP_ANT_CFG_5GHZ:
807b7d5e03cSMatthew Dillon *result = p_cap->halNumAntCfg5Ghz;
808b7d5e03cSMatthew Dillon return HAL_OK;
809b7d5e03cSMatthew Dillon case HAL_CAP_RX_STBC:
810b7d5e03cSMatthew Dillon *result = p_cap->hal_rx_stbc_support;
811b7d5e03cSMatthew Dillon return HAL_OK;
812b7d5e03cSMatthew Dillon case HAL_CAP_TX_STBC:
813b7d5e03cSMatthew Dillon *result = p_cap->hal_tx_stbc_support;
814b7d5e03cSMatthew Dillon return HAL_OK;
815b7d5e03cSMatthew Dillon #endif
816b7d5e03cSMatthew Dillon case HAL_CAP_LDPC:
817b7d5e03cSMatthew Dillon *result = p_cap->halLDPCSupport;
818b7d5e03cSMatthew Dillon return HAL_OK;
819b7d5e03cSMatthew Dillon case HAL_CAP_DYNAMIC_SMPS:
820b7d5e03cSMatthew Dillon return HAL_OK;
821b7d5e03cSMatthew Dillon case HAL_CAP_DS:
822b7d5e03cSMatthew Dillon return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
823b7d5e03cSMatthew Dillon (p_cap->halTxChainMask & 0x3) != 0x3 ||
824b7d5e03cSMatthew Dillon (p_cap->halRxChainMask & 0x3) != 0x3) ?
825b7d5e03cSMatthew Dillon HAL_ENOTSUPP : HAL_OK;
826b7d5e03cSMatthew Dillon case HAL_CAP_TS:
827b7d5e03cSMatthew Dillon return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) ||
828b7d5e03cSMatthew Dillon (p_cap->halTxChainMask & 0x7) != 0x7 ||
829b7d5e03cSMatthew Dillon (p_cap->halRxChainMask & 0x7) != 0x7) ?
830b7d5e03cSMatthew Dillon HAL_ENOTSUPP : HAL_OK;
831b7d5e03cSMatthew Dillon case HAL_CAP_OL_PWRCTRL:
832b7d5e03cSMatthew Dillon return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ?
833b7d5e03cSMatthew Dillon HAL_OK : HAL_ENOTSUPP;
834b7d5e03cSMatthew Dillon case HAL_CAP_CRDC:
835b7d5e03cSMatthew Dillon #if ATH_SUPPORT_CRDC
836b7d5e03cSMatthew Dillon return (AR_SREV_WASP(ah) &&
837b7d5e03cSMatthew Dillon ah->ah_config.ath_hal_crdc_enable) ?
838b7d5e03cSMatthew Dillon HAL_OK : HAL_ENOTSUPP;
839b7d5e03cSMatthew Dillon #else
840b7d5e03cSMatthew Dillon return HAL_ENOTSUPP;
841b7d5e03cSMatthew Dillon #endif
842b7d5e03cSMatthew Dillon #if 0
843b7d5e03cSMatthew Dillon case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS:
844b7d5e03cSMatthew Dillon *result = (u_int32_t)(-1);
845b7d5e03cSMatthew Dillon return HAL_OK;
846b7d5e03cSMatthew Dillon case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS:
847b7d5e03cSMatthew Dillon *result = (u_int32_t)(-1);
848b7d5e03cSMatthew Dillon return HAL_OK;
849b7d5e03cSMatthew Dillon #endif
850b7d5e03cSMatthew Dillon case HAL_CAP_BB_PANIC_WATCHDOG:
851b7d5e03cSMatthew Dillon return HAL_OK;
852b7d5e03cSMatthew Dillon case HAL_CAP_PHYRESTART_CLR_WAR:
853b7d5e03cSMatthew Dillon if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) &&
854b7d5e03cSMatthew Dillon (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10))
855b7d5e03cSMatthew Dillon {
856b7d5e03cSMatthew Dillon return HAL_OK;
857b7d5e03cSMatthew Dillon }
858b7d5e03cSMatthew Dillon else
859b7d5e03cSMatthew Dillon {
860b7d5e03cSMatthew Dillon return HAL_ENOTSUPP;
861b7d5e03cSMatthew Dillon }
862b7d5e03cSMatthew Dillon case HAL_CAP_ENTERPRISE_MODE:
863b7d5e03cSMatthew Dillon *result = ahp->ah_enterprise_mode >> 16;
864b7d5e03cSMatthew Dillon /*
865b7d5e03cSMatthew Dillon * WAR for EV 77658 - Add delimiters to first sub-frame when using
866b7d5e03cSMatthew Dillon * RTS/CTS with aggregation and non-enterprise Osprey.
867b7d5e03cSMatthew Dillon *
868b7d5e03cSMatthew Dillon * Bug fixed in AR9580/Peacock, Wasp1.1 and later
869b7d5e03cSMatthew Dillon */
870b7d5e03cSMatthew Dillon if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) &&
871b7d5e03cSMatthew Dillon !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) ||
872b7d5e03cSMatthew Dillon AR_SREV_WASP_10(ah))) {
873b7d5e03cSMatthew Dillon *result |= AH_ENT_RTSCTS_DELIM_WAR;
874b7d5e03cSMatthew Dillon }
875b7d5e03cSMatthew Dillon return HAL_OK;
876b7d5e03cSMatthew Dillon case HAL_CAP_LDPCWAR:
877b7d5e03cSMatthew Dillon /* WAR for RIFS+LDPC issue is required for all chips currently
878b7d5e03cSMatthew Dillon * supported by ar9300 HAL.
879b7d5e03cSMatthew Dillon */
880b7d5e03cSMatthew Dillon return HAL_OK;
881b7d5e03cSMatthew Dillon case HAL_CAP_ENABLE_APM:
882b7d5e03cSMatthew Dillon *result = p_cap->halApmEnable;
883b7d5e03cSMatthew Dillon return HAL_OK;
884b7d5e03cSMatthew Dillon case HAL_CAP_PCIE_LCR_EXTSYNC_EN:
885b7d5e03cSMatthew Dillon return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
886b7d5e03cSMatthew Dillon case HAL_CAP_PCIE_LCR_OFFSET:
887b7d5e03cSMatthew Dillon *result = p_cap->hal_pcie_lcr_offset;
888b7d5e03cSMatthew Dillon return HAL_OK;
889b7d5e03cSMatthew Dillon case HAL_CAP_SMARTANTENNA:
890b7d5e03cSMatthew Dillon /* FIXME A request is pending with h/w team to add feature bit in
891b7d5e03cSMatthew Dillon * caldata to detect if board has smart antenna or not, once added
892b7d5e03cSMatthew Dillon * we need to fix his piece of code to read and return value without
893b7d5e03cSMatthew Dillon * any compile flags
894b7d5e03cSMatthew Dillon */
895b7d5e03cSMatthew Dillon #if UMAC_SUPPORT_SMARTANTENNA
896b7d5e03cSMatthew Dillon /* enable smart antenna for Peacock, Wasp and scorpion
897b7d5e03cSMatthew Dillon for future chips need to modify */
898b7d5e03cSMatthew Dillon if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) {
899b7d5e03cSMatthew Dillon return HAL_OK;
900b7d5e03cSMatthew Dillon } else {
901b7d5e03cSMatthew Dillon return HAL_ENOTSUPP;
902b7d5e03cSMatthew Dillon }
903b7d5e03cSMatthew Dillon #else
904b7d5e03cSMatthew Dillon return HAL_ENOTSUPP;
905b7d5e03cSMatthew Dillon #endif
906b7d5e03cSMatthew Dillon
907b7d5e03cSMatthew Dillon #ifdef ATH_TRAFFIC_FAST_RECOVER
908b7d5e03cSMatthew Dillon case HAL_CAP_TRAFFIC_FAST_RECOVER:
909b7d5e03cSMatthew Dillon if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) {
910b7d5e03cSMatthew Dillon return HAL_OK;
911b7d5e03cSMatthew Dillon } else {
912b7d5e03cSMatthew Dillon return HAL_ENOTSUPP;
913b7d5e03cSMatthew Dillon }
914b7d5e03cSMatthew Dillon #endif
915a20e5e51SMatthew Dillon
916a20e5e51SMatthew Dillon /* FreeBSD ANI */
917a20e5e51SMatthew Dillon case HAL_CAP_INTMIT: /* interference mitigation */
918a20e5e51SMatthew Dillon switch (capability) {
919a20e5e51SMatthew Dillon case HAL_CAP_INTMIT_PRESENT: /* hardware capability */
920a20e5e51SMatthew Dillon return HAL_OK;
921a20e5e51SMatthew Dillon case HAL_CAP_INTMIT_ENABLE:
922a20e5e51SMatthew Dillon return (ahp->ah_proc_phy_err & HAL_PROCESS_ANI) ?
923a20e5e51SMatthew Dillon HAL_OK : HAL_ENXIO;
924a20e5e51SMatthew Dillon case HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL:
925a20e5e51SMatthew Dillon case HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL:
926a20e5e51SMatthew Dillon // case HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR:
927a20e5e51SMatthew Dillon case HAL_CAP_INTMIT_FIRSTEP_LEVEL:
928a20e5e51SMatthew Dillon case HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL:
929a20e5e51SMatthew Dillon ani = ar9300_ani_get_current_state(ah);
930a20e5e51SMatthew Dillon if (ani == AH_NULL)
931a20e5e51SMatthew Dillon return HAL_ENXIO;
932a20e5e51SMatthew Dillon switch (capability) {
933a20e5e51SMatthew Dillon /* XXX AR9300 HAL has OFDM/CCK noise immunity level params? */
934a20e5e51SMatthew Dillon case 2: *result = ani->ofdm_noise_immunity_level; break;
935a20e5e51SMatthew Dillon case 3: *result = !ani->ofdm_weak_sig_detect_off; break;
936a20e5e51SMatthew Dillon // case 4: *result = ani->cck_weak_sig_threshold; break;
937a20e5e51SMatthew Dillon case 5: *result = ani->firstep_level; break;
938a20e5e51SMatthew Dillon case 6: *result = ani->spur_immunity_level; break;
939a20e5e51SMatthew Dillon }
940a20e5e51SMatthew Dillon return HAL_OK;
941a20e5e51SMatthew Dillon }
942a20e5e51SMatthew Dillon return HAL_EINVAL;
943a20e5e51SMatthew Dillon case HAL_CAP_ENFORCE_TXOP:
944a20e5e51SMatthew Dillon if (capability == 0)
945a20e5e51SMatthew Dillon return (HAL_OK);
946a20e5e51SMatthew Dillon if (capability != 1)
947a20e5e51SMatthew Dillon return (HAL_ENOTSUPP);
948a20e5e51SMatthew Dillon (*result) = !! (ahp->ah_misc_mode & AR_PCU_TXOP_TBTT_LIMIT_ENA);
949a20e5e51SMatthew Dillon return (HAL_OK);
950b7d5e03cSMatthew Dillon default:
951b7d5e03cSMatthew Dillon return ath_hal_getcapability(ah, type, capability, result);
952b7d5e03cSMatthew Dillon }
953b7d5e03cSMatthew Dillon }
954b7d5e03cSMatthew Dillon
955b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_set_capability(struct ath_hal * ah,HAL_CAPABILITY_TYPE type,u_int32_t capability,u_int32_t setting,HAL_STATUS * status)956b7d5e03cSMatthew Dillon ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
957b7d5e03cSMatthew Dillon u_int32_t capability, u_int32_t setting, HAL_STATUS *status)
958b7d5e03cSMatthew Dillon {
959b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
960b7d5e03cSMatthew Dillon const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
961b7d5e03cSMatthew Dillon u_int32_t v;
962b7d5e03cSMatthew Dillon
963b7d5e03cSMatthew Dillon switch (type) {
964b7d5e03cSMatthew Dillon case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
965b7d5e03cSMatthew Dillon if (! p_cap->halTkipMicTxRxKeySupport)
966b7d5e03cSMatthew Dillon return AH_FALSE;
967b7d5e03cSMatthew Dillon
968b7d5e03cSMatthew Dillon if (setting)
969b7d5e03cSMatthew Dillon ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA;
970b7d5e03cSMatthew Dillon else
971b7d5e03cSMatthew Dillon ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
972b7d5e03cSMatthew Dillon
973b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode);
974b7d5e03cSMatthew Dillon return AH_TRUE;
975b7d5e03cSMatthew Dillon
976b7d5e03cSMatthew Dillon case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
977b7d5e03cSMatthew Dillon if (setting) {
978b7d5e03cSMatthew Dillon ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
979b7d5e03cSMatthew Dillon } else {
980b7d5e03cSMatthew Dillon ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
981b7d5e03cSMatthew Dillon }
982b7d5e03cSMatthew Dillon return AH_TRUE;
983b7d5e03cSMatthew Dillon case HAL_CAP_DIVERSITY:
984b7d5e03cSMatthew Dillon v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
985b7d5e03cSMatthew Dillon if (setting) {
986b7d5e03cSMatthew Dillon v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
987b7d5e03cSMatthew Dillon } else {
988b7d5e03cSMatthew Dillon v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
989b7d5e03cSMatthew Dillon }
990b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
991b7d5e03cSMatthew Dillon return AH_TRUE;
992b7d5e03cSMatthew Dillon case HAL_CAP_DIAG: /* hardware diagnostic support */
993b7d5e03cSMatthew Dillon /*
994b7d5e03cSMatthew Dillon * NB: could split this up into virtual capabilities,
995b7d5e03cSMatthew Dillon * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
996b7d5e03cSMatthew Dillon * seems worth the additional complexity.
997b7d5e03cSMatthew Dillon */
998b7d5e03cSMatthew Dillon #ifdef AH_DEBUG
999b7d5e03cSMatthew Dillon AH_PRIVATE(ah)->ah_diagreg = setting;
1000b7d5e03cSMatthew Dillon #else
1001b7d5e03cSMatthew Dillon AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */
1002b7d5e03cSMatthew Dillon #endif
1003b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
1004b7d5e03cSMatthew Dillon return AH_TRUE;
1005b7d5e03cSMatthew Dillon case HAL_CAP_TPC:
1006b7d5e03cSMatthew Dillon ah->ah_config.ath_hal_desc_tpc = (setting != 0);
1007b7d5e03cSMatthew Dillon return AH_TRUE;
1008b7d5e03cSMatthew Dillon case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
1009b7d5e03cSMatthew Dillon if (setting) {
1010b7d5e03cSMatthew Dillon ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
1011b7d5e03cSMatthew Dillon } else {
1012b7d5e03cSMatthew Dillon ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1013b7d5e03cSMatthew Dillon }
1014b7d5e03cSMatthew Dillon return AH_TRUE;
1015b7d5e03cSMatthew Dillon case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
1016b7d5e03cSMatthew Dillon if (p_cap->halTsfAddSupport) {
1017b7d5e03cSMatthew Dillon if (setting) {
1018b7d5e03cSMatthew Dillon ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF;
1019b7d5e03cSMatthew Dillon } else {
1020b7d5e03cSMatthew Dillon ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF;
1021b7d5e03cSMatthew Dillon }
1022b7d5e03cSMatthew Dillon return AH_TRUE;
1023b7d5e03cSMatthew Dillon }
1024b7d5e03cSMatthew Dillon return AH_FALSE;
1025a20e5e51SMatthew Dillon
1026a20e5e51SMatthew Dillon /* FreeBSD interrupt mitigation / ANI */
1027a20e5e51SMatthew Dillon case HAL_CAP_INTMIT: { /* interference mitigation */
1028a20e5e51SMatthew Dillon /* This maps the public ANI commands to the internal ANI commands */
1029a20e5e51SMatthew Dillon /* Private: HAL_ANI_CMD; Public: HAL_CAP_INTMIT_CMD */
1030a20e5e51SMatthew Dillon static const HAL_ANI_CMD cmds[] = {
1031a20e5e51SMatthew Dillon HAL_ANI_PRESENT,
1032a20e5e51SMatthew Dillon HAL_ANI_MODE,
1033a20e5e51SMatthew Dillon HAL_ANI_NOISE_IMMUNITY_LEVEL,
1034a20e5e51SMatthew Dillon HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
1035a20e5e51SMatthew Dillon HAL_ANI_CCK_WEAK_SIGNAL_THR,
1036a20e5e51SMatthew Dillon HAL_ANI_FIRSTEP_LEVEL,
1037a20e5e51SMatthew Dillon HAL_ANI_SPUR_IMMUNITY_LEVEL,
1038a20e5e51SMatthew Dillon };
1039*249483dfSAaron LI return capability < nitems(cmds) ?
1040a20e5e51SMatthew Dillon ar9300_ani_control(ah, cmds[capability], setting) :
1041a20e5e51SMatthew Dillon AH_FALSE;
1042a20e5e51SMatthew Dillon }
1043a20e5e51SMatthew Dillon
1044b7d5e03cSMatthew Dillon case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */
1045b7d5e03cSMatthew Dillon ahp->rx_buf_size = setting & AR_DATABUF_MASK;
1046b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size);
1047b7d5e03cSMatthew Dillon return AH_TRUE;
1048b7d5e03cSMatthew Dillon
1049a20e5e51SMatthew Dillon case HAL_CAP_ENFORCE_TXOP:
1050a20e5e51SMatthew Dillon if (capability != 1)
1051a20e5e51SMatthew Dillon return AH_FALSE;
1052a20e5e51SMatthew Dillon if (setting) {
1053a20e5e51SMatthew Dillon ahp->ah_misc_mode |= AR_PCU_TXOP_TBTT_LIMIT_ENA;
1054a20e5e51SMatthew Dillon OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA);
1055a20e5e51SMatthew Dillon } else {
1056a20e5e51SMatthew Dillon ahp->ah_misc_mode &= ~AR_PCU_TXOP_TBTT_LIMIT_ENA;
1057a20e5e51SMatthew Dillon OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA);
1058a20e5e51SMatthew Dillon }
1059a20e5e51SMatthew Dillon return AH_TRUE;
1060a20e5e51SMatthew Dillon
1061b7d5e03cSMatthew Dillon /* fall thru... */
1062b7d5e03cSMatthew Dillon default:
1063b7d5e03cSMatthew Dillon return ath_hal_setcapability(ah, type, capability, setting, status);
1064b7d5e03cSMatthew Dillon }
1065b7d5e03cSMatthew Dillon }
1066b7d5e03cSMatthew Dillon
1067b7d5e03cSMatthew Dillon #ifdef AH_DEBUG
1068b7d5e03cSMatthew Dillon static void
ar9300_print_reg(struct ath_hal * ah,u_int32_t args)1069b7d5e03cSMatthew Dillon ar9300_print_reg(struct ath_hal *ah, u_int32_t args)
1070b7d5e03cSMatthew Dillon {
1071b7d5e03cSMatthew Dillon u_int32_t i = 0;
1072b7d5e03cSMatthew Dillon
1073b7d5e03cSMatthew Dillon /* Read 0x80d0 to trigger pcie analyzer */
1074b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1075b7d5e03cSMatthew Dillon "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0));
1076b7d5e03cSMatthew Dillon
1077b7d5e03cSMatthew Dillon if (args & HAL_DIAG_PRINT_REG_COUNTER) {
1078b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
1079b7d5e03cSMatthew Dillon u_int32_t tf, rf, rc, cc;
1080b7d5e03cSMatthew Dillon
1081b7d5e03cSMatthew Dillon tf = OS_REG_READ(ah, AR_TFCNT);
1082b7d5e03cSMatthew Dillon rf = OS_REG_READ(ah, AR_RFCNT);
1083b7d5e03cSMatthew Dillon rc = OS_REG_READ(ah, AR_RCCNT);
1084b7d5e03cSMatthew Dillon cc = OS_REG_READ(ah, AR_CCCNT);
1085b7d5e03cSMatthew Dillon
1086b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1087b7d5e03cSMatthew Dillon "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf);
1088b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1089b7d5e03cSMatthew Dillon "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf);
1090b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1091b7d5e03cSMatthew Dillon "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc);
1092b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1093b7d5e03cSMatthew Dillon "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc);
1094b7d5e03cSMatthew Dillon
1095b7d5e03cSMatthew Dillon ahp->last_tf = tf;
1096b7d5e03cSMatthew Dillon ahp->last_rf = rf;
1097b7d5e03cSMatthew Dillon ahp->last_rc = rc;
1098b7d5e03cSMatthew Dillon ahp->last_cc = cc;
1099b7d5e03cSMatthew Dillon
1100b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1101b7d5e03cSMatthew Dillon "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0));
1102b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1103b7d5e03cSMatthew Dillon "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1));
1104b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1105b7d5e03cSMatthew Dillon "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2));
1106b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1107b7d5e03cSMatthew Dillon "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3));
1108b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1109b7d5e03cSMatthew Dillon "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4));
1110b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1111b7d5e03cSMatthew Dillon "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5));
1112b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1113b7d5e03cSMatthew Dillon "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6));
1114b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1115b7d5e03cSMatthew Dillon "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7));
1116b7d5e03cSMatthew Dillon }
1117b7d5e03cSMatthew Dillon
1118b7d5e03cSMatthew Dillon if (args & HAL_DIAG_PRINT_REG_ALL) {
1119b7d5e03cSMatthew Dillon for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) {
1120b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1121b7d5e03cSMatthew Dillon i, OS_REG_READ(ah, i));
1122b7d5e03cSMatthew Dillon }
1123b7d5e03cSMatthew Dillon
1124b7d5e03cSMatthew Dillon for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) {
1125b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1126b7d5e03cSMatthew Dillon i, OS_REG_READ(ah, i));
1127b7d5e03cSMatthew Dillon }
1128b7d5e03cSMatthew Dillon
1129b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1130b7d5e03cSMatthew Dillon "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i));
1131b7d5e03cSMatthew Dillon
1132b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG,
1133b7d5e03cSMatthew Dillon "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i));
1134b7d5e03cSMatthew Dillon
1135b7d5e03cSMatthew Dillon for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) {
1136b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1137b7d5e03cSMatthew Dillon i, OS_REG_READ(ah, i));
1138b7d5e03cSMatthew Dillon }
1139b7d5e03cSMatthew Dillon
1140b7d5e03cSMatthew Dillon for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) {
1141b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1142b7d5e03cSMatthew Dillon i, OS_REG_READ(ah, i));
1143b7d5e03cSMatthew Dillon }
1144b7d5e03cSMatthew Dillon
1145b7d5e03cSMatthew Dillon for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) {
1146b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1147b7d5e03cSMatthew Dillon i, OS_REG_READ(ah, i));
1148b7d5e03cSMatthew Dillon }
1149b7d5e03cSMatthew Dillon
1150b7d5e03cSMatthew Dillon for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) {
1151b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1152b7d5e03cSMatthew Dillon i, OS_REG_READ(ah, i));
1153b7d5e03cSMatthew Dillon }
1154b7d5e03cSMatthew Dillon
1155b7d5e03cSMatthew Dillon for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) {
1156b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1157b7d5e03cSMatthew Dillon i, OS_REG_READ(ah, i));
1158b7d5e03cSMatthew Dillon }
1159b7d5e03cSMatthew Dillon
1160b7d5e03cSMatthew Dillon for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) {
1161b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1162b7d5e03cSMatthew Dillon i, OS_REG_READ(ah, i));
1163b7d5e03cSMatthew Dillon }
1164b7d5e03cSMatthew Dillon
1165b7d5e03cSMatthew Dillon for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) {
1166b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1167b7d5e03cSMatthew Dillon i, OS_REG_READ(ah, i));
1168b7d5e03cSMatthew Dillon }
1169b7d5e03cSMatthew Dillon
1170b7d5e03cSMatthew Dillon for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) {
1171b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1172b7d5e03cSMatthew Dillon i, OS_REG_READ(ah, i));
1173b7d5e03cSMatthew Dillon }
1174b7d5e03cSMatthew Dillon
1175b7d5e03cSMatthew Dillon for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) {
1176b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1177b7d5e03cSMatthew Dillon i, OS_REG_READ(ah, i));
1178b7d5e03cSMatthew Dillon }
1179b7d5e03cSMatthew Dillon
1180b7d5e03cSMatthew Dillon for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) {
1181b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1182b7d5e03cSMatthew Dillon i, OS_REG_READ(ah, i));
1183b7d5e03cSMatthew Dillon }
1184b7d5e03cSMatthew Dillon
1185b7d5e03cSMatthew Dillon for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) {
1186b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n",
1187b7d5e03cSMatthew Dillon i, OS_REG_READ(ah, i));
1188b7d5e03cSMatthew Dillon }
1189b7d5e03cSMatthew Dillon }
1190b7d5e03cSMatthew Dillon }
1191b7d5e03cSMatthew Dillon #endif
1192b7d5e03cSMatthew Dillon
1193b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_get_diag_state(struct ath_hal * ah,int request,const void * args,u_int32_t argsize,void ** result,u_int32_t * resultsize)1194b7d5e03cSMatthew Dillon ar9300_get_diag_state(struct ath_hal *ah, int request,
1195b7d5e03cSMatthew Dillon const void *args, u_int32_t argsize,
1196b7d5e03cSMatthew Dillon void **result, u_int32_t *resultsize)
1197b7d5e03cSMatthew Dillon {
1198b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
1199a20e5e51SMatthew Dillon struct ar9300_ani_state *ani;
1200b7d5e03cSMatthew Dillon
1201b7d5e03cSMatthew Dillon (void) ahp;
1202b7d5e03cSMatthew Dillon if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) {
1203b7d5e03cSMatthew Dillon return AH_TRUE;
1204b7d5e03cSMatthew Dillon }
1205b7d5e03cSMatthew Dillon switch (request) {
1206b7d5e03cSMatthew Dillon #ifdef AH_PRIVATE_DIAG
1207b7d5e03cSMatthew Dillon case HAL_DIAG_EEPROM:
1208b7d5e03cSMatthew Dillon *result = &ahp->ah_eeprom;
1209b7d5e03cSMatthew Dillon *resultsize = sizeof(ar9300_eeprom_t);
1210b7d5e03cSMatthew Dillon return AH_TRUE;
1211b7d5e03cSMatthew Dillon
1212b7d5e03cSMatthew Dillon #if 0 /* XXX - TODO */
1213b7d5e03cSMatthew Dillon case HAL_DIAG_EEPROM_EXP_11A:
1214b7d5e03cSMatthew Dillon case HAL_DIAG_EEPROM_EXP_11B:
1215b7d5e03cSMatthew Dillon case HAL_DIAG_EEPROM_EXP_11G:
1216b7d5e03cSMatthew Dillon pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A];
1217b7d5e03cSMatthew Dillon *result = pe->p_channels;
1218b7d5e03cSMatthew Dillon *resultsize = (*result == AH_NULL) ? 0 :
1219b7d5e03cSMatthew Dillon roundup(sizeof(u_int16_t) * pe->num_channels,
1220b7d5e03cSMatthew Dillon sizeof(u_int32_t)) +
1221b7d5e03cSMatthew Dillon sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels;
1222b7d5e03cSMatthew Dillon return AH_TRUE;
1223b7d5e03cSMatthew Dillon #endif
1224b7d5e03cSMatthew Dillon case HAL_DIAG_RFGAIN:
1225b7d5e03cSMatthew Dillon *result = &ahp->ah_gain_values;
1226b7d5e03cSMatthew Dillon *resultsize = sizeof(GAIN_VALUES);
1227b7d5e03cSMatthew Dillon return AH_TRUE;
1228b7d5e03cSMatthew Dillon case HAL_DIAG_RFGAIN_CURSTEP:
1229b7d5e03cSMatthew Dillon *result = (void *) ahp->ah_gain_values.curr_step;
1230b7d5e03cSMatthew Dillon *resultsize = (*result == AH_NULL) ?
1231b7d5e03cSMatthew Dillon 0 : sizeof(GAIN_OPTIMIZATION_STEP);
1232b7d5e03cSMatthew Dillon return AH_TRUE;
1233b7d5e03cSMatthew Dillon #if 0 /* XXX - TODO */
1234b7d5e03cSMatthew Dillon case HAL_DIAG_PCDAC:
1235b7d5e03cSMatthew Dillon *result = ahp->ah_pcdac_table;
1236b7d5e03cSMatthew Dillon *resultsize = ahp->ah_pcdac_table_size;
1237b7d5e03cSMatthew Dillon return AH_TRUE;
1238b7d5e03cSMatthew Dillon #endif
1239b7d5e03cSMatthew Dillon case HAL_DIAG_ANI_CURRENT:
1240a20e5e51SMatthew Dillon
1241a20e5e51SMatthew Dillon ani = ar9300_ani_get_current_state(ah);
1242a20e5e51SMatthew Dillon if (ani == AH_NULL)
1243a20e5e51SMatthew Dillon return AH_FALSE;
1244a20e5e51SMatthew Dillon /* Convert ar9300 HAL to FreeBSD HAL ANI state */
1245a20e5e51SMatthew Dillon /* XXX TODO: add all of these to the HAL ANI state structure */
1246a20e5e51SMatthew Dillon bzero(&ahp->ext_ani_state, sizeof(ahp->ext_ani_state));
1247a20e5e51SMatthew Dillon /* XXX should this be OFDM or CCK noise immunity level? */
1248a20e5e51SMatthew Dillon ahp->ext_ani_state.noiseImmunityLevel = ani->ofdm_noise_immunity_level;
1249a20e5e51SMatthew Dillon ahp->ext_ani_state.spurImmunityLevel = ani->spur_immunity_level;
1250a20e5e51SMatthew Dillon ahp->ext_ani_state.firstepLevel = ani->firstep_level;
1251a20e5e51SMatthew Dillon ahp->ext_ani_state.ofdmWeakSigDetectOff = ani->ofdm_weak_sig_detect_off;
1252a20e5e51SMatthew Dillon /* mrc_cck_off */
1253a20e5e51SMatthew Dillon /* cck_noise_immunity_level */
1254a20e5e51SMatthew Dillon
1255a20e5e51SMatthew Dillon ahp->ext_ani_state.listenTime = ani->listen_time;
1256a20e5e51SMatthew Dillon
1257a20e5e51SMatthew Dillon *result = &ahp->ext_ani_state;
1258a20e5e51SMatthew Dillon *resultsize = sizeof(ahp->ext_ani_state);
1259a20e5e51SMatthew Dillon #if 0
1260b7d5e03cSMatthew Dillon *result = ar9300_ani_get_current_state(ah);
1261b7d5e03cSMatthew Dillon *resultsize = (*result == AH_NULL) ?
1262b7d5e03cSMatthew Dillon 0 : sizeof(struct ar9300_ani_state);
1263a20e5e51SMatthew Dillon #endif
1264b7d5e03cSMatthew Dillon return AH_TRUE;
1265b7d5e03cSMatthew Dillon case HAL_DIAG_ANI_STATS:
1266b7d5e03cSMatthew Dillon *result = ar9300_ani_get_current_stats(ah);
1267b7d5e03cSMatthew Dillon *resultsize = (*result == AH_NULL) ?
1268a20e5e51SMatthew Dillon 0 : sizeof(HAL_ANI_STATS);
1269b7d5e03cSMatthew Dillon return AH_TRUE;
1270b7d5e03cSMatthew Dillon case HAL_DIAG_ANI_CMD:
1271b7d5e03cSMatthew Dillon if (argsize != 2*sizeof(u_int32_t)) {
1272b7d5e03cSMatthew Dillon return AH_FALSE;
1273b7d5e03cSMatthew Dillon }
1274b7d5e03cSMatthew Dillon ar9300_ani_control(
1275b7d5e03cSMatthew Dillon ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]);
1276b7d5e03cSMatthew Dillon return AH_TRUE;
1277b7d5e03cSMatthew Dillon #if 0
1278b7d5e03cSMatthew Dillon case HAL_DIAG_TXCONT:
1279b7d5e03cSMatthew Dillon /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/
1280b7d5e03cSMatthew Dillon return AH_TRUE;
1281b7d5e03cSMatthew Dillon #endif /* 0 */
1282b7d5e03cSMatthew Dillon #endif /* AH_PRIVATE_DIAG */
1283b7d5e03cSMatthew Dillon case HAL_DIAG_CHANNELS:
1284b7d5e03cSMatthew Dillon #if 0
1285b7d5e03cSMatthew Dillon *result = &(ahp->ah_priv.ah_channels[0]);
1286b7d5e03cSMatthew Dillon *resultsize =
1287b7d5e03cSMatthew Dillon sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan;
1288b7d5e03cSMatthew Dillon #endif
1289b7d5e03cSMatthew Dillon return AH_TRUE;
1290b7d5e03cSMatthew Dillon #ifdef AH_DEBUG
1291b7d5e03cSMatthew Dillon case HAL_DIAG_PRINT_REG:
1292b7d5e03cSMatthew Dillon ar9300_print_reg(ah, *((const u_int32_t *)args));
1293b7d5e03cSMatthew Dillon return AH_TRUE;
1294b7d5e03cSMatthew Dillon #endif
1295b7d5e03cSMatthew Dillon default:
1296b7d5e03cSMatthew Dillon break;
1297b7d5e03cSMatthew Dillon }
1298b7d5e03cSMatthew Dillon
1299b7d5e03cSMatthew Dillon return AH_FALSE;
1300b7d5e03cSMatthew Dillon }
1301b7d5e03cSMatthew Dillon
1302b7d5e03cSMatthew Dillon void
ar9300_dma_reg_dump(struct ath_hal * ah)1303b7d5e03cSMatthew Dillon ar9300_dma_reg_dump(struct ath_hal *ah)
1304b7d5e03cSMatthew Dillon {
1305b7d5e03cSMatthew Dillon #ifdef AH_DEBUG
1306b7d5e03cSMatthew Dillon #define NUM_DMA_DEBUG_REGS 8
1307b7d5e03cSMatthew Dillon #define NUM_QUEUES 10
1308b7d5e03cSMatthew Dillon
1309b7d5e03cSMatthew Dillon u_int32_t val[NUM_DMA_DEBUG_REGS];
1310b7d5e03cSMatthew Dillon int qcu_offset = 0, dcu_offset = 0;
1311b7d5e03cSMatthew Dillon u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg;
1312b7d5e03cSMatthew Dillon int i, j, k;
1313b7d5e03cSMatthew Dillon int16_t nfarray[HAL_NUM_NF_READINGS];
1314b7d5e03cSMatthew Dillon #ifdef ATH_NF_PER_CHAN
1315b7d5e03cSMatthew Dillon HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
1316b7d5e03cSMatthew Dillon #endif /* ATH_NF_PER_CHAN */
1317b7d5e03cSMatthew Dillon HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
1318b7d5e03cSMatthew Dillon
1319b7d5e03cSMatthew Dillon /* selecting DMA OBS 8 */
1320b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_MACMISC,
1321b7d5e03cSMatthew Dillon ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1322b7d5e03cSMatthew Dillon (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1323b7d5e03cSMatthew Dillon
1324b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Raw DMA Debug values:\n");
1325b7d5e03cSMatthew Dillon for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) {
1326b7d5e03cSMatthew Dillon if (i % 4 == 0) {
1327b7d5e03cSMatthew Dillon ath_hal_printf(ah, "\n");
1328b7d5e03cSMatthew Dillon }
1329b7d5e03cSMatthew Dillon
1330b7d5e03cSMatthew Dillon val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
1331b7d5e03cSMatthew Dillon ath_hal_printf(ah, "%d: %08x ", i, val[i]);
1332b7d5e03cSMatthew Dillon }
1333b7d5e03cSMatthew Dillon
1334b7d5e03cSMatthew Dillon ath_hal_printf(ah, "\n\n");
1335b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1336b7d5e03cSMatthew Dillon
1337b7d5e03cSMatthew Dillon for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) {
1338b7d5e03cSMatthew Dillon if (i == 8) {
1339b7d5e03cSMatthew Dillon /* only 8 QCU entries in val[0] */
1340b7d5e03cSMatthew Dillon qcu_offset = 0;
1341b7d5e03cSMatthew Dillon qcu_base++;
1342b7d5e03cSMatthew Dillon }
1343b7d5e03cSMatthew Dillon
1344b7d5e03cSMatthew Dillon if (i == 6) {
1345b7d5e03cSMatthew Dillon /* only 6 DCU entries in val[4] */
1346b7d5e03cSMatthew Dillon dcu_offset = 0;
1347b7d5e03cSMatthew Dillon dcu_base++;
1348b7d5e03cSMatthew Dillon }
1349b7d5e03cSMatthew Dillon
1350b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1351b7d5e03cSMatthew Dillon "%2d %2x %1x %2x %2x\n",
1352b7d5e03cSMatthew Dillon i,
1353b7d5e03cSMatthew Dillon (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset,
1354b7d5e03cSMatthew Dillon (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3),
1355b7d5e03cSMatthew Dillon val[2] & (0x7 << (i * 3)) >> (i * 3),
1356b7d5e03cSMatthew Dillon (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset);
1357b7d5e03cSMatthew Dillon }
1358b7d5e03cSMatthew Dillon
1359b7d5e03cSMatthew Dillon ath_hal_printf(ah, "\n");
1360b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1361b7d5e03cSMatthew Dillon "qcu_stitch state: %2x qcu_fetch state: %2x\n",
1362b7d5e03cSMatthew Dillon (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1363b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1364b7d5e03cSMatthew Dillon "qcu_complete state: %2x dcu_complete state: %2x\n",
1365b7d5e03cSMatthew Dillon (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1366b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1367b7d5e03cSMatthew Dillon "dcu_arb state: %2x dcu_fp state: %2x\n",
1368b7d5e03cSMatthew Dillon (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1369b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1370b7d5e03cSMatthew Dillon "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
1371b7d5e03cSMatthew Dillon (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1372b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1373b7d5e03cSMatthew Dillon "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
1374b7d5e03cSMatthew Dillon (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1375b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1376b7d5e03cSMatthew Dillon "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
1377b7d5e03cSMatthew Dillon (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1378b7d5e03cSMatthew Dillon ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1));
1379b7d5e03cSMatthew Dillon ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR));
1380b7d5e03cSMatthew Dillon
1381b7d5e03cSMatthew Dillon ar9300_upload_noise_floor(ah, 1, nfarray);
1382b7d5e03cSMatthew Dillon ath_hal_printf(ah, "2G:\n");
1383b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Min CCA Out:\n");
1384b7d5e03cSMatthew Dillon ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1385b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1386b7d5e03cSMatthew Dillon nfarray[0], nfarray[1], nfarray[2]);
1387b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1388b7d5e03cSMatthew Dillon nfarray[3], nfarray[4], nfarray[5]);
1389b7d5e03cSMatthew Dillon
1390b7d5e03cSMatthew Dillon ar9300_upload_noise_floor(ah, 0, nfarray);
1391b7d5e03cSMatthew Dillon ath_hal_printf(ah, "5G:\n");
1392b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Min CCA Out:\n");
1393b7d5e03cSMatthew Dillon ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n");
1394b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n",
1395b7d5e03cSMatthew Dillon nfarray[0], nfarray[1], nfarray[2]);
1396b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n",
1397b7d5e03cSMatthew Dillon nfarray[3], nfarray[4], nfarray[5]);
1398b7d5e03cSMatthew Dillon
1399b7d5e03cSMatthew Dillon for (i = 0; i < HAL_NUM_NF_READINGS; i++) {
1400b7d5e03cSMatthew Dillon ath_hal_printf(ah, "%s Chain %d NF History:\n",
1401b7d5e03cSMatthew Dillon ((i < 3) ? "Control " : "Extension "), i%3);
1402b7d5e03cSMatthew Dillon for (j = 0, k = h->base.curr_index;
1403b7d5e03cSMatthew Dillon j < HAL_NF_CAL_HIST_LEN_FULL;
1404b7d5e03cSMatthew Dillon j++, k++) {
1405b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Element %d: %d\n",
1406b7d5e03cSMatthew Dillon j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]);
1407b7d5e03cSMatthew Dillon }
1408b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]);
1409b7d5e03cSMatthew Dillon }
1410b7d5e03cSMatthew Dillon
1411b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW);
1412b7d5e03cSMatthew Dillon ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n",
1413b7d5e03cSMatthew Dillon MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW),
1414b7d5e03cSMatthew Dillon MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW));
1415b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ);
1416b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n",
1417b7d5e03cSMatthew Dillon MS(reg, AR_PHY_DESIRED_SZ_TOT_DES),
1418b7d5e03cSMatthew Dillon MS(reg, AR_PHY_DESIRED_SZ_TOT_DES));
1419b7d5e03cSMatthew Dillon ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n",
1420b7d5e03cSMatthew Dillon MS(reg, AR_PHY_DESIRED_SZ_ADC),
1421b7d5e03cSMatthew Dillon MS(reg, AR_PHY_DESIRED_SZ_ADC));
1422b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, AR_PHY_FIND_SIG);
1423b7d5e03cSMatthew Dillon ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n",
1424b7d5e03cSMatthew Dillon MS(reg, AR_PHY_FIND_SIG_FIRSTEP),
1425b7d5e03cSMatthew Dillon MS(reg, AR_PHY_FIND_SIG_FIRSTEP));
1426b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, AR_PHY_AGC);
1427b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n",
1428b7d5e03cSMatthew Dillon MS(reg, AR_PHY_AGC_COARSE_HIGH),
1429b7d5e03cSMatthew Dillon MS(reg, AR_PHY_AGC_COARSE_HIGH));
1430b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n",
1431b7d5e03cSMatthew Dillon MS(reg, AR_PHY_AGC_COARSE_LOW),
1432b7d5e03cSMatthew Dillon MS(reg, AR_PHY_AGC_COARSE_LOW));
1433b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n",
1434b7d5e03cSMatthew Dillon MS(reg, AR_PHY_AGC_COARSE_PWR_CONST),
1435b7d5e03cSMatthew Dillon MS(reg, AR_PHY_AGC_COARSE_PWR_CONST));
1436b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, AR_PHY_TIMING5);
1437b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n",
1438b7d5e03cSMatthew Dillon MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE));
1439b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n",
1440b7d5e03cSMatthew Dillon MS(reg, AR_PHY_TIMING5_CYCPWR_THR1),
1441b7d5e03cSMatthew Dillon MS(reg, AR_PHY_TIMING5_CYCPWR_THR1));
1442b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n",
1443b7d5e03cSMatthew Dillon MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A),
1444b7d5e03cSMatthew Dillon MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A));
1445b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK);
1446b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n",
1447b7d5e03cSMatthew Dillon MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR));
1448b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n",
1449b7d5e03cSMatthew Dillon MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR),
1450b7d5e03cSMatthew Dillon MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR));
1451b7d5e03cSMatthew Dillon
1452b7d5e03cSMatthew Dillon
1453b7d5e03cSMatthew Dillon /* Step 1a: Set bit 23 of register 0xa360 to 0 */
1454b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0xa360);
1455b7d5e03cSMatthew Dillon reg &= ~0x00800000;
1456b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa360, reg);
1457b7d5e03cSMatthew Dillon
1458b7d5e03cSMatthew Dillon /* Step 2a: Set register 0xa364 to 0x1000 */
1459b7d5e03cSMatthew Dillon reg = 0x1000;
1460b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa364, reg);
1461b7d5e03cSMatthew Dillon
1462b7d5e03cSMatthew Dillon /* Step 3a: Read bits 17:0 of register 0x9c20 */
1463b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0x9c20);
1464b7d5e03cSMatthew Dillon reg &= 0x0003ffff;
1465b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1466b7d5e03cSMatthew Dillon "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n",
1467b7d5e03cSMatthew Dillon __func__, reg);
1468b7d5e03cSMatthew Dillon
1469b7d5e03cSMatthew Dillon /* Step 1b: Set bit 23 of register 0xa360 to 0 */
1470b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0xa360);
1471b7d5e03cSMatthew Dillon reg &= ~0x00800000;
1472b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa360, reg);
1473b7d5e03cSMatthew Dillon
1474b7d5e03cSMatthew Dillon /* Step 2b: Set register 0xa364 to 0x1400 */
1475b7d5e03cSMatthew Dillon reg = 0x1400;
1476b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa364, reg);
1477b7d5e03cSMatthew Dillon
1478b7d5e03cSMatthew Dillon /* Step 3b: Read bits 17:0 of register 0x9c20 */
1479b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0x9c20);
1480b7d5e03cSMatthew Dillon reg &= 0x0003ffff;
1481b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1482b7d5e03cSMatthew Dillon "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n",
1483b7d5e03cSMatthew Dillon __func__, reg);
1484b7d5e03cSMatthew Dillon
1485b7d5e03cSMatthew Dillon /* Step 1c: Set bit 23 of register 0xa360 to 0 */
1486b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0xa360);
1487b7d5e03cSMatthew Dillon reg &= ~0x00800000;
1488b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa360, reg);
1489b7d5e03cSMatthew Dillon
1490b7d5e03cSMatthew Dillon /* Step 2c: Set register 0xa364 to 0x3C00 */
1491b7d5e03cSMatthew Dillon reg = 0x3c00;
1492b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa364, reg);
1493b7d5e03cSMatthew Dillon
1494b7d5e03cSMatthew Dillon /* Step 3c: Read bits 17:0 of register 0x9c20 */
1495b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0x9c20);
1496b7d5e03cSMatthew Dillon reg &= 0x0003ffff;
1497b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1498b7d5e03cSMatthew Dillon "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n",
1499b7d5e03cSMatthew Dillon __func__, reg);
1500b7d5e03cSMatthew Dillon
1501b7d5e03cSMatthew Dillon /* Step 1d: Set bit 24 of register 0xa360 to 0 */
1502b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0xa360);
1503b7d5e03cSMatthew Dillon reg &= ~0x001040000;
1504b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa360, reg);
1505b7d5e03cSMatthew Dillon
1506b7d5e03cSMatthew Dillon /* Step 2d: Set register 0xa364 to 0x5005D */
1507b7d5e03cSMatthew Dillon reg = 0x5005D;
1508b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa364, reg);
1509b7d5e03cSMatthew Dillon
1510b7d5e03cSMatthew Dillon /* Step 3d: Read bits 17:0 of register 0xa368 */
1511b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0xa368);
1512b7d5e03cSMatthew Dillon reg &= 0x0003ffff;
1513b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1514b7d5e03cSMatthew Dillon "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n",
1515b7d5e03cSMatthew Dillon __func__, reg);
1516b7d5e03cSMatthew Dillon
1517b7d5e03cSMatthew Dillon /* Step 1e: Set bit 24 of register 0xa360 to 0 */
1518b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0xa360);
1519b7d5e03cSMatthew Dillon reg &= ~0x001040000;
1520b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa360, reg);
1521b7d5e03cSMatthew Dillon
1522b7d5e03cSMatthew Dillon /* Step 2e: Set register 0xa364 to 0x7005D */
1523b7d5e03cSMatthew Dillon reg = 0x7005D;
1524b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa364, reg);
1525b7d5e03cSMatthew Dillon
1526b7d5e03cSMatthew Dillon /* Step 3e: Read bits 17:0 of register 0xa368 */
1527b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0xa368);
1528b7d5e03cSMatthew Dillon reg &= 0x0003ffff;
1529b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1530b7d5e03cSMatthew Dillon "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n",
1531b7d5e03cSMatthew Dillon __func__, reg);
1532b7d5e03cSMatthew Dillon
1533b7d5e03cSMatthew Dillon /* Step 1f: Set bit 24 of register 0xa360 to 0 */
1534b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0xa360);
1535b7d5e03cSMatthew Dillon reg &= ~0x001000000;
1536b7d5e03cSMatthew Dillon reg |= 0x40000;
1537b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa360, reg);
1538b7d5e03cSMatthew Dillon
1539b7d5e03cSMatthew Dillon /* Step 2f: Set register 0xa364 to 0x3005D */
1540b7d5e03cSMatthew Dillon reg = 0x3005D;
1541b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa364, reg);
1542b7d5e03cSMatthew Dillon
1543b7d5e03cSMatthew Dillon /* Step 3f: Read bits 17:0 of register 0xa368 */
1544b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0xa368);
1545b7d5e03cSMatthew Dillon reg &= 0x0003ffff;
1546b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1547b7d5e03cSMatthew Dillon "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n",
1548b7d5e03cSMatthew Dillon __func__, reg);
1549b7d5e03cSMatthew Dillon
1550b7d5e03cSMatthew Dillon /* Step 1g: Set bit 24 of register 0xa360 to 0 */
1551b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0xa360);
1552b7d5e03cSMatthew Dillon reg &= ~0x001000000;
1553b7d5e03cSMatthew Dillon reg |= 0x40000;
1554b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa360, reg);
1555b7d5e03cSMatthew Dillon
1556b7d5e03cSMatthew Dillon /* Step 2g: Set register 0xa364 to 0x6005D */
1557b7d5e03cSMatthew Dillon reg = 0x6005D;
1558b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa364, reg);
1559b7d5e03cSMatthew Dillon
1560b7d5e03cSMatthew Dillon /* Step 3g: Read bits 17:0 of register 0xa368 */
1561b7d5e03cSMatthew Dillon reg = OS_REG_READ(ah, 0xa368);
1562b7d5e03cSMatthew Dillon reg &= 0x0003ffff;
1563b7d5e03cSMatthew Dillon ath_hal_printf(ah,
1564b7d5e03cSMatthew Dillon "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n",
1565b7d5e03cSMatthew Dillon __func__, reg);
1566b7d5e03cSMatthew Dillon #endif /* AH_DEBUG */
1567b7d5e03cSMatthew Dillon }
1568b7d5e03cSMatthew Dillon
1569b7d5e03cSMatthew Dillon /*
1570b7d5e03cSMatthew Dillon * Return the busy for rx_frame, rx_clear, and tx_frame
1571b7d5e03cSMatthew Dillon */
1572b7d5e03cSMatthew Dillon u_int32_t
ar9300_get_mib_cycle_counts_pct(struct ath_hal * ah,u_int32_t * rxc_pcnt,u_int32_t * rxf_pcnt,u_int32_t * txf_pcnt)1573b7d5e03cSMatthew Dillon ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt,
1574b7d5e03cSMatthew Dillon u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt)
1575b7d5e03cSMatthew Dillon {
1576b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
1577b7d5e03cSMatthew Dillon u_int32_t good = 1;
1578b7d5e03cSMatthew Dillon
1579b7d5e03cSMatthew Dillon u_int32_t rc = OS_REG_READ(ah, AR_RCCNT);
1580b7d5e03cSMatthew Dillon u_int32_t rf = OS_REG_READ(ah, AR_RFCNT);
1581b7d5e03cSMatthew Dillon u_int32_t tf = OS_REG_READ(ah, AR_TFCNT);
1582b7d5e03cSMatthew Dillon u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */
1583b7d5e03cSMatthew Dillon
1584b7d5e03cSMatthew Dillon if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) {
1585b7d5e03cSMatthew Dillon /*
1586b7d5e03cSMatthew Dillon * Cycle counter wrap (or initial call); it's not possible
1587b7d5e03cSMatthew Dillon * to accurately calculate a value because the registers
1588b7d5e03cSMatthew Dillon * right shift rather than wrap--so punt and return 0.
1589b7d5e03cSMatthew Dillon */
1590b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_CHANNEL,
1591b7d5e03cSMatthew Dillon "%s: cycle counter wrap. ExtBusy = 0\n", __func__);
1592b7d5e03cSMatthew Dillon good = 0;
1593b7d5e03cSMatthew Dillon } else {
1594b7d5e03cSMatthew Dillon u_int32_t cc_d = cc - ahp->ah_cycles;
1595b7d5e03cSMatthew Dillon u_int32_t rc_d = rc - ahp->ah_rx_clear;
1596b7d5e03cSMatthew Dillon u_int32_t rf_d = rf - ahp->ah_rx_frame;
1597b7d5e03cSMatthew Dillon u_int32_t tf_d = tf - ahp->ah_tx_frame;
1598b7d5e03cSMatthew Dillon
1599b7d5e03cSMatthew Dillon if (cc_d != 0) {
1600b7d5e03cSMatthew Dillon *rxc_pcnt = rc_d * 100 / cc_d;
1601b7d5e03cSMatthew Dillon *rxf_pcnt = rf_d * 100 / cc_d;
1602b7d5e03cSMatthew Dillon *txf_pcnt = tf_d * 100 / cc_d;
1603b7d5e03cSMatthew Dillon } else {
1604b7d5e03cSMatthew Dillon good = 0;
1605b7d5e03cSMatthew Dillon }
1606b7d5e03cSMatthew Dillon }
1607b7d5e03cSMatthew Dillon
1608b7d5e03cSMatthew Dillon ahp->ah_cycles = cc;
1609b7d5e03cSMatthew Dillon ahp->ah_rx_frame = rf;
1610b7d5e03cSMatthew Dillon ahp->ah_rx_clear = rc;
1611b7d5e03cSMatthew Dillon ahp->ah_tx_frame = tf;
1612b7d5e03cSMatthew Dillon
1613b7d5e03cSMatthew Dillon return good;
1614b7d5e03cSMatthew Dillon }
1615b7d5e03cSMatthew Dillon
1616b7d5e03cSMatthew Dillon /*
1617b7d5e03cSMatthew Dillon * Return approximation of extension channel busy over an time interval
1618b7d5e03cSMatthew Dillon * 0% (clear) -> 100% (busy)
1619b7d5e03cSMatthew Dillon * -1 for invalid estimate
1620b7d5e03cSMatthew Dillon */
1621b7d5e03cSMatthew Dillon uint32_t
ar9300_get_11n_ext_busy(struct ath_hal * ah)1622b7d5e03cSMatthew Dillon ar9300_get_11n_ext_busy(struct ath_hal *ah)
1623b7d5e03cSMatthew Dillon {
1624b7d5e03cSMatthew Dillon /*
1625b7d5e03cSMatthew Dillon * Overflow condition to check before multiplying to get %
1626b7d5e03cSMatthew Dillon * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28)
1627b7d5e03cSMatthew Dillon */
1628b7d5e03cSMatthew Dillon #define OVERFLOW_LIMIT 0x28F5C28
1629b7d5e03cSMatthew Dillon #define ERROR_CODE -1
1630b7d5e03cSMatthew Dillon
1631b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
1632b7d5e03cSMatthew Dillon u_int32_t busy = 0; /* percentage */
1633b7d5e03cSMatthew Dillon int8_t busyper = 0;
1634b7d5e03cSMatthew Dillon u_int32_t cycle_count, ctl_busy, ext_busy;
1635b7d5e03cSMatthew Dillon
1636b7d5e03cSMatthew Dillon /* cycle_count will always be the first to wrap; therefore, read it last
1637b7d5e03cSMatthew Dillon * This sequence of reads is not atomic, and MIB counter wrap
1638b7d5e03cSMatthew Dillon * could happen during it ?
1639b7d5e03cSMatthew Dillon */
1640b7d5e03cSMatthew Dillon ctl_busy = OS_REG_READ(ah, AR_RCCNT);
1641b7d5e03cSMatthew Dillon ext_busy = OS_REG_READ(ah, AR_EXTRCCNT);
1642b7d5e03cSMatthew Dillon cycle_count = OS_REG_READ(ah, AR_CCCNT);
1643b7d5e03cSMatthew Dillon
1644b7d5e03cSMatthew Dillon if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) ||
1645b7d5e03cSMatthew Dillon (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy))
1646b7d5e03cSMatthew Dillon {
1647b7d5e03cSMatthew Dillon /*
1648b7d5e03cSMatthew Dillon * Cycle counter wrap (or initial call); it's not possible
1649b7d5e03cSMatthew Dillon * to accurately calculate a value because the registers
1650b7d5e03cSMatthew Dillon * right shift rather than wrap--so punt and return 0.
1651b7d5e03cSMatthew Dillon */
1652b7d5e03cSMatthew Dillon busyper = ERROR_CODE;
1653b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_CHANNEL,
1654b7d5e03cSMatthew Dillon "%s: cycle counter wrap. ExtBusy = 0\n", __func__);
1655b7d5e03cSMatthew Dillon } else {
1656b7d5e03cSMatthew Dillon u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count;
1657b7d5e03cSMatthew Dillon u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy;
1658b7d5e03cSMatthew Dillon
1659b7d5e03cSMatthew Dillon /*
1660b7d5e03cSMatthew Dillon * Compute extension channel busy percentage
1661b7d5e03cSMatthew Dillon * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100
1662b7d5e03cSMatthew Dillon * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0
1663b7d5e03cSMatthew Dillon * Will never happen, since (ext_busy_delta < cycle_delta) always,
1664b7d5e03cSMatthew Dillon * and shift necessitated by large ext_busy_delta.
1665b7d5e03cSMatthew Dillon * Due to timing difference to read the registers and counter overflow,
1666b7d5e03cSMatthew Dillon * it may still happen that cycle_delta >> 7 = 0.
1667b7d5e03cSMatthew Dillon *
1668b7d5e03cSMatthew Dillon */
1669b7d5e03cSMatthew Dillon if (cycle_delta) {
1670b7d5e03cSMatthew Dillon if (ext_busy_delta > OVERFLOW_LIMIT) {
1671b7d5e03cSMatthew Dillon if (cycle_delta >> 7) {
1672b7d5e03cSMatthew Dillon busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7);
1673b7d5e03cSMatthew Dillon } else {
1674b7d5e03cSMatthew Dillon busyper = ERROR_CODE;
1675b7d5e03cSMatthew Dillon }
1676b7d5e03cSMatthew Dillon } else {
1677b7d5e03cSMatthew Dillon busy = (ext_busy_delta * 100) / cycle_delta;
1678b7d5e03cSMatthew Dillon }
1679b7d5e03cSMatthew Dillon } else {
1680b7d5e03cSMatthew Dillon busyper = ERROR_CODE;
1681b7d5e03cSMatthew Dillon }
1682b7d5e03cSMatthew Dillon
1683b7d5e03cSMatthew Dillon if (busy > 100) {
1684b7d5e03cSMatthew Dillon busy = 100;
1685b7d5e03cSMatthew Dillon }
1686b7d5e03cSMatthew Dillon if ( busyper != ERROR_CODE ) {
1687b7d5e03cSMatthew Dillon busyper = busy;
1688b7d5e03cSMatthew Dillon }
1689b7d5e03cSMatthew Dillon }
1690b7d5e03cSMatthew Dillon
1691b7d5e03cSMatthew Dillon ahp->ah_cycle_count = cycle_count;
1692b7d5e03cSMatthew Dillon ahp->ah_ctl_busy = ctl_busy;
1693b7d5e03cSMatthew Dillon ahp->ah_ext_busy = ext_busy;
1694b7d5e03cSMatthew Dillon
1695b7d5e03cSMatthew Dillon return busyper;
1696b7d5e03cSMatthew Dillon #undef OVERFLOW_LIMIT
1697b7d5e03cSMatthew Dillon #undef ERROR_CODE
1698b7d5e03cSMatthew Dillon }
1699b7d5e03cSMatthew Dillon
1700b7d5e03cSMatthew Dillon /* BB Panic Watchdog declarations */
1701b7d5e03cSMatthew Dillon #define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */
1702b7d5e03cSMatthew Dillon #define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */
1703b7d5e03cSMatthew Dillon
1704b7d5e03cSMatthew Dillon void
ar9300_config_bb_panic_watchdog(struct ath_hal * ah)1705b7d5e03cSMatthew Dillon ar9300_config_bb_panic_watchdog(struct ath_hal *ah)
1706b7d5e03cSMatthew Dillon {
1707b7d5e03cSMatthew Dillon #define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000
1708b7d5e03cSMatthew Dillon const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
1709b7d5e03cSMatthew Dillon u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms;
1710b7d5e03cSMatthew Dillon u_int32_t val, idle_count;
1711b7d5e03cSMatthew Dillon
1712b7d5e03cSMatthew Dillon if (idle_tmo_ms != 0) {
1713b7d5e03cSMatthew Dillon /* enable IRQ, disable chip-reset for BB panic */
1714b7d5e03cSMatthew Dillon val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1715b7d5e03cSMatthew Dillon AR_PHY_BB_PANIC_CNTL2_MASK;
1716b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1717b7d5e03cSMatthew Dillon (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE);
1718b7d5e03cSMatthew Dillon /* bound limit to 10 secs */
1719b7d5e03cSMatthew Dillon if (idle_tmo_ms > 10000) {
1720b7d5e03cSMatthew Dillon idle_tmo_ms = 10000;
1721b7d5e03cSMatthew Dillon }
1722b7d5e03cSMatthew Dillon if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) {
1723b7d5e03cSMatthew Dillon idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR;
1724b7d5e03cSMatthew Dillon } else {
1725b7d5e03cSMatthew Dillon idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR;
1726b7d5e03cSMatthew Dillon }
1727b7d5e03cSMatthew Dillon /*
1728b7d5e03cSMatthew Dillon * enable panic in non-IDLE mode,
1729b7d5e03cSMatthew Dillon * disable in IDLE mode,
1730b7d5e03cSMatthew Dillon * set idle time-out
1731b7d5e03cSMatthew Dillon */
1732b7d5e03cSMatthew Dillon
1733b7d5e03cSMatthew Dillon // EV92527 : Enable IDLE mode panic
1734b7d5e03cSMatthew Dillon
1735b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1736b7d5e03cSMatthew Dillon AR_PHY_BB_PANIC_NON_IDLE_ENABLE |
1737b7d5e03cSMatthew Dillon AR_PHY_BB_PANIC_IDLE_ENABLE |
1738b7d5e03cSMatthew Dillon (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) |
1739b7d5e03cSMatthew Dillon (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2)));
1740b7d5e03cSMatthew Dillon } else {
1741b7d5e03cSMatthew Dillon /* disable IRQ, disable chip-reset for BB panic */
1742b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2,
1743b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) &
1744b7d5e03cSMatthew Dillon ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE));
1745b7d5e03cSMatthew Dillon /* disable panic in non-IDLE mode, disable in IDLE mode */
1746b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1,
1747b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) &
1748b7d5e03cSMatthew Dillon ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE));
1749b7d5e03cSMatthew Dillon }
1750b7d5e03cSMatthew Dillon
1751b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n",
1752b7d5e03cSMatthew Dillon __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms);
1753b7d5e03cSMatthew Dillon #undef HAL_BB_PANIC_IDLE_TIME_OUT
1754b7d5e03cSMatthew Dillon }
1755b7d5e03cSMatthew Dillon
1756b7d5e03cSMatthew Dillon
1757b7d5e03cSMatthew Dillon void
ar9300_handle_bb_panic(struct ath_hal * ah)1758b7d5e03cSMatthew Dillon ar9300_handle_bb_panic(struct ath_hal *ah)
1759b7d5e03cSMatthew Dillon {
1760b7d5e03cSMatthew Dillon u_int32_t status;
1761b7d5e03cSMatthew Dillon /*
1762b7d5e03cSMatthew Dillon * we want to avoid printing in ISR context so we save
1763b7d5e03cSMatthew Dillon * panic watchdog status to be printed later in DPC context
1764b7d5e03cSMatthew Dillon */
1765b7d5e03cSMatthew Dillon AH9300(ah)->ah_bb_panic_last_status = status =
1766b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS);
1767b7d5e03cSMatthew Dillon /*
1768b7d5e03cSMatthew Dillon * panic watchdog timer should reset on status read
1769b7d5e03cSMatthew Dillon * but to make sure we write 0 to the watchdog status bit
1770b7d5e03cSMatthew Dillon */
1771b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR);
1772b7d5e03cSMatthew Dillon }
1773b7d5e03cSMatthew Dillon
1774b7d5e03cSMatthew Dillon int
ar9300_get_bb_panic_info(struct ath_hal * ah,struct hal_bb_panic_info * bb_panic)1775b7d5e03cSMatthew Dillon ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic)
1776b7d5e03cSMatthew Dillon {
1777b7d5e03cSMatthew Dillon bb_panic->status = AH9300(ah)->ah_bb_panic_last_status;
1778b7d5e03cSMatthew Dillon
1779b7d5e03cSMatthew Dillon /*
1780b7d5e03cSMatthew Dillon * For signature 04000539 do not print anything.
1781b7d5e03cSMatthew Dillon * This is a very common occurence as a compromise between
1782b7d5e03cSMatthew Dillon * BB Panic and AH_FALSE detects (EV71009). It indicates
1783b7d5e03cSMatthew Dillon * radar hang, which can be cleared by reprogramming
1784b7d5e03cSMatthew Dillon * radar related register and does not requre a chip reset
1785b7d5e03cSMatthew Dillon */
1786b7d5e03cSMatthew Dillon
1787b7d5e03cSMatthew Dillon /* Suppress BB Status mesg following signature */
1788b7d5e03cSMatthew Dillon switch (bb_panic->status) {
1789b7d5e03cSMatthew Dillon case 0x04000539:
1790b7d5e03cSMatthew Dillon case 0x04008009:
1791b7d5e03cSMatthew Dillon case 0x04000b09:
1792b7d5e03cSMatthew Dillon case 0x1300000a:
1793b7d5e03cSMatthew Dillon return -1;
1794b7d5e03cSMatthew Dillon }
1795b7d5e03cSMatthew Dillon
1796b7d5e03cSMatthew Dillon bb_panic->tsf = ar9300_get_tsf32(ah);
1797b7d5e03cSMatthew Dillon bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS);
1798b7d5e03cSMatthew Dillon bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG);
1799b7d5e03cSMatthew Dillon bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM);
1800b7d5e03cSMatthew Dillon bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM);
1801b7d5e03cSMatthew Dillon bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM);
1802b7d5e03cSMatthew Dillon bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM);
1803b7d5e03cSMatthew Dillon bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM);
1804b7d5e03cSMatthew Dillon bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM);
1805b7d5e03cSMatthew Dillon bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM);
1806b7d5e03cSMatthew Dillon bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1);
1807b7d5e03cSMatthew Dillon bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2);
1808b7d5e03cSMatthew Dillon bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL);
1809b7d5e03cSMatthew Dillon bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0;
1810b7d5e03cSMatthew Dillon bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah,
1811b7d5e03cSMatthew Dillon &bb_panic->rxc_pcnt,
1812b7d5e03cSMatthew Dillon &bb_panic->rxf_pcnt,
1813b7d5e03cSMatthew Dillon &bb_panic->txf_pcnt);
1814b7d5e03cSMatthew Dillon
1815b7d5e03cSMatthew Dillon if (ah->ah_config.ath_hal_show_bb_panic) {
1816b7d5e03cSMatthew Dillon ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, "
1817b7d5e03cSMatthew Dillon "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf);
1818b7d5e03cSMatthew Dillon ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1819b7d5e03cSMatthew Dillon "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1820b7d5e03cSMatthew Dillon bb_panic->wd, bb_panic->det, bb_panic->rdar,
1821b7d5e03cSMatthew Dillon bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm,
1822b7d5e03cSMatthew Dillon bb_panic->t_cck, bb_panic->agc, bb_panic->src);
1823b7d5e03cSMatthew Dillon ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1824b7d5e03cSMatthew Dillon bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2);
1825b7d5e03cSMatthew Dillon ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n",
1826b7d5e03cSMatthew Dillon bb_panic->phy_gen_ctrl);
1827b7d5e03cSMatthew Dillon if (bb_panic->cycles) {
1828b7d5e03cSMatthew Dillon ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, "
1829b7d5e03cSMatthew Dillon "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt,
1830b7d5e03cSMatthew Dillon bb_panic->rxf_pcnt, bb_panic->txf_pcnt);
1831b7d5e03cSMatthew Dillon }
1832b7d5e03cSMatthew Dillon ath_hal_printf(ah, "==== BB update: done ====\n\n");
1833b7d5e03cSMatthew Dillon }
1834b7d5e03cSMatthew Dillon
1835b7d5e03cSMatthew Dillon return 0; //The returned data will be stored for athstats to retrieve it
1836b7d5e03cSMatthew Dillon }
1837b7d5e03cSMatthew Dillon
1838b7d5e03cSMatthew Dillon /* set the reason for HAL reset */
1839b7d5e03cSMatthew Dillon void
ar9300_set_hal_reset_reason(struct ath_hal * ah,u_int8_t resetreason)1840b7d5e03cSMatthew Dillon ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason)
1841b7d5e03cSMatthew Dillon {
1842b7d5e03cSMatthew Dillon AH9300(ah)->ah_reset_reason = resetreason;
1843b7d5e03cSMatthew Dillon }
1844b7d5e03cSMatthew Dillon
1845b7d5e03cSMatthew Dillon /*
1846b7d5e03cSMatthew Dillon * Configure 20/40 operation
1847b7d5e03cSMatthew Dillon *
1848b7d5e03cSMatthew Dillon * 20/40 = joint rx clear (control and extension)
1849b7d5e03cSMatthew Dillon * 20 = rx clear (control)
1850b7d5e03cSMatthew Dillon *
1851b7d5e03cSMatthew Dillon * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz
1852b7d5e03cSMatthew Dillon * when changing from 20/40 => 20 only
1853b7d5e03cSMatthew Dillon */
1854b7d5e03cSMatthew Dillon void
ar9300_set_11n_mac2040(struct ath_hal * ah,HAL_HT_MACMODE mode)1855b7d5e03cSMatthew Dillon ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode)
1856b7d5e03cSMatthew Dillon {
1857b7d5e03cSMatthew Dillon u_int32_t macmode;
1858b7d5e03cSMatthew Dillon
1859b7d5e03cSMatthew Dillon /* Configure MAC for 20/40 operation */
1860b7d5e03cSMatthew Dillon if (mode == HAL_HT_MACMODE_2040 &&
1861b7d5e03cSMatthew Dillon !ah->ah_config.ath_hal_cwm_ignore_ext_cca) {
1862b7d5e03cSMatthew Dillon macmode = AR_2040_JOINED_RX_CLEAR;
1863b7d5e03cSMatthew Dillon } else {
1864b7d5e03cSMatthew Dillon macmode = 0;
1865b7d5e03cSMatthew Dillon }
1866b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_2040_MODE, macmode);
1867b7d5e03cSMatthew Dillon }
1868b7d5e03cSMatthew Dillon
1869b7d5e03cSMatthew Dillon /*
1870b7d5e03cSMatthew Dillon * Get Rx clear (control/extension channel)
1871b7d5e03cSMatthew Dillon *
1872b7d5e03cSMatthew Dillon * Returns active low (busy) for ctrl/ext channel
1873b7d5e03cSMatthew Dillon * Owl 2.0
1874b7d5e03cSMatthew Dillon */
1875b7d5e03cSMatthew Dillon HAL_HT_RXCLEAR
ar9300_get_11n_rx_clear(struct ath_hal * ah)1876b7d5e03cSMatthew Dillon ar9300_get_11n_rx_clear(struct ath_hal *ah)
1877b7d5e03cSMatthew Dillon {
1878b7d5e03cSMatthew Dillon HAL_HT_RXCLEAR rxclear = 0;
1879b7d5e03cSMatthew Dillon u_int32_t val;
1880b7d5e03cSMatthew Dillon
1881b7d5e03cSMatthew Dillon val = OS_REG_READ(ah, AR_DIAG_SW);
1882b7d5e03cSMatthew Dillon
1883b7d5e03cSMatthew Dillon /* control channel */
1884b7d5e03cSMatthew Dillon if (val & AR_DIAG_RX_CLEAR_CTL_LOW) {
1885b7d5e03cSMatthew Dillon rxclear |= HAL_RX_CLEAR_CTL_LOW;
1886b7d5e03cSMatthew Dillon }
1887b7d5e03cSMatthew Dillon /* extension channel */
1888b7d5e03cSMatthew Dillon if (val & AR_DIAG_RX_CLEAR_EXT_LOW) {
1889b7d5e03cSMatthew Dillon rxclear |= HAL_RX_CLEAR_EXT_LOW;
1890b7d5e03cSMatthew Dillon }
1891b7d5e03cSMatthew Dillon return rxclear;
1892b7d5e03cSMatthew Dillon }
1893b7d5e03cSMatthew Dillon
1894b7d5e03cSMatthew Dillon /*
1895b7d5e03cSMatthew Dillon * Set Rx clear (control/extension channel)
1896b7d5e03cSMatthew Dillon *
1897b7d5e03cSMatthew Dillon * Useful for forcing the channel to appear busy for
1898b7d5e03cSMatthew Dillon * debugging/diagnostics
1899b7d5e03cSMatthew Dillon * Owl 2.0
1900b7d5e03cSMatthew Dillon */
1901b7d5e03cSMatthew Dillon void
ar9300_set_11n_rx_clear(struct ath_hal * ah,HAL_HT_RXCLEAR rxclear)1902b7d5e03cSMatthew Dillon ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear)
1903b7d5e03cSMatthew Dillon {
1904b7d5e03cSMatthew Dillon /* control channel */
1905b7d5e03cSMatthew Dillon if (rxclear & HAL_RX_CLEAR_CTL_LOW) {
1906b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW);
1907b7d5e03cSMatthew Dillon } else {
1908b7d5e03cSMatthew Dillon OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW);
1909b7d5e03cSMatthew Dillon }
1910b7d5e03cSMatthew Dillon /* extension channel */
1911b7d5e03cSMatthew Dillon if (rxclear & HAL_RX_CLEAR_EXT_LOW) {
1912b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW);
1913b7d5e03cSMatthew Dillon } else {
1914b7d5e03cSMatthew Dillon OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW);
1915b7d5e03cSMatthew Dillon }
1916b7d5e03cSMatthew Dillon }
1917b7d5e03cSMatthew Dillon
1918b7d5e03cSMatthew Dillon
1919b7d5e03cSMatthew Dillon /*
1920b7d5e03cSMatthew Dillon * HAL support code for force ppm tracking workaround.
1921b7d5e03cSMatthew Dillon */
1922b7d5e03cSMatthew Dillon
1923b7d5e03cSMatthew Dillon u_int32_t
ar9300_ppm_get_rssi_dump(struct ath_hal * ah)1924b7d5e03cSMatthew Dillon ar9300_ppm_get_rssi_dump(struct ath_hal *ah)
1925b7d5e03cSMatthew Dillon {
1926b7d5e03cSMatthew Dillon u_int32_t retval;
1927b7d5e03cSMatthew Dillon u_int32_t off1;
1928b7d5e03cSMatthew Dillon u_int32_t off2;
1929b7d5e03cSMatthew Dillon
1930b7d5e03cSMatthew Dillon if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) {
1931b7d5e03cSMatthew Dillon off1 = 0x2000;
1932b7d5e03cSMatthew Dillon off2 = 0x1000;
1933b7d5e03cSMatthew Dillon } else {
1934b7d5e03cSMatthew Dillon off1 = 0x1000;
1935b7d5e03cSMatthew Dillon off2 = 0x2000;
1936b7d5e03cSMatthew Dillon }
1937b7d5e03cSMatthew Dillon
1938b7d5e03cSMatthew Dillon retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) |
1939b7d5e03cSMatthew Dillon ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) |
1940b7d5e03cSMatthew Dillon ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16);
1941b7d5e03cSMatthew Dillon
1942b7d5e03cSMatthew Dillon return retval;
1943b7d5e03cSMatthew Dillon }
1944b7d5e03cSMatthew Dillon
1945b7d5e03cSMatthew Dillon u_int32_t
ar9300_ppm_force(struct ath_hal * ah)1946b7d5e03cSMatthew Dillon ar9300_ppm_force(struct ath_hal *ah)
1947b7d5e03cSMatthew Dillon {
1948b7d5e03cSMatthew Dillon u_int32_t data_fine;
1949b7d5e03cSMatthew Dillon u_int32_t data4;
1950b7d5e03cSMatthew Dillon //u_int32_t off1;
1951b7d5e03cSMatthew Dillon //u_int32_t off2;
1952b7d5e03cSMatthew Dillon HAL_BOOL signed_val = AH_FALSE;
1953b7d5e03cSMatthew Dillon
1954b7d5e03cSMatthew Dillon // if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) {
1955b7d5e03cSMatthew Dillon // off1 = 0x2000;
1956b7d5e03cSMatthew Dillon // off2 = 0x1000;
1957b7d5e03cSMatthew Dillon // } else {
1958b7d5e03cSMatthew Dillon // off1 = 0x1000;
1959b7d5e03cSMatthew Dillon // off2 = 0x2000;
1960b7d5e03cSMatthew Dillon // }
1961b7d5e03cSMatthew Dillon data_fine =
1962b7d5e03cSMatthew Dillon AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK &
1963b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF);
1964b7d5e03cSMatthew Dillon
1965b7d5e03cSMatthew Dillon /*
1966b7d5e03cSMatthew Dillon * bit [11-0] is new ppm value. bit 11 is the signed bit.
1967b7d5e03cSMatthew Dillon * So check value from bit[10:0].
1968b7d5e03cSMatthew Dillon * Now get the abs val of the ppm value read in bit[0:11].
1969b7d5e03cSMatthew Dillon * After that do bound check on abs value.
1970b7d5e03cSMatthew Dillon * if value is off limit, CAP the value and and restore signed bit.
1971b7d5e03cSMatthew Dillon */
1972b7d5e03cSMatthew Dillon if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT)
1973b7d5e03cSMatthew Dillon {
1974b7d5e03cSMatthew Dillon /* get the positive value */
1975b7d5e03cSMatthew Dillon data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1976b7d5e03cSMatthew Dillon signed_val = AH_TRUE;
1977b7d5e03cSMatthew Dillon }
1978b7d5e03cSMatthew Dillon if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT)
1979b7d5e03cSMatthew Dillon {
1980b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_REGIO,
1981b7d5e03cSMatthew Dillon "%s Correcting ppm out of range %x\n",
1982b7d5e03cSMatthew Dillon __func__, (data_fine & 0x7ff));
1983b7d5e03cSMatthew Dillon data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT;
1984b7d5e03cSMatthew Dillon }
1985b7d5e03cSMatthew Dillon /*
1986b7d5e03cSMatthew Dillon * Restore signed value if changed above.
1987b7d5e03cSMatthew Dillon * Use typecast to avoid compilation errors
1988b7d5e03cSMatthew Dillon */
1989b7d5e03cSMatthew Dillon if (signed_val) {
1990b7d5e03cSMatthew Dillon data_fine = (-(int32_t)data_fine) &
1991b7d5e03cSMatthew Dillon AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK;
1992b7d5e03cSMatthew Dillon }
1993b7d5e03cSMatthew Dillon
1994b7d5e03cSMatthew Dillon /* write value */
1995b7d5e03cSMatthew Dillon data4 = OS_REG_READ(ah, AR_PHY_TIMING2) &
1996b7d5e03cSMatthew Dillon ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
1997b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_TIMING2,
1998b7d5e03cSMatthew Dillon data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM);
1999b7d5e03cSMatthew Dillon
2000b7d5e03cSMatthew Dillon return data_fine;
2001b7d5e03cSMatthew Dillon }
2002b7d5e03cSMatthew Dillon
2003b7d5e03cSMatthew Dillon void
ar9300_ppm_un_force(struct ath_hal * ah)2004b7d5e03cSMatthew Dillon ar9300_ppm_un_force(struct ath_hal *ah)
2005b7d5e03cSMatthew Dillon {
2006b7d5e03cSMatthew Dillon u_int32_t data4;
2007b7d5e03cSMatthew Dillon
2008b7d5e03cSMatthew Dillon data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM;
2009b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_TIMING2, data4);
2010b7d5e03cSMatthew Dillon }
2011b7d5e03cSMatthew Dillon
2012b7d5e03cSMatthew Dillon u_int32_t
ar9300_ppm_arm_trigger(struct ath_hal * ah)2013b7d5e03cSMatthew Dillon ar9300_ppm_arm_trigger(struct ath_hal *ah)
2014b7d5e03cSMatthew Dillon {
2015b7d5e03cSMatthew Dillon u_int32_t val;
2016b7d5e03cSMatthew Dillon u_int32_t ret;
2017b7d5e03cSMatthew Dillon
2018b7d5e03cSMatthew Dillon val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY);
2019b7d5e03cSMatthew Dillon ret = OS_REG_READ(ah, AR_TSF_L32);
2020b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY,
2021b7d5e03cSMatthew Dillon val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK);
2022b7d5e03cSMatthew Dillon
2023b7d5e03cSMatthew Dillon /* return low word of TSF at arm time */
2024b7d5e03cSMatthew Dillon return ret;
2025b7d5e03cSMatthew Dillon }
2026b7d5e03cSMatthew Dillon
2027b7d5e03cSMatthew Dillon int
ar9300_ppm_get_trigger(struct ath_hal * ah)2028b7d5e03cSMatthew Dillon ar9300_ppm_get_trigger(struct ath_hal *ah)
2029b7d5e03cSMatthew Dillon {
2030b7d5e03cSMatthew Dillon if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) &
2031b7d5e03cSMatthew Dillon AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK)
2032b7d5e03cSMatthew Dillon {
2033b7d5e03cSMatthew Dillon /* has not triggered yet, return AH_FALSE */
2034b7d5e03cSMatthew Dillon return 0;
2035b7d5e03cSMatthew Dillon }
2036b7d5e03cSMatthew Dillon
2037b7d5e03cSMatthew Dillon /* else triggered, return AH_TRUE */
2038b7d5e03cSMatthew Dillon return 1;
2039b7d5e03cSMatthew Dillon }
2040b7d5e03cSMatthew Dillon
2041b7d5e03cSMatthew Dillon void
ar9300_mark_phy_inactive(struct ath_hal * ah)2042b7d5e03cSMatthew Dillon ar9300_mark_phy_inactive(struct ath_hal *ah)
2043b7d5e03cSMatthew Dillon {
2044b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
2045b7d5e03cSMatthew Dillon }
2046b7d5e03cSMatthew Dillon
2047b7d5e03cSMatthew Dillon /* DEBUG */
2048b7d5e03cSMatthew Dillon u_int32_t
ar9300_ppm_get_force_state(struct ath_hal * ah)2049b7d5e03cSMatthew Dillon ar9300_ppm_get_force_state(struct ath_hal *ah)
2050b7d5e03cSMatthew Dillon {
2051b7d5e03cSMatthew Dillon return
2052b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_TIMING2) &
2053b7d5e03cSMatthew Dillon (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL);
2054b7d5e03cSMatthew Dillon }
2055b7d5e03cSMatthew Dillon
2056b7d5e03cSMatthew Dillon /*
2057b7d5e03cSMatthew Dillon * Return the Cycle counts for rx_frame, rx_clear, and tx_frame
2058b7d5e03cSMatthew Dillon */
2059b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_get_mib_cycle_counts(struct ath_hal * ah,HAL_SURVEY_SAMPLE * hs)2060b7d5e03cSMatthew Dillon ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs)
2061b7d5e03cSMatthew Dillon {
2062b7d5e03cSMatthew Dillon /*
2063b7d5e03cSMatthew Dillon * XXX FreeBSD todo: reimplement this
2064b7d5e03cSMatthew Dillon */
2065b7d5e03cSMatthew Dillon #if 0
2066b7d5e03cSMatthew Dillon p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
2067b7d5e03cSMatthew Dillon p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
2068b7d5e03cSMatthew Dillon p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
2069b7d5e03cSMatthew Dillon p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT);
2070b7d5e03cSMatthew Dillon p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) ==
2071b7d5e03cSMatthew Dillon p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE;
2072b7d5e03cSMatthew Dillon p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) ==
2073b7d5e03cSMatthew Dillon p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE;
2074b7d5e03cSMatthew Dillon #endif
2075b7d5e03cSMatthew Dillon return AH_FALSE;
2076b7d5e03cSMatthew Dillon }
2077b7d5e03cSMatthew Dillon
2078b7d5e03cSMatthew Dillon void
ar9300_clear_mib_counters(struct ath_hal * ah)2079b7d5e03cSMatthew Dillon ar9300_clear_mib_counters(struct ath_hal *ah)
2080b7d5e03cSMatthew Dillon {
2081b7d5e03cSMatthew Dillon u_int32_t reg_val;
2082b7d5e03cSMatthew Dillon
2083b7d5e03cSMatthew Dillon reg_val = OS_REG_READ(ah, AR_MIBC);
2084b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC);
2085b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC);
2086b7d5e03cSMatthew Dillon }
2087b7d5e03cSMatthew Dillon
2088b7d5e03cSMatthew Dillon
2089b7d5e03cSMatthew Dillon /* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */
2090b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_set_rifs_delay(struct ath_hal * ah,HAL_BOOL enable)2091b7d5e03cSMatthew Dillon ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable)
2092b7d5e03cSMatthew Dillon {
2093b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2094b7d5e03cSMatthew Dillon HAL_CHANNEL_INTERNAL *ichan =
2095b7d5e03cSMatthew Dillon ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
2096b7d5e03cSMatthew Dillon HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan);
2097b7d5e03cSMatthew Dillon u_int32_t tmp = 0;
2098b7d5e03cSMatthew Dillon
2099b7d5e03cSMatthew Dillon if (enable) {
2100b7d5e03cSMatthew Dillon if (ahp->ah_rifs_enabled == AH_TRUE) {
2101b7d5e03cSMatthew Dillon return AH_TRUE;
2102b7d5e03cSMatthew Dillon }
2103b7d5e03cSMatthew Dillon
2104b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]);
2105b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2106b7d5e03cSMatthew Dillon ahp->ah_rifs_reg[1]);
2107b7d5e03cSMatthew Dillon
2108b7d5e03cSMatthew Dillon ahp->ah_rifs_enabled = AH_TRUE;
2109b7d5e03cSMatthew Dillon OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg));
2110b7d5e03cSMatthew Dillon } else {
2111b7d5e03cSMatthew Dillon if (ahp->ah_rifs_enabled == AH_TRUE) {
2112b7d5e03cSMatthew Dillon ahp->ah_rifs_reg[0] = OS_REG_READ(ah,
2113b7d5e03cSMatthew Dillon AR_PHY_SEARCH_START_DELAY);
2114b7d5e03cSMatthew Dillon ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH);
2115b7d5e03cSMatthew Dillon }
2116b7d5e03cSMatthew Dillon /* Change rifs init delay to 0 */
2117b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH,
2118b7d5e03cSMatthew Dillon (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY)));
2119b7d5e03cSMatthew Dillon tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY);
2120b7d5e03cSMatthew Dillon if (is_chan_2g) {
2121b7d5e03cSMatthew Dillon if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2122b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500);
2123b7d5e03cSMatthew Dillon } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */
2124b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250);
2125b7d5e03cSMatthew Dillon }
2126b7d5e03cSMatthew Dillon } else {
2127b7d5e03cSMatthew Dillon if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) {
2128b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370);
2129b7d5e03cSMatthew Dillon } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */
2130b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8);
2131b7d5e03cSMatthew Dillon }
2132b7d5e03cSMatthew Dillon }
2133b7d5e03cSMatthew Dillon
2134b7d5e03cSMatthew Dillon ahp->ah_rifs_enabled = AH_FALSE;
2135b7d5e03cSMatthew Dillon }
2136b7d5e03cSMatthew Dillon return AH_TRUE;
2137b7d5e03cSMatthew Dillon
2138b7d5e03cSMatthew Dillon } /* ar9300_set_rifs_delay () */
2139b7d5e03cSMatthew Dillon
2140b7d5e03cSMatthew Dillon /* Set the current RIFS Rx setting */
2141b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_set_11n_rx_rifs(struct ath_hal * ah,HAL_BOOL enable)2142b7d5e03cSMatthew Dillon ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable)
2143b7d5e03cSMatthew Dillon {
2144b7d5e03cSMatthew Dillon /* Non-Owl 11n chips */
2145b7d5e03cSMatthew Dillon if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) {
2146b7d5e03cSMatthew Dillon if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) {
2147b7d5e03cSMatthew Dillon return ar9300_set_rifs_delay(ah, enable);
2148b7d5e03cSMatthew Dillon }
2149b7d5e03cSMatthew Dillon return AH_FALSE;
2150b7d5e03cSMatthew Dillon }
2151b7d5e03cSMatthew Dillon
2152b7d5e03cSMatthew Dillon return AH_TRUE;
2153b7d5e03cSMatthew Dillon } /* ar9300_set_11n_rx_rifs () */
2154b7d5e03cSMatthew Dillon
2155b7d5e03cSMatthew Dillon static hal_mac_hangs_t
ar9300_compare_dbg_hang(struct ath_hal * ah,mac_dbg_regs_t mac_dbg,hal_mac_hang_check_t hang_check,hal_mac_hangs_t hangs,u_int8_t * dcu_chain)2156b7d5e03cSMatthew Dillon ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg,
2157b7d5e03cSMatthew Dillon hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain)
2158b7d5e03cSMatthew Dillon {
2159b7d5e03cSMatthew Dillon int i = 0;
2160b7d5e03cSMatthew Dillon hal_mac_hangs_t found_hangs = 0;
2161b7d5e03cSMatthew Dillon
2162b7d5e03cSMatthew Dillon if (hangs & dcu_chain_state) {
2163b7d5e03cSMatthew Dillon for (i = 0; i < 6; i++) {
2164b7d5e03cSMatthew Dillon if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) ==
2165b7d5e03cSMatthew Dillon hang_check.dcu_chain_state)
2166b7d5e03cSMatthew Dillon {
2167b7d5e03cSMatthew Dillon found_hangs |= dcu_chain_state;
2168b7d5e03cSMatthew Dillon *dcu_chain = i;
2169b7d5e03cSMatthew Dillon }
2170b7d5e03cSMatthew Dillon }
2171b7d5e03cSMatthew Dillon for (i = 0; i < 4; i++) {
2172b7d5e03cSMatthew Dillon if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) ==
2173b7d5e03cSMatthew Dillon hang_check.dcu_chain_state)
2174b7d5e03cSMatthew Dillon {
2175b7d5e03cSMatthew Dillon found_hangs |= dcu_chain_state;
2176b7d5e03cSMatthew Dillon *dcu_chain = i + 6;
2177b7d5e03cSMatthew Dillon }
2178b7d5e03cSMatthew Dillon }
2179b7d5e03cSMatthew Dillon }
2180b7d5e03cSMatthew Dillon
2181b7d5e03cSMatthew Dillon if (hangs & dcu_complete_state) {
2182b7d5e03cSMatthew Dillon if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) {
2183b7d5e03cSMatthew Dillon found_hangs |= dcu_complete_state;
2184b7d5e03cSMatthew Dillon }
2185b7d5e03cSMatthew Dillon }
2186b7d5e03cSMatthew Dillon
2187b7d5e03cSMatthew Dillon return found_hangs;
2188b7d5e03cSMatthew Dillon
2189b7d5e03cSMatthew Dillon } /* end - ar9300_compare_dbg_hang */
2190b7d5e03cSMatthew Dillon
2191b7d5e03cSMatthew Dillon #define NUM_STATUS_READS 50
2192b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_detect_mac_hang(struct ath_hal * ah)2193b7d5e03cSMatthew Dillon ar9300_detect_mac_hang(struct ath_hal *ah)
2194b7d5e03cSMatthew Dillon {
2195b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2196b7d5e03cSMatthew Dillon mac_dbg_regs_t mac_dbg;
2197b7d5e03cSMatthew Dillon hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0};
2198b7d5e03cSMatthew Dillon hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state);
2199b7d5e03cSMatthew Dillon int i = 0;
2200b7d5e03cSMatthew Dillon u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val;
2201b7d5e03cSMatthew Dillon
2202b7d5e03cSMatthew Dillon if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) {
2203b7d5e03cSMatthew Dillon return AH_FALSE;
2204b7d5e03cSMatthew Dillon }
2205b7d5e03cSMatthew Dillon
2206b7d5e03cSMatthew Dillon OS_MEMZERO(&mac_dbg, sizeof(mac_dbg));
2207b7d5e03cSMatthew Dillon
2208b7d5e03cSMatthew Dillon mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
2209b7d5e03cSMatthew Dillon mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
2210b7d5e03cSMatthew Dillon mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
2211b7d5e03cSMatthew Dillon
2212b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n",
2213b7d5e03cSMatthew Dillon mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5,
2214b7d5e03cSMatthew Dillon mac_dbg.dma_dbg_6);
2215b7d5e03cSMatthew Dillon
2216b7d5e03cSMatthew Dillon if (hang_sig1 !=
2217b7d5e03cSMatthew Dillon ar9300_compare_dbg_hang(ah, mac_dbg,
2218b7d5e03cSMatthew Dillon hang_sig1_val, hang_sig1, &dcu_chain))
2219b7d5e03cSMatthew Dillon {
2220b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n");
2221b7d5e03cSMatthew Dillon return AH_FALSE;
2222b7d5e03cSMatthew Dillon }
2223b7d5e03cSMatthew Dillon
2224b7d5e03cSMatthew Dillon shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain);
2225b7d5e03cSMatthew Dillon shift_val *= 5;
2226b7d5e03cSMatthew Dillon
2227b7d5e03cSMatthew Dillon for (i = 1; i <= NUM_STATUS_READS; i++) {
2228b7d5e03cSMatthew Dillon if (dcu_chain < 6) {
2229b7d5e03cSMatthew Dillon mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4);
2230b7d5e03cSMatthew Dillon current_dcu_chain_state =
2231b7d5e03cSMatthew Dillon ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f);
2232b7d5e03cSMatthew Dillon } else {
2233b7d5e03cSMatthew Dillon mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5);
2234b7d5e03cSMatthew Dillon current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f);
2235b7d5e03cSMatthew Dillon }
2236b7d5e03cSMatthew Dillon mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6);
2237b7d5e03cSMatthew Dillon
2238b7d5e03cSMatthew Dillon if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state)
2239b7d5e03cSMatthew Dillon || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) {
2240b7d5e03cSMatthew Dillon return AH_FALSE;
2241b7d5e03cSMatthew Dillon }
2242b7d5e03cSMatthew Dillon }
2243b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__,
2244b7d5e03cSMatthew Dillon ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]);
2245b7d5e03cSMatthew Dillon ahp->ah_hang[MAC_HANG_SIG1]++;
2246b7d5e03cSMatthew Dillon return AH_TRUE;
2247b7d5e03cSMatthew Dillon
2248b7d5e03cSMatthew Dillon } /* end - ar9300_detect_mac_hang */
2249b7d5e03cSMatthew Dillon
2250b7d5e03cSMatthew Dillon /* Determine if the baseband is hung by reading the Observation Bus Register */
2251b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_detect_bb_hang(struct ath_hal * ah)2252b7d5e03cSMatthew Dillon ar9300_detect_bb_hang(struct ath_hal *ah)
2253b7d5e03cSMatthew Dillon {
2254b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2255b7d5e03cSMatthew Dillon u_int32_t hang_sig = 0;
2256b7d5e03cSMatthew Dillon int i = 0;
2257b7d5e03cSMatthew Dillon /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times
2258b7d5e03cSMatthew Dillon *
2259b7d5e03cSMatthew Dillon * 4 known BB hang signatures -
2260b7d5e03cSMatthew Dillon * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E
2261b7d5e03cSMatthew Dillon * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52
2262b7d5e03cSMatthew Dillon * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18
2263b7d5e03cSMatthew Dillon * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2,
2264b7d5e03cSMatthew Dillon * Rx State (bits 20-24) is 0x7.
2265b7d5e03cSMatthew Dillon */
2266b7d5e03cSMatthew Dillon hal_hw_hang_check_t hang_list [] =
2267b7d5e03cSMatthew Dillon {
2268b7d5e03cSMatthew Dillon /* Offset Reg Value Reg Mask Hang Offset */
2269b7d5e03cSMatthew Dillon {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1},
2270b7d5e03cSMatthew Dillon {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2},
2271b7d5e03cSMatthew Dillon {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3},
2272b7d5e03cSMatthew Dillon {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4}
2273b7d5e03cSMatthew Dillon };
2274b7d5e03cSMatthew Dillon
2275b7d5e03cSMatthew Dillon if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR |
2276b7d5e03cSMatthew Dillon HAL_DFS_BB_HANG_WAR |
2277b7d5e03cSMatthew Dillon HAL_RX_STUCK_LOW_BB_HANG_WAR))) {
2278b7d5e03cSMatthew Dillon return AH_FALSE;
2279b7d5e03cSMatthew Dillon }
2280b7d5e03cSMatthew Dillon
2281b7d5e03cSMatthew Dillon hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1);
2282b7d5e03cSMatthew Dillon for (i = 1; i <= NUM_STATUS_READS; i++) {
2283b7d5e03cSMatthew Dillon if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) {
2284b7d5e03cSMatthew Dillon return AH_FALSE;
2285b7d5e03cSMatthew Dillon }
2286b7d5e03cSMatthew Dillon }
2287b7d5e03cSMatthew Dillon
2288*249483dfSAaron LI for (i = 0; i < nitems(hang_list); i++) {
2289b7d5e03cSMatthew Dillon if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) {
2290b7d5e03cSMatthew Dillon ahp->ah_hang[hang_list[i].hang_offset]++;
2291b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d "
2292b7d5e03cSMatthew Dillon "sig3count=%d sig4count=%d\n", __func__,
2293b7d5e03cSMatthew Dillon ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2],
2294b7d5e03cSMatthew Dillon ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]);
2295b7d5e03cSMatthew Dillon return AH_TRUE;
2296b7d5e03cSMatthew Dillon }
2297b7d5e03cSMatthew Dillon }
2298b7d5e03cSMatthew Dillon
2299b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! "
2300b7d5e03cSMatthew Dillon "<0x806c>=0x%x\n", __func__, hang_sig);
2301b7d5e03cSMatthew Dillon
2302b7d5e03cSMatthew Dillon return AH_FALSE;
2303b7d5e03cSMatthew Dillon
2304b7d5e03cSMatthew Dillon } /* end - ar9300_detect_bb_hang () */
2305b7d5e03cSMatthew Dillon
2306b7d5e03cSMatthew Dillon #undef NUM_STATUS_READS
2307b7d5e03cSMatthew Dillon
2308b7d5e03cSMatthew Dillon HAL_STATUS
ar9300_select_ant_config(struct ath_hal * ah,u_int32_t cfg)2309b7d5e03cSMatthew Dillon ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg)
2310b7d5e03cSMatthew Dillon {
2311b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2312b7d5e03cSMatthew Dillon const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2313b7d5e03cSMatthew Dillon HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2314b7d5e03cSMatthew Dillon const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2315b7d5e03cSMatthew Dillon u_int16_t ant_config;
2316b7d5e03cSMatthew Dillon u_int32_t hal_num_ant_config;
2317b7d5e03cSMatthew Dillon
2318b7d5e03cSMatthew Dillon hal_num_ant_config = IS_CHAN_2GHZ(ichan) ?
2319b7d5e03cSMatthew Dillon p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
2320b7d5e03cSMatthew Dillon
2321b7d5e03cSMatthew Dillon if (cfg < hal_num_ant_config) {
2322b7d5e03cSMatthew Dillon if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) {
2323b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
2324b7d5e03cSMatthew Dillon return HAL_OK;
2325b7d5e03cSMatthew Dillon }
2326b7d5e03cSMatthew Dillon }
2327b7d5e03cSMatthew Dillon
2328b7d5e03cSMatthew Dillon return HAL_EINVAL;
2329b7d5e03cSMatthew Dillon }
2330b7d5e03cSMatthew Dillon
2331b7d5e03cSMatthew Dillon /*
2332b7d5e03cSMatthew Dillon * Functions to get/set DCS mode
2333b7d5e03cSMatthew Dillon */
2334b7d5e03cSMatthew Dillon void
ar9300_set_dcs_mode(struct ath_hal * ah,u_int32_t mode)2335b7d5e03cSMatthew Dillon ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode)
2336b7d5e03cSMatthew Dillon {
2337b7d5e03cSMatthew Dillon AH9300(ah)->ah_dcs_enable = mode;
2338b7d5e03cSMatthew Dillon }
2339b7d5e03cSMatthew Dillon
2340b7d5e03cSMatthew Dillon u_int32_t
ar9300_get_dcs_mode(struct ath_hal * ah)2341b7d5e03cSMatthew Dillon ar9300_get_dcs_mode(struct ath_hal *ah)
2342b7d5e03cSMatthew Dillon {
2343b7d5e03cSMatthew Dillon return AH9300(ah)->ah_dcs_enable;
2344b7d5e03cSMatthew Dillon }
2345b7d5e03cSMatthew Dillon
2346b7d5e03cSMatthew Dillon #if ATH_BT_COEX
2347b7d5e03cSMatthew Dillon void
ar9300_set_bt_coex_info(struct ath_hal * ah,HAL_BT_COEX_INFO * btinfo)2348b7d5e03cSMatthew Dillon ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo)
2349b7d5e03cSMatthew Dillon {
2350b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2351b7d5e03cSMatthew Dillon
2352b7d5e03cSMatthew Dillon ahp->ah_bt_module = btinfo->bt_module;
2353b7d5e03cSMatthew Dillon ahp->ah_bt_coex_config_type = btinfo->bt_coex_config;
2354b7d5e03cSMatthew Dillon ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active;
2355b7d5e03cSMatthew Dillon ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority;
2356b7d5e03cSMatthew Dillon ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active;
2357b7d5e03cSMatthew Dillon ahp->ah_bt_active_polarity = btinfo->bt_active_polarity;
2358b7d5e03cSMatthew Dillon ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant;
2359b7d5e03cSMatthew Dillon ahp->ah_bt_wlan_isolation = btinfo->bt_isolation;
2360b7d5e03cSMatthew Dillon }
2361b7d5e03cSMatthew Dillon
2362b7d5e03cSMatthew Dillon void
ar9300_bt_coex_config(struct ath_hal * ah,HAL_BT_COEX_CONFIG * btconf)2363b7d5e03cSMatthew Dillon ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf)
2364b7d5e03cSMatthew Dillon {
2365b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2366b7d5e03cSMatthew Dillon HAL_BOOL rx_clear_polarity;
2367b7d5e03cSMatthew Dillon
2368b7d5e03cSMatthew Dillon /*
2369b7d5e03cSMatthew Dillon * For Kiwi and Osprey, the polarity of rx_clear is active high.
2370b7d5e03cSMatthew Dillon * The bt_rxclear_polarity flag from ath_dev needs to be inverted.
2371b7d5e03cSMatthew Dillon */
2372b7d5e03cSMatthew Dillon rx_clear_polarity = !btconf->bt_rxclear_polarity;
2373b7d5e03cSMatthew Dillon
2374b7d5e03cSMatthew Dillon ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) |
2375b7d5e03cSMatthew Dillon SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) |
2376b7d5e03cSMatthew Dillon SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
2377b7d5e03cSMatthew Dillon SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
2378b7d5e03cSMatthew Dillon SM(btconf->bt_mode, AR_BT_MODE) |
2379b7d5e03cSMatthew Dillon SM(btconf->bt_quiet_collision, AR_BT_QUIET) |
2380b7d5e03cSMatthew Dillon SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) |
2381b7d5e03cSMatthew Dillon SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) |
2382b7d5e03cSMatthew Dillon SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME);
2383b7d5e03cSMatthew Dillon
2384b7d5e03cSMatthew Dillon ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR);
2385b7d5e03cSMatthew Dillon
2386b7d5e03cSMatthew Dillon if (ahp->ah_bt_coex_single_ant == AH_FALSE) {
2387b7d5e03cSMatthew Dillon /* Enable ACK to go out even though BT has higher priority. */
2388b7d5e03cSMatthew Dillon ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT;
2389b7d5e03cSMatthew Dillon }
2390b7d5e03cSMatthew Dillon }
2391b7d5e03cSMatthew Dillon
2392b7d5e03cSMatthew Dillon void
ar9300_bt_coex_set_qcu_thresh(struct ath_hal * ah,int qnum)2393b7d5e03cSMatthew Dillon ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum)
2394b7d5e03cSMatthew Dillon {
2395b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2396b7d5e03cSMatthew Dillon
2397b7d5e03cSMatthew Dillon /* clear the old value, then set the new value */
2398b7d5e03cSMatthew Dillon ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH;
2399b7d5e03cSMatthew Dillon ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH);
2400b7d5e03cSMatthew Dillon }
2401b7d5e03cSMatthew Dillon
2402b7d5e03cSMatthew Dillon void
ar9300_bt_coex_set_weights(struct ath_hal * ah,u_int32_t stomp_type)2403b7d5e03cSMatthew Dillon ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
2404b7d5e03cSMatthew Dillon {
2405b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2406b7d5e03cSMatthew Dillon
2407b7d5e03cSMatthew Dillon ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT;
2408b7d5e03cSMatthew Dillon ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT;
2409b7d5e03cSMatthew Dillon ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT;
2410b7d5e03cSMatthew Dillon ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT;
2411b7d5e03cSMatthew Dillon
2412b7d5e03cSMatthew Dillon switch (stomp_type) {
2413b7d5e03cSMatthew Dillon case HAL_BT_COEX_STOMP_ALL:
2414b7d5e03cSMatthew Dillon ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0;
2415b7d5e03cSMatthew Dillon ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1;
2416b7d5e03cSMatthew Dillon break;
2417b7d5e03cSMatthew Dillon case HAL_BT_COEX_STOMP_LOW:
2418b7d5e03cSMatthew Dillon ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0;
2419b7d5e03cSMatthew Dillon ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1;
2420b7d5e03cSMatthew Dillon break;
2421b7d5e03cSMatthew Dillon case HAL_BT_COEX_STOMP_ALL_FORCE:
2422b7d5e03cSMatthew Dillon ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0;
2423b7d5e03cSMatthew Dillon ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1;
2424b7d5e03cSMatthew Dillon break;
2425b7d5e03cSMatthew Dillon case HAL_BT_COEX_STOMP_LOW_FORCE:
2426b7d5e03cSMatthew Dillon ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0;
2427b7d5e03cSMatthew Dillon ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1;
2428b7d5e03cSMatthew Dillon break;
2429b7d5e03cSMatthew Dillon case HAL_BT_COEX_STOMP_NONE:
2430b7d5e03cSMatthew Dillon case HAL_BT_COEX_NO_STOMP:
2431b7d5e03cSMatthew Dillon ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0;
2432b7d5e03cSMatthew Dillon ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1;
2433b7d5e03cSMatthew Dillon break;
2434b7d5e03cSMatthew Dillon default:
2435b7d5e03cSMatthew Dillon /* There is a force_weight from registry */
2436b7d5e03cSMatthew Dillon ahp->ah_bt_coex_wlan_weight[0] = stomp_type;
2437b7d5e03cSMatthew Dillon ahp->ah_bt_coex_wlan_weight[1] = stomp_type;
2438b7d5e03cSMatthew Dillon break;
2439b7d5e03cSMatthew Dillon }
2440b7d5e03cSMatthew Dillon }
2441b7d5e03cSMatthew Dillon
2442b7d5e03cSMatthew Dillon void
ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal * ah,u_int32_t thresh)2443b7d5e03cSMatthew Dillon ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh)
2444b7d5e03cSMatthew Dillon {
2445b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2446b7d5e03cSMatthew Dillon
2447b7d5e03cSMatthew Dillon /* clear the old value, then set the new value */
2448b7d5e03cSMatthew Dillon ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH;
2449b7d5e03cSMatthew Dillon ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH);
2450b7d5e03cSMatthew Dillon }
2451b7d5e03cSMatthew Dillon
2452b7d5e03cSMatthew Dillon static void
ar9300_bt_coex_antenna_diversity(struct ath_hal * ah,u_int32_t value)2453b7d5e03cSMatthew Dillon ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value)
2454b7d5e03cSMatthew Dillon {
2455b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2456b7d5e03cSMatthew Dillon #if ATH_ANT_DIV_COMB
2457b7d5e03cSMatthew Dillon //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2458b7d5e03cSMatthew Dillon const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
2459b7d5e03cSMatthew Dillon #endif
2460b7d5e03cSMatthew Dillon
2461b7d5e03cSMatthew Dillon if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW)
2462b7d5e03cSMatthew Dillon {
2463b7d5e03cSMatthew Dillon if (ahp->ah_diversity_control == HAL_ANT_VARIABLE)
2464b7d5e03cSMatthew Dillon {
2465b7d5e03cSMatthew Dillon /* Config antenna diversity */
2466b7d5e03cSMatthew Dillon #if ATH_ANT_DIV_COMB
2467b7d5e03cSMatthew Dillon ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan);
2468b7d5e03cSMatthew Dillon #endif
2469b7d5e03cSMatthew Dillon }
2470b7d5e03cSMatthew Dillon }
2471b7d5e03cSMatthew Dillon }
2472b7d5e03cSMatthew Dillon
2473b7d5e03cSMatthew Dillon
2474b7d5e03cSMatthew Dillon void
ar9300_bt_coex_set_parameter(struct ath_hal * ah,u_int32_t type,u_int32_t value)2475b7d5e03cSMatthew Dillon ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type,
2476b7d5e03cSMatthew Dillon u_int32_t value)
2477b7d5e03cSMatthew Dillon {
2478b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2479b7d5e03cSMatthew Dillon struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2480b7d5e03cSMatthew Dillon
2481b7d5e03cSMatthew Dillon switch (type) {
2482b7d5e03cSMatthew Dillon case HAL_BT_COEX_SET_ACK_PWR:
2483b7d5e03cSMatthew Dillon if (value) {
2484b7d5e03cSMatthew Dillon ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2485b7d5e03cSMatthew Dillon } else {
2486b7d5e03cSMatthew Dillon ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR;
2487b7d5e03cSMatthew Dillon }
2488b7d5e03cSMatthew Dillon ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2489b7d5e03cSMatthew Dillon ahpriv->ah_extraTxPow, 0);
2490b7d5e03cSMatthew Dillon break;
2491b7d5e03cSMatthew Dillon
2492b7d5e03cSMatthew Dillon case HAL_BT_COEX_ANTENNA_DIVERSITY:
2493b7d5e03cSMatthew Dillon if (AR_SREV_POSEIDON(ah)) {
2494b7d5e03cSMatthew Dillon ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW;
2495b7d5e03cSMatthew Dillon if (value) {
2496b7d5e03cSMatthew Dillon ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2497b7d5e03cSMatthew Dillon }
2498b7d5e03cSMatthew Dillon else {
2499b7d5e03cSMatthew Dillon ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE;
2500b7d5e03cSMatthew Dillon }
2501b7d5e03cSMatthew Dillon ar9300_bt_coex_antenna_diversity(ah, value);
2502b7d5e03cSMatthew Dillon }
2503b7d5e03cSMatthew Dillon break;
2504b7d5e03cSMatthew Dillon case HAL_BT_COEX_LOWER_TX_PWR:
2505b7d5e03cSMatthew Dillon if (value) {
2506b7d5e03cSMatthew Dillon ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2507b7d5e03cSMatthew Dillon }
2508b7d5e03cSMatthew Dillon else {
2509b7d5e03cSMatthew Dillon ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR;
2510b7d5e03cSMatthew Dillon }
2511b7d5e03cSMatthew Dillon ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2512b7d5e03cSMatthew Dillon ahpriv->ah_extraTxPow, 0);
2513b7d5e03cSMatthew Dillon break;
2514b7d5e03cSMatthew Dillon #if ATH_SUPPORT_MCI
2515b7d5e03cSMatthew Dillon case HAL_BT_COEX_MCI_MAX_TX_PWR:
2516b7d5e03cSMatthew Dillon if ((ah->ah_config.ath_hal_mci_config &
2517b7d5e03cSMatthew Dillon ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN)
2518b7d5e03cSMatthew Dillon {
2519b7d5e03cSMatthew Dillon if (value) {
2520b7d5e03cSMatthew Dillon ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2521b7d5e03cSMatthew Dillon ahp->ah_mci_concur_tx_en = AH_TRUE;
2522b7d5e03cSMatthew Dillon }
2523b7d5e03cSMatthew Dillon else {
2524b7d5e03cSMatthew Dillon ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR;
2525b7d5e03cSMatthew Dillon ahp->ah_mci_concur_tx_en = AH_FALSE;
2526b7d5e03cSMatthew Dillon }
2527b7d5e03cSMatthew Dillon ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit,
2528b7d5e03cSMatthew Dillon ahpriv->ah_extraTxPow, 0);
2529b7d5e03cSMatthew Dillon }
2530b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
2531b7d5e03cSMatthew Dillon ahp->ah_mci_concur_tx_en);
2532b7d5e03cSMatthew Dillon break;
2533b7d5e03cSMatthew Dillon case HAL_BT_COEX_MCI_FTP_STOMP_RX:
2534b7d5e03cSMatthew Dillon if (value) {
2535b7d5e03cSMatthew Dillon ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2536b7d5e03cSMatthew Dillon }
2537b7d5e03cSMatthew Dillon else {
2538b7d5e03cSMatthew Dillon ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX;
2539b7d5e03cSMatthew Dillon }
2540b7d5e03cSMatthew Dillon break;
2541b7d5e03cSMatthew Dillon #endif
2542b7d5e03cSMatthew Dillon default:
2543b7d5e03cSMatthew Dillon break;
2544b7d5e03cSMatthew Dillon }
2545b7d5e03cSMatthew Dillon }
2546b7d5e03cSMatthew Dillon
2547b7d5e03cSMatthew Dillon void
ar9300_bt_coex_disable(struct ath_hal * ah)2548b7d5e03cSMatthew Dillon ar9300_bt_coex_disable(struct ath_hal *ah)
2549b7d5e03cSMatthew Dillon {
2550b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2551b7d5e03cSMatthew Dillon
2552b7d5e03cSMatthew Dillon /* Always drive rx_clear_external output as 0 */
2553b7d5e03cSMatthew Dillon ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select,
2554b7d5e03cSMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
2555b7d5e03cSMatthew Dillon
2556b7d5e03cSMatthew Dillon if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2557b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2558b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2559b7d5e03cSMatthew Dillon }
2560b7d5e03cSMatthew Dillon
2561b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
2562b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
2563b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0);
2564b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0);
2565b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0);
2566b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0);
2567b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0);
2568b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0);
2569b7d5e03cSMatthew Dillon
2570b7d5e03cSMatthew Dillon ahp->ah_bt_coex_enabled = AH_FALSE;
2571b7d5e03cSMatthew Dillon }
2572b7d5e03cSMatthew Dillon
2573b7d5e03cSMatthew Dillon int
ar9300_bt_coex_enable(struct ath_hal * ah)2574b7d5e03cSMatthew Dillon ar9300_bt_coex_enable(struct ath_hal *ah)
2575b7d5e03cSMatthew Dillon {
2576b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2577b7d5e03cSMatthew Dillon
2578b7d5e03cSMatthew Dillon /* Program coex mode and weight registers to actually enable coex */
2579b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode);
2580b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2);
2581b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]);
2582b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]);
2583b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]);
2584b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]);
2585b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]);
2586b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]);
2587b7d5e03cSMatthew Dillon
2588b7d5e03cSMatthew Dillon if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) {
2589b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER);
2590b7d5e03cSMatthew Dillon } else {
2591b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER);
2592b7d5e03cSMatthew Dillon }
2593b7d5e03cSMatthew Dillon
2594b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
2595b7d5e03cSMatthew Dillon if (ahp->ah_bt_coex_single_ant == AH_TRUE) {
2596b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1);
2597b7d5e03cSMatthew Dillon } else {
2598b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
2599b7d5e03cSMatthew Dillon }
2600b7d5e03cSMatthew Dillon
2601b7d5e03cSMatthew Dillon if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2602b7d5e03cSMatthew Dillon /* For 3-wire, configure the desired GPIO port for rx_clear */
2603b7d5e03cSMatthew Dillon ath_hal_gpioCfgOutput(ah,
2604b7d5e03cSMatthew Dillon ahp->ah_wlan_active_gpio_select,
2605b7d5e03cSMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE);
2606b7d5e03cSMatthew Dillon }
2607b7d5e03cSMatthew Dillon else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2608b7d5e03cSMatthew Dillon (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2609b7d5e03cSMatthew Dillon {
2610b7d5e03cSMatthew Dillon /* For 2-wire, configure the desired GPIO port for TX_FRAME output */
2611b7d5e03cSMatthew Dillon ath_hal_gpioCfgOutput(ah,
2612b7d5e03cSMatthew Dillon ahp->ah_wlan_active_gpio_select,
2613b7d5e03cSMatthew Dillon HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME);
2614b7d5e03cSMatthew Dillon }
2615b7d5e03cSMatthew Dillon
2616b7d5e03cSMatthew Dillon /*
2617b7d5e03cSMatthew Dillon * Enable a weak pull down on BT_ACTIVE.
2618b7d5e03cSMatthew Dillon * When BT device is disabled, BT_ACTIVE might be floating.
2619b7d5e03cSMatthew Dillon */
2620b7d5e03cSMatthew Dillon OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU),
2621b7d5e03cSMatthew Dillon (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)),
2622b7d5e03cSMatthew Dillon (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2)));
2623b7d5e03cSMatthew Dillon
2624b7d5e03cSMatthew Dillon ahp->ah_bt_coex_enabled = AH_TRUE;
2625b7d5e03cSMatthew Dillon
2626b7d5e03cSMatthew Dillon return 0;
2627b7d5e03cSMatthew Dillon }
2628b7d5e03cSMatthew Dillon
ar9300_get_bt_active_gpio(struct ath_hal * ah,u_int32_t reg)2629b7d5e03cSMatthew Dillon u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg)
2630b7d5e03cSMatthew Dillon {
2631b7d5e03cSMatthew Dillon return 0;
2632b7d5e03cSMatthew Dillon }
2633b7d5e03cSMatthew Dillon
ar9300_get_wlan_active_gpio(struct ath_hal * ah,u_int32_t reg,u_int32_t bOn)2634b7d5e03cSMatthew Dillon u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn)
2635b7d5e03cSMatthew Dillon {
2636b7d5e03cSMatthew Dillon return bOn;
2637b7d5e03cSMatthew Dillon }
2638b7d5e03cSMatthew Dillon
2639b7d5e03cSMatthew Dillon void
ar9300_init_bt_coex(struct ath_hal * ah)2640b7d5e03cSMatthew Dillon ar9300_init_bt_coex(struct ath_hal *ah)
2641b7d5e03cSMatthew Dillon {
2642b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2643b7d5e03cSMatthew Dillon
2644b7d5e03cSMatthew Dillon if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) {
2645b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2646b7d5e03cSMatthew Dillon (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
2647b7d5e03cSMatthew Dillon AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
2648b7d5e03cSMatthew Dillon
2649b7d5e03cSMatthew Dillon /*
2650b7d5e03cSMatthew Dillon * Set input mux for bt_prority_async and
2651b7d5e03cSMatthew Dillon * bt_active_async to GPIO pins
2652b7d5e03cSMatthew Dillon */
2653b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah,
2654b7d5e03cSMatthew Dillon AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2655b7d5e03cSMatthew Dillon AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2656b7d5e03cSMatthew Dillon ahp->ah_bt_active_gpio_select);
2657b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah,
2658b7d5e03cSMatthew Dillon AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2659b7d5e03cSMatthew Dillon AR_GPIO_INPUT_MUX1_BT_PRIORITY,
2660b7d5e03cSMatthew Dillon ahp->ah_bt_priority_gpio_select);
2661b7d5e03cSMatthew Dillon
2662b7d5e03cSMatthew Dillon /* Configure the desired GPIO ports for input */
2663b7d5e03cSMatthew Dillon ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2664b7d5e03cSMatthew Dillon ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select);
2665b7d5e03cSMatthew Dillon
2666b7d5e03cSMatthew Dillon if (ahp->ah_bt_coex_enabled) {
2667b7d5e03cSMatthew Dillon ar9300_bt_coex_enable(ah);
2668b7d5e03cSMatthew Dillon } else {
2669b7d5e03cSMatthew Dillon ar9300_bt_coex_disable(ah);
2670b7d5e03cSMatthew Dillon }
2671b7d5e03cSMatthew Dillon }
2672b7d5e03cSMatthew Dillon else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) &&
2673b7d5e03cSMatthew Dillon (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0))
2674b7d5e03cSMatthew Dillon {
2675b7d5e03cSMatthew Dillon /* 2-wire */
2676b7d5e03cSMatthew Dillon if (ahp->ah_bt_coex_enabled) {
2677b7d5e03cSMatthew Dillon /* Connect bt_active_async to baseband */
2678b7d5e03cSMatthew Dillon OS_REG_CLR_BIT(ah,
2679b7d5e03cSMatthew Dillon AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2680b7d5e03cSMatthew Dillon (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
2681b7d5e03cSMatthew Dillon AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
2682b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah,
2683b7d5e03cSMatthew Dillon AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL),
2684b7d5e03cSMatthew Dillon AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
2685b7d5e03cSMatthew Dillon
2686b7d5e03cSMatthew Dillon /*
2687b7d5e03cSMatthew Dillon * Set input mux for bt_prority_async and
2688b7d5e03cSMatthew Dillon * bt_active_async to GPIO pins
2689b7d5e03cSMatthew Dillon */
2690b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah,
2691b7d5e03cSMatthew Dillon AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1),
2692b7d5e03cSMatthew Dillon AR_GPIO_INPUT_MUX1_BT_ACTIVE,
2693b7d5e03cSMatthew Dillon ahp->ah_bt_active_gpio_select);
2694b7d5e03cSMatthew Dillon
2695b7d5e03cSMatthew Dillon /* Configure the desired GPIO ports for input */
2696b7d5e03cSMatthew Dillon ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select);
2697b7d5e03cSMatthew Dillon
2698b7d5e03cSMatthew Dillon /* Enable coexistence on initialization */
2699b7d5e03cSMatthew Dillon ar9300_bt_coex_enable(ah);
2700b7d5e03cSMatthew Dillon }
2701b7d5e03cSMatthew Dillon }
2702b7d5e03cSMatthew Dillon #if ATH_SUPPORT_MCI
2703b7d5e03cSMatthew Dillon else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) {
2704b7d5e03cSMatthew Dillon if (ahp->ah_bt_coex_enabled) {
2705b7d5e03cSMatthew Dillon ar9300_mci_bt_coex_enable(ah);
2706b7d5e03cSMatthew Dillon }
2707b7d5e03cSMatthew Dillon else {
2708b7d5e03cSMatthew Dillon ar9300_mci_bt_coex_disable(ah);
2709b7d5e03cSMatthew Dillon }
2710b7d5e03cSMatthew Dillon }
2711b7d5e03cSMatthew Dillon #endif /* ATH_SUPPORT_MCI */
2712b7d5e03cSMatthew Dillon }
2713b7d5e03cSMatthew Dillon
2714b7d5e03cSMatthew Dillon #endif /* ATH_BT_COEX */
2715b7d5e03cSMatthew Dillon
ar9300_set_proxy_sta(struct ath_hal * ah,HAL_BOOL enable)2716b7d5e03cSMatthew Dillon HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable)
2717b7d5e03cSMatthew Dillon {
2718b7d5e03cSMatthew Dillon u_int32_t val;
2719b7d5e03cSMatthew Dillon int wasp_mm_rev;
2720b7d5e03cSMatthew Dillon
2721b7d5e03cSMatthew Dillon #define AR_SOC_RST_REVISION_ID 0xB8060090
2722b7d5e03cSMatthew Dillon #define REG_READ(_reg) *((volatile u_int32_t *)(_reg))
2723b7d5e03cSMatthew Dillon wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) &
2724b7d5e03cSMatthew Dillon AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >>
2725b7d5e03cSMatthew Dillon AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT;
2726b7d5e03cSMatthew Dillon #undef AR_SOC_RST_REVISION_ID
2727b7d5e03cSMatthew Dillon #undef REG_READ
2728b7d5e03cSMatthew Dillon
2729b7d5e03cSMatthew Dillon /*
2730b7d5e03cSMatthew Dillon * Azimuth (ProxySTA) Mode is only supported correctly by
2731b7d5e03cSMatthew Dillon * Peacock or WASP 1.3.0.1 or later (hopefully) chips.
2732b7d5e03cSMatthew Dillon *
2733b7d5e03cSMatthew Dillon * Enable this feature for Scorpion at this time. The silicon
2734b7d5e03cSMatthew Dillon * still needs to be validated.
2735b7d5e03cSMatthew Dillon */
2736b7d5e03cSMatthew Dillon if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) &&
2737b7d5e03cSMatthew Dillon !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) &&
2738b7d5e03cSMatthew Dillon !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) &&
2739b7d5e03cSMatthew Dillon ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) ||
2740b7d5e03cSMatthew Dillon (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 &&
2741b7d5e03cSMatthew Dillon wasp_mm_rev >= 0 /* 1 */))))
2742b7d5e03cSMatthew Dillon {
2743b7d5e03cSMatthew Dillon HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, "
2744b7d5e03cSMatthew Dillon "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n",
2745b7d5e03cSMatthew Dillon __func__, AH_PRIVATE((ah))->ah_macVersion,
2746b7d5e03cSMatthew Dillon AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev);
2747b7d5e03cSMatthew Dillon return HAL_ENOTSUPP;
2748b7d5e03cSMatthew Dillon }
2749b7d5e03cSMatthew Dillon
2750b7d5e03cSMatthew Dillon OS_REG_WRITE(ah,
2751b7d5e03cSMatthew Dillon AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996);
2752b7d5e03cSMatthew Dillon
2753b7d5e03cSMatthew Dillon /* turn on mode bit[24] for proxy sta */
2754b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PCU_MISC_MODE2,
2755b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA);
2756b7d5e03cSMatthew Dillon
2757b7d5e03cSMatthew Dillon val = OS_REG_READ(ah, AR_AZIMUTH_MODE);
2758b7d5e03cSMatthew Dillon if (enable) {
2759b7d5e03cSMatthew Dillon val |= AR_AZIMUTH_KEY_SEARCH_AD1 |
2760b7d5e03cSMatthew Dillon AR_AZIMUTH_CTS_MATCH_TX_AD2 |
2761b7d5e03cSMatthew Dillon AR_AZIMUTH_BA_USES_AD1;
2762b7d5e03cSMatthew Dillon /* turn off filter pass hold (bit 9) */
2763b7d5e03cSMatthew Dillon val &= ~AR_AZIMUTH_FILTER_PASS_HOLD;
2764b7d5e03cSMatthew Dillon } else {
2765b7d5e03cSMatthew Dillon val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 |
2766b7d5e03cSMatthew Dillon AR_AZIMUTH_CTS_MATCH_TX_AD2 |
2767b7d5e03cSMatthew Dillon AR_AZIMUTH_BA_USES_AD1);
2768b7d5e03cSMatthew Dillon }
2769b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val);
2770b7d5e03cSMatthew Dillon
2771b7d5e03cSMatthew Dillon /* enable promiscous mode */
2772b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_RX_FILTER,
2773b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM);
2774b7d5e03cSMatthew Dillon /* enable promiscous in azimuth mode */
2775b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE);
2776b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE);
2777b7d5e03cSMatthew Dillon
2778b7d5e03cSMatthew Dillon /* turn on filter pass hold (bit 9) */
2779b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_AZIMUTH_MODE,
2780b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD);
2781b7d5e03cSMatthew Dillon
2782b7d5e03cSMatthew Dillon return HAL_OK;
2783b7d5e03cSMatthew Dillon }
2784b7d5e03cSMatthew Dillon
2785b7d5e03cSMatthew Dillon #if 0
2786b7d5e03cSMatthew Dillon void ar9300_mat_enable(struct ath_hal *ah, int enable)
2787b7d5e03cSMatthew Dillon {
2788b7d5e03cSMatthew Dillon /*
2789b7d5e03cSMatthew Dillon * MAT (s/w ProxySTA) implementation requires to turn off interrupt
2790b7d5e03cSMatthew Dillon * mitigation and turn on key search always for better performance.
2791b7d5e03cSMatthew Dillon */
2792b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2793b7d5e03cSMatthew Dillon struct ath_hal_private *ap = AH_PRIVATE(ah);
2794b7d5e03cSMatthew Dillon
2795b7d5e03cSMatthew Dillon ahp->ah_intr_mitigation_rx = !enable;
2796b7d5e03cSMatthew Dillon if (ahp->ah_intr_mitigation_rx) {
2797b7d5e03cSMatthew Dillon /*
2798b7d5e03cSMatthew Dillon * Enable Interrupt Mitigation for Rx.
2799b7d5e03cSMatthew Dillon * If no build-specific limits for the rx interrupt mitigation
2800b7d5e03cSMatthew Dillon * timer have been specified, use conservative defaults.
2801b7d5e03cSMatthew Dillon */
2802b7d5e03cSMatthew Dillon #ifndef AH_RIMT_VAL_LAST
2803b7d5e03cSMatthew Dillon #define AH_RIMT_LAST_MICROSEC 500
2804b7d5e03cSMatthew Dillon #endif
2805b7d5e03cSMatthew Dillon #ifndef AH_RIMT_VAL_FIRST
2806b7d5e03cSMatthew Dillon #define AH_RIMT_FIRST_MICROSEC 2000
2807b7d5e03cSMatthew Dillon #endif
2808b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC);
2809b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC);
2810b7d5e03cSMatthew Dillon } else {
2811b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_RIMT, 0);
2812b7d5e03cSMatthew Dillon }
2813b7d5e03cSMatthew Dillon
2814b7d5e03cSMatthew Dillon ahp->ah_enable_keysearch_always = !!enable;
2815b7d5e03cSMatthew Dillon ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always);
2816b7d5e03cSMatthew Dillon }
2817b7d5e03cSMatthew Dillon #endif
2818b7d5e03cSMatthew Dillon
ar9300_enable_tpc(struct ath_hal * ah)2819b7d5e03cSMatthew Dillon void ar9300_enable_tpc(struct ath_hal *ah)
2820b7d5e03cSMatthew Dillon {
2821b7d5e03cSMatthew Dillon u_int32_t val = 0;
2822b7d5e03cSMatthew Dillon
2823b7d5e03cSMatthew Dillon ah->ah_config.ath_hal_desc_tpc = 1;
2824b7d5e03cSMatthew Dillon
2825b7d5e03cSMatthew Dillon /* Enable TPC */
2826b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1);
2827b7d5e03cSMatthew Dillon
2828b7d5e03cSMatthew Dillon /*
2829b7d5e03cSMatthew Dillon * Disable per chain power reduction since we are already
2830b7d5e03cSMatthew Dillon * accounting for this in our calculations
2831b7d5e03cSMatthew Dillon */
2832b7d5e03cSMatthew Dillon val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB);
2833b7d5e03cSMatthew Dillon if (AR_SREV_WASP(ah)) {
2834b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2835b7d5e03cSMatthew Dillon val & AR_PHY_POWER_TX_SUB_2_DISABLE);
2836b7d5e03cSMatthew Dillon } else {
2837b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2838b7d5e03cSMatthew Dillon val & AR_PHY_POWER_TX_SUB_3_DISABLE);
2839b7d5e03cSMatthew Dillon }
2840b7d5e03cSMatthew Dillon }
2841b7d5e03cSMatthew Dillon
2842b7d5e03cSMatthew Dillon
2843b7d5e03cSMatthew Dillon /*
2844b7d5e03cSMatthew Dillon * ar9300_force_tsf_sync
2845b7d5e03cSMatthew Dillon * This function forces the TSF sync to the given bssid, this is implemented
2846b7d5e03cSMatthew Dillon * as a temp hack to get the AoW demo, and is primarily used in the WDS client
2847b7d5e03cSMatthew Dillon * mode of operation, where we sync the TSF to RootAP TSF values
2848b7d5e03cSMatthew Dillon */
2849b7d5e03cSMatthew Dillon void
ar9300_force_tsf_sync(struct ath_hal * ah,const u_int8_t * bssid,u_int16_t assoc_id)2850b7d5e03cSMatthew Dillon ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid,
2851b7d5e03cSMatthew Dillon u_int16_t assoc_id)
2852b7d5e03cSMatthew Dillon {
2853b7d5e03cSMatthew Dillon ar9300_set_operating_mode(ah, HAL_M_STA);
2854b7d5e03cSMatthew Dillon ar9300_write_associd(ah, bssid, assoc_id);
2855b7d5e03cSMatthew Dillon }
2856b7d5e03cSMatthew Dillon
ar9300_chk_rssi_update_tx_pwr(struct ath_hal * ah,int rssi)2857b7d5e03cSMatthew Dillon void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi)
2858b7d5e03cSMatthew Dillon {
2859b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
2860b7d5e03cSMatthew Dillon u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val;
2861b7d5e03cSMatthew Dillon u_int32_t temp_powertx_rate9_reg_val;
2862b7d5e03cSMatthew Dillon int8_t olpc_power_offset = 0;
2863b7d5e03cSMatthew Dillon int8_t tmp_olpc_val = 0;
2864b7d5e03cSMatthew Dillon HAL_RSSI_TX_POWER old_greentx_status;
2865b7d5e03cSMatthew Dillon u_int8_t target_power_val_t[ar9300_rate_size];
2866b7d5e03cSMatthew Dillon int8_t tmp_rss1_thr1, tmp_rss1_thr2;
2867b7d5e03cSMatthew Dillon
2868b7d5e03cSMatthew Dillon if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) ||
2869b7d5e03cSMatthew Dillon !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) {
2870b7d5e03cSMatthew Dillon return;
2871b7d5e03cSMatthew Dillon }
2872b7d5e03cSMatthew Dillon
2873b7d5e03cSMatthew Dillon old_greentx_status = AH9300(ah)->green_tx_status;
2874b7d5e03cSMatthew Dillon if (ahp->ah_hw_green_tx_enable) {
2875b7d5e03cSMatthew Dillon tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB;
2876b7d5e03cSMatthew Dillon tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB;
2877b7d5e03cSMatthew Dillon } else {
2878b7d5e03cSMatthew Dillon tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB;
2879b7d5e03cSMatthew Dillon tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB;
2880b7d5e03cSMatthew Dillon }
2881b7d5e03cSMatthew Dillon
2882b7d5e03cSMatthew Dillon if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1)
2883b7d5e03cSMatthew Dillon && (rssi > tmp_rss1_thr1))
2884b7d5e03cSMatthew Dillon {
2885b7d5e03cSMatthew Dillon if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) {
2886b7d5e03cSMatthew Dillon AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT;
2887b7d5e03cSMatthew Dillon }
2888b7d5e03cSMatthew Dillon } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2
2889b7d5e03cSMatthew Dillon && (rssi > tmp_rss1_thr2))
2890b7d5e03cSMatthew Dillon {
2891b7d5e03cSMatthew Dillon if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) {
2892b7d5e03cSMatthew Dillon AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE;
2893b7d5e03cSMatthew Dillon }
2894b7d5e03cSMatthew Dillon } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) {
2895b7d5e03cSMatthew Dillon if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) {
2896b7d5e03cSMatthew Dillon AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG;
2897b7d5e03cSMatthew Dillon }
2898b7d5e03cSMatthew Dillon }
2899b7d5e03cSMatthew Dillon
2900b7d5e03cSMatthew Dillon /* If status is not change, don't do anything */
2901b7d5e03cSMatthew Dillon if (old_greentx_status == AH9300(ah)->green_tx_status) {
2902b7d5e03cSMatthew Dillon return;
2903b7d5e03cSMatthew Dillon }
2904b7d5e03cSMatthew Dillon
2905b7d5e03cSMatthew Dillon /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */
2906b7d5e03cSMatthew Dillon if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE)
2907b7d5e03cSMatthew Dillon && AR_SREV_POSEIDON(ah))
2908b7d5e03cSMatthew Dillon {
2909b7d5e03cSMatthew Dillon if (ahp->ah_hw_green_tx_enable) {
2910b7d5e03cSMatthew Dillon switch (AH9300(ah)->green_tx_status) {
2911b7d5e03cSMatthew Dillon case HAL_RSSI_TX_POWER_SHORT:
2912b7d5e03cSMatthew Dillon /* 1. TxPower Config */
2913b7d5e03cSMatthew Dillon OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short,
2914b7d5e03cSMatthew Dillon sizeof(target_power_val_t));
2915b7d5e03cSMatthew Dillon /* 1.1 Store OLPC Delta Calibration Offset*/
2916b7d5e03cSMatthew Dillon olpc_power_offset = 0;
2917b7d5e03cSMatthew Dillon /* 2. Store OB/DB */
2918b7d5e03cSMatthew Dillon /* 3. Store TPC settting */
2919b7d5e03cSMatthew Dillon temp_tcp_reg_val = (SM(14, AR_TPC_ACK) |
2920b7d5e03cSMatthew Dillon SM(14, AR_TPC_CTS) |
2921b7d5e03cSMatthew Dillon SM(14, AR_TPC_CHIRP) |
2922b7d5e03cSMatthew Dillon SM(14, AR_TPC_RPT));
2923b7d5e03cSMatthew Dillon /* 4. Store BB_powertx_rate9 value */
2924b7d5e03cSMatthew Dillon temp_powertx_rate9_reg_val =
2925b7d5e03cSMatthew Dillon AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE;
2926b7d5e03cSMatthew Dillon break;
2927b7d5e03cSMatthew Dillon case HAL_RSSI_TX_POWER_MIDDLE:
2928b7d5e03cSMatthew Dillon /* 1. TxPower Config */
2929b7d5e03cSMatthew Dillon OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle,
2930b7d5e03cSMatthew Dillon sizeof(target_power_val_t));
2931b7d5e03cSMatthew Dillon /* 1.1 Store OLPC Delta Calibration Offset*/
2932b7d5e03cSMatthew Dillon olpc_power_offset = 0;
2933b7d5e03cSMatthew Dillon /* 2. Store OB/DB */
2934b7d5e03cSMatthew Dillon /* 3. Store TPC settting */
2935b7d5e03cSMatthew Dillon temp_tcp_reg_val = (SM(18, AR_TPC_ACK) |
2936b7d5e03cSMatthew Dillon SM(18, AR_TPC_CTS) |
2937b7d5e03cSMatthew Dillon SM(18, AR_TPC_CHIRP) |
2938b7d5e03cSMatthew Dillon SM(18, AR_TPC_RPT));
2939b7d5e03cSMatthew Dillon /* 4. Store BB_powertx_rate9 value */
2940b7d5e03cSMatthew Dillon temp_powertx_rate9_reg_val =
2941b7d5e03cSMatthew Dillon AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE;
2942b7d5e03cSMatthew Dillon break;
2943b7d5e03cSMatthew Dillon case HAL_RSSI_TX_POWER_LONG:
2944b7d5e03cSMatthew Dillon default:
2945b7d5e03cSMatthew Dillon /* 1. TxPower Config */
2946b7d5e03cSMatthew Dillon OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
2947b7d5e03cSMatthew Dillon sizeof(target_power_val_t));
2948b7d5e03cSMatthew Dillon /* 1.1 Store OLPC Delta Calibration Offset*/
2949b7d5e03cSMatthew Dillon olpc_power_offset = 0;
2950b7d5e03cSMatthew Dillon /* 2. Store OB/DB1/DB2 */
2951b7d5e03cSMatthew Dillon /* 3. Store TPC settting */
2952b7d5e03cSMatthew Dillon temp_tcp_reg_val =
2953b7d5e03cSMatthew Dillon AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
2954b7d5e03cSMatthew Dillon /* 4. Store BB_powertx_rate9 value */
2955b7d5e03cSMatthew Dillon temp_powertx_rate9_reg_val =
2956b7d5e03cSMatthew Dillon AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
2957b7d5e03cSMatthew Dillon break;
2958b7d5e03cSMatthew Dillon }
2959b7d5e03cSMatthew Dillon } else {
2960b7d5e03cSMatthew Dillon switch (AH9300(ah)->green_tx_status) {
2961b7d5e03cSMatthew Dillon case HAL_RSSI_TX_POWER_SHORT:
2962b7d5e03cSMatthew Dillon /* 1. TxPower Config */
2963b7d5e03cSMatthew Dillon OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short,
2964b7d5e03cSMatthew Dillon sizeof(target_power_val_t));
2965b7d5e03cSMatthew Dillon /* 1.1 Store OLPC Delta Calibration Offset*/
2966b7d5e03cSMatthew Dillon olpc_power_offset =
2967b7d5e03cSMatthew Dillon wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] -
2968b7d5e03cSMatthew Dillon wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
2969b7d5e03cSMatthew Dillon /* 2. Store OB/DB */
2970b7d5e03cSMatthew Dillon temp_obdb_reg_val =
2971b7d5e03cSMatthew Dillon AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
2972b7d5e03cSMatthew Dillon temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
2973b7d5e03cSMatthew Dillon AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
2974b7d5e03cSMatthew Dillon AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
2975b7d5e03cSMatthew Dillon AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
2976b7d5e03cSMatthew Dillon temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
2977b7d5e03cSMatthew Dillon SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2978b7d5e03cSMatthew Dillon AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
2979b7d5e03cSMatthew Dillon SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2980b7d5e03cSMatthew Dillon AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) |
2981b7d5e03cSMatthew Dillon SM(WB225_OB_GREEN_TX_SHORT_VALUE,
2982b7d5e03cSMatthew Dillon AR_PHY_65NM_CH0_TXRF2_OB2G_QAM));
2983b7d5e03cSMatthew Dillon /* 3. Store TPC settting */
2984b7d5e03cSMatthew Dillon temp_tcp_reg_val = (SM(6, AR_TPC_ACK) |
2985b7d5e03cSMatthew Dillon SM(6, AR_TPC_CTS) |
2986b7d5e03cSMatthew Dillon SM(6, AR_TPC_CHIRP) |
2987b7d5e03cSMatthew Dillon SM(6, AR_TPC_RPT));
2988b7d5e03cSMatthew Dillon /* 4. Store BB_powertx_rate9 value */
2989b7d5e03cSMatthew Dillon temp_powertx_rate9_reg_val =
2990b7d5e03cSMatthew Dillon WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE;
2991b7d5e03cSMatthew Dillon break;
2992b7d5e03cSMatthew Dillon case HAL_RSSI_TX_POWER_MIDDLE:
2993b7d5e03cSMatthew Dillon /* 1. TxPower Config */
2994b7d5e03cSMatthew Dillon OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle,
2995b7d5e03cSMatthew Dillon sizeof(target_power_val_t));
2996b7d5e03cSMatthew Dillon /* 1.1 Store OLPC Delta Calibration Offset*/
2997b7d5e03cSMatthew Dillon olpc_power_offset =
2998b7d5e03cSMatthew Dillon wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] -
2999b7d5e03cSMatthew Dillon wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
3000b7d5e03cSMatthew Dillon /* 2. Store OB/DB */
3001b7d5e03cSMatthew Dillon temp_obdb_reg_val =
3002b7d5e03cSMatthew Dillon AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
3003b7d5e03cSMatthew Dillon temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G |
3004b7d5e03cSMatthew Dillon AR_PHY_65NM_CH0_TXRF2_OB2G_CCK |
3005b7d5e03cSMatthew Dillon AR_PHY_65NM_CH0_TXRF2_OB2G_PSK |
3006b7d5e03cSMatthew Dillon AR_PHY_65NM_CH0_TXRF2_OB2G_QAM);
3007b7d5e03cSMatthew Dillon temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) |
3008b7d5e03cSMatthew Dillon SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
3009b7d5e03cSMatthew Dillon AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) |
3010b7d5e03cSMatthew Dillon SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
3011b7d5e03cSMatthew Dillon AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) |
3012b7d5e03cSMatthew Dillon SM(WB225_OB_GREEN_TX_MIDDLE_VALUE,
3013b7d5e03cSMatthew Dillon AR_PHY_65NM_CH0_TXRF2_OB2G_QAM));
3014b7d5e03cSMatthew Dillon /* 3. Store TPC settting */
3015b7d5e03cSMatthew Dillon temp_tcp_reg_val = (SM(14, AR_TPC_ACK) |
3016b7d5e03cSMatthew Dillon SM(14, AR_TPC_CTS) |
3017b7d5e03cSMatthew Dillon SM(14, AR_TPC_CHIRP) |
3018b7d5e03cSMatthew Dillon SM(14, AR_TPC_RPT));
3019b7d5e03cSMatthew Dillon /* 4. Store BB_powertx_rate9 value */
3020b7d5e03cSMatthew Dillon temp_powertx_rate9_reg_val =
3021b7d5e03cSMatthew Dillon WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE;
3022b7d5e03cSMatthew Dillon break;
3023b7d5e03cSMatthew Dillon case HAL_RSSI_TX_POWER_LONG:
3024b7d5e03cSMatthew Dillon default:
3025b7d5e03cSMatthew Dillon /* 1. TxPower Config */
3026b7d5e03cSMatthew Dillon OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power,
3027b7d5e03cSMatthew Dillon sizeof(target_power_val_t));
3028b7d5e03cSMatthew Dillon /* 1.1 Store OLPC Delta Calibration Offset*/
3029b7d5e03cSMatthew Dillon olpc_power_offset =
3030b7d5e03cSMatthew Dillon wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] -
3031b7d5e03cSMatthew Dillon wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE];
3032b7d5e03cSMatthew Dillon /* 2. Store OB/DB1/DB2 */
3033b7d5e03cSMatthew Dillon temp_obdb_reg_val =
3034b7d5e03cSMatthew Dillon AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB];
3035b7d5e03cSMatthew Dillon /* 3. Store TPC settting */
3036b7d5e03cSMatthew Dillon temp_tcp_reg_val =
3037b7d5e03cSMatthew Dillon AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC];
3038b7d5e03cSMatthew Dillon /* 4. Store BB_powertx_rate9 value */
3039b7d5e03cSMatthew Dillon temp_powertx_rate9_reg_val =
3040b7d5e03cSMatthew Dillon AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9];
3041b7d5e03cSMatthew Dillon break;
3042b7d5e03cSMatthew Dillon }
3043b7d5e03cSMatthew Dillon }
3044b7d5e03cSMatthew Dillon /* 1.1 Do OLPC Delta Calibration Offset */
3045b7d5e03cSMatthew Dillon tmp_olpc_val =
3046b7d5e03cSMatthew Dillon (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET];
3047b7d5e03cSMatthew Dillon tmp_olpc_val += olpc_power_offset;
3048b7d5e03cSMatthew Dillon OS_REG_RMW(ah, AR_PHY_TPC_11_B0,
3049b7d5e03cSMatthew Dillon (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
3050b7d5e03cSMatthew Dillon AR_PHY_TPC_OLPC_GAIN_DELTA);
3051b7d5e03cSMatthew Dillon
3052b7d5e03cSMatthew Dillon /* 1.2 TxPower Config */
3053b7d5e03cSMatthew Dillon ar9300_transmit_power_reg_write(ah, target_power_val_t);
3054b7d5e03cSMatthew Dillon /* 2. Config OB/DB */
3055b7d5e03cSMatthew Dillon if (!ahp->ah_hw_green_tx_enable) {
3056b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val);
3057b7d5e03cSMatthew Dillon }
3058b7d5e03cSMatthew Dillon /* 3. config TPC settting */
3059b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val);
3060b7d5e03cSMatthew Dillon /* 4. config BB_powertx_rate9 value */
3061b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val);
3062b7d5e03cSMatthew Dillon }
3063b7d5e03cSMatthew Dillon }
3064b7d5e03cSMatthew Dillon
3065b7d5e03cSMatthew Dillon #if 0
3066b7d5e03cSMatthew Dillon void
3067b7d5e03cSMatthew Dillon ar9300_get_vow_stats(
3068b7d5e03cSMatthew Dillon struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags)
3069b7d5e03cSMatthew Dillon {
3070b7d5e03cSMatthew Dillon if (vow_reg_flags & AR_REG_TX_FRM_CNT) {
3071b7d5e03cSMatthew Dillon p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT);
3072b7d5e03cSMatthew Dillon }
3073b7d5e03cSMatthew Dillon if (vow_reg_flags & AR_REG_RX_FRM_CNT) {
3074b7d5e03cSMatthew Dillon p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT);
3075b7d5e03cSMatthew Dillon }
3076b7d5e03cSMatthew Dillon if (vow_reg_flags & AR_REG_RX_CLR_CNT) {
3077b7d5e03cSMatthew Dillon p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT);
3078b7d5e03cSMatthew Dillon }
3079b7d5e03cSMatthew Dillon if (vow_reg_flags & AR_REG_CYCLE_CNT) {
3080b7d5e03cSMatthew Dillon p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT);
3081b7d5e03cSMatthew Dillon }
3082b7d5e03cSMatthew Dillon if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) {
3083b7d5e03cSMatthew Dillon p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT);
3084b7d5e03cSMatthew Dillon }
3085b7d5e03cSMatthew Dillon }
3086b7d5e03cSMatthew Dillon #endif
3087b7d5e03cSMatthew Dillon
3088b7d5e03cSMatthew Dillon /*
3089b7d5e03cSMatthew Dillon * ar9300_is_skip_paprd_by_greentx
3090b7d5e03cSMatthew Dillon *
3091b7d5e03cSMatthew Dillon * This function check if we need to skip PAPRD tuning
3092b7d5e03cSMatthew Dillon * when GreenTx in specific state.
3093b7d5e03cSMatthew Dillon */
3094b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_is_skip_paprd_by_greentx(struct ath_hal * ah)3095b7d5e03cSMatthew Dillon ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah)
3096b7d5e03cSMatthew Dillon {
3097b7d5e03cSMatthew Dillon if (AR_SREV_POSEIDON(ah) &&
3098b7d5e03cSMatthew Dillon ah->ah_config.ath_hal_sta_update_tx_pwr_enable &&
3099b7d5e03cSMatthew Dillon ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) ||
3100b7d5e03cSMatthew Dillon (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE)))
3101b7d5e03cSMatthew Dillon {
3102b7d5e03cSMatthew Dillon return AH_TRUE;
3103b7d5e03cSMatthew Dillon }
3104b7d5e03cSMatthew Dillon return AH_FALSE;
3105b7d5e03cSMatthew Dillon }
3106b7d5e03cSMatthew Dillon
3107b7d5e03cSMatthew Dillon void
ar9300_control_signals_for_green_tx_mode(struct ath_hal * ah)3108b7d5e03cSMatthew Dillon ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah)
3109b7d5e03cSMatthew Dillon {
3110b7d5e03cSMatthew Dillon unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3]
3111b7d5e03cSMatthew Dillon unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3]
3112b7d5e03cSMatthew Dillon unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3]
3113b7d5e03cSMatthew Dillon unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3]
3114b7d5e03cSMatthew Dillon unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3]
3115b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
3116b7d5e03cSMatthew Dillon
3117b7d5e03cSMatthew Dillon if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) {
3118b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3119b7d5e03cSMatthew Dillon AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0);
3120b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3121b7d5e03cSMatthew Dillon AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0);
3122b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3123b7d5e03cSMatthew Dillon AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0);
3124b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3125b7d5e03cSMatthew Dillon AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0);
3126b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON,
3127b7d5e03cSMatthew Dillon AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0);
3128b7d5e03cSMatthew Dillon }
3129b7d5e03cSMatthew Dillon }
3130b7d5e03cSMatthew Dillon
ar9300_hwgreentx_set_pal_spare(struct ath_hal * ah,int value)3131b7d5e03cSMatthew Dillon void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value)
3132b7d5e03cSMatthew Dillon {
3133b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
3134b7d5e03cSMatthew Dillon
3135b7d5e03cSMatthew Dillon if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) {
3136b7d5e03cSMatthew Dillon if ((value == 0) || (value == 1)) {
3137b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3,
3138b7d5e03cSMatthew Dillon AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value);
3139b7d5e03cSMatthew Dillon }
3140b7d5e03cSMatthew Dillon }
3141b7d5e03cSMatthew Dillon }
3142b7d5e03cSMatthew Dillon
ar9300_reset_hw_beacon_proc_crc(struct ath_hal * ah)3143b7d5e03cSMatthew Dillon void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah)
3144b7d5e03cSMatthew Dillon {
3145b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC);
3146b7d5e03cSMatthew Dillon }
3147b7d5e03cSMatthew Dillon
ar9300_get_hw_beacon_rssi(struct ath_hal * ah)3148b7d5e03cSMatthew Dillon int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah)
3149b7d5e03cSMatthew Dillon {
3150b7d5e03cSMatthew Dillon int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL);
3151b7d5e03cSMatthew Dillon
3152b7d5e03cSMatthew Dillon /* RSSI format is 8.4. Ignore lowest four bits */
3153b7d5e03cSMatthew Dillon val = val >> 4;
3154b7d5e03cSMatthew Dillon return val;
3155b7d5e03cSMatthew Dillon }
3156b7d5e03cSMatthew Dillon
ar9300_set_hw_beacon_rssi_threshold(struct ath_hal * ah,u_int32_t rssi_threshold)3157b7d5e03cSMatthew Dillon void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah,
3158b7d5e03cSMatthew Dillon u_int32_t rssi_threshold)
3159b7d5e03cSMatthew Dillon {
3160b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
3161b7d5e03cSMatthew Dillon
3162b7d5e03cSMatthew Dillon OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold);
3163b7d5e03cSMatthew Dillon
3164b7d5e03cSMatthew Dillon /* save value for restoring after chip reset */
3165b7d5e03cSMatthew Dillon ahp->ah_beacon_rssi_threshold = rssi_threshold;
3166b7d5e03cSMatthew Dillon }
3167b7d5e03cSMatthew Dillon
ar9300_reset_hw_beacon_rssi(struct ath_hal * ah)3168b7d5e03cSMatthew Dillon void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah)
3169b7d5e03cSMatthew Dillon {
3170b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST);
3171b7d5e03cSMatthew Dillon }
3172b7d5e03cSMatthew Dillon
ar9300_set_hw_beacon_proc(struct ath_hal * ah,HAL_BOOL on)3173b7d5e03cSMatthew Dillon void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on)
3174b7d5e03cSMatthew Dillon {
3175b7d5e03cSMatthew Dillon if (on) {
3176b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
3177b7d5e03cSMatthew Dillon AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
3178b7d5e03cSMatthew Dillon }
3179b7d5e03cSMatthew Dillon else {
3180b7d5e03cSMatthew Dillon OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
3181b7d5e03cSMatthew Dillon AR_HWBCNPROC1_EXCLUDE_TIM_ELM);
3182b7d5e03cSMatthew Dillon }
3183b7d5e03cSMatthew Dillon }
3184b7d5e03cSMatthew Dillon /*
3185b7d5e03cSMatthew Dillon * Gets the contents of the specified key cache entry.
3186b7d5e03cSMatthew Dillon */
3187b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_print_keycache(struct ath_hal * ah)3188b7d5e03cSMatthew Dillon ar9300_print_keycache(struct ath_hal *ah)
3189b7d5e03cSMatthew Dillon {
3190b7d5e03cSMatthew Dillon
3191b7d5e03cSMatthew Dillon const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
3192b7d5e03cSMatthew Dillon u_int32_t key0, key1, key2, key3, key4;
3193b7d5e03cSMatthew Dillon u_int32_t mac_hi, mac_lo;
3194b7d5e03cSMatthew Dillon u_int16_t entry = 0;
3195b7d5e03cSMatthew Dillon u_int32_t valid = 0;
3196b7d5e03cSMatthew Dillon u_int32_t key_type;
3197b7d5e03cSMatthew Dillon
3198b7d5e03cSMatthew Dillon ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n");
3199b7d5e03cSMatthew Dillon
3200b7d5e03cSMatthew Dillon for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {
3201b7d5e03cSMatthew Dillon key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry));
3202b7d5e03cSMatthew Dillon key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry));
3203b7d5e03cSMatthew Dillon key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry));
3204b7d5e03cSMatthew Dillon key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry));
3205b7d5e03cSMatthew Dillon key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry));
3206b7d5e03cSMatthew Dillon
3207b7d5e03cSMatthew Dillon key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry));
3208b7d5e03cSMatthew Dillon
3209b7d5e03cSMatthew Dillon mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry));
3210b7d5e03cSMatthew Dillon mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry));
3211b7d5e03cSMatthew Dillon
3212b7d5e03cSMatthew Dillon if (mac_hi & AR_KEYTABLE_VALID) {
3213b7d5e03cSMatthew Dillon valid = 1;
3214b7d5e03cSMatthew Dillon } else {
3215b7d5e03cSMatthew Dillon valid = 0;
3216b7d5e03cSMatthew Dillon }
3217b7d5e03cSMatthew Dillon
3218b7d5e03cSMatthew Dillon if ((mac_hi != 0) && (mac_lo != 0)) {
3219b7d5e03cSMatthew Dillon mac_hi &= ~0x8000;
3220b7d5e03cSMatthew Dillon mac_hi <<= 1;
3221b7d5e03cSMatthew Dillon mac_hi |= ((mac_lo & (1 << 31) )) >> 31;
3222b7d5e03cSMatthew Dillon mac_lo <<= 1;
3223b7d5e03cSMatthew Dillon }
3224b7d5e03cSMatthew Dillon
3225b7d5e03cSMatthew Dillon ath_hal_printf(ah,
3226b7d5e03cSMatthew Dillon "%03d "
3227b7d5e03cSMatthew Dillon "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
3228b7d5e03cSMatthew Dillon " %02d %02d "
3229b7d5e03cSMatthew Dillon "%02x:%02x:%02x:%02x:%02x:%02x \n",
3230b7d5e03cSMatthew Dillon entry,
3231b7d5e03cSMatthew Dillon (key0 << 24) >> 24, (key0 << 16) >> 24,
3232b7d5e03cSMatthew Dillon (key0 << 8) >> 24, key0 >> 24,
3233b7d5e03cSMatthew Dillon (key1 << 24) >> 24, (key1 << 16) >> 24,
3234b7d5e03cSMatthew Dillon //(key1 << 8) >> 24, key1 >> 24,
3235b7d5e03cSMatthew Dillon (key2 << 24) >> 24, (key2 << 16) >> 24,
3236b7d5e03cSMatthew Dillon (key2 << 8) >> 24, key2 >> 24,
3237b7d5e03cSMatthew Dillon (key3 << 24) >> 24, (key3 << 16) >> 24,
3238b7d5e03cSMatthew Dillon //(key3 << 8) >> 24, key3 >> 24,
3239b7d5e03cSMatthew Dillon (key4 << 24) >> 24, (key4 << 16) >> 24,
3240b7d5e03cSMatthew Dillon (key4 << 8) >> 24, key4 >> 24,
3241b7d5e03cSMatthew Dillon valid, key_type,
3242b7d5e03cSMatthew Dillon (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24,
3243b7d5e03cSMatthew Dillon (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 );
3244b7d5e03cSMatthew Dillon }
3245b7d5e03cSMatthew Dillon
3246b7d5e03cSMatthew Dillon return AH_TRUE;
3247b7d5e03cSMatthew Dillon }
3248b7d5e03cSMatthew Dillon
3249b7d5e03cSMatthew Dillon /* enable/disable smart antenna mode */
3250b7d5e03cSMatthew Dillon HAL_BOOL
ar9300_set_smart_antenna(struct ath_hal * ah,HAL_BOOL enable)3251b7d5e03cSMatthew Dillon ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable)
3252b7d5e03cSMatthew Dillon {
3253b7d5e03cSMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
3254b7d5e03cSMatthew Dillon
3255b7d5e03cSMatthew Dillon if (enable) {
3256b7d5e03cSMatthew Dillon OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3257b7d5e03cSMatthew Dillon } else {
3258b7d5e03cSMatthew Dillon OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA);
3259b7d5e03cSMatthew Dillon }
3260b7d5e03cSMatthew Dillon
3261b7d5e03cSMatthew Dillon /* if scropion and smart antenna is enabled, write swcom1 with 0x440
3262b7d5e03cSMatthew Dillon * and swcom2 with 0
3263b7d5e03cSMatthew Dillon * FIXME Ideally these registers need to be made read from caldata.
3264b7d5e03cSMatthew Dillon * Until the calibration team gets them, keep them along with board
3265b7d5e03cSMatthew Dillon * configuration.
3266b7d5e03cSMatthew Dillon */
3267b7d5e03cSMatthew Dillon if (enable && AR_SREV_SCORPION(ah) &&
3268b7d5e03cSMatthew Dillon (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) {
3269b7d5e03cSMatthew Dillon
3270b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440);
3271b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0);
3272b7d5e03cSMatthew Dillon }
3273b7d5e03cSMatthew Dillon
3274b7d5e03cSMatthew Dillon ahp->ah_smartantenna_enable = enable;
3275b7d5e03cSMatthew Dillon return 1;
3276b7d5e03cSMatthew Dillon }
3277b7d5e03cSMatthew Dillon
3278b7d5e03cSMatthew Dillon #ifdef ATH_TX99_DIAG
3279b7d5e03cSMatthew Dillon #ifndef ATH_SUPPORT_HTC
3280b7d5e03cSMatthew Dillon void
ar9300_tx99_channel_pwr_update(struct ath_hal * ah,HAL_CHANNEL * c,u_int32_t txpower)3281b7d5e03cSMatthew Dillon ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c,
3282b7d5e03cSMatthew Dillon u_int32_t txpower)
3283b7d5e03cSMatthew Dillon {
3284b7d5e03cSMatthew Dillon #define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s))
3285b7d5e03cSMatthew Dillon static int16_t p_pwr_array[ar9300_rate_size] = { 0 };
3286b7d5e03cSMatthew Dillon int32_t i;
3287b7d5e03cSMatthew Dillon
3288b7d5e03cSMatthew Dillon /* The max power is limited to 63 */
3289b7d5e03cSMatthew Dillon if (txpower <= AR9300_MAX_RATE_POWER) {
3290b7d5e03cSMatthew Dillon for (i = 0; i < ar9300_rate_size; i++) {
3291b7d5e03cSMatthew Dillon p_pwr_array[i] = txpower;
3292b7d5e03cSMatthew Dillon }
3293b7d5e03cSMatthew Dillon } else {
3294b7d5e03cSMatthew Dillon for (i = 0; i < ar9300_rate_size; i++) {
3295b7d5e03cSMatthew Dillon p_pwr_array[i] = AR9300_MAX_RATE_POWER;
3296b7d5e03cSMatthew Dillon }
3297b7d5e03cSMatthew Dillon }
3298b7d5e03cSMatthew Dillon
3299b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa458, 0);
3300b7d5e03cSMatthew Dillon
3301b7d5e03cSMatthew Dillon /* Write the OFDM power per rate set */
3302b7d5e03cSMatthew Dillon /* 6 (LSB), 9, 12, 18 (MSB) */
3303b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa3c0,
3304b7d5e03cSMatthew Dillon PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24)
3305b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16)
3306b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8)
3307b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)
3308b7d5e03cSMatthew Dillon );
3309b7d5e03cSMatthew Dillon /* 24 (LSB), 36, 48, 54 (MSB) */
3310b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa3c4,
3311b7d5e03cSMatthew Dillon PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24)
3312b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16)
3313b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8)
3314b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0)
3315b7d5e03cSMatthew Dillon );
3316b7d5e03cSMatthew Dillon
3317b7d5e03cSMatthew Dillon /* Write the CCK power per rate set */
3318b7d5e03cSMatthew Dillon /* 1L (LSB), reserved, 2L, 2S (MSB) */
3319b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa3c8,
3320b7d5e03cSMatthew Dillon PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24)
3321b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16)
3322b7d5e03cSMatthew Dillon /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */
3323b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)
3324b7d5e03cSMatthew Dillon );
3325b7d5e03cSMatthew Dillon /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3326b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa3cc,
3327b7d5e03cSMatthew Dillon PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24)
3328b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16)
3329b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8)
3330b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0)
3331b7d5e03cSMatthew Dillon );
3332b7d5e03cSMatthew Dillon
3333b7d5e03cSMatthew Dillon /* Write the HT20 power per rate set */
3334b7d5e03cSMatthew Dillon /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3335b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa3d0,
3336b7d5e03cSMatthew Dillon PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24)
3337b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16)
3338b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)
3339b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0)
3340b7d5e03cSMatthew Dillon );
3341b7d5e03cSMatthew Dillon
3342b7d5e03cSMatthew Dillon /* 6 (LSB), 7, 12, 13 (MSB) */
3343b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa3d4,
3344b7d5e03cSMatthew Dillon PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24)
3345b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16)
3346b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8)
3347b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0)
3348b7d5e03cSMatthew Dillon );
3349b7d5e03cSMatthew Dillon
3350b7d5e03cSMatthew Dillon /* 14 (LSB), 15, 20, 21 */
3351b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa3e4,
3352b7d5e03cSMatthew Dillon PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24)
3353b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16)
3354b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8)
3355b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0)
3356b7d5e03cSMatthew Dillon );
3357b7d5e03cSMatthew Dillon
3358b7d5e03cSMatthew Dillon /* Mixed HT20 and HT40 rates */
3359b7d5e03cSMatthew Dillon /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
3360b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa3e8,
3361b7d5e03cSMatthew Dillon PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24)
3362b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16)
3363b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8)
3364b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0)
3365b7d5e03cSMatthew Dillon );
3366b7d5e03cSMatthew Dillon
3367b7d5e03cSMatthew Dillon /* Write the HT40 power per rate set */
3368b7d5e03cSMatthew Dillon /* correct PAR difference between HT40 and HT20/LEGACY */
3369b7d5e03cSMatthew Dillon /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3370b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa3d8,
3371b7d5e03cSMatthew Dillon PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24)
3372b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16)
3373b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8)
3374b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0)
3375b7d5e03cSMatthew Dillon );
3376b7d5e03cSMatthew Dillon
3377b7d5e03cSMatthew Dillon /* 6 (LSB), 7, 12, 13 (MSB) */
3378b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa3dc,
3379b7d5e03cSMatthew Dillon PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24)
3380b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16)
3381b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8)
3382b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0)
3383b7d5e03cSMatthew Dillon );
3384b7d5e03cSMatthew Dillon
3385b7d5e03cSMatthew Dillon /* 14 (LSB), 15, 20, 21 */
3386b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa3ec,
3387b7d5e03cSMatthew Dillon PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24)
3388b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16)
3389b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8)
3390b7d5e03cSMatthew Dillon | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0)
3391b7d5e03cSMatthew Dillon );
3392b7d5e03cSMatthew Dillon #undef PWR_MAS
3393b7d5e03cSMatthew Dillon }
3394b7d5e03cSMatthew Dillon
3395b7d5e03cSMatthew Dillon void
ar9300_tx99_chainmsk_setup(struct ath_hal * ah,int tx_chainmask)3396b7d5e03cSMatthew Dillon ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask)
3397b7d5e03cSMatthew Dillon {
3398b7d5e03cSMatthew Dillon if (tx_chainmask == 0x5) {
3399b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3400b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
3401b7d5e03cSMatthew Dillon }
3402b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask);
3403b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask);
3404b7d5e03cSMatthew Dillon
3405b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
3406b7d5e03cSMatthew Dillon if (tx_chainmask == 0x5) {
3407b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
3408b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN);
3409b7d5e03cSMatthew Dillon }
3410b7d5e03cSMatthew Dillon }
3411b7d5e03cSMatthew Dillon
3412b7d5e03cSMatthew Dillon void
ar9300_tx99_set_single_carrier(struct ath_hal * ah,int tx_chain_mask,int chtype)3413b7d5e03cSMatthew Dillon ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask,
3414b7d5e03cSMatthew Dillon int chtype)
3415b7d5e03cSMatthew Dillon {
3416b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff);
3417b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1));
3418b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa350,
3419b7d5e03cSMatthew Dillon (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13));
3420b7d5e03cSMatthew Dillon
3421b7d5e03cSMatthew Dillon /* 11G mode */
3422b7d5e03cSMatthew Dillon if (!chtype) {
3423b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3424b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2));
3425b7d5e03cSMatthew Dillon if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3426b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3427b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3428b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3429b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3430b7d5e03cSMatthew Dillon | (0x1 << 26) | (0x7 << 24))
3431b7d5e03cSMatthew Dillon & ~(0x1 << 22));
3432b7d5e03cSMatthew Dillon } else {
3433b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3434b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3435b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3436b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3437b7d5e03cSMatthew Dillon | (0x1 << 26) | (0x7 << 24))
3438b7d5e03cSMatthew Dillon & ~(0x1 << 22));
3439b7d5e03cSMatthew Dillon }
3440b7d5e03cSMatthew Dillon
3441b7d5e03cSMatthew Dillon /* chain zero */
3442b7d5e03cSMatthew Dillon if ((tx_chain_mask & 0x01) == 0x01) {
3443b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1,
3444b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
3445b7d5e03cSMatthew Dillon | (0x1 << 31) | (0x5 << 15)
3446b7d5e03cSMatthew Dillon | (0x3 << 9)) & ~(0x1 << 27)
3447b7d5e03cSMatthew Dillon & ~(0x1 << 12));
3448b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3449b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3450b7d5e03cSMatthew Dillon | (0x1 << 12) | (0x1 << 10)
3451b7d5e03cSMatthew Dillon | (0x1 << 9) | (0x1 << 8)
3452b7d5e03cSMatthew Dillon | (0x1 << 7)) & ~(0x1 << 11));
3453b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3454b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3455b7d5e03cSMatthew Dillon | (0x1 << 29) | (0x1 << 25)
3456b7d5e03cSMatthew Dillon | (0x1 << 23) | (0x1 << 19)
3457b7d5e03cSMatthew Dillon | (0x1 << 10) | (0x1 << 9)
3458b7d5e03cSMatthew Dillon | (0x1 << 8) | (0x1 << 3))
3459b7d5e03cSMatthew Dillon & ~(0x1 << 28)& ~(0x1 << 24)
3460b7d5e03cSMatthew Dillon & ~(0x1 << 22)& ~(0x1 << 7));
3461b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3462b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
3463b7d5e03cSMatthew Dillon | (0x1 << 23))& ~(0x1 << 21));
3464b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1,
3465b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
3466b7d5e03cSMatthew Dillon | (0x1 << 12) | (0x1 << 10)
3467b7d5e03cSMatthew Dillon | (0x1 << 9) | (0x1 << 8)
3468b7d5e03cSMatthew Dillon | (0x1 << 6) | (0x1 << 5)
3469b7d5e03cSMatthew Dillon | (0x1 << 4) | (0x1 << 3)
3470b7d5e03cSMatthew Dillon | (0x1 << 2));
3471b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2,
3472b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31));
3473b7d5e03cSMatthew Dillon }
3474b7d5e03cSMatthew Dillon if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3475b7d5e03cSMatthew Dillon /* chain one */
3476b7d5e03cSMatthew Dillon if ((tx_chain_mask & 0x02) == 0x02 ) {
3477b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1,
3478b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
3479b7d5e03cSMatthew Dillon | (0x1 << 31) | (0x5 << 15)
3480b7d5e03cSMatthew Dillon | (0x3 << 9)) & ~(0x1 << 27)
3481b7d5e03cSMatthew Dillon & ~(0x1 << 12));
3482b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3483b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3484b7d5e03cSMatthew Dillon | (0x1 << 12) | (0x1 << 10)
3485b7d5e03cSMatthew Dillon | (0x1 << 9) | (0x1 << 8)
3486b7d5e03cSMatthew Dillon | (0x1 << 7)) & ~(0x1 << 11));
3487b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3488b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3489b7d5e03cSMatthew Dillon | (0x1 << 29) | (0x1 << 25)
3490b7d5e03cSMatthew Dillon | (0x1 << 23) | (0x1 << 19)
3491b7d5e03cSMatthew Dillon | (0x1 << 10) | (0x1 << 9)
3492b7d5e03cSMatthew Dillon | (0x1 << 8) | (0x1 << 3))
3493b7d5e03cSMatthew Dillon & ~(0x1 << 28)& ~(0x1 << 24)
3494b7d5e03cSMatthew Dillon & ~(0x1 << 22)& ~(0x1 << 7));
3495b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3496b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
3497b7d5e03cSMatthew Dillon | (0x1 << 23))& ~(0x1 << 21));
3498b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1,
3499b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
3500b7d5e03cSMatthew Dillon | (0x1 << 12) | (0x1 << 10)
3501b7d5e03cSMatthew Dillon | (0x1 << 9) | (0x1 << 8)
3502b7d5e03cSMatthew Dillon | (0x1 << 6) | (0x1 << 5)
3503b7d5e03cSMatthew Dillon | (0x1 << 4) | (0x1 << 3)
3504b7d5e03cSMatthew Dillon | (0x1 << 2));
3505b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2,
3506b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31));
3507b7d5e03cSMatthew Dillon }
3508b7d5e03cSMatthew Dillon }
3509b7d5e03cSMatthew Dillon if (AR_SREV_OSPREY(ah)) {
3510b7d5e03cSMatthew Dillon /* chain two */
3511b7d5e03cSMatthew Dillon if ((tx_chain_mask & 0x04) == 0x04 ) {
3512b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1,
3513b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
3514b7d5e03cSMatthew Dillon | (0x1 << 31) | (0x5 << 15)
3515b7d5e03cSMatthew Dillon | (0x3 << 9)) & ~(0x1 << 27)
3516b7d5e03cSMatthew Dillon & ~(0x1 << 12));
3517b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3518b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3519b7d5e03cSMatthew Dillon | (0x1 << 12) | (0x1 << 10)
3520b7d5e03cSMatthew Dillon | (0x1 << 9) | (0x1 << 8)
3521b7d5e03cSMatthew Dillon | (0x1 << 7)) & ~(0x1 << 11));
3522b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3523b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3524b7d5e03cSMatthew Dillon | (0x1 << 29) | (0x1 << 25)
3525b7d5e03cSMatthew Dillon | (0x1 << 23) | (0x1 << 19)
3526b7d5e03cSMatthew Dillon | (0x1 << 10) | (0x1 << 9)
3527b7d5e03cSMatthew Dillon | (0x1 << 8) | (0x1 << 3))
3528b7d5e03cSMatthew Dillon & ~(0x1 << 28)& ~(0x1 << 24)
3529b7d5e03cSMatthew Dillon & ~(0x1 << 22)& ~(0x1 << 7));
3530b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3531b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
3532b7d5e03cSMatthew Dillon | (0x1 << 23))& ~(0x1 << 21));
3533b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1,
3534b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
3535b7d5e03cSMatthew Dillon | (0x1 << 12) | (0x1 << 10)
3536b7d5e03cSMatthew Dillon | (0x1 << 9) | (0x1 << 8)
3537b7d5e03cSMatthew Dillon | (0x1 << 6) | (0x1 << 5)
3538b7d5e03cSMatthew Dillon | (0x1 << 4) | (0x1 << 3)
3539b7d5e03cSMatthew Dillon | (0x1 << 2));
3540b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2,
3541b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31));
3542b7d5e03cSMatthew Dillon }
3543b7d5e03cSMatthew Dillon }
3544b7d5e03cSMatthew Dillon
3545b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa28c, 0x11111);
3546b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa288, 0x111);
3547b7d5e03cSMatthew Dillon } else {
3548b7d5e03cSMatthew Dillon /* chain zero */
3549b7d5e03cSMatthew Dillon if ((tx_chain_mask & 0x01) == 0x01) {
3550b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1,
3551b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1)
3552b7d5e03cSMatthew Dillon | (0x1 << 31) | (0x1 << 27)
3553b7d5e03cSMatthew Dillon | (0x3 << 23) | (0x1 << 19)
3554b7d5e03cSMatthew Dillon | (0x1 << 15) | (0x3 << 9))
3555b7d5e03cSMatthew Dillon & ~(0x1 << 12));
3556b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3557b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3558b7d5e03cSMatthew Dillon | (0x1 << 12) | (0x1 << 10)
3559b7d5e03cSMatthew Dillon | (0x1 << 9) | (0x1 << 8)
3560b7d5e03cSMatthew Dillon | (0x1 << 7) | (0x1 << 3)
3561b7d5e03cSMatthew Dillon | (0x1 << 2) | (0x1 << 1))
3562b7d5e03cSMatthew Dillon & ~(0x1 << 11)& ~(0x1 << 0));
3563b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3564b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3565b7d5e03cSMatthew Dillon | (0x1 << 29) | (0x1 << 25)
3566b7d5e03cSMatthew Dillon | (0x1 << 23) | (0x1 << 19)
3567b7d5e03cSMatthew Dillon | (0x1 << 10) | (0x1 << 9)
3568b7d5e03cSMatthew Dillon | (0x1 << 8) | (0x1 << 3))
3569b7d5e03cSMatthew Dillon & ~(0x1 << 28)& ~(0x1 << 24)
3570b7d5e03cSMatthew Dillon & ~(0x1 << 22)& ~(0x1 << 7));
3571b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3572b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1)
3573b7d5e03cSMatthew Dillon | (0x1 << 23))& ~(0x1 << 21));
3574b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2,
3575b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2)
3576b7d5e03cSMatthew Dillon | (0x3 << 3) | (0x3 << 0));
3577b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3,
3578b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3)
3579b7d5e03cSMatthew Dillon | (0x3 << 29) | (0x3 << 26)
3580b7d5e03cSMatthew Dillon | (0x2 << 23) | (0x2 << 20)
3581b7d5e03cSMatthew Dillon | (0x2 << 17))& ~(0x1 << 14));
3582b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1,
3583b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1)
3584b7d5e03cSMatthew Dillon | (0x1 << 12) | (0x1 << 10)
3585b7d5e03cSMatthew Dillon | (0x1 << 9) | (0x1 << 8)
3586b7d5e03cSMatthew Dillon | (0x1 << 6) | (0x1 << 5)
3587b7d5e03cSMatthew Dillon | (0x1 << 4) | (0x1 << 3)
3588b7d5e03cSMatthew Dillon | (0x1 << 2));
3589b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2,
3590b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31));
3591b7d5e03cSMatthew Dillon if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3592b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3593b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3594b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3595b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3596b7d5e03cSMatthew Dillon | (0x1 << 26) | (0x7 << 24)
3597b7d5e03cSMatthew Dillon | (0x3 << 22));
3598b7d5e03cSMatthew Dillon } else {
3599b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3600b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3601b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3602b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3603b7d5e03cSMatthew Dillon | (0x1 << 26) | (0x7 << 24)
3604b7d5e03cSMatthew Dillon | (0x3 << 22));
3605b7d5e03cSMatthew Dillon }
3606b7d5e03cSMatthew Dillon
3607b7d5e03cSMatthew Dillon if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3608b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3609b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3610b7d5e03cSMatthew Dillon | (0x1 << 3) | (0x1 << 2)
3611b7d5e03cSMatthew Dillon | (0x1 << 1)) & ~(0x1 << 0));
3612b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3613b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3614b7d5e03cSMatthew Dillon | (0x1 << 19) | (0x1 << 3));
3615b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3616b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23));
3617b7d5e03cSMatthew Dillon }
3618b7d5e03cSMatthew Dillon if (AR_SREV_OSPREY(ah)) {
3619b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3620b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3621b7d5e03cSMatthew Dillon | (0x1 << 3) | (0x1 << 2)
3622b7d5e03cSMatthew Dillon | (0x1 << 1)) & ~(0x1 << 0));
3623b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3624b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3625b7d5e03cSMatthew Dillon | (0x1 << 19) | (0x1 << 3));
3626b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3627b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23));
3628b7d5e03cSMatthew Dillon }
3629b7d5e03cSMatthew Dillon }
3630b7d5e03cSMatthew Dillon if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3631b7d5e03cSMatthew Dillon /* chain one */
3632b7d5e03cSMatthew Dillon if ((tx_chain_mask & 0x02) == 0x02 ) {
3633b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3634b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3635b7d5e03cSMatthew Dillon | (0x1 << 3) | (0x1 << 2)
3636b7d5e03cSMatthew Dillon | (0x1 << 1)) & ~(0x1 << 0));
3637b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3638b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3639b7d5e03cSMatthew Dillon | (0x1 << 19) | (0x1 << 3));
3640b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3641b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23));
3642b7d5e03cSMatthew Dillon if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3643b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3644b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3645b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3646b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3647b7d5e03cSMatthew Dillon | (0x1 << 26) | (0x7 << 24)
3648b7d5e03cSMatthew Dillon | (0x3 << 22));
3649b7d5e03cSMatthew Dillon } else {
3650b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3651b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3652b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3653b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3654b7d5e03cSMatthew Dillon | (0x1 << 26) | (0x7 << 24)
3655b7d5e03cSMatthew Dillon | (0x3 << 22));
3656b7d5e03cSMatthew Dillon }
3657b7d5e03cSMatthew Dillon
3658b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1,
3659b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1)
3660b7d5e03cSMatthew Dillon | (0x1 << 31) | (0x1 << 27)
3661b7d5e03cSMatthew Dillon | (0x3 << 23) | (0x1 << 19)
3662b7d5e03cSMatthew Dillon | (0x1 << 15) | (0x3 << 9))
3663b7d5e03cSMatthew Dillon & ~(0x1 << 12));
3664b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3665b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3666b7d5e03cSMatthew Dillon | (0x1 << 12) | (0x1 << 10)
3667b7d5e03cSMatthew Dillon | (0x1 << 9) | (0x1 << 8)
3668b7d5e03cSMatthew Dillon | (0x1 << 7) | (0x1 << 3)
3669b7d5e03cSMatthew Dillon | (0x1 << 2) | (0x1 << 1))
3670b7d5e03cSMatthew Dillon & ~(0x1 << 11)& ~(0x1 << 0));
3671b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3672b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3673b7d5e03cSMatthew Dillon | (0x1 << 29) | (0x1 << 25)
3674b7d5e03cSMatthew Dillon | (0x1 << 23) | (0x1 << 19)
3675b7d5e03cSMatthew Dillon | (0x1 << 10) | (0x1 << 9)
3676b7d5e03cSMatthew Dillon | (0x1 << 8) | (0x1 << 3))
3677b7d5e03cSMatthew Dillon & ~(0x1 << 28)& ~(0x1 << 24)
3678b7d5e03cSMatthew Dillon & ~(0x1 << 22)& ~(0x1 << 7));
3679b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3680b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1)
3681b7d5e03cSMatthew Dillon | (0x1 << 23))& ~(0x1 << 21));
3682b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2,
3683b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2)
3684b7d5e03cSMatthew Dillon | (0x3 << 3) | (0x3 << 0));
3685b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3,
3686b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3)
3687b7d5e03cSMatthew Dillon | (0x3 << 29) | (0x3 << 26)
3688b7d5e03cSMatthew Dillon | (0x2 << 23) | (0x2 << 20)
3689b7d5e03cSMatthew Dillon | (0x2 << 17))& ~(0x1 << 14));
3690b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1,
3691b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1)
3692b7d5e03cSMatthew Dillon | (0x1 << 12) | (0x1 << 10)
3693b7d5e03cSMatthew Dillon | (0x1 << 9) | (0x1 << 8)
3694b7d5e03cSMatthew Dillon | (0x1 << 6) | (0x1 << 5)
3695b7d5e03cSMatthew Dillon | (0x1 << 4) | (0x1 << 3)
3696b7d5e03cSMatthew Dillon | (0x1 << 2));
3697b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2,
3698b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31));
3699b7d5e03cSMatthew Dillon
3700b7d5e03cSMatthew Dillon if (AR_SREV_OSPREY(ah)) {
3701b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3702b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3703b7d5e03cSMatthew Dillon | (0x1 << 3) | (0x1 << 2)
3704b7d5e03cSMatthew Dillon | (0x1 << 1)) & ~(0x1 << 0));
3705b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3706b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3707b7d5e03cSMatthew Dillon | (0x1 << 19) | (0x1 << 3));
3708b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3709b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23));
3710b7d5e03cSMatthew Dillon }
3711b7d5e03cSMatthew Dillon }
3712b7d5e03cSMatthew Dillon }
3713b7d5e03cSMatthew Dillon if (AR_SREV_OSPREY(ah)) {
3714b7d5e03cSMatthew Dillon /* chain two */
3715b7d5e03cSMatthew Dillon if ((tx_chain_mask & 0x04) == 0x04 ) {
3716b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2,
3717b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2)
3718b7d5e03cSMatthew Dillon | (0x1 << 3) | (0x1 << 2)
3719b7d5e03cSMatthew Dillon | (0x1 << 1)) & ~(0x1 << 0));
3720b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3,
3721b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3)
3722b7d5e03cSMatthew Dillon | (0x1 << 19) | (0x1 << 3));
3723b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1,
3724b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23));
3725b7d5e03cSMatthew Dillon if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) {
3726b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP,
3727b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4));
3728b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2,
3729b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2)
3730b7d5e03cSMatthew Dillon | (0x1 << 26) | (0x7 << 24)
3731b7d5e03cSMatthew Dillon | (0x3 << 22));
3732b7d5e03cSMatthew Dillon } else {
3733b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_HORNET_CH0_TOP,
3734b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4));
3735b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2,
3736b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_HORNET_CH0_TOP2)
3737b7d5e03cSMatthew Dillon | (0x1 << 26) | (0x7 << 24)
3738b7d5e03cSMatthew Dillon | (0x3 << 22));
3739b7d5e03cSMatthew Dillon }
3740b7d5e03cSMatthew Dillon
3741b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2,
3742b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2)
3743b7d5e03cSMatthew Dillon | (0x1 << 3) | (0x1 << 2)
3744b7d5e03cSMatthew Dillon | (0x1 << 1)) & ~(0x1 << 0));
3745b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3,
3746b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3)
3747b7d5e03cSMatthew Dillon | (0x1 << 19) | (0x1 << 3));
3748b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1,
3749b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23));
3750b7d5e03cSMatthew Dillon
3751b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1,
3752b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1)
3753b7d5e03cSMatthew Dillon | (0x1 << 31) | (0x1 << 27)
3754b7d5e03cSMatthew Dillon | (0x3 << 23) | (0x1 << 19)
3755b7d5e03cSMatthew Dillon | (0x1 << 15) | (0x3 << 9))
3756b7d5e03cSMatthew Dillon & ~(0x1 << 12));
3757b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2,
3758b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2)
3759b7d5e03cSMatthew Dillon | (0x1 << 12) | (0x1 << 10)
3760b7d5e03cSMatthew Dillon | (0x1 << 9) | (0x1 << 8)
3761b7d5e03cSMatthew Dillon | (0x1 << 7) | (0x1 << 3)
3762b7d5e03cSMatthew Dillon | (0x1 << 2) | (0x1 << 1))
3763b7d5e03cSMatthew Dillon & ~(0x1 << 11)& ~(0x1 << 0));
3764b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3,
3765b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3)
3766b7d5e03cSMatthew Dillon | (0x1 << 29) | (0x1 << 25)
3767b7d5e03cSMatthew Dillon | (0x1 << 23) | (0x1 << 19)
3768b7d5e03cSMatthew Dillon | (0x1 << 10) | (0x1 << 9)
3769b7d5e03cSMatthew Dillon | (0x1 << 8) | (0x1 << 3))
3770b7d5e03cSMatthew Dillon & ~(0x1 << 28)& ~(0x1 << 24)
3771b7d5e03cSMatthew Dillon & ~(0x1 << 22)& ~(0x1 << 7));
3772b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1,
3773b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1)
3774b7d5e03cSMatthew Dillon | (0x1 << 23))& ~(0x1 << 21));
3775b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2,
3776b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2)
3777b7d5e03cSMatthew Dillon | (0x3 << 3) | (0x3 << 0));
3778b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3,
3779b7d5e03cSMatthew Dillon (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3)
3780b7d5e03cSMatthew Dillon | (0x3 << 29) | (0x3 << 26)
3781b7d5e03cSMatthew Dillon | (0x2 << 23) | (0x2 << 20)
3782b7d5e03cSMatthew Dillon | (0x2 << 17))& ~(0x1 << 14));
3783b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1,
3784b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1)
3785b7d5e03cSMatthew Dillon | (0x1 << 12) | (0x1 << 10)
3786b7d5e03cSMatthew Dillon | (0x1 << 9) | (0x1 << 8)
3787b7d5e03cSMatthew Dillon | (0x1 << 6) | (0x1 << 5)
3788b7d5e03cSMatthew Dillon | (0x1 << 4) | (0x1 << 3)
3789b7d5e03cSMatthew Dillon | (0x1 << 2));
3790b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2,
3791b7d5e03cSMatthew Dillon OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31));
3792b7d5e03cSMatthew Dillon }
3793b7d5e03cSMatthew Dillon }
3794b7d5e03cSMatthew Dillon
3795b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa28c, 0x22222);
3796b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, 0xa288, 0x222);
3797b7d5e03cSMatthew Dillon }
3798b7d5e03cSMatthew Dillon }
3799b7d5e03cSMatthew Dillon
3800b7d5e03cSMatthew Dillon void
ar9300_tx99_start(struct ath_hal * ah,u_int8_t * data)3801b7d5e03cSMatthew Dillon ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data)
3802b7d5e03cSMatthew Dillon {
3803b7d5e03cSMatthew Dillon u_int32_t val;
3804b7d5e03cSMatthew Dillon u_int32_t qnum = (u_int32_t)data;
3805b7d5e03cSMatthew Dillon
3806b7d5e03cSMatthew Dillon /* Disable AGC to A2 */
3807b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR));
3808b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
3809b7d5e03cSMatthew Dillon
3810b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */
3811b7d5e03cSMatthew Dillon /* set CW_MIN and CW_MAX both to 0, AIFS=2 */
3812b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
3813b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
3814b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
3815b7d5e03cSMatthew Dillon /* 200 ok for HT20, 400 ok for HT40 */
3816b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
3817b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
3818b7d5e03cSMatthew Dillon
3819b7d5e03cSMatthew Dillon /* set QCU modes to early termination */
3820b7d5e03cSMatthew Dillon val = OS_REG_READ(ah, AR_QMISC(qnum));
3821b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ);
3822b7d5e03cSMatthew Dillon }
3823b7d5e03cSMatthew Dillon
3824b7d5e03cSMatthew Dillon void
ar9300_tx99_stop(struct ath_hal * ah)3825b7d5e03cSMatthew Dillon ar9300_tx99_stop(struct ath_hal *ah)
3826b7d5e03cSMatthew Dillon {
3827b7d5e03cSMatthew Dillon /* this should follow the setting of start */
3828b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR);
3829b7d5e03cSMatthew Dillon OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS);
3830b7d5e03cSMatthew Dillon }
3831b7d5e03cSMatthew Dillon #endif /* ATH_TX99_DIAG */
3832b7d5e03cSMatthew Dillon #endif /* ATH_SUPPORT_HTC */
3833b7d5e03cSMatthew Dillon
3834b7d5e03cSMatthew Dillon HAL_BOOL
ar9300Get3StreamSignature(struct ath_hal * ah)3835b7d5e03cSMatthew Dillon ar9300Get3StreamSignature(struct ath_hal *ah)
3836b7d5e03cSMatthew Dillon {
3837b7d5e03cSMatthew Dillon return AH_FALSE;
3838b7d5e03cSMatthew Dillon }
3839b7d5e03cSMatthew Dillon
3840b7d5e03cSMatthew Dillon HAL_BOOL
ar9300ForceVCS(struct ath_hal * ah)3841b7d5e03cSMatthew Dillon ar9300ForceVCS(struct ath_hal *ah)
3842b7d5e03cSMatthew Dillon {
3843b7d5e03cSMatthew Dillon return AH_FALSE;
3844b7d5e03cSMatthew Dillon }
3845b7d5e03cSMatthew Dillon
3846b7d5e03cSMatthew Dillon HAL_BOOL
ar9300SetDfs3StreamFix(struct ath_hal * ah,u_int32_t val)3847b7d5e03cSMatthew Dillon ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val)
3848b7d5e03cSMatthew Dillon {
3849b7d5e03cSMatthew Dillon return AH_FALSE;
3850b7d5e03cSMatthew Dillon }
3851a20e5e51SMatthew Dillon
3852a20e5e51SMatthew Dillon HAL_BOOL
ar9300_set_ctl_pwr(struct ath_hal * ah,u_int8_t * ctl_array)3853a20e5e51SMatthew Dillon ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array)
3854a20e5e51SMatthew Dillon {
3855a20e5e51SMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
3856a20e5e51SMatthew Dillon ar9300_eeprom_t *p_eep_data = &ahp->ah_eeprom;
3857a20e5e51SMatthew Dillon u_int8_t *ctl_index;
3858a20e5e51SMatthew Dillon u_int32_t offset = 0;
3859a20e5e51SMatthew Dillon
3860a20e5e51SMatthew Dillon if (!ctl_array)
3861a20e5e51SMatthew Dillon return AH_FALSE;
3862a20e5e51SMatthew Dillon
3863a20e5e51SMatthew Dillon /* copy 2G ctl freqbin and power data */
3864a20e5e51SMatthew Dillon ctl_index = p_eep_data->ctl_index_2g;
3865a20e5e51SMatthew Dillon OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_2G, ctl_array,
3866a20e5e51SMatthew Dillon OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G + /* ctl_freqbin_2G */
3867a20e5e51SMatthew Dillon OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); /* ctl_power_data_2g */
3868a20e5e51SMatthew Dillon offset = (OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G) +
3869a20e5e51SMatthew Dillon ( OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G));
3870a20e5e51SMatthew Dillon
3871a20e5e51SMatthew Dillon
3872a20e5e51SMatthew Dillon /* copy 2G ctl freqbin and power data */
3873a20e5e51SMatthew Dillon ctl_index = p_eep_data->ctl_index_5g;
3874a20e5e51SMatthew Dillon OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_5G, ctl_array + offset,
3875a20e5e51SMatthew Dillon OSPREY_NUM_CTLS_5G * OSPREY_NUM_BAND_EDGES_5G + /* ctl_freqbin_5G */
3876a20e5e51SMatthew Dillon OSPREY_NUM_CTLS_5G * sizeof(OSP_CAL_CTL_DATA_5G)); /* ctl_power_data_5g */
3877a20e5e51SMatthew Dillon
3878a20e5e51SMatthew Dillon return AH_FALSE;
3879a20e5e51SMatthew Dillon }
3880a20e5e51SMatthew Dillon
3881a20e5e51SMatthew Dillon void
ar9300_set_txchainmaskopt(struct ath_hal * ah,u_int8_t mask)3882a20e5e51SMatthew Dillon ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask)
3883a20e5e51SMatthew Dillon {
3884a20e5e51SMatthew Dillon struct ath_hal_9300 *ahp = AH9300(ah);
3885a20e5e51SMatthew Dillon
3886a20e5e51SMatthew Dillon /* optional txchainmask should be subset of primary txchainmask */
3887a20e5e51SMatthew Dillon if ((mask & ahp->ah_tx_chainmask) != mask) {
3888a20e5e51SMatthew Dillon ahp->ah_tx_chainmaskopt = 0;
3889a20e5e51SMatthew Dillon ath_hal_printf(ah, "Error: ah_tx_chainmask=%d, mask=%d\n", ahp->ah_tx_chainmask, mask);
3890a20e5e51SMatthew Dillon return;
3891a20e5e51SMatthew Dillon }
3892a20e5e51SMatthew Dillon
3893a20e5e51SMatthew Dillon ahp->ah_tx_chainmaskopt = mask;
3894a20e5e51SMatthew Dillon }
3895