1 /* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _ATH_AR9300_EEP_H_ 18 #define _ATH_AR9300_EEP_H_ 19 20 #include "opt_ah.h" 21 22 #include "ah.h" 23 24 #if defined(WIN32) || defined(WIN64) 25 #pragma pack (push, ar9300, 1) 26 #endif 27 28 /* FreeBSD extras - should be in ah_eeprom.h ? */ 29 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 30 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 31 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 32 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 33 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 34 #define AR_EEPROM_EEPCAP_MAXQCU_S 4 35 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 36 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 37 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 38 39 40 #define MSTATE 100 41 #define MOUTPUT 2048 42 #define MDEFAULT 15 43 #define MVALUE 100 44 45 enum CompressAlgorithm 46 { 47 _compress_none = 0, 48 _compress_lzma, 49 _compress_pairs, 50 _compress_block, 51 _compress4, 52 _compress5, 53 _compress6, 54 _compress7, 55 }; 56 57 58 enum 59 { 60 calibration_data_none = 0, 61 calibration_data_dram, 62 calibration_data_flash, 63 calibration_data_eeprom, 64 calibration_data_otp, 65 #ifdef ATH_CAL_NAND_FLASH 66 calibration_data_nand, 67 #endif 68 CalibrationDataDontLoad, 69 }; 70 #define HOST_CALDATA_SIZE (16*1024) 71 72 // 73 // DO NOT CHANGE THE DEFINTIONS OF THESE SYMBOLS. 74 // Add additional definitions to the end. 75 // Yes, the first one is 2. Do not use 0 or 1. 76 // 77 enum Ar9300EepromTemplate 78 { 79 ar9300_eeprom_template_generic = 2, 80 ar9300_eeprom_template_hb112 = 3, 81 ar9300_eeprom_template_hb116 = 4, 82 ar9300_eeprom_template_xb112 = 5, 83 ar9300_eeprom_template_xb113 = 6, 84 ar9300_eeprom_template_xb114 = 7, 85 ar9300_eeprom_template_tb417 = 8, 86 ar9300_eeprom_template_ap111 = 9, 87 ar9300_eeprom_template_ap121 = 10, 88 ar9300_eeprom_template_hornet_generic = 11, 89 ar9300_eeprom_template_wasp_2 = 12, 90 ar9300_eeprom_template_wasp_k31 = 13, 91 ar9300_eeprom_template_osprey_k31 = 14, 92 ar9300_eeprom_template_aphrodite = 15 93 }; 94 95 #define ar9300_eeprom_template_default ar9300_eeprom_template_generic 96 #define Ar9300EepromFormatDefault 2 97 98 #define reference_current 0 99 #define compression_header_length 4 100 #define compression_checksum_length 2 101 102 #define OSPREY_EEP_VER 0xD000 103 #define OSPREY_EEP_VER_MINOR_MASK 0xFFF 104 #define OSPREY_EEP_MINOR_VER_1 0x1 105 #define OSPREY_EEP_MINOR_VER OSPREY_EEP_MINOR_VER_1 106 107 // 16-bit offset location start of calibration struct 108 #define OSPREY_EEP_START_LOC 256 109 #define OSPREY_NUM_5G_CAL_PIERS 8 110 #define OSPREY_NUM_2G_CAL_PIERS 3 111 #define OSPREY_NUM_5G_20_TARGET_POWERS 8 112 #define OSPREY_NUM_5G_40_TARGET_POWERS 8 113 #define OSPREY_NUM_2G_CCK_TARGET_POWERS 2 114 #define OSPREY_NUM_2G_20_TARGET_POWERS 3 115 #define OSPREY_NUM_2G_40_TARGET_POWERS 3 116 //#define OSPREY_NUM_CTLS 21 117 #define OSPREY_NUM_CTLS_5G 9 118 #define OSPREY_NUM_CTLS_2G 12 119 #define OSPREY_CTL_MODE_M 0xF 120 #define OSPREY_NUM_BAND_EDGES_5G 8 121 #define OSPREY_NUM_BAND_EDGES_2G 4 122 #define OSPREY_NUM_PD_GAINS 4 123 #define OSPREY_PD_GAINS_IN_MASK 4 124 #define OSPREY_PD_GAIN_ICEPTS 5 125 #define OSPREY_EEPROM_MODAL_SPURS 5 126 #define OSPREY_MAX_RATE_POWER 63 127 #define OSPREY_NUM_PDADC_VALUES 128 128 #define OSPREY_NUM_RATES 16 129 #define OSPREY_BCHAN_UNUSED 0xFF 130 #define OSPREY_MAX_PWR_RANGE_IN_HALF_DB 64 131 #define OSPREY_OPFLAGS_11A 0x01 132 #define OSPREY_OPFLAGS_11G 0x02 133 #define OSPREY_OPFLAGS_5G_HT40 0x04 134 #define OSPREY_OPFLAGS_2G_HT40 0x08 135 #define OSPREY_OPFLAGS_5G_HT20 0x10 136 #define OSPREY_OPFLAGS_2G_HT20 0x20 137 #define OSPREY_EEPMISC_BIG_ENDIAN 0x01 138 #define OSPREY_EEPMISC_WOW 0x02 139 #define OSPREY_CUSTOMER_DATA_SIZE 20 140 141 #define FREQ2FBIN(x,y) \ 142 (((uintmax_t)(y) == (uintmax_t)HAL_FREQ_BAND_2GHZ) ? ((x) - 2300) : (((x) - 4800) / 5)) 143 #define FBIN2FREQ(x,y) \ 144 (((uintmax_t)(y) == (uintmax_t)HAL_FREQ_BAND_2GHZ) ? (2300 + x) : (4800 + 5 * x)) 145 #define OSPREY_MAX_CHAINS 3 146 #define OSPREY_ANT_16S 25 147 #define OSPREY_FUTURE_MODAL_SZ 6 148 149 #define OSPREY_NUM_ANT_CHAIN_FIELDS 7 150 #define OSPREY_NUM_ANT_COMMON_FIELDS 4 151 #define OSPREY_SIZE_ANT_CHAIN_FIELD 3 152 #define OSPREY_SIZE_ANT_COMMON_FIELD 4 153 #define OSPREY_ANT_CHAIN_MASK 0x7 154 #define OSPREY_ANT_COMMON_MASK 0xf 155 #define OSPREY_CHAIN_0_IDX 0 156 #define OSPREY_CHAIN_1_IDX 1 157 #define OSPREY_CHAIN_2_IDX 2 158 #define OSPREY_1_CHAINMASK 1 159 #define OSPREY_2LOHI_CHAINMASK 5 160 #define OSPREY_2LOMID_CHAINMASK 3 161 #define OSPREY_3_CHAINMASK 7 162 163 #define AR928X_NUM_ANT_CHAIN_FIELDS 6 164 #define AR928X_SIZE_ANT_CHAIN_FIELD 2 165 #define AR928X_ANT_CHAIN_MASK 0x3 166 167 /* Delta from which to start power to pdadc table */ 168 /* This offset is used in both open loop and closed loop power control 169 * schemes. In open loop power control, it is not really needed, but for 170 * the "sake of consistency" it was kept. 171 * For certain AP designs, this value is overwritten by the value in the flag 172 * "pwrTableOffset" just before writing the pdadc vs pwr into the chip registers. 173 */ 174 #define OSPREY_PWR_TABLE_OFFSET 0 175 176 //enable flags for voltage and temp compensation 177 #define ENABLE_TEMP_COMPENSATION 0x01 178 #define ENABLE_VOLT_COMPENSATION 0x02 179 180 #define FLASH_BASE_CALDATA_OFFSET 0x1000 181 #define AR9300_EEPROM_SIZE 16*1024 // byte addressable 182 #define FIXED_CCA_THRESHOLD 15 183 184 typedef struct eepFlags { 185 u_int8_t op_flags; 186 u_int8_t eepMisc; 187 } __packed EEP_FLAGS; 188 189 typedef enum targetPowerHTRates { 190 HT_TARGET_RATE_0_8_16, 191 HT_TARGET_RATE_1_3_9_11_17_19, 192 HT_TARGET_RATE_4, 193 HT_TARGET_RATE_5, 194 HT_TARGET_RATE_6, 195 HT_TARGET_RATE_7, 196 HT_TARGET_RATE_12, 197 HT_TARGET_RATE_13, 198 HT_TARGET_RATE_14, 199 HT_TARGET_RATE_15, 200 HT_TARGET_RATE_20, 201 HT_TARGET_RATE_21, 202 HT_TARGET_RATE_22, 203 HT_TARGET_RATE_23 204 }TARGET_POWER_HT_RATES; 205 206 static const int mapRate2Index[24]= 207 { 208 0,1,1,1,2, 209 3,4,5,0,1, 210 1,1,6,7,8, 211 9,0,1,1,1, 212 10,11,12,13 213 }; 214 215 typedef enum targetPowerLegacyRates { 216 LEGACY_TARGET_RATE_6_24, 217 LEGACY_TARGET_RATE_36, 218 LEGACY_TARGET_RATE_48, 219 LEGACY_TARGET_RATE_54 220 }TARGET_POWER_LEGACY_RATES; 221 222 typedef enum targetPowerCckRates { 223 LEGACY_TARGET_RATE_1L_5L, 224 LEGACY_TARGET_RATE_5S, 225 LEGACY_TARGET_RATE_11L, 226 LEGACY_TARGET_RATE_11S 227 }TARGET_POWER_CCK_RATES; 228 229 #define MAX_MODAL_RESERVED 11 230 #define MAX_MODAL_FUTURE 5 231 #define MAX_BASE_EXTENSION_FUTURE 2 232 #define MAX_TEMP_SLOPE 8 233 #define OSPREY_CHECKSUM_LOCATION (OSPREY_EEP_START_LOC + 1) 234 235 typedef struct osprey_BaseEepHeader { 236 u_int16_t reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration 237 u_int8_t txrx_mask; //4 bits tx and 4 bits rx 238 EEP_FLAGS op_cap_flags; 239 u_int8_t rf_silent; 240 u_int8_t blue_tooth_options; 241 u_int8_t device_cap; 242 u_int8_t device_type; // takes lower byte in eeprom location 243 int8_t pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration 244 u_int8_t params_for_tuning_caps[2]; //placeholder, get more details from Don 245 u_int8_t feature_enable; //bit0 - enable tx temp comp 246 //bit1 - enable tx volt comp 247 //bit2 - enable fastClock - default to 1 248 //bit3 - enable doubling - default to 1 249 //bit4 - enable internal regulator - default to 1 250 //bit5 - enable paprd - default to 0 251 //bit6 - enable TuningCaps - default to 0 252 //bit7 - enable tx_frame_to_xpa_on - default to 0 253 u_int8_t misc_configuration; //misc flags: bit0 - turn down drivestrength 254 // bit 1:2 - 0=don't force, 1=force to thermometer 0, 2=force to thermometer 1, 3=force to thermometer 2 255 // bit 3 - reduce chain mask from 0x7 to 0x3 on 2 stream rates 256 // bit 4 - enable quick drop 257 // bit 5 - enable 8 temp slop 258 // bit 6; enable xLNA_bias_strength 259 // bit 7; enable rf_gain_cap 260 u_int8_t eeprom_write_enable_gpio; 261 u_int8_t wlan_disable_gpio; 262 u_int8_t wlan_led_gpio; 263 u_int8_t rx_band_select_gpio; 264 u_int8_t txrxgain; 265 u_int32_t swreg; // SW controlled internal regulator fields 266 } __packed OSPREY_BASE_EEP_HEADER; 267 268 typedef struct osprey_BaseExtension_1 { 269 u_int8_t ant_div_control; 270 u_int8_t future[MAX_BASE_EXTENSION_FUTURE]; 271 u_int8_t misc_enable; 272 int8_t tempslopextension[MAX_TEMP_SLOPE]; 273 int8_t quick_drop_low; 274 int8_t quick_drop_high; 275 } __packed OSPREY_BASE_EXTENSION_1; 276 277 typedef struct osprey_BaseExtension_2 { 278 int8_t temp_slope_low; 279 int8_t temp_slope_high; 280 u_int8_t xatten1_db_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 281 u_int8_t xatten1_margin_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 282 u_int8_t xatten1_db_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 283 u_int8_t xatten1_margin_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 284 } __packed OSPREY_BASE_EXTENSION_2; 285 286 typedef struct spurChanStruct { 287 u_int16_t spur_chan; 288 u_int8_t spurRangeLow; 289 u_int8_t spurRangeHigh; 290 } __packed SPUR_CHAN; 291 292 //Note the order of the fields in this structure has been optimized to put all fields likely to change together 293 typedef struct ospreyModalEepHeader { 294 u_int32_t ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting) 295 u_int32_t ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 296 u_int16_t ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each) 297 u_int8_t xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0) 298 u_int8_t xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12 299 int8_t temp_slope; 300 int8_t voltSlope; 301 u_int8_t spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format 302 int8_t noise_floor_thresh_ch[OSPREY_MAX_CHAINS];// 3 //Check if the register is per chain 303 u_int8_t reserved[MAX_MODAL_RESERVED]; 304 int8_t quick_drop; 305 u_int8_t xpa_bias_lvl; // 1 306 u_int8_t tx_frame_to_data_start; // 1 307 u_int8_t tx_frame_to_pa_on; // 1 308 u_int8_t txClip; // 4 bits tx_clip, 4 bits dac_scale_cck 309 int8_t antenna_gain; // 1 310 u_int8_t switchSettling; // 1 311 int8_t adcDesiredSize; // 1 312 u_int8_t tx_end_to_xpa_off; // 1 313 u_int8_t txEndToRxOn; // 1 314 u_int8_t tx_frame_to_xpa_on; // 1 315 u_int8_t thresh62; // 1 316 u_int32_t paprd_rate_mask_ht20; 317 u_int32_t paprd_rate_mask_ht40; 318 u_int16_t switchcomspdt; 319 u_int8_t xLNA_bias_strength; // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2 320 u_int8_t rf_gain_cap; 321 u_int8_t tx_gain_cap; // bit0:4 txgain cap, txgain index for max_txgain + 20 (10dBm higher than max txgain) 322 u_int8_t futureModal[MAX_MODAL_FUTURE]; 323 // last 12 bytes stolen and moved to newly created base extension structure 324 } __packed OSPREY_MODAL_EEP_HEADER; // == 100 B 325 326 typedef struct ospCalDataPerFreqOpLoop { 327 int8_t ref_power; /* */ 328 u_int8_t volt_meas; /* pdadc voltage at power measurement */ 329 u_int8_t temp_meas; /* pcdac used for power measurement */ 330 int8_t rx_noisefloor_cal; /*range is -60 to -127 create a mapping equation 1db resolution */ 331 int8_t rx_noisefloor_power; /*range is same as noisefloor */ 332 u_int8_t rxTempMeas; /*temp measured when noisefloor cal was performed */ 333 } __packed OSP_CAL_DATA_PER_FREQ_OP_LOOP; 334 335 typedef struct CalTargetPowerLegacy { 336 u_int8_t t_pow2x[4]; 337 } __packed CAL_TARGET_POWER_LEG; 338 339 typedef struct ospCalTargetPowerHt { 340 u_int8_t t_pow2x[14]; 341 } __packed OSP_CAL_TARGET_POWER_HT; 342 343 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 344 typedef struct CalCtlEdgePwr { 345 u_int8_t flag :2, 346 t_power :6; 347 } __packed CAL_CTL_EDGE_PWR; 348 #else 349 typedef struct CalCtlEdgePwr { 350 u_int8_t t_power :6, 351 flag :2; 352 } __packed CAL_CTL_EDGE_PWR; 353 #endif 354 355 typedef struct ospCalCtlData_5G { 356 CAL_CTL_EDGE_PWR ctl_edges[OSPREY_NUM_BAND_EDGES_5G]; 357 } __packed OSP_CAL_CTL_DATA_5G; 358 359 typedef struct ospCalCtlData_2G { 360 CAL_CTL_EDGE_PWR ctl_edges[OSPREY_NUM_BAND_EDGES_2G]; 361 } __packed OSP_CAL_CTL_DATA_2G; 362 363 typedef struct ospreyEeprom { 364 u_int8_t eeprom_version; 365 u_int8_t template_version; 366 u_int8_t mac_addr[6]; 367 u_int8_t custData[OSPREY_CUSTOMER_DATA_SIZE]; 368 369 OSPREY_BASE_EEP_HEADER base_eep_header; 370 371 OSPREY_MODAL_EEP_HEADER modal_header_2g; 372 OSPREY_BASE_EXTENSION_1 base_ext1; 373 u_int8_t cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]; 374 OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]; 375 u_int8_t cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 376 u_int8_t cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS]; 377 u_int8_t cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]; 378 u_int8_t cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]; 379 CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]; 380 CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]; 381 OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]; 382 OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]; 383 u_int8_t ctl_index_2g[OSPREY_NUM_CTLS_2G]; 384 u_int8_t ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G]; 385 OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G]; 386 387 OSPREY_MODAL_EEP_HEADER modal_header_5g; 388 OSPREY_BASE_EXTENSION_2 base_ext2; 389 u_int8_t cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]; 390 OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]; 391 u_int8_t cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]; 392 u_int8_t cal_target_freqbin_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]; 393 u_int8_t cal_target_freqbin_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]; 394 CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]; 395 OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]; 396 OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]; 397 u_int8_t ctl_index_5g[OSPREY_NUM_CTLS_5G]; 398 u_int8_t ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G]; 399 OSP_CAL_CTL_DATA_5G ctl_power_data_5g[OSPREY_NUM_CTLS_5G]; 400 } __packed ar9300_eeprom_t; 401 402 403 /* 404 ** SWAP Functions 405 ** used to read EEPROM data, which is apparently stored in little 406 ** endian form. We have included both forms of the swap functions, 407 ** one for big endian and one for little endian. The indices of the 408 ** array elements are the differences 409 */ 410 #if AH_BYTE_ORDER == AH_BIG_ENDIAN 411 412 #define AR9300_EEPROM_MAGIC 0x5aa5 413 #define SWAP16(_x) ( (u_int16_t)( (((const u_int8_t *)(&_x))[0] ) |\ 414 ( ( (const u_int8_t *)( &_x ) )[1]<< 8) ) ) 415 416 #define SWAP32(_x) ((u_int32_t)( \ 417 (((const u_int8_t *)(&_x))[0]) | \ 418 (((const u_int8_t *)(&_x))[1]<< 8) | \ 419 (((const u_int8_t *)(&_x))[2]<<16) | \ 420 (((const u_int8_t *)(&_x))[3]<<24))) 421 422 #else // AH_BYTE_ORDER 423 424 #define AR9300_EEPROM_MAGIC 0xa55a 425 #define SWAP16(_x) ( (u_int16_t)( (((const u_int8_t *)(&_x))[1] ) |\ 426 ( ( (const u_int8_t *)( &_x ) )[0]<< 8) ) ) 427 428 #define SWAP32(_x) ((u_int32_t)( \ 429 (((const u_int8_t *)(&_x))[3]) | \ 430 (((const u_int8_t *)(&_x))[2]<< 8) | \ 431 (((const u_int8_t *)(&_x))[1]<<16) | \ 432 (((const u_int8_t *)(&_x))[0]<<24))) 433 434 #endif // AH_BYTE_ORDER 435 436 // OTP registers for OSPREY 437 438 #define AR_GPIO_IN_OUT 0x4048 // GPIO input / output register 439 #define OTP_MEM_START_ADDRESS 0x14000 440 #define OTP_STATUS0_OTP_SM_BUSY 0x00015f18 441 #define OTP_STATUS1_EFUSE_READ_DATA 0x00015f1c 442 443 #define OTP_LDO_CONTROL_ENABLE 0x00015f24 444 #define OTP_LDO_STATUS_POWER_ON 0x00015f2c 445 #define OTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00015f00 446 // OTP register for Jupiter 447 #define GLB_OTP_LDO_CONTROL_ENABLE 0x00020020 448 #define GLB_OTP_LDO_STATUS_POWER_ON 0x00020028 449 #define OTP_PGENB_SETUP_HOLD_TIME_DELAY 0x15f34 450 451 // OTP register for Jupiter BT 452 #define BTOTP_MEM_START_ADDRESS 0x64000 453 #define BTOTP_STATUS0_OTP_SM_BUSY 0x00065f18 454 #define BTOTP_STATUS1_EFUSE_READ_DATA 0x00065f1c 455 #define BTOTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00065f00 456 #define BTOTP_INTF2 0x00065f08 457 #define BTOTP_PGENB_SETUP_HOLD_TIME_DELAY 0x65f34 458 #define BT_RESET_CTL 0x44000 459 #define BT_CLOCK_CONTROL 0x44028 460 461 462 // OTP register for WASP 463 #define OTP_MEM_START_ADDRESS_WASP 0x00030000 464 #define OTP_STATUS0_OTP_SM_BUSY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1018) 465 #define OTP_STATUS1_EFUSE_READ_DATA_WASP (OTP_MEM_START_ADDRESS_WASP + 0x101C) 466 #define OTP_LDO_CONTROL_ENABLE_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1024) 467 #define OTP_LDO_STATUS_POWER_ON_WASP (OTP_MEM_START_ADDRESS_WASP + 0x102C) 468 #define OTP_INTF0_EFUSE_WR_ENABLE_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1000) 469 // Below control the access timing of OTP read/write 470 #define OTP_PG_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1008) 471 #define OTP_RD_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x100C) 472 #define OTP_VDDQ_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1030) 473 #define OTP_PGENB_SETUP_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1034) 474 #define OTP_STROBE_PULSE_INTERVAL_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1038) 475 #define OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x103C) 476 477 #define AR9300_EEPROM_MAGIC_OFFSET 0x0 478 /* reg_off = 4 * (eep_off) */ 479 #define AR9300_EEPROM_S 2 480 #define AR9300_EEPROM_OFFSET 0x2000 481 #ifdef AR9100 482 #define AR9300_EEPROM_START_ADDR 0x1fff1000 483 #else 484 #define AR9300_EEPROM_START_ADDR 0x503f1200 485 #endif 486 #define AR9300_FLASH_CAL_START_OFFSET 0x1000 487 #define AR9300_EEPROM_MAX 0xae0 488 #define IS_EEP_MINOR_V3(_ahp) (ar9300_eeprom_get((_ahp), EEP_MINOR_REV) >= AR9300_EEP_MINOR_VER_3) 489 490 #define ar9300_get_ntxchains(_txchainmask) \ 491 (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 492 493 /* RF silent fields in \ */ 494 #define EEP_RFSILENT_ENABLED 0x0001 /* bit 0: enabled/disabled */ 495 #define EEP_RFSILENT_ENABLED_S 0 /* bit 0: enabled/disabled */ 496 #define EEP_RFSILENT_POLARITY 0x0002 /* bit 1: polarity */ 497 #define EEP_RFSILENT_POLARITY_S 1 /* bit 1: polarity */ 498 #define EEP_RFSILENT_GPIO_SEL 0x00fc /* bits 2..7: gpio PIN */ 499 #define EEP_RFSILENT_GPIO_SEL_S 2 /* bits 2..7: gpio PIN */ 500 #define AR9300_EEP_VER 0xE 501 #define AR9300_BCHAN_UNUSED 0xFF 502 #define AR9300_MAX_RATE_POWER 63 503 504 typedef enum { 505 CALDATA_AUTO=0, 506 CALDATA_EEPROM, 507 CALDATA_FLASH, 508 CALDATA_OTP 509 } CALDATA_TYPE; 510 511 typedef enum { 512 EEP_NFTHRESH_5, 513 EEP_NFTHRESH_2, 514 EEP_MAC_MSW, 515 EEP_MAC_MID, 516 EEP_MAC_LSW, 517 EEP_REG_0, 518 EEP_REG_1, 519 EEP_OP_CAP, 520 EEP_OP_MODE, 521 EEP_RF_SILENT, 522 EEP_OB_5, 523 EEP_DB_5, 524 EEP_OB_2, 525 EEP_DB_2, 526 EEP_MINOR_REV, 527 EEP_TX_MASK, 528 EEP_RX_MASK, 529 EEP_FSTCLK_5G, 530 EEP_RXGAIN_TYPE, 531 EEP_OL_PWRCTRL, 532 EEP_TXGAIN_TYPE, 533 EEP_RC_CHAIN_MASK, 534 EEP_DAC_HPWR_5G, 535 EEP_FRAC_N_5G, 536 EEP_DEV_TYPE, 537 EEP_TEMPSENSE_SLOPE, 538 EEP_TEMPSENSE_SLOPE_PAL_ON, 539 EEP_PWR_TABLE_OFFSET, 540 EEP_DRIVE_STRENGTH, 541 EEP_INTERNAL_REGULATOR, 542 EEP_SWREG, 543 EEP_PAPRD_ENABLED, 544 EEP_ANTDIV_control, 545 EEP_CHAIN_MASK_REDUCE, 546 } EEPROM_PARAM; 547 548 #define AR9300_RATES_OFDM_OFFSET 0 549 #define AR9300_RATES_CCK_OFFSET 4 550 #define AR9300_RATES_HT20_OFFSET 8 551 #define AR9300_RATES_HT40_OFFSET 22 552 typedef enum ar9300_Rates { 553 ALL_TARGET_LEGACY_6_24, 554 ALL_TARGET_LEGACY_36, 555 ALL_TARGET_LEGACY_48, 556 ALL_TARGET_LEGACY_54, 557 ALL_TARGET_LEGACY_1L_5L, 558 ALL_TARGET_LEGACY_5S, 559 ALL_TARGET_LEGACY_11L, 560 ALL_TARGET_LEGACY_11S, 561 ALL_TARGET_HT20_0_8_16, 562 ALL_TARGET_HT20_1_3_9_11_17_19, 563 ALL_TARGET_HT20_4, 564 ALL_TARGET_HT20_5, 565 ALL_TARGET_HT20_6, 566 ALL_TARGET_HT20_7, 567 ALL_TARGET_HT20_12, 568 ALL_TARGET_HT20_13, 569 ALL_TARGET_HT20_14, 570 ALL_TARGET_HT20_15, 571 ALL_TARGET_HT20_20, 572 ALL_TARGET_HT20_21, 573 ALL_TARGET_HT20_22, 574 ALL_TARGET_HT20_23, 575 ALL_TARGET_HT40_0_8_16, 576 ALL_TARGET_HT40_1_3_9_11_17_19, 577 ALL_TARGET_HT40_4, 578 ALL_TARGET_HT40_5, 579 ALL_TARGET_HT40_6, 580 ALL_TARGET_HT40_7, 581 ALL_TARGET_HT40_12, 582 ALL_TARGET_HT40_13, 583 ALL_TARGET_HT40_14, 584 ALL_TARGET_HT40_15, 585 ALL_TARGET_HT40_20, 586 ALL_TARGET_HT40_21, 587 ALL_TARGET_HT40_22, 588 ALL_TARGET_HT40_23, 589 ar9300_rate_size 590 } AR9300_RATES; 591 592 593 /************************************************************************** 594 * fbin2freq 595 * 596 * Get channel value from binary representation held in eeprom 597 * RETURNS: the frequency in MHz 598 */ 599 static inline u_int16_t 600 fbin2freq(u_int8_t fbin, HAL_BOOL is_2ghz) 601 { 602 /* 603 * Reserved value 0xFF provides an empty definition both as 604 * an fbin and as a frequency - do not convert 605 */ 606 if (fbin == AR9300_BCHAN_UNUSED) 607 { 608 return fbin; 609 } 610 611 return (u_int16_t)((is_2ghz) ? (2300 + fbin) : (4800 + 5 * fbin)); 612 } 613 614 extern int CompressionHeaderUnpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor); 615 extern void Ar9300EepromFormatConvert(ar9300_eeprom_t *mptr); 616 extern HAL_BOOL ar9300_eeprom_restore(struct ath_hal *ah); 617 extern int ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr, int /*msize*/); 618 extern int ar9300_eeprom_base_address(struct ath_hal *ah); 619 extern int ar9300_eeprom_volatile(struct ath_hal *ah); 620 extern int ar9300_eeprom_low_limit(struct ath_hal *ah); 621 extern u_int16_t ar9300_compression_checksum(u_int8_t *data, int dsize); 622 extern int ar9300_compression_header_unpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor); 623 624 extern u_int16_t ar9300_eeprom_struct_size(void); 625 extern ar9300_eeprom_t *ar9300EepromStructInit(int default_index); 626 extern ar9300_eeprom_t *ar9300EepromStructGet(void); 627 extern ar9300_eeprom_t *ar9300_eeprom_struct_default(int default_index); 628 extern ar9300_eeprom_t *ar9300_eeprom_struct_default_find_by_id(int ver); 629 extern int ar9300_eeprom_struct_default_many(void); 630 extern int ar9300EepromUpdateCalPier(int pierIdx, int freq, int chain, 631 int pwrCorrection, int volt_meas, int temp_meas); 632 extern int ar9300_power_control_override(struct ath_hal *ah, int frequency, int *correction, int *voltage, int *temperature); 633 634 extern void ar9300EepromDisplayCalData(int for2GHz); 635 extern void ar9300EepromDisplayAll(void); 636 extern void ar9300_set_target_power_from_eeprom(struct ath_hal *ah, u_int16_t freq, 637 u_int8_t *target_power_val_t2); 638 extern HAL_BOOL ar9300_eeprom_set_power_per_rate_table(struct ath_hal *ah, 639 ar9300_eeprom_t *p_eep_data, 640 const struct ieee80211_channel *chan, 641 u_int8_t *p_pwr_array, 642 u_int16_t cfg_ctl, 643 u_int16_t antenna_reduction, 644 u_int16_t twice_max_regulatory_power, 645 u_int16_t power_limit, 646 u_int8_t chainmask); 647 extern int ar9300_transmit_power_reg_write(struct ath_hal *ah, u_int8_t *p_pwr_array); 648 649 extern u_int8_t ar9300_eeprom_get_legacy_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); 650 extern u_int8_t ar9300_eeprom_get_ht20_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); 651 extern u_int8_t ar9300_eeprom_get_ht40_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz); 652 extern u_int8_t ar9300_eeprom_get_cck_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq); 653 extern HAL_BOOL ar9300_internal_regulator_apply(struct ath_hal *ah); 654 extern HAL_BOOL ar9300_drive_strength_apply(struct ath_hal *ah); 655 extern HAL_BOOL ar9300_attenuation_apply(struct ath_hal *ah, u_int16_t channel); 656 extern int32_t ar9300_thermometer_get(struct ath_hal *ah); 657 extern HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah); 658 extern HAL_BOOL ar9300_xpa_timing_control_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 659 extern HAL_BOOL ar9300_x_lNA_bias_strength_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 660 661 extern int32_t ar9300MacAdressGet(u_int8_t *mac); 662 extern int32_t ar9300CustomerDataGet(u_int8_t *data, int32_t len); 663 extern int32_t ar9300ReconfigDriveStrengthGet(void); 664 extern int32_t ar9300EnableTempCompensationGet(void); 665 extern int32_t ar9300EnableVoltCompensationGet(void); 666 extern int32_t ar9300FastClockEnableGet(void); 667 extern int32_t ar9300EnableDoublingGet(void); 668 669 extern u_int16_t *ar9300_regulatory_domain_get(struct ath_hal *ah); 670 extern int32_t ar9300_eeprom_write_enable_gpio_get(struct ath_hal *ah); 671 extern int32_t ar9300_wlan_led_gpio_get(struct ath_hal *ah); 672 extern int32_t ar9300_wlan_disable_gpio_get(struct ath_hal *ah); 673 extern int32_t ar9300_rx_band_select_gpio_get(struct ath_hal *ah); 674 extern int32_t ar9300_rx_gain_index_get(struct ath_hal *ah); 675 extern int32_t ar9300_tx_gain_index_get(struct ath_hal *ah); 676 extern int32_t ar9300_xpa_bias_level_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 677 extern HAL_BOOL ar9300_xpa_bias_level_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 678 extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 679 extern u_int32_t ar9300_ant_ctrl_common2_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 680 extern u_int16_t ar9300_ant_ctrl_chain_get(struct ath_hal *ah, int chain, HAL_BOOL is_2ghz); 681 extern HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz); 682 /* since valid noise floor values are negative, returns 1 on error */ 683 extern int32_t ar9300_noise_floor_cal_or_power_get( 684 struct ath_hal *ah, int32_t frequency, int32_t ichain, HAL_BOOL use_cal); 685 #define ar9300NoiseFloorGet(ah, frequency, ichain) \ 686 ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 1/*use_cal*/) 687 #define ar9300NoiseFloorPowerGet(ah, frequency, ichain) \ 688 ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 0/*use_cal*/) 689 extern void ar9300_eeprom_template_preference(int32_t value); 690 extern int32_t ar9300_eeprom_template_install(struct ath_hal *ah, int32_t value); 691 extern void ar9300_calibration_data_set(struct ath_hal *ah, int32_t source); 692 extern int32_t ar9300_calibration_data_get(struct ath_hal *ah); 693 extern int32_t ar9300_calibration_data_address_get(struct ath_hal *ah); 694 extern void ar9300_calibration_data_address_set(struct ath_hal *ah, int32_t source); 695 extern HAL_BOOL ar9300_calibration_data_read_flash(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 696 extern HAL_BOOL ar9300_calibration_data_read_eeprom(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 697 extern HAL_BOOL ar9300_calibration_data_read_otp(struct ath_hal *ah, long address, u_int8_t *buffer, int many, HAL_BOOL is_wifi); 698 extern HAL_BOOL ar9300_calibration_data_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 699 extern int32_t ar9300_eeprom_size(struct ath_hal *ah); 700 extern int32_t ar9300_otp_size(struct ath_hal *ah); 701 extern HAL_BOOL ar9300_calibration_data_read_array(struct ath_hal *ah, int address, u_int8_t *buffer, int many); 702 703 704 705 #if defined(WIN32) || defined(WIN64) 706 #pragma pack (pop, ar9300) 707 #endif 708 709 #endif /* _ATH_AR9300_EEP_H_ */ 710