1 /* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.1.2.1 2002/11/21 23:37:11 sam Exp $ */ 2 /* $DragonFly: src/sys/dev/crypto/hifn/hifn7751reg.h,v 1.2 2003/06/17 04:28:27 dillon Exp $ */ 3 /* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ 4 5 /* 6 * Invertex AEON / Hifn 7751 driver 7 * Copyright (c) 1999 Invertex Inc. All rights reserved. 8 * Copyright (c) 1999 Theo de Raadt 9 * Copyright (c) 2000-2001 Network Security Technologies, Inc. 10 * http://www.netsec.net 11 * 12 * Please send any comments, feedback, bug-fixes, or feature requests to 13 * software@invertex.com. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. The name of the author may not be used to endorse or promote products 25 * derived from this software without specific prior written permission. 26 * 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 30 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 31 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 * 39 * Effort sponsored in part by the Defense Advanced Research Projects 40 * Agency (DARPA) and Air Force Research Laboratory, Air Force 41 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 42 * 43 */ 44 #ifndef __HIFN_H__ 45 #define __HIFN_H__ 46 47 #include <sys/endian.h> 48 49 /* 50 * Some PCI configuration space offset defines. The names were made 51 * identical to the names used by the Linux kernel. 52 */ 53 #define HIFN_BAR0 (PCIR_MAPS+0x0) /* PUC register map */ 54 #define HIFN_BAR1 (PCIR_MAPS+0x4) /* DMA register map */ 55 #define HIFN_TRDY_TIMEOUT 0x40 56 #define HIFN_RETRY_TIMEOUT 0x41 57 58 /* 59 * PCI vendor and device identifiers 60 * (the names are preserved from their OpenBSD source). 61 */ 62 #define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ 63 #define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ 64 #define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ 65 #define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ 66 #define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ 67 68 #define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ 69 #define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ 70 71 #define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ 72 #define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ 73 74 /* 75 * The values below should multiple of 4 -- and be large enough to handle 76 * any command the driver implements. 77 * 78 * MAX_COMMAND = base command + mac command + encrypt command + 79 * mac-key + rc4-key 80 * MAX_RESULT = base result + mac result + mac + encrypt result 81 * 82 * 83 */ 84 #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) 85 #define HIFN_MAX_RESULT (8 + 4 + 20 + 4) 86 87 /* 88 * hifn_desc_t 89 * 90 * Holds an individual descriptor for any of the rings. 91 */ 92 typedef struct hifn_desc { 93 volatile u_int32_t l; /* length and status bits */ 94 volatile u_int32_t p; 95 } hifn_desc_t; 96 97 /* 98 * Masks for the "length" field of struct hifn_desc. 99 */ 100 #define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ 101 #define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ 102 #define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ 103 #define HIFN_D_OVER 0x08000000 /* overflow */ 104 #define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ 105 #define HIFN_D_JUMP 0x40000000 /* jump descriptor */ 106 #define HIFN_D_VALID 0x80000000 /* valid bit */ 107 108 109 /* 110 * Processing Unit Registers (offset from BASEREG0) 111 */ 112 #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ 113 #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ 114 #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ 115 #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ 116 #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ 117 #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ 118 #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ 119 #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ 120 #define HIFN_0_SPACESIZE 0x20 /* Register space size */ 121 122 /* Processing Unit Control Register (HIFN_0_PUCTRL) */ 123 #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ 124 #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ 125 #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ 126 #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ 127 #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ 128 129 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ 130 #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ 131 #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ 132 #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 133 #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 134 #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ 135 #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ 136 #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ 137 #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ 138 #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ 139 #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ 140 141 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ 142 #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ 143 #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ 144 #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ 145 #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ 146 #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ 147 #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ 148 #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ 149 #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ 150 #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ 151 #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ 152 #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ 153 #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ 154 #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ 155 #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ 156 #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ 157 #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ 158 #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ 159 #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ 160 #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ 161 #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ 162 #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ 163 #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ 164 #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ 165 166 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ 167 #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ 168 #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ 169 #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 170 #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 171 #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ 172 #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ 173 #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ 174 #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ 175 #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ 176 #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ 177 178 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ 179 #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ 180 #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ 181 #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ 182 #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ 183 #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ 184 #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ 185 #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ 186 #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ 187 #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ 188 #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ 189 #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ 190 #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ 191 #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ 192 #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ 193 #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ 194 #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ 195 #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ 196 197 /* FIFO Status Register (HIFN_0_FIFOSTAT) */ 198 #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ 199 #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ 200 201 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ 202 #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */ 203 204 /* 205 * DMA Interface Registers (offset from BASEREG1) 206 */ 207 #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ 208 #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ 209 #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ 210 #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ 211 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ 212 #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ 213 #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ 214 #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ 215 #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ 216 #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ 217 #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ 218 #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ 219 #define HIFN_1_REVID 0x98 /* Revision ID */ 220 221 #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ 222 #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ 223 #define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */ 224 #define HIFN_1_PUB_OP 0x308 /* Public Operand */ 225 #define HIFN_1_PUB_STATUS 0x30c /* Public Status */ 226 #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt nable */ 227 #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ 228 #define HIFN_1_RNG_DATA 0x318 /* RNG data */ 229 #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ 230 #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ 231 232 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */ 233 #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ 234 #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ 235 #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ 236 #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ 237 #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ 238 #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ 239 #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ 240 #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ 241 #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ 242 #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ 243 #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ 244 #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ 245 #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ 246 #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ 247 #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ 248 #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ 249 #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ 250 #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ 251 #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ 252 #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ 253 #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ 254 #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ 255 #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ 256 #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ 257 #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ 258 #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ 259 #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ 260 #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ 261 #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ 262 #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ 263 #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ 264 #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ 265 #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ 266 #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ 267 #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ 268 #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ 269 #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ 270 #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ 271 272 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ 273 #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ 274 #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ 275 #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ 276 #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ 277 #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ 278 #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ 279 #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ 280 #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ 281 #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ 282 #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ 283 #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ 284 #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ 285 #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ 286 #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ 287 #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ 288 #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ 289 #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ 290 #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ 291 #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ 292 #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ 293 #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ 294 #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ 295 296 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */ 297 #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ 298 #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ 299 #define HIFN_DMACNFG_UNLOCK 0x00000800 300 #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ 301 #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ 302 #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ 303 #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ 304 #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ 305 306 /* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ 307 #define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ 308 309 /* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ 310 #define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ 311 #define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ 312 #define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ 313 314 /* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ 315 #define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ 316 #define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ 317 318 /* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ 319 #define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ 320 #define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ 321 #define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ 322 #define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ 323 #define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ 324 #define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ 325 #define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ 326 #define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ 327 #define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ 328 329 /* Public key reset register (HIFN_1_PUB_RESET) */ 330 #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ 331 332 /* Public operation register (HIFN_1_PUB_OP) */ 333 #define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ 334 #define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ 335 #define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ 336 #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ 337 #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ 338 #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ 339 #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ 340 #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ 341 #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ 342 #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ 343 #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ 344 #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ 345 #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ 346 #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ 347 #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ 348 #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ 349 #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ 350 351 /* Public operand length register (HIFN_1_PUB_OPLEN) */ 352 #define HIFN_PUBOPLEN_MODLEN 0x0000007f 353 #define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 354 #define HIFN_PUBOPLEN_REDLEN 0x003c0000 355 356 /* Public status register (HIFN_1_PUB_STATUS) */ 357 #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ 358 #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ 359 360 /* Public interrupt enable register (HIFN_1_PUB_IEN) */ 361 #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ 362 363 /* Random number generator config register (HIFN_1_RNG_CONFIG) */ 364 #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ 365 366 /* 367 * Register offsets in register set 1 368 */ 369 370 #define HIFN_UNLOCK_SECRET1 0xf4 371 #define HIFN_UNLOCK_SECRET2 0xfc 372 373 /********************************************************************* 374 * Structs for board commands 375 * 376 *********************************************************************/ 377 378 /* 379 * Structure to help build up the command data structure. 380 */ 381 typedef struct hifn_base_command { 382 volatile u_int16_t masks; 383 volatile u_int16_t session_num; 384 volatile u_int16_t total_source_count; 385 volatile u_int16_t total_dest_count; 386 } hifn_base_command_t; 387 388 #define HIFN_BASE_CMD_MAC 0x0400 389 #define HIFN_BASE_CMD_CRYPT 0x0800 390 #define HIFN_BASE_CMD_DECODE 0x2000 391 #define HIFN_BASE_CMD_SRCLEN_M 0xc000 392 #define HIFN_BASE_CMD_SRCLEN_S 14 393 #define HIFN_BASE_CMD_DSTLEN_M 0x3000 394 #define HIFN_BASE_CMD_DSTLEN_S 12 395 #define HIFN_BASE_CMD_LENMASK_HI 0x30000 396 #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff 397 398 /* 399 * Structure to help build up the command data structure. 400 */ 401 typedef struct hifn_crypt_command { 402 volatile u_int16_t masks; 403 volatile u_int16_t header_skip; 404 volatile u_int16_t source_count; 405 volatile u_int16_t reserved; 406 } hifn_crypt_command_t; 407 408 #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ 409 #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ 410 #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ 411 #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ 412 #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* DES mode: */ 413 #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ 414 #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ 415 #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ 416 #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ 417 #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ 418 #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ 419 #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ 420 421 #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 422 #define HIFN_CRYPT_CMD_SRCLEN_S 14 423 424 /* 425 * Structure to help build up the command data structure. 426 */ 427 typedef struct hifn_mac_command { 428 volatile u_int16_t masks; 429 volatile u_int16_t header_skip; 430 volatile u_int16_t source_count; 431 volatile u_int16_t reserved; 432 } hifn_mac_command_t; 433 434 #define HIFN_MAC_CMD_ALG_MASK 0x0001 435 #define HIFN_MAC_CMD_ALG_SHA1 0x0000 436 #define HIFN_MAC_CMD_ALG_MD5 0x0001 437 #define HIFN_MAC_CMD_MODE_MASK 0x000c 438 #define HIFN_MAC_CMD_MODE_HMAC 0x0000 439 #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 440 #define HIFN_MAC_CMD_MODE_HASH 0x0008 441 #define HIFN_MAC_CMD_MODE_FULL 0x0004 442 #define HIFN_MAC_CMD_TRUNC 0x0010 443 #define HIFN_MAC_CMD_RESULT 0x0020 444 #define HIFN_MAC_CMD_APPEND 0x0040 445 #define HIFN_MAC_CMD_SRCLEN_M 0xc000 446 #define HIFN_MAC_CMD_SRCLEN_S 14 447 448 /* 449 * MAC POS IPsec initiates authentication after encryption on encodes 450 * and before decryption on decodes. 451 */ 452 #define HIFN_MAC_CMD_POS_IPSEC 0x0200 453 #define HIFN_MAC_CMD_NEW_KEY 0x0800 454 455 /* 456 * The poll frequency and poll scalar defines are unshifted values used 457 * to set fields in the DMA Configuration Register. 458 */ 459 #ifndef HIFN_POLL_FREQUENCY 460 #define HIFN_POLL_FREQUENCY 0x1 461 #endif 462 463 #ifndef HIFN_POLL_SCALAR 464 #define HIFN_POLL_SCALAR 0x0 465 #endif 466 467 #define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ 468 #define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ 469 #endif /* __HIFN_H__ */ 470