1 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.12 2003/06/04 17:56:59 sam Exp $ */ 2 /* $DragonFly: src/sys/dev/crypto/ubsec/ubsec.c,v 1.13 2006/12/22 23:26:15 swildner Exp $ */ 3 /* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */ 4 5 /* 6 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 7 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 8 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 9 * 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by Jason L. Wright 23 * 4. The name of the author may not be used to endorse or promote products 24 * derived from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 29 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Effort sponsored in part by the Defense Advanced Research Projects 39 * Agency (DARPA) and Air Force Research Laboratory, Air Force 40 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41 * 42 */ 43 44 /* 45 * uBsec 5[56]01, 58xx hardware crypto accelerator 46 */ 47 48 #include "opt_ubsec.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/proc.h> 53 #include <sys/errno.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/mbuf.h> 57 #include <sys/sysctl.h> 58 #include <sys/endian.h> 59 #include <sys/bus.h> 60 #include <sys/rman.h> 61 #include <sys/md5.h> 62 #include <sys/random.h> 63 #include <sys/thread2.h> 64 65 #include <vm/vm.h> 66 #include <vm/pmap.h> 67 68 #include <machine/clock.h> 69 70 #include <crypto/sha1.h> 71 #include <opencrypto/cryptodev.h> 72 #include <opencrypto/cryptosoft.h> 73 74 #include "cryptodev_if.h" 75 76 #include <bus/pci/pcivar.h> 77 #include <bus/pci/pcireg.h> 78 79 /* grr, #defines for gratuitous incompatibility in queue.h */ 80 #define SIMPLEQ_HEAD STAILQ_HEAD 81 #define SIMPLEQ_ENTRY STAILQ_ENTRY 82 #define SIMPLEQ_INIT STAILQ_INIT 83 #define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL 84 #define SIMPLEQ_EMPTY STAILQ_EMPTY 85 #define SIMPLEQ_FIRST STAILQ_FIRST 86 #define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD 87 #define SIMPLEQ_FOREACH STAILQ_FOREACH 88 /* ditto for endian.h */ 89 #define letoh16(x) le16toh(x) 90 #define letoh32(x) le32toh(x) 91 92 #ifdef UBSEC_RNDTEST 93 #include "../rndtest/rndtest.h" 94 #endif 95 #include "ubsecreg.h" 96 #include "ubsecvar.h" 97 98 /* 99 * Prototypes and count for the pci_device structure 100 */ 101 static int ubsec_probe(device_t); 102 static int ubsec_attach(device_t); 103 static int ubsec_detach(device_t); 104 static int ubsec_suspend(device_t); 105 static int ubsec_resume(device_t); 106 static void ubsec_shutdown(device_t); 107 static void ubsec_intr(void *); 108 static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *); 109 static int ubsec_freesession(void *, u_int64_t); 110 static int ubsec_process(void *, struct cryptop *, int); 111 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 112 static void ubsec_feed(struct ubsec_softc *); 113 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 114 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 115 static int ubsec_feed2(struct ubsec_softc *); 116 static void ubsec_rng(void *); 117 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 118 struct ubsec_dma_alloc *, int); 119 #define ubsec_dma_sync(_dma, _flags) \ 120 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 121 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 122 static int ubsec_dmamap_aligned(struct ubsec_operand *op); 123 124 static void ubsec_reset_board(struct ubsec_softc *sc); 125 static void ubsec_init_board(struct ubsec_softc *sc); 126 static void ubsec_init_pciregs(device_t dev); 127 static void ubsec_totalreset(struct ubsec_softc *sc); 128 129 static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q); 130 131 static int ubsec_kprocess(void*, struct cryptkop *, int); 132 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int); 133 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int); 134 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int); 135 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 136 static int ubsec_ksigbits(struct crparam *); 137 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 138 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 139 140 141 static device_method_t ubsec_methods[] = { 142 /* Device interface */ 143 DEVMETHOD(device_probe, ubsec_probe), 144 DEVMETHOD(device_attach, ubsec_attach), 145 DEVMETHOD(device_detach, ubsec_detach), 146 DEVMETHOD(device_suspend, ubsec_suspend), 147 DEVMETHOD(device_resume, ubsec_resume), 148 DEVMETHOD(device_shutdown, ubsec_shutdown), 149 150 /* bus interface */ 151 DEVMETHOD(bus_print_child, bus_generic_print_child), 152 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 153 154 /* crypto device methods */ 155 DEVMETHOD(cryptodev_newsession, ubsec_newsession), 156 DEVMETHOD(cryptodev_freesession,ubsec_freesession), 157 DEVMETHOD(cryptodev_process, ubsec_process), 158 DEVMETHOD(cryptodev_kprocess, ubsec_kprocess), 159 160 { 0, 0 } 161 }; 162 static driver_t ubsec_driver = { 163 "ubsec", 164 ubsec_methods, 165 sizeof (struct ubsec_softc) 166 }; 167 static devclass_t ubsec_devclass; 168 169 DECLARE_DUMMY_MODULE(ubsec); 170 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0); 171 MODULE_DEPEND(ubsec, crypto, 1, 1, 1); 172 #ifdef UBSEC_RNDTEST 173 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1); 174 #endif 175 176 SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters"); 177 178 #ifdef UBSEC_DEBUG 179 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 180 static void ubsec_dump_mcr(struct ubsec_mcr *); 181 static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *); 182 183 static int ubsec_debug = 0; 184 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug, 185 0, "control debugging msgs"); 186 #endif 187 188 #define READ_REG(sc,r) \ 189 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 190 191 #define WRITE_REG(sc,reg,val) \ 192 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 193 194 #define SWAP32(x) (x) = htole32(ntohl((x))) 195 #define HTOLE32(x) (x) = htole32(x) 196 197 198 struct ubsec_stats ubsecstats; 199 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats, 200 ubsec_stats, "driver statistics"); 201 202 static int 203 ubsec_probe(device_t dev) 204 { 205 if (pci_get_vendor(dev) == PCI_VENDOR_SUN && 206 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 || 207 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K)) 208 return (0); 209 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 210 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 || 211 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)) 212 return (0); 213 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 214 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 || 215 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 216 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 || 217 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 || 218 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 219 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 220 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 221 )) 222 return (0); 223 return (ENXIO); 224 } 225 226 static const char* 227 ubsec_partname(struct ubsec_softc *sc) 228 { 229 /* XXX sprintf numbers when not decoded */ 230 switch (pci_get_vendor(sc->sc_dev)) { 231 case PCI_VENDOR_BROADCOM: 232 switch (pci_get_device(sc->sc_dev)) { 233 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801"; 234 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802"; 235 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805"; 236 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820"; 237 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821"; 238 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822"; 239 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823"; 240 } 241 return "Broadcom unknown-part"; 242 case PCI_VENDOR_BLUESTEEL: 243 switch (pci_get_device(sc->sc_dev)) { 244 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601"; 245 } 246 return "Bluesteel unknown-part"; 247 case PCI_VENDOR_SUN: 248 switch (pci_get_device(sc->sc_dev)) { 249 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821"; 250 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K"; 251 } 252 return "Sun unknown-part"; 253 } 254 return "Unknown-vendor unknown-part"; 255 } 256 257 static void 258 default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 259 { 260 u_int32_t *p = (u_int32_t *)buf; 261 for (count /= sizeof (u_int32_t); count; count--) 262 add_true_randomness(*p++); 263 } 264 265 static int 266 ubsec_attach(device_t dev) 267 { 268 struct ubsec_softc *sc = device_get_softc(dev); 269 struct ubsec_dma *dmap; 270 u_int32_t cmd, i; 271 int rid; 272 273 KASSERT(sc != NULL, ("ubsec_attach: null software carrier!")); 274 bzero(sc, sizeof (*sc)); 275 sc->sc_dev = dev; 276 277 SIMPLEQ_INIT(&sc->sc_queue); 278 SIMPLEQ_INIT(&sc->sc_qchip); 279 SIMPLEQ_INIT(&sc->sc_queue2); 280 SIMPLEQ_INIT(&sc->sc_qchip2); 281 SIMPLEQ_INIT(&sc->sc_q2free); 282 283 /* XXX handle power management */ 284 285 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 286 287 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 288 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601) 289 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 290 291 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 292 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 293 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805)) 294 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 295 296 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 297 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820) 298 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 299 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 300 301 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 302 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 303 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 304 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) || 305 (pci_get_vendor(dev) == PCI_VENDOR_SUN && 306 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K || 307 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) { 308 /* NB: the 5821/5822 defines some additional status bits */ 309 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 310 BS_STAT_MCR2_ALLEMPTY; 311 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 312 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 313 } 314 315 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 316 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 317 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 318 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 319 320 if (!(cmd & PCIM_CMD_MEMEN)) { 321 device_printf(dev, "failed to enable memory mapping\n"); 322 goto bad; 323 } 324 325 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 326 device_printf(dev, "failed to enable bus mastering\n"); 327 goto bad; 328 } 329 330 /* 331 * Setup memory-mapping of PCI registers. 332 */ 333 rid = BS_BAR; 334 sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 335 0, ~0, 1, RF_ACTIVE); 336 if (sc->sc_sr == NULL) { 337 device_printf(dev, "cannot map register space\n"); 338 goto bad; 339 } 340 sc->sc_st = rman_get_bustag(sc->sc_sr); 341 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 342 343 /* 344 * Arrange interrupt line. 345 */ 346 rid = 0; 347 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 348 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 349 if (sc->sc_irq == NULL) { 350 device_printf(dev, "could not map interrupt\n"); 351 goto bad1; 352 } 353 /* 354 * NB: Network code assumes we are blocked with splimp() 355 * so make sure the IRQ is mapped appropriately. 356 */ 357 if (bus_setup_intr(dev, sc->sc_irq, 0, 358 ubsec_intr, sc, 359 &sc->sc_ih, NULL)) { 360 device_printf(dev, "could not establish interrupt\n"); 361 goto bad2; 362 } 363 364 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 365 if (sc->sc_cid < 0) { 366 device_printf(dev, "could not get crypto driver id\n"); 367 goto bad3; 368 } 369 370 /* 371 * Setup DMA descriptor area. 372 */ 373 if (bus_dma_tag_create(NULL, /* parent */ 374 1, 0, /* alignment, bounds */ 375 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 376 BUS_SPACE_MAXADDR, /* highaddr */ 377 NULL, NULL, /* filter, filterarg */ 378 0x3ffff, /* maxsize */ 379 UBS_MAX_SCATTER, /* nsegments */ 380 0xffff, /* maxsegsize */ 381 BUS_DMA_ALLOCNOW, /* flags */ 382 &sc->sc_dmat)) { 383 device_printf(dev, "cannot allocate DMA tag\n"); 384 goto bad4; 385 } 386 SIMPLEQ_INIT(&sc->sc_freequeue); 387 dmap = sc->sc_dmaa; 388 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 389 struct ubsec_q *q; 390 391 q = kmalloc(sizeof(struct ubsec_q), M_DEVBUF, M_WAITOK); 392 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 393 &dmap->d_alloc, 0)) { 394 device_printf(dev, "cannot allocate dma buffers\n"); 395 kfree(q, M_DEVBUF); 396 break; 397 } 398 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 399 400 q->q_dma = dmap; 401 sc->sc_queuea[i] = q; 402 403 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 404 } 405 406 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc)); 407 408 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); 409 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); 410 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); 411 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); 412 413 /* 414 * Reset Broadcom chip 415 */ 416 ubsec_reset_board(sc); 417 418 /* 419 * Init Broadcom specific PCI settings 420 */ 421 ubsec_init_pciregs(dev); 422 423 /* 424 * Init Broadcom chip 425 */ 426 ubsec_init_board(sc); 427 428 #ifndef UBSEC_NO_RNG 429 if (sc->sc_flags & UBS_FLAGS_RNG) { 430 sc->sc_statmask |= BS_STAT_MCR2_DONE; 431 #ifdef UBSEC_RNDTEST 432 sc->sc_rndtest = rndtest_attach(dev); 433 if (sc->sc_rndtest) 434 sc->sc_harvest = rndtest_harvest; 435 else 436 sc->sc_harvest = default_harvest; 437 #else 438 sc->sc_harvest = default_harvest; 439 #endif 440 441 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 442 &sc->sc_rng.rng_q.q_mcr, 0)) 443 goto skip_rng; 444 445 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 446 &sc->sc_rng.rng_q.q_ctx, 0)) { 447 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 448 goto skip_rng; 449 } 450 451 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 452 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 453 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 454 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 455 goto skip_rng; 456 } 457 458 if (hz >= 100) 459 sc->sc_rnghz = hz / 100; 460 else 461 sc->sc_rnghz = 1; 462 callout_init(&sc->sc_rngto); 463 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 464 skip_rng: 465 ; 466 } 467 #endif /* UBSEC_NO_RNG */ 468 469 if (sc->sc_flags & UBS_FLAGS_KEY) { 470 sc->sc_statmask |= BS_STAT_MCR2_DONE; 471 472 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); 473 #if 0 474 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); 475 #endif 476 } 477 return (0); 478 bad4: 479 crypto_unregister_all(sc->sc_cid); 480 bad3: 481 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 482 bad2: 483 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 484 bad1: 485 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 486 bad: 487 return (ENXIO); 488 } 489 490 /* 491 * Detach a device that successfully probed. 492 */ 493 static int 494 ubsec_detach(device_t dev) 495 { 496 struct ubsec_softc *sc = device_get_softc(dev); 497 498 KASSERT(sc != NULL, ("ubsec_detach: null software carrier")); 499 500 /* XXX wait/abort active ops */ 501 502 crit_enter(); 503 504 callout_stop(&sc->sc_rngto); 505 506 crypto_unregister_all(sc->sc_cid); 507 508 #ifdef UBSEC_RNDTEST 509 if (sc->sc_rndtest) 510 rndtest_detach(sc->sc_rndtest); 511 #endif 512 513 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 514 struct ubsec_q *q; 515 516 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 517 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next); 518 ubsec_dma_free(sc, &q->q_dma->d_alloc); 519 kfree(q, M_DEVBUF); 520 } 521 #ifndef UBSEC_NO_RNG 522 if (sc->sc_flags & UBS_FLAGS_RNG) { 523 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 524 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 525 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 526 } 527 #endif /* UBSEC_NO_RNG */ 528 529 bus_generic_detach(dev); 530 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 531 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 532 533 bus_dma_tag_destroy(sc->sc_dmat); 534 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 535 536 crit_exit(); 537 538 return (0); 539 } 540 541 /* 542 * Stop all chip i/o so that the kernel's probe routines don't 543 * get confused by errant DMAs when rebooting. 544 */ 545 static void 546 ubsec_shutdown(device_t dev) 547 { 548 #ifdef notyet 549 ubsec_stop(device_get_softc(dev)); 550 #endif 551 } 552 553 /* 554 * Device suspend routine. 555 */ 556 static int 557 ubsec_suspend(device_t dev) 558 { 559 struct ubsec_softc *sc = device_get_softc(dev); 560 561 KASSERT(sc != NULL, ("ubsec_suspend: null software carrier")); 562 #ifdef notyet 563 /* XXX stop the device and save PCI settings */ 564 #endif 565 sc->sc_suspended = 1; 566 567 return (0); 568 } 569 570 static int 571 ubsec_resume(device_t dev) 572 { 573 struct ubsec_softc *sc = device_get_softc(dev); 574 575 KASSERT(sc != NULL, ("ubsec_resume: null software carrier")); 576 #ifdef notyet 577 /* XXX retore PCI settings and start the device */ 578 #endif 579 sc->sc_suspended = 0; 580 return (0); 581 } 582 583 /* 584 * UBSEC Interrupt routine 585 */ 586 static void 587 ubsec_intr(void *arg) 588 { 589 struct ubsec_softc *sc = arg; 590 volatile u_int32_t stat; 591 struct ubsec_q *q; 592 struct ubsec_dma *dmap; 593 int npkts = 0, i; 594 595 stat = READ_REG(sc, BS_STAT); 596 stat &= sc->sc_statmask; 597 if (stat == 0) { 598 return; 599 } 600 601 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 602 603 /* 604 * Check to see if we have any packets waiting for us 605 */ 606 if ((stat & BS_STAT_MCR1_DONE)) { 607 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 608 q = SIMPLEQ_FIRST(&sc->sc_qchip); 609 dmap = q->q_dma; 610 611 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 612 break; 613 614 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); 615 616 npkts = q->q_nstacked_mcrs; 617 sc->sc_nqchip -= 1+npkts; 618 /* 619 * search for further sc_qchip ubsec_q's that share 620 * the same MCR, and complete them too, they must be 621 * at the top. 622 */ 623 for (i = 0; i < npkts; i++) { 624 if(q->q_stacked_mcr[i]) { 625 ubsec_callback(sc, q->q_stacked_mcr[i]); 626 } else { 627 break; 628 } 629 } 630 ubsec_callback(sc, q); 631 } 632 633 /* 634 * Don't send any more packet to chip if there has been 635 * a DMAERR. 636 */ 637 if (!(stat & BS_STAT_DMAERR)) 638 ubsec_feed(sc); 639 } 640 641 /* 642 * Check to see if we have any key setups/rng's waiting for us 643 */ 644 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 645 (stat & BS_STAT_MCR2_DONE)) { 646 struct ubsec_q2 *q2; 647 struct ubsec_mcr *mcr; 648 649 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 650 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 651 652 ubsec_dma_sync(&q2->q_mcr, 653 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 654 655 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 656 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 657 ubsec_dma_sync(&q2->q_mcr, 658 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 659 break; 660 } 661 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q_next); 662 ubsec_callback2(sc, q2); 663 /* 664 * Don't send any more packet to chip if there has been 665 * a DMAERR. 666 */ 667 if (!(stat & BS_STAT_DMAERR)) 668 ubsec_feed2(sc); 669 } 670 } 671 672 /* 673 * Check to see if we got any DMA Error 674 */ 675 if (stat & BS_STAT_DMAERR) { 676 #ifdef UBSEC_DEBUG 677 if (ubsec_debug) { 678 volatile u_int32_t a = READ_REG(sc, BS_ERR); 679 680 kprintf("dmaerr %s@%08x\n", 681 (a & BS_ERR_READ) ? "read" : "write", 682 a & BS_ERR_ADDR); 683 } 684 #endif /* UBSEC_DEBUG */ 685 ubsecstats.hst_dmaerr++; 686 ubsec_totalreset(sc); 687 ubsec_feed(sc); 688 } 689 690 if (sc->sc_needwakeup) { /* XXX check high watermark */ 691 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 692 #ifdef UBSEC_DEBUG 693 if (ubsec_debug) 694 device_printf(sc->sc_dev, "wakeup crypto (%x)\n", 695 sc->sc_needwakeup); 696 #endif /* UBSEC_DEBUG */ 697 sc->sc_needwakeup &= ~wakeup; 698 crypto_unblock(sc->sc_cid, wakeup); 699 } 700 } 701 702 /* 703 * ubsec_feed() - aggregate and post requests to chip 704 */ 705 static void 706 ubsec_feed(struct ubsec_softc *sc) 707 { 708 struct ubsec_q *q, *q2; 709 int npkts, i; 710 void *v; 711 u_int32_t stat; 712 713 /* 714 * Decide how many ops to combine in a single MCR. We cannot 715 * aggregate more than UBS_MAX_AGGR because this is the number 716 * of slots defined in the data structure. Note that 717 * aggregation only happens if ops are marked batch'able. 718 * Aggregating ops reduces the number of interrupts to the host 719 * but also (potentially) increases the latency for processing 720 * completed ops as we only get an interrupt when all aggregated 721 * ops have completed. 722 */ 723 if (sc->sc_nqueue == 0) 724 return; 725 if (sc->sc_nqueue > 1) { 726 npkts = 0; 727 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) { 728 npkts++; 729 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0) 730 break; 731 } 732 } else 733 npkts = 1; 734 /* 735 * Check device status before going any further. 736 */ 737 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 738 if (stat & BS_STAT_DMAERR) { 739 ubsec_totalreset(sc); 740 ubsecstats.hst_dmaerr++; 741 } else 742 ubsecstats.hst_mcr1full++; 743 return; 744 } 745 if (sc->sc_nqueue > ubsecstats.hst_maxqueue) 746 ubsecstats.hst_maxqueue = sc->sc_nqueue; 747 if (npkts > UBS_MAX_AGGR) 748 npkts = UBS_MAX_AGGR; 749 if (npkts < 2) /* special case 1 op */ 750 goto feed1; 751 752 ubsecstats.hst_totbatch += npkts-1; 753 #ifdef UBSEC_DEBUG 754 if (ubsec_debug) 755 kprintf("merging %d records\n", npkts); 756 #endif /* UBSEC_DEBUG */ 757 758 q = SIMPLEQ_FIRST(&sc->sc_queue); 759 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); 760 --sc->sc_nqueue; 761 762 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 763 if (q->q_dst_map != NULL) 764 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 765 766 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 767 768 for (i = 0; i < q->q_nstacked_mcrs; i++) { 769 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 770 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 771 BUS_DMASYNC_PREWRITE); 772 if (q2->q_dst_map != NULL) 773 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 774 BUS_DMASYNC_PREREAD); 775 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); 776 --sc->sc_nqueue; 777 778 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - 779 sizeof(struct ubsec_mcr_add)); 780 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 781 q->q_stacked_mcr[i] = q2; 782 } 783 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 784 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 785 sc->sc_nqchip += npkts; 786 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 787 ubsecstats.hst_maxqchip = sc->sc_nqchip; 788 ubsec_dma_sync(&q->q_dma->d_alloc, 789 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 790 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 791 offsetof(struct ubsec_dmachunk, d_mcr)); 792 return; 793 794 feed1: 795 q = SIMPLEQ_FIRST(&sc->sc_queue); 796 797 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 798 if (q->q_dst_map != NULL) 799 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 800 ubsec_dma_sync(&q->q_dma->d_alloc, 801 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 802 803 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 804 offsetof(struct ubsec_dmachunk, d_mcr)); 805 #ifdef UBSEC_DEBUG 806 if (ubsec_debug) 807 kprintf("feed1: q->chip %p %08x stat %08x\n", 808 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr), 809 stat); 810 #endif /* UBSEC_DEBUG */ 811 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); 812 --sc->sc_nqueue; 813 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 814 sc->sc_nqchip++; 815 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 816 ubsecstats.hst_maxqchip = sc->sc_nqchip; 817 return; 818 } 819 820 static void 821 ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key) 822 { 823 824 /* Go ahead and compute key in ubsec's byte order */ 825 if (algo == CRYPTO_DES_CBC) { 826 bcopy(key, &ses->ses_deskey[0], 8); 827 bcopy(key, &ses->ses_deskey[2], 8); 828 bcopy(key, &ses->ses_deskey[4], 8); 829 } else 830 bcopy(key, ses->ses_deskey, 24); 831 832 SWAP32(ses->ses_deskey[0]); 833 SWAP32(ses->ses_deskey[1]); 834 SWAP32(ses->ses_deskey[2]); 835 SWAP32(ses->ses_deskey[3]); 836 SWAP32(ses->ses_deskey[4]); 837 SWAP32(ses->ses_deskey[5]); 838 } 839 840 static void 841 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen) 842 { 843 MD5_CTX md5ctx; 844 SHA1_CTX sha1ctx; 845 int i; 846 847 for (i = 0; i < klen; i++) 848 key[i] ^= HMAC_IPAD_VAL; 849 850 if (algo == CRYPTO_MD5_HMAC) { 851 MD5Init(&md5ctx); 852 MD5Update(&md5ctx, key, klen); 853 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); 854 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state)); 855 } else { 856 SHA1Init(&sha1ctx); 857 SHA1Update(&sha1ctx, key, klen); 858 SHA1Update(&sha1ctx, hmac_ipad_buffer, 859 SHA1_HMAC_BLOCK_LEN - klen); 860 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); 861 } 862 863 for (i = 0; i < klen; i++) 864 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 865 866 if (algo == CRYPTO_MD5_HMAC) { 867 MD5Init(&md5ctx); 868 MD5Update(&md5ctx, key, klen); 869 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); 870 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state)); 871 } else { 872 SHA1Init(&sha1ctx); 873 SHA1Update(&sha1ctx, key, klen); 874 SHA1Update(&sha1ctx, hmac_opad_buffer, 875 SHA1_HMAC_BLOCK_LEN - klen); 876 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); 877 } 878 879 for (i = 0; i < klen; i++) 880 key[i] ^= HMAC_OPAD_VAL; 881 } 882 883 /* 884 * Allocate a new 'session' and return an encoded session id. 'sidp' 885 * contains our registration id, and should contain an encoded session 886 * id on successful allocation. 887 */ 888 static int 889 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 890 { 891 struct cryptoini *c, *encini = NULL, *macini = NULL; 892 struct ubsec_softc *sc = arg; 893 struct ubsec_session *ses = NULL; 894 int sesn; 895 #if 0 896 MD5_CTX md5ctx; 897 SHA1_CTX sha1ctx; 898 int i; 899 #endif 900 901 KASSERT(sc != NULL, ("ubsec_newsession: null softc")); 902 if (sidp == NULL || cri == NULL || sc == NULL) 903 return (EINVAL); 904 905 for (c = cri; c != NULL; c = c->cri_next) { 906 if (c->cri_alg == CRYPTO_MD5_HMAC || 907 c->cri_alg == CRYPTO_SHA1_HMAC) { 908 if (macini) 909 return (EINVAL); 910 macini = c; 911 } else if (c->cri_alg == CRYPTO_DES_CBC || 912 c->cri_alg == CRYPTO_3DES_CBC) { 913 if (encini) 914 return (EINVAL); 915 encini = c; 916 } else 917 return (EINVAL); 918 } 919 if (encini == NULL && macini == NULL) 920 return (EINVAL); 921 922 if (sc->sc_sessions == NULL) { 923 ses = sc->sc_sessions = kmalloc(sizeof(struct ubsec_session), 924 M_DEVBUF, M_INTWAIT); 925 sesn = 0; 926 sc->sc_nsessions = 1; 927 } else { 928 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 929 if (sc->sc_sessions[sesn].ses_used == 0) { 930 ses = &sc->sc_sessions[sesn]; 931 break; 932 } 933 } 934 935 if (ses == NULL) { 936 sesn = sc->sc_nsessions; 937 ses = kmalloc((sesn + 1) * sizeof(struct ubsec_session), 938 M_DEVBUF, M_INTWAIT); 939 bcopy(sc->sc_sessions, ses, sesn * 940 sizeof(struct ubsec_session)); 941 bzero(sc->sc_sessions, sesn * 942 sizeof(struct ubsec_session)); 943 kfree(sc->sc_sessions, M_DEVBUF); 944 sc->sc_sessions = ses; 945 ses = &sc->sc_sessions[sesn]; 946 sc->sc_nsessions++; 947 } 948 } 949 950 bzero(ses, sizeof(struct ubsec_session)); 951 ses->ses_used = 1; 952 if (encini) { 953 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 954 if (encini->cri_key != NULL) { 955 ubsec_setup_enckey(ses, encini->cri_alg, 956 encini->cri_key); 957 } 958 #if 0 959 /* get an IV, network byte order */ 960 /* XXX may read fewer than requested */ 961 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 962 963 /* Go ahead and compute key in ubsec's byte order */ 964 if (encini->cri_alg == CRYPTO_DES_CBC) { 965 bcopy(encini->cri_key, &ses->ses_deskey[0], 8); 966 bcopy(encini->cri_key, &ses->ses_deskey[2], 8); 967 bcopy(encini->cri_key, &ses->ses_deskey[4], 8); 968 } else 969 bcopy(encini->cri_key, ses->ses_deskey, 24); 970 971 SWAP32(ses->ses_deskey[0]); 972 SWAP32(ses->ses_deskey[1]); 973 SWAP32(ses->ses_deskey[2]); 974 SWAP32(ses->ses_deskey[3]); 975 SWAP32(ses->ses_deskey[4]); 976 SWAP32(ses->ses_deskey[5]); 977 #endif 978 } 979 980 if (macini) { 981 ses->ses_mlen = macini->cri_mlen; 982 if (ses->ses_mlen == 0) { 983 if (macini->cri_alg == CRYPTO_MD5_HMAC) 984 ses->ses_mlen = MD5_HASH_LEN; 985 else 986 ses->ses_mlen = SHA1_HASH_LEN; 987 } 988 989 if (macini->cri_key != NULL) { 990 ubsec_setup_mackey(ses, macini->cri_alg, 991 macini->cri_key, macini->cri_klen/8); 992 } 993 #if 0 994 for (i = 0; i < macini->cri_klen / 8; i++) 995 macini->cri_key[i] ^= HMAC_IPAD_VAL; 996 997 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 998 MD5Init(&md5ctx); 999 MD5Update(&md5ctx, macini->cri_key, 1000 macini->cri_klen / 8); 1001 MD5Update(&md5ctx, hmac_ipad_buffer, 1002 MD5_HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1003 bcopy(md5ctx.state, ses->ses_hminner, 1004 sizeof(md5ctx.state)); 1005 } else { 1006 SHA1Init(&sha1ctx); 1007 SHA1Update(&sha1ctx, macini->cri_key, 1008 macini->cri_klen / 8); 1009 SHA1Update(&sha1ctx, hmac_ipad_buffer, 1010 SHA1_HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1011 bcopy(sha1ctx.h.b32, ses->ses_hminner, 1012 sizeof(sha1ctx.h.b32)); 1013 } 1014 1015 for (i = 0; i < macini->cri_klen / 8; i++) 1016 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 1017 1018 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 1019 MD5Init(&md5ctx); 1020 MD5Update(&md5ctx, macini->cri_key, 1021 macini->cri_klen / 8); 1022 MD5Update(&md5ctx, hmac_opad_buffer, 1023 MD5_HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1024 bcopy(md5ctx.state, ses->ses_hmouter, 1025 sizeof(md5ctx.state)); 1026 } else { 1027 SHA1Init(&sha1ctx); 1028 SHA1Update(&sha1ctx, macini->cri_key, 1029 macini->cri_klen / 8); 1030 SHA1Update(&sha1ctx, hmac_opad_buffer, 1031 SHA1_HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 1032 bcopy(sha1ctx.h.b32, ses->ses_hmouter, 1033 sizeof(sha1ctx.h.b32)); 1034 } 1035 1036 for (i = 0; i < macini->cri_klen / 8; i++) 1037 macini->cri_key[i] ^= HMAC_OPAD_VAL; 1038 #endif 1039 } 1040 1041 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); 1042 return (0); 1043 } 1044 1045 /* 1046 * Deallocate a session. 1047 */ 1048 static int 1049 ubsec_freesession(void *arg, u_int64_t tid) 1050 { 1051 struct ubsec_softc *sc = arg; 1052 int session; 1053 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 1054 1055 KASSERT(sc != NULL, ("ubsec_freesession: null softc")); 1056 if (sc == NULL) 1057 return (EINVAL); 1058 1059 session = UBSEC_SESSION(sid); 1060 if (session >= sc->sc_nsessions) 1061 return (EINVAL); 1062 1063 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 1064 return (0); 1065 } 1066 1067 static void 1068 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1069 { 1070 struct ubsec_operand *op = arg; 1071 1072 KASSERT(nsegs <= UBS_MAX_SCATTER, 1073 ("Too many DMA segments returned when mapping operand")); 1074 #ifdef UBSEC_DEBUG 1075 if (ubsec_debug) 1076 kprintf("ubsec_op_cb: mapsize %u nsegs %d\n", 1077 (u_int) mapsize, nsegs); 1078 #endif 1079 op->mapsize = mapsize; 1080 op->nsegs = nsegs; 1081 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1082 } 1083 1084 static int 1085 ubsec_process(void *arg, struct cryptop *crp, int hint) 1086 { 1087 struct ubsec_q *q = NULL; 1088 int err = 0, i, j, nicealign; 1089 struct ubsec_softc *sc = arg; 1090 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1091 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1092 int sskip, dskip, stheend, dtheend; 1093 int16_t coffset; 1094 struct ubsec_session *ses; 1095 struct ubsec_pktctx ctx; 1096 struct ubsec_dma *dmap = NULL; 1097 1098 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1099 ubsecstats.hst_invalid++; 1100 return (EINVAL); 1101 } 1102 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1103 ubsecstats.hst_badsession++; 1104 return (EINVAL); 1105 } 1106 1107 crit_enter(); 1108 1109 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1110 ubsecstats.hst_queuefull++; 1111 sc->sc_needwakeup |= CRYPTO_SYMQ; 1112 crit_exit(); 1113 return (ERESTART); 1114 } 1115 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1116 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next); 1117 crit_exit(); 1118 1119 dmap = q->q_dma; /* Save dma pointer */ 1120 bzero(q, sizeof(struct ubsec_q)); 1121 bzero(&ctx, sizeof(ctx)); 1122 1123 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1124 q->q_dma = dmap; 1125 ses = &sc->sc_sessions[q->q_sesn]; 1126 1127 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1128 q->q_src_m = (struct mbuf *)crp->crp_buf; 1129 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1130 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1131 q->q_src_io = (struct uio *)crp->crp_buf; 1132 q->q_dst_io = (struct uio *)crp->crp_buf; 1133 } else { 1134 ubsecstats.hst_badflags++; 1135 err = EINVAL; 1136 goto errout; /* XXX we don't handle contiguous blocks! */ 1137 } 1138 1139 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 1140 1141 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1142 dmap->d_dma->d_mcr.mcr_flags = 0; 1143 q->q_crp = crp; 1144 1145 crd1 = crp->crp_desc; 1146 if (crd1 == NULL) { 1147 ubsecstats.hst_nodesc++; 1148 err = EINVAL; 1149 goto errout; 1150 } 1151 crd2 = crd1->crd_next; 1152 1153 if (crd2 == NULL) { 1154 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1155 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1156 maccrd = crd1; 1157 enccrd = NULL; 1158 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1159 crd1->crd_alg == CRYPTO_3DES_CBC) { 1160 maccrd = NULL; 1161 enccrd = crd1; 1162 } else { 1163 ubsecstats.hst_badalg++; 1164 err = EINVAL; 1165 goto errout; 1166 } 1167 } else { 1168 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1169 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1170 (crd2->crd_alg == CRYPTO_DES_CBC || 1171 crd2->crd_alg == CRYPTO_3DES_CBC) && 1172 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1173 maccrd = crd1; 1174 enccrd = crd2; 1175 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1176 crd1->crd_alg == CRYPTO_3DES_CBC) && 1177 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1178 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1179 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1180 enccrd = crd1; 1181 maccrd = crd2; 1182 } else { 1183 /* 1184 * We cannot order the ubsec as requested 1185 */ 1186 ubsecstats.hst_badalg++; 1187 err = EINVAL; 1188 goto errout; 1189 } 1190 } 1191 1192 if (enccrd) { 1193 encoffset = enccrd->crd_skip; 1194 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1195 1196 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1197 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1198 1199 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1200 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1201 else { 1202 ctx.pc_iv[0] = ses->ses_iv[0]; 1203 ctx.pc_iv[1] = ses->ses_iv[1]; 1204 } 1205 1206 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1207 if (crp->crp_flags & CRYPTO_F_IMBUF) 1208 m_copyback(q->q_src_m, 1209 enccrd->crd_inject, 1210 8, (caddr_t)ctx.pc_iv); 1211 else if (crp->crp_flags & CRYPTO_F_IOV) 1212 cuio_copyback(q->q_src_io, 1213 enccrd->crd_inject, 1214 8, (caddr_t)ctx.pc_iv); 1215 } 1216 } else { 1217 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1218 1219 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1220 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1221 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1222 m_copydata(q->q_src_m, enccrd->crd_inject, 1223 8, (caddr_t)ctx.pc_iv); 1224 else if (crp->crp_flags & CRYPTO_F_IOV) 1225 cuio_copydata(q->q_src_io, 1226 enccrd->crd_inject, 8, 1227 (caddr_t)ctx.pc_iv); 1228 } 1229 1230 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1231 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1232 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1233 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1234 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1235 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1236 SWAP32(ctx.pc_iv[0]); 1237 SWAP32(ctx.pc_iv[1]); 1238 } 1239 1240 if (maccrd) { 1241 macoffset = maccrd->crd_skip; 1242 1243 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1244 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1245 else 1246 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1247 1248 for (i = 0; i < 5; i++) { 1249 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1250 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1251 1252 HTOLE32(ctx.pc_hminner[i]); 1253 HTOLE32(ctx.pc_hmouter[i]); 1254 } 1255 } 1256 1257 if (enccrd && maccrd) { 1258 /* 1259 * ubsec cannot handle packets where the end of encryption 1260 * and authentication are not the same, or where the 1261 * encrypted part begins before the authenticated part. 1262 */ 1263 if ((encoffset + enccrd->crd_len) != 1264 (macoffset + maccrd->crd_len)) { 1265 ubsecstats.hst_lenmismatch++; 1266 err = EINVAL; 1267 goto errout; 1268 } 1269 if (enccrd->crd_skip < maccrd->crd_skip) { 1270 ubsecstats.hst_skipmismatch++; 1271 err = EINVAL; 1272 goto errout; 1273 } 1274 sskip = maccrd->crd_skip; 1275 cpskip = dskip = enccrd->crd_skip; 1276 stheend = maccrd->crd_len; 1277 dtheend = enccrd->crd_len; 1278 coffset = enccrd->crd_skip - maccrd->crd_skip; 1279 cpoffset = cpskip + dtheend; 1280 #ifdef UBSEC_DEBUG 1281 if (ubsec_debug) { 1282 kprintf("mac: skip %d, len %d, inject %d\n", 1283 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1284 kprintf("enc: skip %d, len %d, inject %d\n", 1285 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1286 kprintf("src: skip %d, len %d\n", sskip, stheend); 1287 kprintf("dst: skip %d, len %d\n", dskip, dtheend); 1288 kprintf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1289 coffset, stheend, cpskip, cpoffset); 1290 } 1291 #endif 1292 } else { 1293 cpskip = dskip = sskip = macoffset + encoffset; 1294 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1295 cpoffset = cpskip + dtheend; 1296 coffset = 0; 1297 } 1298 ctx.pc_offset = htole16(coffset >> 2); 1299 1300 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) { 1301 ubsecstats.hst_nomap++; 1302 err = ENOMEM; 1303 goto errout; 1304 } 1305 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1306 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1307 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1308 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1309 q->q_src_map = NULL; 1310 ubsecstats.hst_noload++; 1311 err = ENOMEM; 1312 goto errout; 1313 } 1314 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1315 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1316 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1317 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1318 q->q_src_map = NULL; 1319 ubsecstats.hst_noload++; 1320 err = ENOMEM; 1321 goto errout; 1322 } 1323 } 1324 nicealign = ubsec_dmamap_aligned(&q->q_src); 1325 1326 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1327 1328 #ifdef UBSEC_DEBUG 1329 if (ubsec_debug) 1330 kprintf("src skip: %d nicealign: %u\n", sskip, nicealign); 1331 #endif 1332 for (i = j = 0; i < q->q_src_nsegs; i++) { 1333 struct ubsec_pktbuf *pb; 1334 bus_size_t packl = q->q_src_segs[i].ds_len; 1335 bus_addr_t packp = q->q_src_segs[i].ds_addr; 1336 1337 if (sskip >= packl) { 1338 sskip -= packl; 1339 continue; 1340 } 1341 1342 packl -= sskip; 1343 packp += sskip; 1344 sskip = 0; 1345 1346 if (packl > 0xfffc) { 1347 err = EIO; 1348 goto errout; 1349 } 1350 1351 if (j == 0) 1352 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1353 else 1354 pb = &dmap->d_dma->d_sbuf[j - 1]; 1355 1356 pb->pb_addr = htole32(packp); 1357 1358 if (stheend) { 1359 if (packl > stheend) { 1360 pb->pb_len = htole32(stheend); 1361 stheend = 0; 1362 } else { 1363 pb->pb_len = htole32(packl); 1364 stheend -= packl; 1365 } 1366 } else 1367 pb->pb_len = htole32(packl); 1368 1369 if ((i + 1) == q->q_src_nsegs) 1370 pb->pb_next = 0; 1371 else 1372 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1373 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1374 j++; 1375 } 1376 1377 if (enccrd == NULL && maccrd != NULL) { 1378 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1379 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1380 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1381 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1382 #ifdef UBSEC_DEBUG 1383 if (ubsec_debug) 1384 kprintf("opkt: %x %x %x\n", 1385 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1386 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1387 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1388 #endif 1389 } else { 1390 if (crp->crp_flags & CRYPTO_F_IOV) { 1391 if (!nicealign) { 1392 ubsecstats.hst_iovmisaligned++; 1393 err = EINVAL; 1394 goto errout; 1395 } 1396 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1397 &q->q_dst_map)) { 1398 ubsecstats.hst_nomap++; 1399 err = ENOMEM; 1400 goto errout; 1401 } 1402 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1403 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) { 1404 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1405 q->q_dst_map = NULL; 1406 ubsecstats.hst_noload++; 1407 err = ENOMEM; 1408 goto errout; 1409 } 1410 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1411 if (nicealign) { 1412 q->q_dst = q->q_src; 1413 } else { 1414 int totlen, len; 1415 struct mbuf *m, *top, **mp; 1416 1417 ubsecstats.hst_unaligned++; 1418 totlen = q->q_src_mapsize; 1419 if (q->q_src_m->m_flags & M_PKTHDR) { 1420 len = MHLEN; 1421 MGETHDR(m, MB_DONTWAIT, MT_DATA); 1422 if (m && !m_dup_pkthdr(m, q->q_src_m, MB_DONTWAIT)) { 1423 m_free(m); 1424 m = NULL; 1425 } 1426 } else { 1427 len = MLEN; 1428 MGET(m, MB_DONTWAIT, MT_DATA); 1429 } 1430 if (m == NULL) { 1431 ubsecstats.hst_nombuf++; 1432 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1433 goto errout; 1434 } 1435 if (totlen >= MINCLSIZE) { 1436 MCLGET(m, MB_DONTWAIT); 1437 if ((m->m_flags & M_EXT) == 0) { 1438 m_free(m); 1439 ubsecstats.hst_nomcl++; 1440 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1441 goto errout; 1442 } 1443 len = MCLBYTES; 1444 } 1445 m->m_len = len; 1446 top = NULL; 1447 mp = ⊤ 1448 1449 while (totlen > 0) { 1450 if (top) { 1451 MGET(m, MB_DONTWAIT, MT_DATA); 1452 if (m == NULL) { 1453 m_freem(top); 1454 ubsecstats.hst_nombuf++; 1455 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1456 goto errout; 1457 } 1458 len = MLEN; 1459 } 1460 if (top && totlen >= MINCLSIZE) { 1461 MCLGET(m, MB_DONTWAIT); 1462 if ((m->m_flags & M_EXT) == 0) { 1463 *mp = m; 1464 m_freem(top); 1465 ubsecstats.hst_nomcl++; 1466 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1467 goto errout; 1468 } 1469 len = MCLBYTES; 1470 } 1471 m->m_len = len = min(totlen, len); 1472 totlen -= len; 1473 *mp = m; 1474 mp = &m->m_next; 1475 } 1476 q->q_dst_m = top; 1477 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1478 cpskip, cpoffset); 1479 if (bus_dmamap_create(sc->sc_dmat, 1480 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) { 1481 ubsecstats.hst_nomap++; 1482 err = ENOMEM; 1483 goto errout; 1484 } 1485 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1486 q->q_dst_map, q->q_dst_m, 1487 ubsec_op_cb, &q->q_dst, 1488 BUS_DMA_NOWAIT) != 0) { 1489 bus_dmamap_destroy(sc->sc_dmat, 1490 q->q_dst_map); 1491 q->q_dst_map = NULL; 1492 ubsecstats.hst_noload++; 1493 err = ENOMEM; 1494 goto errout; 1495 } 1496 } 1497 } else { 1498 ubsecstats.hst_badflags++; 1499 err = EINVAL; 1500 goto errout; 1501 } 1502 1503 #ifdef UBSEC_DEBUG 1504 if (ubsec_debug) 1505 kprintf("dst skip: %d\n", dskip); 1506 #endif 1507 for (i = j = 0; i < q->q_dst_nsegs; i++) { 1508 struct ubsec_pktbuf *pb; 1509 bus_size_t packl = q->q_dst_segs[i].ds_len; 1510 bus_addr_t packp = q->q_dst_segs[i].ds_addr; 1511 1512 if (dskip >= packl) { 1513 dskip -= packl; 1514 continue; 1515 } 1516 1517 packl -= dskip; 1518 packp += dskip; 1519 dskip = 0; 1520 1521 if (packl > 0xfffc) { 1522 err = EIO; 1523 goto errout; 1524 } 1525 1526 if (j == 0) 1527 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1528 else 1529 pb = &dmap->d_dma->d_dbuf[j - 1]; 1530 1531 pb->pb_addr = htole32(packp); 1532 1533 if (dtheend) { 1534 if (packl > dtheend) { 1535 pb->pb_len = htole32(dtheend); 1536 dtheend = 0; 1537 } else { 1538 pb->pb_len = htole32(packl); 1539 dtheend -= packl; 1540 } 1541 } else 1542 pb->pb_len = htole32(packl); 1543 1544 if ((i + 1) == q->q_dst_nsegs) { 1545 if (maccrd) 1546 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1547 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1548 else 1549 pb->pb_next = 0; 1550 } else 1551 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1552 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1553 j++; 1554 } 1555 } 1556 1557 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1558 offsetof(struct ubsec_dmachunk, d_ctx)); 1559 1560 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1561 struct ubsec_pktctx_long *ctxl; 1562 1563 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1564 offsetof(struct ubsec_dmachunk, d_ctx)); 1565 1566 /* transform small context into long context */ 1567 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1568 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1569 ctxl->pc_flags = ctx.pc_flags; 1570 ctxl->pc_offset = ctx.pc_offset; 1571 for (i = 0; i < 6; i++) 1572 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1573 for (i = 0; i < 5; i++) 1574 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1575 for (i = 0; i < 5; i++) 1576 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1577 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1578 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1579 } else 1580 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1581 offsetof(struct ubsec_dmachunk, d_ctx), 1582 sizeof(struct ubsec_pktctx)); 1583 1584 crit_enter(); 1585 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1586 sc->sc_nqueue++; 1587 ubsecstats.hst_ipackets++; 1588 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size; 1589 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR) 1590 ubsec_feed(sc); 1591 crit_exit(); 1592 return (0); 1593 1594 errout: 1595 if (q != NULL) { 1596 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1597 m_freem(q->q_dst_m); 1598 1599 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1600 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1601 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1602 } 1603 if (q->q_src_map != NULL) { 1604 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1605 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1606 } 1607 1608 crit_enter(); 1609 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1610 crit_exit(); 1611 } 1612 if (err != ERESTART) { 1613 crp->crp_etype = err; 1614 crypto_done(crp); 1615 } else { 1616 sc->sc_needwakeup |= CRYPTO_SYMQ; 1617 } 1618 return (err); 1619 } 1620 1621 static void 1622 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1623 { 1624 struct cryptop *crp = (struct cryptop *)q->q_crp; 1625 struct cryptodesc *crd; 1626 struct ubsec_dma *dmap = q->q_dma; 1627 1628 ubsecstats.hst_opackets++; 1629 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1630 1631 ubsec_dma_sync(&dmap->d_alloc, 1632 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1633 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1634 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1635 BUS_DMASYNC_POSTREAD); 1636 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1637 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1638 } 1639 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE); 1640 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1641 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1642 1643 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1644 m_freem(q->q_src_m); 1645 crp->crp_buf = (caddr_t)q->q_dst_m; 1646 } 1647 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len; 1648 1649 /* copy out IV for future use */ 1650 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1651 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1652 if (crd->crd_alg != CRYPTO_DES_CBC && 1653 crd->crd_alg != CRYPTO_3DES_CBC) 1654 continue; 1655 if (crp->crp_flags & CRYPTO_F_IMBUF) 1656 m_copydata((struct mbuf *)crp->crp_buf, 1657 crd->crd_skip + crd->crd_len - 8, 8, 1658 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1659 else if (crp->crp_flags & CRYPTO_F_IOV) { 1660 cuio_copydata((struct uio *)crp->crp_buf, 1661 crd->crd_skip + crd->crd_len - 8, 8, 1662 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1663 } 1664 break; 1665 } 1666 } 1667 1668 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1669 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1670 crd->crd_alg != CRYPTO_SHA1_HMAC) 1671 continue; 1672 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, 1673 sc->sc_sessions[q->q_sesn].ses_mlen, 1674 (caddr_t)dmap->d_dma->d_macbuf); 1675 #if 0 1676 if (crp->crp_flags & CRYPTO_F_IMBUF) 1677 m_copyback((struct mbuf *)crp->crp_buf, 1678 crd->crd_inject, 12, 1679 (caddr_t)dmap->d_dma->d_macbuf); 1680 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1681 bcopy((caddr_t)dmap->d_dma->d_macbuf, 1682 crp->crp_mac, 12); 1683 break; 1684 #endif 1685 } 1686 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1687 crypto_done(crp); 1688 } 1689 1690 static void 1691 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1692 { 1693 int i, j, dlen, slen; 1694 caddr_t dptr, sptr; 1695 1696 j = 0; 1697 sptr = srcm->m_data; 1698 slen = srcm->m_len; 1699 dptr = dstm->m_data; 1700 dlen = dstm->m_len; 1701 1702 while (1) { 1703 for (i = 0; i < min(slen, dlen); i++) { 1704 if (j < hoffset || j >= toffset) 1705 *dptr++ = *sptr++; 1706 slen--; 1707 dlen--; 1708 j++; 1709 } 1710 if (slen == 0) { 1711 srcm = srcm->m_next; 1712 if (srcm == NULL) 1713 return; 1714 sptr = srcm->m_data; 1715 slen = srcm->m_len; 1716 } 1717 if (dlen == 0) { 1718 dstm = dstm->m_next; 1719 if (dstm == NULL) 1720 return; 1721 dptr = dstm->m_data; 1722 dlen = dstm->m_len; 1723 } 1724 } 1725 } 1726 1727 /* 1728 * feed the key generator, must be called at splimp() or higher. 1729 */ 1730 static int 1731 ubsec_feed2(struct ubsec_softc *sc) 1732 { 1733 struct ubsec_q2 *q; 1734 1735 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1736 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1737 break; 1738 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1739 1740 ubsec_dma_sync(&q->q_mcr, 1741 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1742 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE); 1743 1744 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1745 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q_next); 1746 --sc->sc_nqueue2; 1747 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1748 } 1749 return (0); 1750 } 1751 1752 /* 1753 * Callback for handling random numbers 1754 */ 1755 static void 1756 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1757 { 1758 struct cryptkop *krp; 1759 struct ubsec_ctx_keyop *ctx; 1760 1761 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1762 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE); 1763 1764 switch (q->q_type) { 1765 #ifndef UBSEC_NO_RNG 1766 case UBS_CTXOP_RNGBYPASS: { 1767 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1768 1769 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD); 1770 (*sc->sc_harvest)(sc->sc_rndtest, 1771 rng->rng_buf.dma_vaddr, 1772 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t)); 1773 rng->rng_used = 0; 1774 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1775 break; 1776 } 1777 #endif 1778 case UBS_CTXOP_MODEXP: { 1779 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1780 u_int rlen, clen; 1781 1782 krp = me->me_krp; 1783 rlen = (me->me_modbits + 7) / 8; 1784 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1785 1786 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE); 1787 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE); 1788 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD); 1789 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE); 1790 1791 if (clen < rlen) 1792 krp->krp_status = E2BIG; 1793 else { 1794 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1795 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1796 (krp->krp_param[krp->krp_iparams].crp_nbits 1797 + 7) / 8); 1798 bcopy(me->me_C.dma_vaddr, 1799 krp->krp_param[krp->krp_iparams].crp_p, 1800 (me->me_modbits + 7) / 8); 1801 } else 1802 ubsec_kshift_l(me->me_shiftbits, 1803 me->me_C.dma_vaddr, me->me_normbits, 1804 krp->krp_param[krp->krp_iparams].crp_p, 1805 krp->krp_param[krp->krp_iparams].crp_nbits); 1806 } 1807 1808 crypto_kdone(krp); 1809 1810 /* bzero all potentially sensitive data */ 1811 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1812 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1813 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1814 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1815 1816 /* Can't free here, so put us on the free list. */ 1817 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1818 break; 1819 } 1820 case UBS_CTXOP_RSAPRIV: { 1821 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1822 u_int len; 1823 1824 krp = rp->rpr_krp; 1825 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE); 1826 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD); 1827 1828 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1829 bcopy(rp->rpr_msgout.dma_vaddr, 1830 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1831 1832 crypto_kdone(krp); 1833 1834 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1835 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1836 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1837 1838 /* Can't free here, so put us on the free list. */ 1839 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1840 break; 1841 } 1842 default: 1843 device_printf(sc->sc_dev, "unknown ctx op: %x\n", 1844 letoh16(ctx->ctx_op)); 1845 break; 1846 } 1847 } 1848 1849 #ifndef UBSEC_NO_RNG 1850 static void 1851 ubsec_rng(void *vsc) 1852 { 1853 struct ubsec_softc *sc = vsc; 1854 struct ubsec_q2_rng *rng = &sc->sc_rng; 1855 struct ubsec_mcr *mcr; 1856 struct ubsec_ctx_rngbypass *ctx; 1857 1858 crit_enter(); 1859 if (rng->rng_used) { 1860 crit_exit(); 1861 return; 1862 } 1863 sc->sc_nqueue2++; 1864 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1865 goto out; 1866 1867 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1868 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1869 1870 mcr->mcr_pkts = htole16(1); 1871 mcr->mcr_flags = 0; 1872 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1873 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1874 mcr->mcr_ipktbuf.pb_len = 0; 1875 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1876 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1877 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1878 UBS_PKTBUF_LEN); 1879 mcr->mcr_opktbuf.pb_next = 0; 1880 1881 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1882 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS); 1883 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS; 1884 1885 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD); 1886 1887 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1888 rng->rng_used = 1; 1889 ubsec_feed2(sc); 1890 ubsecstats.hst_rng++; 1891 crit_exit(); 1892 1893 return; 1894 1895 out: 1896 /* 1897 * Something weird happened, generate our own call back. 1898 */ 1899 sc->sc_nqueue2--; 1900 crit_exit(); 1901 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1902 } 1903 #endif /* UBSEC_NO_RNG */ 1904 1905 static void 1906 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1907 { 1908 bus_addr_t *paddr = (bus_addr_t*) arg; 1909 *paddr = segs->ds_addr; 1910 } 1911 1912 static int 1913 ubsec_dma_malloc( 1914 struct ubsec_softc *sc, 1915 bus_size_t size, 1916 struct ubsec_dma_alloc *dma, 1917 int mapflags 1918 ) 1919 { 1920 int r; 1921 1922 /* XXX could specify sc_dmat as parent but that just adds overhead */ 1923 r = bus_dma_tag_create(NULL, /* parent */ 1924 1, 0, /* alignment, bounds */ 1925 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1926 BUS_SPACE_MAXADDR, /* highaddr */ 1927 NULL, NULL, /* filter, filterarg */ 1928 size, /* maxsize */ 1929 1, /* nsegments */ 1930 size, /* maxsegsize */ 1931 BUS_DMA_ALLOCNOW, /* flags */ 1932 &dma->dma_tag); 1933 if (r != 0) { 1934 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1935 "bus_dma_tag_create failed; error %u\n", r); 1936 goto fail_0; 1937 } 1938 1939 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1940 if (r != 0) { 1941 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1942 "bus_dmamap_create failed; error %u\n", r); 1943 goto fail_1; 1944 } 1945 1946 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1947 BUS_DMA_NOWAIT, &dma->dma_map); 1948 if (r != 0) { 1949 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1950 "bus_dmammem_alloc failed; size %ju, error %u\n", 1951 (intmax_t)size, r); 1952 goto fail_2; 1953 } 1954 1955 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1956 size, 1957 ubsec_dmamap_cb, 1958 &dma->dma_paddr, 1959 mapflags | BUS_DMA_NOWAIT); 1960 if (r != 0) { 1961 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1962 "bus_dmamap_load failed; error %u\n", r); 1963 goto fail_3; 1964 } 1965 1966 dma->dma_size = size; 1967 return (0); 1968 1969 fail_3: 1970 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1971 fail_2: 1972 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1973 fail_1: 1974 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1975 bus_dma_tag_destroy(dma->dma_tag); 1976 fail_0: 1977 dma->dma_map = NULL; 1978 dma->dma_tag = NULL; 1979 return (r); 1980 } 1981 1982 static void 1983 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1984 { 1985 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1986 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1987 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1988 bus_dma_tag_destroy(dma->dma_tag); 1989 } 1990 1991 /* 1992 * Resets the board. Values in the regesters are left as is 1993 * from the reset (i.e. initial values are assigned elsewhere). 1994 */ 1995 static void 1996 ubsec_reset_board(struct ubsec_softc *sc) 1997 { 1998 volatile u_int32_t ctrl; 1999 2000 ctrl = READ_REG(sc, BS_CTRL); 2001 ctrl |= BS_CTRL_RESET; 2002 WRITE_REG(sc, BS_CTRL, ctrl); 2003 2004 /* 2005 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 2006 */ 2007 DELAY(10); 2008 } 2009 2010 /* 2011 * Init Broadcom registers 2012 */ 2013 static void 2014 ubsec_init_board(struct ubsec_softc *sc) 2015 { 2016 u_int32_t ctrl; 2017 2018 ctrl = READ_REG(sc, BS_CTRL); 2019 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 2020 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 2021 2022 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) 2023 ctrl |= BS_CTRL_MCR2INT; 2024 else 2025 ctrl &= ~BS_CTRL_MCR2INT; 2026 2027 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2028 ctrl &= ~BS_CTRL_SWNORM; 2029 2030 WRITE_REG(sc, BS_CTRL, ctrl); 2031 } 2032 2033 /* 2034 * Init Broadcom PCI registers 2035 */ 2036 static void 2037 ubsec_init_pciregs(device_t dev) 2038 { 2039 #if 0 2040 u_int32_t misc; 2041 2042 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT); 2043 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT)) 2044 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT); 2045 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT)) 2046 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT); 2047 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc); 2048 #endif 2049 2050 /* 2051 * This will set the cache line size to 1, this will 2052 * force the BCM58xx chip just to do burst read/writes. 2053 * Cache line read/writes are to slow 2054 */ 2055 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1); 2056 } 2057 2058 /* 2059 * Clean up after a chip crash. 2060 * It is assumed that the caller in splimp() 2061 */ 2062 static void 2063 ubsec_cleanchip(struct ubsec_softc *sc) 2064 { 2065 struct ubsec_q *q; 2066 2067 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 2068 q = SIMPLEQ_FIRST(&sc->sc_qchip); 2069 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); 2070 ubsec_free_q(sc, q); 2071 } 2072 sc->sc_nqchip = 0; 2073 } 2074 2075 /* 2076 * free a ubsec_q 2077 * It is assumed that the caller is within spimp() 2078 */ 2079 static int 2080 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2081 { 2082 struct ubsec_q *q2; 2083 struct cryptop *crp; 2084 int npkts; 2085 int i; 2086 2087 npkts = q->q_nstacked_mcrs; 2088 2089 for (i = 0; i < npkts; i++) { 2090 if(q->q_stacked_mcr[i]) { 2091 q2 = q->q_stacked_mcr[i]; 2092 2093 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 2094 m_freem(q2->q_dst_m); 2095 2096 crp = (struct cryptop *)q2->q_crp; 2097 2098 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2099 2100 crp->crp_etype = EFAULT; 2101 crypto_done(crp); 2102 } else { 2103 break; 2104 } 2105 } 2106 2107 /* 2108 * Free header MCR 2109 */ 2110 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2111 m_freem(q->q_dst_m); 2112 2113 crp = (struct cryptop *)q->q_crp; 2114 2115 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2116 2117 crp->crp_etype = EFAULT; 2118 crypto_done(crp); 2119 return(0); 2120 } 2121 2122 /* 2123 * Routine to reset the chip and clean up. 2124 * It is assumed that the caller is in splimp() 2125 */ 2126 static void 2127 ubsec_totalreset(struct ubsec_softc *sc) 2128 { 2129 ubsec_reset_board(sc); 2130 ubsec_init_board(sc); 2131 ubsec_cleanchip(sc); 2132 } 2133 2134 static int 2135 ubsec_dmamap_aligned(struct ubsec_operand *op) 2136 { 2137 int i; 2138 2139 for (i = 0; i < op->nsegs; i++) { 2140 if (op->segs[i].ds_addr & 3) 2141 return (0); 2142 if ((i != (op->nsegs - 1)) && 2143 (op->segs[i].ds_len & 3)) 2144 return (0); 2145 } 2146 return (1); 2147 } 2148 2149 static void 2150 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2151 { 2152 switch (q->q_type) { 2153 case UBS_CTXOP_MODEXP: { 2154 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2155 2156 ubsec_dma_free(sc, &me->me_q.q_mcr); 2157 ubsec_dma_free(sc, &me->me_q.q_ctx); 2158 ubsec_dma_free(sc, &me->me_M); 2159 ubsec_dma_free(sc, &me->me_E); 2160 ubsec_dma_free(sc, &me->me_C); 2161 ubsec_dma_free(sc, &me->me_epb); 2162 kfree(me, M_DEVBUF); 2163 break; 2164 } 2165 case UBS_CTXOP_RSAPRIV: { 2166 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2167 2168 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2169 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2170 ubsec_dma_free(sc, &rp->rpr_msgin); 2171 ubsec_dma_free(sc, &rp->rpr_msgout); 2172 kfree(rp, M_DEVBUF); 2173 break; 2174 } 2175 default: 2176 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type); 2177 break; 2178 } 2179 } 2180 2181 static int 2182 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2183 { 2184 struct ubsec_softc *sc = arg; 2185 int r; 2186 2187 if (krp == NULL || krp->krp_callback == NULL) 2188 return (EINVAL); 2189 2190 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2191 struct ubsec_q2 *q; 2192 2193 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2194 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q_next); 2195 ubsec_kfree(sc, q); 2196 } 2197 2198 switch (krp->krp_op) { 2199 case CRK_MOD_EXP: 2200 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2201 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2202 else 2203 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2204 break; 2205 case CRK_MOD_EXP_CRT: 2206 return (ubsec_kprocess_rsapriv(sc, krp, hint)); 2207 default: 2208 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n", 2209 krp->krp_op); 2210 krp->krp_status = EOPNOTSUPP; 2211 crypto_kdone(krp); 2212 return (0); 2213 } 2214 return (0); /* silence compiler */ 2215 } 2216 2217 /* 2218 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2219 */ 2220 static int 2221 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2222 { 2223 struct ubsec_q2_modexp *me; 2224 struct ubsec_mcr *mcr; 2225 struct ubsec_ctx_modexp *ctx; 2226 struct ubsec_pktbuf *epb; 2227 int err = 0; 2228 u_int nbits, normbits, mbits, shiftbits, ebits; 2229 2230 me = kmalloc(sizeof *me, M_DEVBUF, M_INTWAIT | M_ZERO); 2231 me->me_krp = krp; 2232 me->me_q.q_type = UBS_CTXOP_MODEXP; 2233 2234 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2235 if (nbits <= 512) 2236 normbits = 512; 2237 else if (nbits <= 768) 2238 normbits = 768; 2239 else if (nbits <= 1024) 2240 normbits = 1024; 2241 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2242 normbits = 1536; 2243 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2244 normbits = 2048; 2245 else { 2246 err = E2BIG; 2247 goto errout; 2248 } 2249 2250 shiftbits = normbits - nbits; 2251 2252 me->me_modbits = nbits; 2253 me->me_shiftbits = shiftbits; 2254 me->me_normbits = normbits; 2255 2256 /* Sanity check: result bits must be >= true modulus bits. */ 2257 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2258 err = ERANGE; 2259 goto errout; 2260 } 2261 2262 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2263 &me->me_q.q_mcr, 0)) { 2264 err = ENOMEM; 2265 goto errout; 2266 } 2267 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2268 2269 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2270 &me->me_q.q_ctx, 0)) { 2271 err = ENOMEM; 2272 goto errout; 2273 } 2274 2275 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2276 if (mbits > nbits) { 2277 err = E2BIG; 2278 goto errout; 2279 } 2280 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2281 err = ENOMEM; 2282 goto errout; 2283 } 2284 ubsec_kshift_r(shiftbits, 2285 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2286 me->me_M.dma_vaddr, normbits); 2287 2288 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2289 err = ENOMEM; 2290 goto errout; 2291 } 2292 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2293 2294 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2295 if (ebits > nbits) { 2296 err = E2BIG; 2297 goto errout; 2298 } 2299 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2300 err = ENOMEM; 2301 goto errout; 2302 } 2303 ubsec_kshift_r(shiftbits, 2304 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2305 me->me_E.dma_vaddr, normbits); 2306 2307 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2308 &me->me_epb, 0)) { 2309 err = ENOMEM; 2310 goto errout; 2311 } 2312 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2313 epb->pb_addr = htole32(me->me_E.dma_paddr); 2314 epb->pb_next = 0; 2315 epb->pb_len = htole32(normbits / 8); 2316 2317 #ifdef UBSEC_DEBUG 2318 if (ubsec_debug) { 2319 kprintf("Epb "); 2320 ubsec_dump_pb(epb); 2321 } 2322 #endif 2323 2324 mcr->mcr_pkts = htole16(1); 2325 mcr->mcr_flags = 0; 2326 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2327 mcr->mcr_reserved = 0; 2328 mcr->mcr_pktlen = 0; 2329 2330 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2331 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2332 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2333 2334 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2335 mcr->mcr_opktbuf.pb_next = 0; 2336 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2337 2338 #ifdef DIAGNOSTIC 2339 /* Misaligned output buffer will hang the chip. */ 2340 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2341 panic("%s: modexp invalid addr 0x%x\n", 2342 device_get_nameunit(sc->sc_dev), 2343 letoh32(mcr->mcr_opktbuf.pb_addr)); 2344 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2345 panic("%s: modexp invalid len 0x%x\n", 2346 device_get_nameunit(sc->sc_dev), 2347 letoh32(mcr->mcr_opktbuf.pb_len)); 2348 #endif 2349 2350 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2351 bzero(ctx, sizeof(*ctx)); 2352 ubsec_kshift_r(shiftbits, 2353 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2354 ctx->me_N, normbits); 2355 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2356 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2357 ctx->me_E_len = htole16(nbits); 2358 ctx->me_N_len = htole16(nbits); 2359 2360 #ifdef UBSEC_DEBUG 2361 if (ubsec_debug) { 2362 ubsec_dump_mcr(mcr); 2363 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2364 } 2365 #endif 2366 2367 /* 2368 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2369 * everything else. 2370 */ 2371 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2372 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2373 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2374 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2375 2376 /* Enqueue and we're done... */ 2377 crit_enter(); 2378 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2379 ubsec_feed2(sc); 2380 ubsecstats.hst_modexp++; 2381 crit_exit(); 2382 2383 return (0); 2384 2385 errout: 2386 if (me != NULL) { 2387 if (me->me_q.q_mcr.dma_map != NULL) 2388 ubsec_dma_free(sc, &me->me_q.q_mcr); 2389 if (me->me_q.q_ctx.dma_map != NULL) { 2390 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2391 ubsec_dma_free(sc, &me->me_q.q_ctx); 2392 } 2393 if (me->me_M.dma_map != NULL) { 2394 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2395 ubsec_dma_free(sc, &me->me_M); 2396 } 2397 if (me->me_E.dma_map != NULL) { 2398 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2399 ubsec_dma_free(sc, &me->me_E); 2400 } 2401 if (me->me_C.dma_map != NULL) { 2402 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2403 ubsec_dma_free(sc, &me->me_C); 2404 } 2405 if (me->me_epb.dma_map != NULL) 2406 ubsec_dma_free(sc, &me->me_epb); 2407 kfree(me, M_DEVBUF); 2408 } 2409 krp->krp_status = err; 2410 crypto_kdone(krp); 2411 return (0); 2412 } 2413 2414 /* 2415 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2416 */ 2417 static int 2418 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2419 { 2420 struct ubsec_q2_modexp *me; 2421 struct ubsec_mcr *mcr; 2422 struct ubsec_ctx_modexp *ctx; 2423 struct ubsec_pktbuf *epb; 2424 int err = 0; 2425 u_int nbits, normbits, mbits, shiftbits, ebits; 2426 2427 me = kmalloc(sizeof *me, M_DEVBUF, M_INTWAIT | M_ZERO); 2428 me->me_krp = krp; 2429 me->me_q.q_type = UBS_CTXOP_MODEXP; 2430 2431 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2432 if (nbits <= 512) 2433 normbits = 512; 2434 else if (nbits <= 768) 2435 normbits = 768; 2436 else if (nbits <= 1024) 2437 normbits = 1024; 2438 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2439 normbits = 1536; 2440 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2441 normbits = 2048; 2442 else { 2443 err = E2BIG; 2444 goto errout; 2445 } 2446 2447 shiftbits = normbits - nbits; 2448 2449 /* XXX ??? */ 2450 me->me_modbits = nbits; 2451 me->me_shiftbits = shiftbits; 2452 me->me_normbits = normbits; 2453 2454 /* Sanity check: result bits must be >= true modulus bits. */ 2455 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2456 err = ERANGE; 2457 goto errout; 2458 } 2459 2460 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2461 &me->me_q.q_mcr, 0)) { 2462 err = ENOMEM; 2463 goto errout; 2464 } 2465 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2466 2467 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2468 &me->me_q.q_ctx, 0)) { 2469 err = ENOMEM; 2470 goto errout; 2471 } 2472 2473 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2474 if (mbits > nbits) { 2475 err = E2BIG; 2476 goto errout; 2477 } 2478 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2479 err = ENOMEM; 2480 goto errout; 2481 } 2482 bzero(me->me_M.dma_vaddr, normbits / 8); 2483 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2484 me->me_M.dma_vaddr, (mbits + 7) / 8); 2485 2486 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2487 err = ENOMEM; 2488 goto errout; 2489 } 2490 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2491 2492 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2493 if (ebits > nbits) { 2494 err = E2BIG; 2495 goto errout; 2496 } 2497 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2498 err = ENOMEM; 2499 goto errout; 2500 } 2501 bzero(me->me_E.dma_vaddr, normbits / 8); 2502 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2503 me->me_E.dma_vaddr, (ebits + 7) / 8); 2504 2505 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2506 &me->me_epb, 0)) { 2507 err = ENOMEM; 2508 goto errout; 2509 } 2510 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2511 epb->pb_addr = htole32(me->me_E.dma_paddr); 2512 epb->pb_next = 0; 2513 epb->pb_len = htole32((ebits + 7) / 8); 2514 2515 #ifdef UBSEC_DEBUG 2516 if (ubsec_debug) { 2517 kprintf("Epb "); 2518 ubsec_dump_pb(epb); 2519 } 2520 #endif 2521 2522 mcr->mcr_pkts = htole16(1); 2523 mcr->mcr_flags = 0; 2524 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2525 mcr->mcr_reserved = 0; 2526 mcr->mcr_pktlen = 0; 2527 2528 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2529 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2530 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2531 2532 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2533 mcr->mcr_opktbuf.pb_next = 0; 2534 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2535 2536 #ifdef DIAGNOSTIC 2537 /* Misaligned output buffer will hang the chip. */ 2538 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2539 panic("%s: modexp invalid addr 0x%x\n", 2540 device_get_nameunit(sc->sc_dev), 2541 letoh32(mcr->mcr_opktbuf.pb_addr)); 2542 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2543 panic("%s: modexp invalid len 0x%x\n", 2544 device_get_nameunit(sc->sc_dev), 2545 letoh32(mcr->mcr_opktbuf.pb_len)); 2546 #endif 2547 2548 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2549 bzero(ctx, sizeof(*ctx)); 2550 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2551 (nbits + 7) / 8); 2552 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2553 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2554 ctx->me_E_len = htole16(ebits); 2555 ctx->me_N_len = htole16(nbits); 2556 2557 #ifdef UBSEC_DEBUG 2558 if (ubsec_debug) { 2559 ubsec_dump_mcr(mcr); 2560 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2561 } 2562 #endif 2563 2564 /* 2565 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2566 * everything else. 2567 */ 2568 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2569 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2570 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2571 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2572 2573 /* Enqueue and we're done... */ 2574 crit_enter(); 2575 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2576 ubsec_feed2(sc); 2577 crit_exit(); 2578 2579 return (0); 2580 2581 errout: 2582 if (me != NULL) { 2583 if (me->me_q.q_mcr.dma_map != NULL) 2584 ubsec_dma_free(sc, &me->me_q.q_mcr); 2585 if (me->me_q.q_ctx.dma_map != NULL) { 2586 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2587 ubsec_dma_free(sc, &me->me_q.q_ctx); 2588 } 2589 if (me->me_M.dma_map != NULL) { 2590 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2591 ubsec_dma_free(sc, &me->me_M); 2592 } 2593 if (me->me_E.dma_map != NULL) { 2594 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2595 ubsec_dma_free(sc, &me->me_E); 2596 } 2597 if (me->me_C.dma_map != NULL) { 2598 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2599 ubsec_dma_free(sc, &me->me_C); 2600 } 2601 if (me->me_epb.dma_map != NULL) 2602 ubsec_dma_free(sc, &me->me_epb); 2603 kfree(me, M_DEVBUF); 2604 } 2605 krp->krp_status = err; 2606 crypto_kdone(krp); 2607 return (0); 2608 } 2609 2610 static int 2611 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2612 { 2613 struct ubsec_q2_rsapriv *rp = NULL; 2614 struct ubsec_mcr *mcr; 2615 struct ubsec_ctx_rsapriv *ctx; 2616 int err = 0; 2617 u_int padlen, msglen; 2618 2619 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2620 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2621 if (msglen > padlen) 2622 padlen = msglen; 2623 2624 if (padlen <= 256) 2625 padlen = 256; 2626 else if (padlen <= 384) 2627 padlen = 384; 2628 else if (padlen <= 512) 2629 padlen = 512; 2630 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2631 padlen = 768; 2632 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2633 padlen = 1024; 2634 else { 2635 err = E2BIG; 2636 goto errout; 2637 } 2638 2639 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2640 err = E2BIG; 2641 goto errout; 2642 } 2643 2644 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2645 err = E2BIG; 2646 goto errout; 2647 } 2648 2649 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2650 err = E2BIG; 2651 goto errout; 2652 } 2653 2654 rp = kmalloc(sizeof *rp, M_DEVBUF, M_INTWAIT | M_ZERO); 2655 rp->rpr_krp = krp; 2656 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2657 2658 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2659 &rp->rpr_q.q_mcr, 0)) { 2660 err = ENOMEM; 2661 goto errout; 2662 } 2663 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2664 2665 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2666 &rp->rpr_q.q_ctx, 0)) { 2667 err = ENOMEM; 2668 goto errout; 2669 } 2670 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2671 bzero(ctx, sizeof *ctx); 2672 2673 /* Copy in p */ 2674 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2675 &ctx->rpr_buf[0 * (padlen / 8)], 2676 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2677 2678 /* Copy in q */ 2679 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2680 &ctx->rpr_buf[1 * (padlen / 8)], 2681 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2682 2683 /* Copy in dp */ 2684 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2685 &ctx->rpr_buf[2 * (padlen / 8)], 2686 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2687 2688 /* Copy in dq */ 2689 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2690 &ctx->rpr_buf[3 * (padlen / 8)], 2691 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2692 2693 /* Copy in pinv */ 2694 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2695 &ctx->rpr_buf[4 * (padlen / 8)], 2696 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2697 2698 msglen = padlen * 2; 2699 2700 /* Copy in input message (aligned buffer/length). */ 2701 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2702 /* Is this likely? */ 2703 err = E2BIG; 2704 goto errout; 2705 } 2706 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2707 err = ENOMEM; 2708 goto errout; 2709 } 2710 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2711 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2712 rp->rpr_msgin.dma_vaddr, 2713 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2714 2715 /* Prepare space for output message (aligned buffer/length). */ 2716 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2717 /* Is this likely? */ 2718 err = E2BIG; 2719 goto errout; 2720 } 2721 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2722 err = ENOMEM; 2723 goto errout; 2724 } 2725 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2726 2727 mcr->mcr_pkts = htole16(1); 2728 mcr->mcr_flags = 0; 2729 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2730 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2731 mcr->mcr_ipktbuf.pb_next = 0; 2732 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2733 mcr->mcr_reserved = 0; 2734 mcr->mcr_pktlen = htole16(msglen); 2735 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2736 mcr->mcr_opktbuf.pb_next = 0; 2737 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2738 2739 #ifdef DIAGNOSTIC 2740 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2741 panic("%s: rsapriv: invalid msgin %x(0x%x)", 2742 device_get_nameunit(sc->sc_dev), 2743 rp->rpr_msgin.dma_paddr, rp->rpr_msgin.dma_size); 2744 } 2745 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2746 panic("%s: rsapriv: invalid msgout %x(0x%x)", 2747 device_get_nameunit(sc->sc_dev), 2748 rp->rpr_msgout.dma_paddr, rp->rpr_msgout.dma_size); 2749 } 2750 #endif 2751 2752 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2753 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2754 ctx->rpr_q_len = htole16(padlen); 2755 ctx->rpr_p_len = htole16(padlen); 2756 2757 /* 2758 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2759 * everything else. 2760 */ 2761 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE); 2762 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD); 2763 2764 /* Enqueue and we're done... */ 2765 crit_enter(); 2766 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2767 ubsec_feed2(sc); 2768 ubsecstats.hst_modexpcrt++; 2769 crit_exit(); 2770 return (0); 2771 2772 errout: 2773 if (rp != NULL) { 2774 if (rp->rpr_q.q_mcr.dma_map != NULL) 2775 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2776 if (rp->rpr_msgin.dma_map != NULL) { 2777 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2778 ubsec_dma_free(sc, &rp->rpr_msgin); 2779 } 2780 if (rp->rpr_msgout.dma_map != NULL) { 2781 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2782 ubsec_dma_free(sc, &rp->rpr_msgout); 2783 } 2784 kfree(rp, M_DEVBUF); 2785 } 2786 krp->krp_status = err; 2787 crypto_kdone(krp); 2788 return (0); 2789 } 2790 2791 #ifdef UBSEC_DEBUG 2792 static void 2793 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2794 { 2795 kprintf("addr 0x%x (0x%x) next 0x%x\n", 2796 pb->pb_addr, pb->pb_len, pb->pb_next); 2797 } 2798 2799 static void 2800 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c) 2801 { 2802 kprintf("CTX (0x%x):\n", c->ctx_len); 2803 switch (letoh16(c->ctx_op)) { 2804 case UBS_CTXOP_RNGBYPASS: 2805 case UBS_CTXOP_RNGSHA1: 2806 break; 2807 case UBS_CTXOP_MODEXP: 2808 { 2809 struct ubsec_ctx_modexp *cx = (void *)c; 2810 int i, len; 2811 2812 kprintf(" Elen %u, Nlen %u\n", 2813 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2814 len = (cx->me_N_len + 7)/8; 2815 for (i = 0; i < len; i++) 2816 kprintf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2817 kprintf("\n"); 2818 break; 2819 } 2820 default: 2821 kprintf("unknown context: %x\n", c->ctx_op); 2822 } 2823 kprintf("END CTX\n"); 2824 } 2825 2826 static void 2827 ubsec_dump_mcr(struct ubsec_mcr *mcr) 2828 { 2829 volatile struct ubsec_mcr_add *ma; 2830 int i; 2831 2832 kprintf("MCR:\n"); 2833 kprintf(" pkts: %u, flags 0x%x\n", 2834 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2835 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2836 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2837 kprintf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2838 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2839 letoh16(ma->mcr_reserved)); 2840 kprintf(" %d: ipkt ", i); 2841 ubsec_dump_pb(&ma->mcr_ipktbuf); 2842 kprintf(" %d: opkt ", i); 2843 ubsec_dump_pb(&ma->mcr_opktbuf); 2844 ma++; 2845 } 2846 kprintf("END MCR\n"); 2847 } 2848 #endif /* UBSEC_DEBUG */ 2849 2850 /* 2851 * Return the number of significant bits of a big number. 2852 */ 2853 static int 2854 ubsec_ksigbits(struct crparam *cr) 2855 { 2856 u_int plen = (cr->crp_nbits + 7) / 8; 2857 int i, sig = plen * 8; 2858 u_int8_t c, *p = cr->crp_p; 2859 2860 for (i = plen - 1; i >= 0; i--) { 2861 c = p[i]; 2862 if (c != 0) { 2863 while ((c & 0x80) == 0) { 2864 sig--; 2865 c <<= 1; 2866 } 2867 break; 2868 } 2869 sig -= 8; 2870 } 2871 return (sig); 2872 } 2873 2874 static void 2875 ubsec_kshift_r( 2876 u_int shiftbits, 2877 u_int8_t *src, u_int srcbits, 2878 u_int8_t *dst, u_int dstbits) 2879 { 2880 u_int slen, dlen; 2881 int i, si, di, n; 2882 2883 slen = (srcbits + 7) / 8; 2884 dlen = (dstbits + 7) / 8; 2885 2886 for (i = 0; i < slen; i++) 2887 dst[i] = src[i]; 2888 for (i = 0; i < dlen - slen; i++) 2889 dst[slen + i] = 0; 2890 2891 n = shiftbits / 8; 2892 if (n != 0) { 2893 si = dlen - n - 1; 2894 di = dlen - 1; 2895 while (si >= 0) 2896 dst[di--] = dst[si--]; 2897 while (di >= 0) 2898 dst[di--] = 0; 2899 } 2900 2901 n = shiftbits % 8; 2902 if (n != 0) { 2903 for (i = dlen - 1; i > 0; i--) 2904 dst[i] = (dst[i] << n) | 2905 (dst[i - 1] >> (8 - n)); 2906 dst[0] = dst[0] << n; 2907 } 2908 } 2909 2910 static void 2911 ubsec_kshift_l( 2912 u_int shiftbits, 2913 u_int8_t *src, u_int srcbits, 2914 u_int8_t *dst, u_int dstbits) 2915 { 2916 int slen, dlen, i, n; 2917 2918 slen = (srcbits + 7) / 8; 2919 dlen = (dstbits + 7) / 8; 2920 2921 n = shiftbits / 8; 2922 for (i = 0; i < slen; i++) 2923 dst[i] = src[i + n]; 2924 for (i = 0; i < dlen - slen; i++) 2925 dst[slen + i] = 0; 2926 2927 n = shiftbits % 8; 2928 if (n != 0) { 2929 for (i = 0; i < (dlen - 1); i++) 2930 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2931 dst[dlen - 1] = dst[dlen - 1] >> n; 2932 } 2933 } 2934