1 /* 2 * Generic driver for the Advanced Systems Inc. SCSI controllers 3 * Product specific probe and attach routines can be found in: 4 * 5 * i386/isa/adv_isa.c ABP5140, ABP542, ABP5150, ABP842, ABP852 6 * i386/eisa/adv_eisa.c ABP742, ABP752 7 * pci/adv_pci.c ABP920, ABP930, ABP930U, ABP930UA, ABP940, ABP940U, 8 * ABP940UA, ABP950, ABP960, ABP960U, ABP960UA, 9 * ABP970, ABP970U 10 * 11 * Copyright (c) 1996-2000 Justin Gibbs. 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions, and the following disclaimer, 19 * without modification, immediately at the beginning of the file. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/advansys/advansys.c,v 1.14.2.4 2002/01/06 21:21:42 dwmalone Exp $ 36 * $DragonFly: src/sys/dev/disk/advansys/advansys.c,v 1.7 2005/06/03 16:57:12 eirikn Exp $ 37 */ 38 /* 39 * Ported from: 40 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 41 * 42 * Copyright (c) 1995-1997 Advanced System Products, Inc. 43 * All Rights Reserved. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that redistributions of source 47 * code retain the above copyright notice and this comment without 48 * modification. 49 */ 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/thread2.h> 56 57 #include <machine/bus_pio.h> 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <sys/bus.h> 61 #include <sys/rman.h> 62 63 #include <bus/cam/cam.h> 64 #include <bus/cam/cam_ccb.h> 65 #include <bus/cam/cam_sim.h> 66 #include <bus/cam/cam_xpt_sim.h> 67 #include <bus/cam/cam_xpt_periph.h> 68 #include <bus/cam/cam_debug.h> 69 70 #include <bus/cam/scsi/scsi_all.h> 71 #include <bus/cam/scsi/scsi_message.h> 72 73 #include <vm/vm.h> 74 #include <vm/vm_param.h> 75 #include <vm/pmap.h> 76 77 #include "advansys.h" 78 79 static void adv_action(struct cam_sim *sim, union ccb *ccb); 80 static void adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs, 81 int nsegments, int error); 82 static void adv_poll(struct cam_sim *sim); 83 static void adv_run_doneq(struct adv_softc *adv); 84 static struct adv_ccb_info * 85 adv_alloc_ccb_info(struct adv_softc *adv); 86 static void adv_destroy_ccb_info(struct adv_softc *adv, 87 struct adv_ccb_info *cinfo); 88 static __inline struct adv_ccb_info * 89 adv_get_ccb_info(struct adv_softc *adv); 90 static __inline void adv_free_ccb_info(struct adv_softc *adv, 91 struct adv_ccb_info *cinfo); 92 static __inline void adv_set_state(struct adv_softc *adv, adv_state state); 93 static __inline void adv_clear_state(struct adv_softc *adv, union ccb* ccb); 94 static void adv_clear_state_really(struct adv_softc *adv, union ccb* ccb); 95 96 static __inline struct adv_ccb_info * 97 adv_get_ccb_info(struct adv_softc *adv) 98 { 99 struct adv_ccb_info *cinfo; 100 101 crit_enter(); 102 if ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) { 103 SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links); 104 } else { 105 cinfo = adv_alloc_ccb_info(adv); 106 } 107 crit_exit(); 108 109 return (cinfo); 110 } 111 112 static __inline void 113 adv_free_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo) 114 { 115 crit_enter(); 116 cinfo->state = ACCB_FREE; 117 SLIST_INSERT_HEAD(&adv->free_ccb_infos, cinfo, links); 118 crit_exit(); 119 } 120 121 static __inline void 122 adv_set_state(struct adv_softc *adv, adv_state state) 123 { 124 if (adv->state == 0) 125 xpt_freeze_simq(adv->sim, /*count*/1); 126 adv->state |= state; 127 } 128 129 static __inline void 130 adv_clear_state(struct adv_softc *adv, union ccb* ccb) 131 { 132 if (adv->state != 0) 133 adv_clear_state_really(adv, ccb); 134 } 135 136 static void 137 adv_clear_state_really(struct adv_softc *adv, union ccb* ccb) 138 { 139 if ((adv->state & ADV_BUSDMA_BLOCK_CLEARED) != 0) 140 adv->state &= ~(ADV_BUSDMA_BLOCK_CLEARED|ADV_BUSDMA_BLOCK); 141 if ((adv->state & ADV_RESOURCE_SHORTAGE) != 0) { 142 int openings; 143 144 openings = adv->max_openings - adv->cur_active - ADV_MIN_FREE_Q; 145 if (openings >= adv->openings_needed) { 146 adv->state &= ~ADV_RESOURCE_SHORTAGE; 147 adv->openings_needed = 0; 148 } 149 } 150 151 if ((adv->state & ADV_IN_TIMEOUT) != 0) { 152 struct adv_ccb_info *cinfo; 153 154 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr; 155 if ((cinfo->state & ACCB_RECOVERY_CCB) != 0) { 156 struct ccb_hdr *ccb_h; 157 158 /* 159 * We now traverse our list of pending CCBs 160 * and reinstate their timeouts. 161 */ 162 ccb_h = LIST_FIRST(&adv->pending_ccbs); 163 while (ccb_h != NULL) { 164 callout_reset(&ccb_h->timeout_ch, 165 (ccb_h->timeout * hz) / 1000, 166 adv_timeout, ccb_h); 167 ccb_h = LIST_NEXT(ccb_h, sim_links.le); 168 } 169 adv->state &= ~ADV_IN_TIMEOUT; 170 printf("%s: No longer in timeout\n", adv_name(adv)); 171 } 172 } 173 if (adv->state == 0) 174 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 175 } 176 177 void 178 adv_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 179 { 180 bus_addr_t* physaddr; 181 182 physaddr = (bus_addr_t*)arg; 183 *physaddr = segs->ds_addr; 184 } 185 186 char * 187 adv_name(struct adv_softc *adv) 188 { 189 static char name[10]; 190 191 snprintf(name, sizeof(name), "adv%d", adv->unit); 192 return (name); 193 } 194 195 static void 196 adv_action(struct cam_sim *sim, union ccb *ccb) 197 { 198 struct adv_softc *adv; 199 200 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("adv_action\n")); 201 202 adv = (struct adv_softc *)cam_sim_softc(sim); 203 204 switch (ccb->ccb_h.func_code) { 205 /* Common cases first */ 206 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 207 { 208 struct ccb_hdr *ccb_h; 209 struct ccb_scsiio *csio; 210 struct adv_ccb_info *cinfo; 211 212 ccb_h = &ccb->ccb_h; 213 csio = &ccb->csio; 214 cinfo = adv_get_ccb_info(adv); 215 if (cinfo == NULL) 216 panic("XXX Handle CCB info error!!!"); 217 218 ccb_h->ccb_cinfo_ptr = cinfo; 219 cinfo->ccb = ccb; 220 221 /* Only use S/G if there is a transfer */ 222 if ((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 223 if ((ccb_h->flags & CAM_SCATTER_VALID) == 0) { 224 /* 225 * We've been given a pointer 226 * to a single buffer 227 */ 228 if ((ccb_h->flags & CAM_DATA_PHYS) == 0) { 229 int error; 230 231 crit_enter(); 232 error = 233 bus_dmamap_load(adv->buffer_dmat, 234 cinfo->dmamap, 235 csio->data_ptr, 236 csio->dxfer_len, 237 adv_execute_ccb, 238 csio, /*flags*/0); 239 if (error == EINPROGRESS) { 240 /* 241 * So as to maintain ordering, 242 * freeze the controller queue 243 * until our mapping is 244 * returned. 245 */ 246 adv_set_state(adv, 247 ADV_BUSDMA_BLOCK); 248 } 249 crit_exit(); 250 } else { 251 struct bus_dma_segment seg; 252 253 /* Pointer to physical buffer */ 254 seg.ds_addr = 255 (bus_addr_t)csio->data_ptr; 256 seg.ds_len = csio->dxfer_len; 257 adv_execute_ccb(csio, &seg, 1, 0); 258 } 259 } else { 260 struct bus_dma_segment *segs; 261 if ((ccb_h->flags & CAM_DATA_PHYS) != 0) 262 panic("adv_setup_data - Physical " 263 "segment pointers unsupported"); 264 265 if ((ccb_h->flags & CAM_SG_LIST_PHYS) == 0) 266 panic("adv_setup_data - Virtual " 267 "segment addresses unsupported"); 268 269 /* Just use the segments provided */ 270 segs = (struct bus_dma_segment *)csio->data_ptr; 271 adv_execute_ccb(ccb, segs, csio->sglist_cnt, 0); 272 } 273 } else { 274 adv_execute_ccb(ccb, NULL, 0, 0); 275 } 276 break; 277 } 278 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 279 case XPT_TARGET_IO: /* Execute target I/O request */ 280 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 281 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 282 case XPT_EN_LUN: /* Enable LUN as a target */ 283 case XPT_ABORT: /* Abort the specified CCB */ 284 /* XXX Implement */ 285 ccb->ccb_h.status = CAM_REQ_INVALID; 286 xpt_done(ccb); 287 break; 288 case XPT_SET_TRAN_SETTINGS: 289 { 290 struct ccb_trans_settings *cts; 291 target_bit_vector targ_mask; 292 struct adv_transinfo *tconf; 293 u_int update_type; 294 295 cts = &ccb->cts; 296 targ_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id); 297 update_type = 0; 298 299 /* 300 * The user must specify which type of settings he wishes 301 * to change. 302 */ 303 if (((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) 304 && ((cts->flags & CCB_TRANS_USER_SETTINGS) == 0)) { 305 tconf = &adv->tinfo[cts->ccb_h.target_id].current; 306 update_type |= ADV_TRANS_GOAL; 307 } else if (((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) 308 && ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) == 0)) { 309 tconf = &adv->tinfo[cts->ccb_h.target_id].user; 310 update_type |= ADV_TRANS_USER; 311 } else { 312 ccb->ccb_h.status = CAM_REQ_INVALID; 313 break; 314 } 315 316 crit_enter(); 317 if ((update_type & ADV_TRANS_GOAL) != 0) { 318 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 319 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0) 320 adv->disc_enable |= targ_mask; 321 else 322 adv->disc_enable &= ~targ_mask; 323 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B, 324 adv->disc_enable); 325 } 326 327 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 328 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0) 329 adv->cmd_qng_enabled |= targ_mask; 330 else 331 adv->cmd_qng_enabled &= ~targ_mask; 332 } 333 } 334 335 if ((update_type & ADV_TRANS_USER) != 0) { 336 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) { 337 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0) 338 adv->user_disc_enable |= targ_mask; 339 else 340 adv->user_disc_enable &= ~targ_mask; 341 } 342 343 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) { 344 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0) 345 adv->user_cmd_qng_enabled |= targ_mask; 346 else 347 adv->user_cmd_qng_enabled &= ~targ_mask; 348 } 349 } 350 351 /* 352 * If the user specifies either the sync rate, or offset, 353 * but not both, the unspecified parameter defaults to its 354 * current value in transfer negotiations. 355 */ 356 if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0) 357 || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) { 358 /* 359 * If the user provided a sync rate but no offset, 360 * use the current offset. 361 */ 362 if ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) == 0) 363 cts->sync_offset = tconf->offset; 364 365 /* 366 * If the user provided an offset but no sync rate, 367 * use the current sync rate. 368 */ 369 if ((cts->valid & CCB_TRANS_SYNC_RATE_VALID) == 0) 370 cts->sync_period = tconf->period; 371 372 adv_period_offset_to_sdtr(adv, &cts->sync_period, 373 &cts->sync_offset, 374 cts->ccb_h.target_id); 375 376 adv_set_syncrate(adv, /*struct cam_path */NULL, 377 cts->ccb_h.target_id, cts->sync_period, 378 cts->sync_offset, update_type); 379 } 380 381 crit_exit(); 382 ccb->ccb_h.status = CAM_REQ_CMP; 383 xpt_done(ccb); 384 break; 385 } 386 case XPT_GET_TRAN_SETTINGS: 387 /* Get default/user set transfer settings for the target */ 388 { 389 struct ccb_trans_settings *cts; 390 struct adv_transinfo *tconf; 391 target_bit_vector target_mask; 392 393 cts = &ccb->cts; 394 target_mask = ADV_TID_TO_TARGET_MASK(cts->ccb_h.target_id); 395 396 cts->flags &= ~(CCB_TRANS_DISC_ENB|CCB_TRANS_TAG_ENB); 397 398 crit_enter(); 399 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) { 400 tconf = &adv->tinfo[cts->ccb_h.target_id].current; 401 if ((adv->disc_enable & target_mask) != 0) 402 cts->flags |= CCB_TRANS_DISC_ENB; 403 if ((adv->cmd_qng_enabled & target_mask) != 0) 404 cts->flags |= CCB_TRANS_TAG_ENB; 405 } else { 406 tconf = &adv->tinfo[cts->ccb_h.target_id].user; 407 if ((adv->user_disc_enable & target_mask) != 0) 408 cts->flags |= CCB_TRANS_DISC_ENB; 409 if ((adv->user_cmd_qng_enabled & target_mask) != 0) 410 cts->flags |= CCB_TRANS_TAG_ENB; 411 } 412 413 cts->sync_period = tconf->period; 414 cts->sync_offset = tconf->offset; 415 crit_exit(); 416 417 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT; 418 cts->valid = CCB_TRANS_SYNC_RATE_VALID 419 | CCB_TRANS_SYNC_OFFSET_VALID 420 | CCB_TRANS_BUS_WIDTH_VALID 421 | CCB_TRANS_DISC_VALID 422 | CCB_TRANS_TQ_VALID; 423 ccb->ccb_h.status = CAM_REQ_CMP; 424 xpt_done(ccb); 425 break; 426 } 427 case XPT_CALC_GEOMETRY: 428 { 429 struct ccb_calc_geometry *ccg; 430 u_int32_t size_mb; 431 u_int32_t secs_per_cylinder; 432 int extended; 433 434 ccg = &ccb->ccg; 435 size_mb = ccg->volume_size 436 / ((1024L * 1024L) / ccg->block_size); 437 extended = (adv->control & ADV_CNTL_BIOS_GT_1GB) != 0; 438 439 if (size_mb > 1024 && extended) { 440 ccg->heads = 255; 441 ccg->secs_per_track = 63; 442 } else { 443 ccg->heads = 64; 444 ccg->secs_per_track = 32; 445 } 446 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 447 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 448 ccb->ccb_h.status = CAM_REQ_CMP; 449 xpt_done(ccb); 450 break; 451 } 452 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 453 { 454 crit_enter(); 455 adv_stop_execution(adv); 456 adv_reset_bus(adv, /*initiate_reset*/TRUE); 457 adv_start_execution(adv); 458 crit_exit(); 459 460 ccb->ccb_h.status = CAM_REQ_CMP; 461 xpt_done(ccb); 462 break; 463 } 464 case XPT_TERM_IO: /* Terminate the I/O process */ 465 /* XXX Implement */ 466 ccb->ccb_h.status = CAM_REQ_INVALID; 467 xpt_done(ccb); 468 break; 469 case XPT_PATH_INQ: /* Path routing inquiry */ 470 { 471 struct ccb_pathinq *cpi = &ccb->cpi; 472 473 cpi->version_num = 1; /* XXX??? */ 474 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE; 475 cpi->target_sprt = 0; 476 cpi->hba_misc = 0; 477 cpi->hba_eng_cnt = 0; 478 cpi->max_target = 7; 479 cpi->max_lun = 7; 480 cpi->initiator_id = adv->scsi_id; 481 cpi->bus_id = cam_sim_bus(sim); 482 cpi->base_transfer_speed = 3300; 483 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 484 strncpy(cpi->hba_vid, "Advansys", HBA_IDLEN); 485 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 486 cpi->unit_number = cam_sim_unit(sim); 487 cpi->ccb_h.status = CAM_REQ_CMP; 488 xpt_done(ccb); 489 break; 490 } 491 default: 492 ccb->ccb_h.status = CAM_REQ_INVALID; 493 xpt_done(ccb); 494 break; 495 } 496 } 497 498 /* 499 * Currently, the output of bus_dmammap_load suits our needs just 500 * fine, but should it change, we'd need to do something here. 501 */ 502 #define adv_fixup_dmasegs(adv, dm_segs) (struct adv_sg_entry *)(dm_segs) 503 504 static void 505 adv_execute_ccb(void *arg, bus_dma_segment_t *dm_segs, 506 int nsegments, int error) 507 { 508 struct ccb_scsiio *csio; 509 struct ccb_hdr *ccb_h; 510 struct cam_sim *sim; 511 struct adv_softc *adv; 512 struct adv_ccb_info *cinfo; 513 struct adv_scsi_q scsiq; 514 struct adv_sg_head sghead; 515 516 csio = (struct ccb_scsiio *)arg; 517 ccb_h = &csio->ccb_h; 518 sim = xpt_path_sim(ccb_h->path); 519 adv = (struct adv_softc *)cam_sim_softc(sim); 520 cinfo = (struct adv_ccb_info *)csio->ccb_h.ccb_cinfo_ptr; 521 522 /* 523 * Setup our done routine to release the simq on 524 * the next ccb that completes. 525 */ 526 if ((adv->state & ADV_BUSDMA_BLOCK) != 0) 527 adv->state |= ADV_BUSDMA_BLOCK_CLEARED; 528 529 if ((ccb_h->flags & CAM_CDB_POINTER) != 0) { 530 if ((ccb_h->flags & CAM_CDB_PHYS) == 0) { 531 /* XXX Need phystovirt!!!! */ 532 /* How about pmap_kenter??? */ 533 scsiq.cdbptr = csio->cdb_io.cdb_ptr; 534 } else { 535 scsiq.cdbptr = csio->cdb_io.cdb_ptr; 536 } 537 } else { 538 scsiq.cdbptr = csio->cdb_io.cdb_bytes; 539 } 540 /* 541 * Build up the request 542 */ 543 scsiq.q1.status = 0; 544 scsiq.q1.q_no = 0; 545 scsiq.q1.cntl = 0; 546 scsiq.q1.sg_queue_cnt = 0; 547 scsiq.q1.target_id = ADV_TID_TO_TARGET_MASK(ccb_h->target_id); 548 scsiq.q1.target_lun = ccb_h->target_lun; 549 scsiq.q1.sense_len = csio->sense_len; 550 scsiq.q1.extra_bytes = 0; 551 scsiq.q2.ccb_index = cinfo - adv->ccb_infos; 552 scsiq.q2.target_ix = ADV_TIDLUN_TO_IX(ccb_h->target_id, 553 ccb_h->target_lun); 554 scsiq.q2.flag = 0; 555 scsiq.q2.cdb_len = csio->cdb_len; 556 if ((ccb_h->flags & CAM_TAG_ACTION_VALID) != 0) 557 scsiq.q2.tag_code = csio->tag_action; 558 else 559 scsiq.q2.tag_code = 0; 560 scsiq.q2.vm_id = 0; 561 562 if (nsegments != 0) { 563 bus_dmasync_op_t op; 564 565 scsiq.q1.data_addr = dm_segs->ds_addr; 566 scsiq.q1.data_cnt = dm_segs->ds_len; 567 if (nsegments > 1) { 568 scsiq.q1.cntl |= QC_SG_HEAD; 569 sghead.entry_cnt 570 = sghead.entry_to_copy 571 = nsegments; 572 sghead.res = 0; 573 sghead.sg_list = adv_fixup_dmasegs(adv, dm_segs); 574 scsiq.sg_head = &sghead; 575 } else { 576 scsiq.sg_head = NULL; 577 } 578 if ((ccb_h->flags & CAM_DIR_MASK) == CAM_DIR_IN) 579 op = BUS_DMASYNC_PREREAD; 580 else 581 op = BUS_DMASYNC_PREWRITE; 582 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op); 583 } else { 584 scsiq.q1.data_addr = 0; 585 scsiq.q1.data_cnt = 0; 586 scsiq.sg_head = NULL; 587 } 588 589 590 crit_enter(); 591 /* 592 * Last time we need to check if this SCB needs to 593 * be aborted. 594 */ 595 if (ccb_h->status != CAM_REQ_INPROG) { 596 if (nsegments != 0) 597 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap); 598 adv_clear_state(adv, (union ccb *)csio); 599 adv_free_ccb_info(adv, cinfo); 600 xpt_done((union ccb *)csio); 601 crit_exit(); 602 return; 603 } 604 605 if (adv_execute_scsi_queue(adv, &scsiq, csio->dxfer_len) != 0) { 606 /* Temporary resource shortage */ 607 adv_set_state(adv, ADV_RESOURCE_SHORTAGE); 608 if (nsegments != 0) 609 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap); 610 csio->ccb_h.status = CAM_REQUEUE_REQ; 611 adv_clear_state(adv, (union ccb *)csio); 612 adv_free_ccb_info(adv, cinfo); 613 xpt_done((union ccb *)csio); 614 crit_exit(); 615 return; 616 } 617 cinfo->state |= ACCB_ACTIVE; 618 ccb_h->status |= CAM_SIM_QUEUED; 619 LIST_INSERT_HEAD(&adv->pending_ccbs, ccb_h, sim_links.le); 620 /* Schedule our timeout */ 621 callout_reset(&ccb_h->timeout_ch, (ccb_h->timeout * hz)/1000, 622 adv_timeout, csio); 623 crit_exit(); 624 } 625 626 static struct adv_ccb_info * 627 adv_alloc_ccb_info(struct adv_softc *adv) 628 { 629 int error; 630 struct adv_ccb_info *cinfo; 631 632 cinfo = &adv->ccb_infos[adv->ccb_infos_allocated]; 633 cinfo->state = ACCB_FREE; 634 error = bus_dmamap_create(adv->buffer_dmat, /*flags*/0, 635 &cinfo->dmamap); 636 if (error != 0) { 637 printf("%s: Unable to allocate CCB info " 638 "dmamap - error %d\n", adv_name(adv), error); 639 return (NULL); 640 } 641 adv->ccb_infos_allocated++; 642 return (cinfo); 643 } 644 645 static void 646 adv_destroy_ccb_info(struct adv_softc *adv, struct adv_ccb_info *cinfo) 647 { 648 bus_dmamap_destroy(adv->buffer_dmat, cinfo->dmamap); 649 } 650 651 void 652 adv_timeout(void *arg) 653 { 654 union ccb *ccb; 655 struct adv_softc *adv; 656 struct adv_ccb_info *cinfo; 657 658 ccb = (union ccb *)arg; 659 adv = (struct adv_softc *)xpt_path_sim(ccb->ccb_h.path)->softc; 660 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr; 661 662 xpt_print_path(ccb->ccb_h.path); 663 printf("Timed out\n"); 664 665 crit_enter(); 666 /* Have we been taken care of already?? */ 667 if (cinfo == NULL || cinfo->state == ACCB_FREE) { 668 crit_exit(); 669 return; 670 } 671 672 adv_stop_execution(adv); 673 674 if ((cinfo->state & ACCB_ABORT_QUEUED) == 0) { 675 struct ccb_hdr *ccb_h; 676 677 /* 678 * In order to simplify the recovery process, we ask the XPT 679 * layer to halt the queue of new transactions and we traverse 680 * the list of pending CCBs and remove their timeouts. This 681 * means that the driver attempts to clear only one error 682 * condition at a time. In general, timeouts that occur 683 * close together are related anyway, so there is no benefit 684 * in attempting to handle errors in parrallel. Timeouts will 685 * be reinstated when the recovery process ends. 686 */ 687 adv_set_state(adv, ADV_IN_TIMEOUT); 688 689 /* This CCB is the CCB representing our recovery actions */ 690 cinfo->state |= ACCB_RECOVERY_CCB|ACCB_ABORT_QUEUED; 691 692 ccb_h = LIST_FIRST(&adv->pending_ccbs); 693 while (ccb_h != NULL) { 694 callout_stop(&ccb_h->timeout_ch); 695 ccb_h = LIST_NEXT(ccb_h, sim_links.le); 696 } 697 698 /* XXX Should send a BDR */ 699 /* Attempt an abort as our first tact */ 700 xpt_print_path(ccb->ccb_h.path); 701 printf("Attempting abort\n"); 702 adv_abort_ccb(adv, ccb->ccb_h.target_id, 703 ccb->ccb_h.target_lun, ccb, 704 CAM_CMD_TIMEOUT, /*queued_only*/FALSE); 705 callout_reset(&ccb->ccb_h.timeout_ch, 2 * hz, adv_timeout, ccb); 706 } else { 707 /* Our attempt to perform an abort failed, go for a reset */ 708 xpt_print_path(ccb->ccb_h.path); 709 printf("Resetting bus\n"); 710 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 711 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 712 adv_reset_bus(adv, /*initiate_reset*/TRUE); 713 } 714 adv_start_execution(adv); 715 crit_exit(); 716 } 717 718 struct adv_softc * 719 adv_alloc(device_t dev, bus_space_tag_t tag, bus_space_handle_t bsh) 720 { 721 struct adv_softc *adv = device_get_softc(dev); 722 723 /* 724 * Allocate a storage area for us 725 */ 726 LIST_INIT(&adv->pending_ccbs); 727 SLIST_INIT(&adv->free_ccb_infos); 728 adv->dev = dev; 729 adv->unit = device_get_unit(dev); 730 adv->tag = tag; 731 adv->bsh = bsh; 732 733 return(adv); 734 } 735 736 void 737 adv_free(struct adv_softc *adv) 738 { 739 switch (adv->init_level) { 740 case 6: 741 { 742 struct adv_ccb_info *cinfo; 743 744 while ((cinfo = SLIST_FIRST(&adv->free_ccb_infos)) != NULL) { 745 SLIST_REMOVE_HEAD(&adv->free_ccb_infos, links); 746 adv_destroy_ccb_info(adv, cinfo); 747 } 748 749 bus_dmamap_unload(adv->sense_dmat, adv->sense_dmamap); 750 } 751 case 5: 752 bus_dmamem_free(adv->sense_dmat, adv->sense_buffers, 753 adv->sense_dmamap); 754 case 4: 755 bus_dma_tag_destroy(adv->sense_dmat); 756 case 3: 757 bus_dma_tag_destroy(adv->buffer_dmat); 758 case 2: 759 bus_dma_tag_destroy(adv->parent_dmat); 760 case 1: 761 if (adv->ccb_infos != NULL) 762 free(adv->ccb_infos, M_DEVBUF); 763 case 0: 764 break; 765 } 766 } 767 768 int 769 adv_init(struct adv_softc *adv) 770 { 771 struct adv_eeprom_config eeprom_config; 772 int checksum, i; 773 int max_sync; 774 u_int16_t config_lsw; 775 u_int16_t config_msw; 776 777 adv_lib_init(adv); 778 779 /* 780 * Stop script execution. 781 */ 782 adv_write_lram_16(adv, ADV_HALTCODE_W, 0x00FE); 783 adv_stop_execution(adv); 784 if (adv_stop_chip(adv) == 0 || adv_is_chip_halted(adv) == 0) { 785 printf("adv%d: Unable to halt adapter. Initialization" 786 "failed\n", adv->unit); 787 return (1); 788 } 789 ADV_OUTW(adv, ADV_REG_PROG_COUNTER, ADV_MCODE_START_ADDR); 790 if (ADV_INW(adv, ADV_REG_PROG_COUNTER) != ADV_MCODE_START_ADDR) { 791 printf("adv%d: Unable to set program counter. Initialization" 792 "failed\n", adv->unit); 793 return (1); 794 } 795 796 config_msw = ADV_INW(adv, ADV_CONFIG_MSW); 797 config_lsw = ADV_INW(adv, ADV_CONFIG_LSW); 798 799 if ((config_msw & ADV_CFG_MSW_CLR_MASK) != 0) { 800 config_msw &= ~ADV_CFG_MSW_CLR_MASK; 801 /* 802 * XXX The Linux code flags this as an error, 803 * but what should we report to the user??? 804 * It seems that clearing the config register 805 * makes this error recoverable. 806 */ 807 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw); 808 } 809 810 /* Suck in the configuration from the EEProm */ 811 checksum = adv_get_eeprom_config(adv, &eeprom_config); 812 813 if (ADV_INW(adv, ADV_CHIP_STATUS) & ADV_CSW_AUTO_CONFIG) { 814 /* 815 * XXX The Linux code sets a warning level for this 816 * condition, yet nothing of meaning is printed to 817 * the user. What does this mean??? 818 */ 819 if (adv->chip_version == 3) { 820 if (eeprom_config.cfg_lsw != config_lsw) 821 eeprom_config.cfg_lsw = config_lsw; 822 if (eeprom_config.cfg_msw != config_msw) { 823 eeprom_config.cfg_msw = config_msw; 824 } 825 } 826 } 827 if (checksum == eeprom_config.chksum) { 828 829 /* Range/Sanity checking */ 830 if (eeprom_config.max_total_qng < ADV_MIN_TOTAL_QNG) { 831 eeprom_config.max_total_qng = ADV_MIN_TOTAL_QNG; 832 } 833 if (eeprom_config.max_total_qng > ADV_MAX_TOTAL_QNG) { 834 eeprom_config.max_total_qng = ADV_MAX_TOTAL_QNG; 835 } 836 if (eeprom_config.max_tag_qng > eeprom_config.max_total_qng) { 837 eeprom_config.max_tag_qng = eeprom_config.max_total_qng; 838 } 839 if (eeprom_config.max_tag_qng < ADV_MIN_TAG_Q_PER_DVC) { 840 eeprom_config.max_tag_qng = ADV_MIN_TAG_Q_PER_DVC; 841 } 842 adv->max_openings = eeprom_config.max_total_qng; 843 adv->user_disc_enable = eeprom_config.disc_enable; 844 adv->user_cmd_qng_enabled = eeprom_config.use_cmd_qng; 845 adv->isa_dma_speed = EEPROM_DMA_SPEED(eeprom_config); 846 adv->scsi_id = EEPROM_SCSIID(eeprom_config) & ADV_MAX_TID; 847 EEPROM_SET_SCSIID(eeprom_config, adv->scsi_id); 848 adv->control = eeprom_config.cntl; 849 for (i = 0; i <= ADV_MAX_TID; i++) { 850 u_int8_t sync_data; 851 852 if ((eeprom_config.init_sdtr & (0x1 << i)) == 0) 853 sync_data = 0; 854 else 855 sync_data = eeprom_config.sdtr_data[i]; 856 adv_sdtr_to_period_offset(adv, 857 sync_data, 858 &adv->tinfo[i].user.period, 859 &adv->tinfo[i].user.offset, 860 i); 861 } 862 config_lsw = eeprom_config.cfg_lsw; 863 eeprom_config.cfg_msw = config_msw; 864 } else { 865 u_int8_t sync_data; 866 867 printf("adv%d: Warning EEPROM Checksum mismatch. " 868 "Using default device parameters\n", adv->unit); 869 870 /* Set reasonable defaults since we can't read the EEPROM */ 871 adv->isa_dma_speed = /*ADV_DEF_ISA_DMA_SPEED*/1; 872 adv->max_openings = ADV_DEF_MAX_TOTAL_QNG; 873 adv->disc_enable = TARGET_BIT_VECTOR_SET; 874 adv->user_disc_enable = TARGET_BIT_VECTOR_SET; 875 adv->cmd_qng_enabled = TARGET_BIT_VECTOR_SET; 876 adv->user_cmd_qng_enabled = TARGET_BIT_VECTOR_SET; 877 adv->scsi_id = 7; 878 adv->control = 0xFFFF; 879 880 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050) 881 /* Default to no Ultra to support the 3030 */ 882 adv->control &= ~ADV_CNTL_SDTR_ENABLE_ULTRA; 883 sync_data = ADV_DEF_SDTR_OFFSET | (ADV_DEF_SDTR_INDEX << 4); 884 for (i = 0; i <= ADV_MAX_TID; i++) { 885 adv_sdtr_to_period_offset(adv, sync_data, 886 &adv->tinfo[i].user.period, 887 &adv->tinfo[i].user.offset, 888 i); 889 } 890 config_lsw |= ADV_CFG_LSW_SCSI_PARITY_ON; 891 } 892 config_msw &= ~ADV_CFG_MSW_CLR_MASK; 893 config_lsw |= ADV_CFG_LSW_HOST_INT_ON; 894 if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA) 895 && (adv->control & ADV_CNTL_SDTR_ENABLE_ULTRA) == 0) 896 /* 25ns or 10MHz */ 897 max_sync = 25; 898 else 899 /* Unlimited */ 900 max_sync = 0; 901 for (i = 0; i <= ADV_MAX_TID; i++) { 902 if (adv->tinfo[i].user.period < max_sync) 903 adv->tinfo[i].user.period = max_sync; 904 } 905 906 if (adv_test_external_lram(adv) == 0) { 907 if ((adv->type & (ADV_PCI|ADV_ULTRA)) == (ADV_PCI|ADV_ULTRA)) { 908 eeprom_config.max_total_qng = 909 ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 910 eeprom_config.max_tag_qng = 911 ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG; 912 } else { 913 eeprom_config.cfg_msw |= 0x0800; 914 config_msw |= 0x0800; 915 eeprom_config.max_total_qng = 916 ADV_MAX_PCI_INRAM_TOTAL_QNG; 917 eeprom_config.max_tag_qng = ADV_MAX_INRAM_TAG_QNG; 918 } 919 adv->max_openings = eeprom_config.max_total_qng; 920 } 921 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw); 922 ADV_OUTW(adv, ADV_CONFIG_LSW, config_lsw); 923 #if 0 924 /* 925 * Don't write the eeprom data back for now. 926 * I'd rather not mess up the user's card. We also don't 927 * fully sanitize the eeprom settings above for the write-back 928 * to be 100% correct. 929 */ 930 if (adv_set_eeprom_config(adv, &eeprom_config) != 0) 931 printf("%s: WARNING! Failure writing to EEPROM.\n", 932 adv_name(adv)); 933 #endif 934 935 adv_set_chip_scsiid(adv, adv->scsi_id); 936 if (adv_init_lram_and_mcode(adv)) 937 return (1); 938 939 adv->disc_enable = adv->user_disc_enable; 940 941 adv_write_lram_8(adv, ADVV_DISC_ENABLE_B, adv->disc_enable); 942 for (i = 0; i <= ADV_MAX_TID; i++) { 943 /* 944 * Start off in async mode. 945 */ 946 adv_set_syncrate(adv, /*struct cam_path */NULL, 947 i, /*period*/0, /*offset*/0, 948 ADV_TRANS_CUR); 949 /* 950 * Enable the use of tagged commands on all targets. 951 * This allows the kernel driver to make up it's own mind 952 * as it sees fit to tag queue instead of having the 953 * firmware try and second guess the tag_code settins. 954 */ 955 adv_write_lram_8(adv, ADVV_MAX_DVC_QNG_BEG + i, 956 adv->max_openings); 957 } 958 adv_write_lram_8(adv, ADVV_USE_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET); 959 adv_write_lram_8(adv, ADVV_CAN_TAGGED_QNG_B, TARGET_BIT_VECTOR_SET); 960 printf("adv%d: AdvanSys %s Host Adapter, SCSI ID %d, queue depth %d\n", 961 adv->unit, (adv->type & ADV_ULTRA) && (max_sync == 0) 962 ? "Ultra SCSI" : "SCSI", 963 adv->scsi_id, adv->max_openings); 964 return (0); 965 } 966 967 void 968 adv_intr(void *arg) 969 { 970 struct adv_softc *adv; 971 u_int16_t chipstat; 972 u_int16_t saved_ram_addr; 973 u_int8_t ctrl_reg; 974 u_int8_t saved_ctrl_reg; 975 u_int8_t host_flag; 976 977 adv = (struct adv_softc *)arg; 978 979 chipstat = ADV_INW(adv, ADV_CHIP_STATUS); 980 981 /* Is it for us? */ 982 if ((chipstat & (ADV_CSW_INT_PENDING|ADV_CSW_SCSI_RESET_LATCH)) == 0) 983 return; 984 985 ctrl_reg = ADV_INB(adv, ADV_CHIP_CTRL); 986 saved_ctrl_reg = ctrl_reg & (~(ADV_CC_SCSI_RESET | ADV_CC_CHIP_RESET | 987 ADV_CC_SINGLE_STEP | ADV_CC_DIAG | 988 ADV_CC_TEST)); 989 990 if ((chipstat & (ADV_CSW_SCSI_RESET_LATCH|ADV_CSW_SCSI_RESET_ACTIVE))) { 991 printf("Detected Bus Reset\n"); 992 adv_reset_bus(adv, /*initiate_reset*/FALSE); 993 return; 994 } 995 996 if ((chipstat & ADV_CSW_INT_PENDING) != 0) { 997 998 saved_ram_addr = ADV_INW(adv, ADV_LRAM_ADDR); 999 host_flag = adv_read_lram_8(adv, ADVV_HOST_FLAG_B); 1000 adv_write_lram_8(adv, ADVV_HOST_FLAG_B, 1001 host_flag | ADV_HOST_FLAG_IN_ISR); 1002 1003 adv_ack_interrupt(adv); 1004 1005 if ((chipstat & ADV_CSW_HALTED) != 0 1006 && (ctrl_reg & ADV_CC_SINGLE_STEP) != 0) { 1007 adv_isr_chip_halted(adv); 1008 saved_ctrl_reg &= ~ADV_CC_HALT; 1009 } else { 1010 adv_run_doneq(adv); 1011 } 1012 ADV_OUTW(adv, ADV_LRAM_ADDR, saved_ram_addr); 1013 #ifdef DIAGNOSTIC 1014 if (ADV_INW(adv, ADV_LRAM_ADDR) != saved_ram_addr) 1015 panic("adv_intr: Unable to set LRAM addr"); 1016 #endif 1017 adv_write_lram_8(adv, ADVV_HOST_FLAG_B, host_flag); 1018 } 1019 1020 ADV_OUTB(adv, ADV_CHIP_CTRL, saved_ctrl_reg); 1021 } 1022 1023 void 1024 adv_run_doneq(struct adv_softc *adv) 1025 { 1026 struct adv_q_done_info scsiq; 1027 u_int doneq_head; 1028 u_int done_qno; 1029 1030 doneq_head = adv_read_lram_16(adv, ADVV_DONE_Q_TAIL_W) & 0xFF; 1031 done_qno = adv_read_lram_8(adv, ADV_QNO_TO_QADDR(doneq_head) 1032 + ADV_SCSIQ_B_FWD); 1033 while (done_qno != ADV_QLINK_END) { 1034 union ccb* ccb; 1035 struct adv_ccb_info *cinfo; 1036 u_int done_qaddr; 1037 u_int sg_queue_cnt; 1038 int aborted; 1039 1040 done_qaddr = ADV_QNO_TO_QADDR(done_qno); 1041 1042 /* Pull status from this request */ 1043 sg_queue_cnt = adv_copy_lram_doneq(adv, done_qaddr, &scsiq, 1044 adv->max_dma_count); 1045 1046 /* Mark it as free */ 1047 adv_write_lram_8(adv, done_qaddr + ADV_SCSIQ_B_STATUS, 1048 scsiq.q_status & ~(QS_READY|QS_ABORTED)); 1049 1050 /* Process request based on retrieved info */ 1051 if ((scsiq.cntl & QC_SG_HEAD) != 0) { 1052 u_int i; 1053 1054 /* 1055 * S/G based request. Free all of the queue 1056 * structures that contained S/G information. 1057 */ 1058 for (i = 0; i < sg_queue_cnt; i++) { 1059 done_qno = adv_read_lram_8(adv, done_qaddr 1060 + ADV_SCSIQ_B_FWD); 1061 1062 #ifdef DIAGNOSTIC 1063 if (done_qno == ADV_QLINK_END) { 1064 panic("adv_qdone: Corrupted SG " 1065 "list encountered"); 1066 } 1067 #endif 1068 done_qaddr = ADV_QNO_TO_QADDR(done_qno); 1069 1070 /* Mark SG queue as free */ 1071 adv_write_lram_8(adv, done_qaddr 1072 + ADV_SCSIQ_B_STATUS, QS_FREE); 1073 } 1074 } else 1075 sg_queue_cnt = 0; 1076 #ifdef DIAGNOSTIC 1077 if (adv->cur_active < (sg_queue_cnt + 1)) 1078 panic("adv_qdone: Attempting to free more " 1079 "queues than are active"); 1080 #endif 1081 adv->cur_active -= sg_queue_cnt + 1; 1082 1083 aborted = (scsiq.q_status & QS_ABORTED) != 0; 1084 1085 if ((scsiq.q_status != QS_DONE) 1086 && (scsiq.q_status & QS_ABORTED) == 0) 1087 panic("adv_qdone: completed scsiq with unknown status"); 1088 1089 scsiq.remain_bytes += scsiq.extra_bytes; 1090 1091 if ((scsiq.d3.done_stat == QD_WITH_ERROR) && 1092 (scsiq.d3.host_stat == QHSTA_M_DATA_OVER_RUN)) { 1093 if ((scsiq.cntl & (QC_DATA_IN|QC_DATA_OUT)) == 0) { 1094 scsiq.d3.done_stat = QD_NO_ERROR; 1095 scsiq.d3.host_stat = QHSTA_NO_ERROR; 1096 } 1097 } 1098 1099 cinfo = &adv->ccb_infos[scsiq.d2.ccb_index]; 1100 ccb = cinfo->ccb; 1101 ccb->csio.resid = scsiq.remain_bytes; 1102 adv_done(adv, ccb, 1103 scsiq.d3.done_stat, scsiq.d3.host_stat, 1104 scsiq.d3.scsi_stat, scsiq.q_no); 1105 1106 doneq_head = done_qno; 1107 done_qno = adv_read_lram_8(adv, done_qaddr + ADV_SCSIQ_B_FWD); 1108 } 1109 adv_write_lram_16(adv, ADVV_DONE_Q_TAIL_W, doneq_head); 1110 } 1111 1112 1113 void 1114 adv_done(struct adv_softc *adv, union ccb *ccb, u_int done_stat, 1115 u_int host_stat, u_int scsi_status, u_int q_no) 1116 { 1117 struct adv_ccb_info *cinfo; 1118 1119 cinfo = (struct adv_ccb_info *)ccb->ccb_h.ccb_cinfo_ptr; 1120 LIST_REMOVE(&ccb->ccb_h, sim_links.le); 1121 callout_stop(&ccb->ccb_h.timeout_ch); 1122 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1123 bus_dmasync_op_t op; 1124 1125 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 1126 op = BUS_DMASYNC_POSTREAD; 1127 else 1128 op = BUS_DMASYNC_POSTWRITE; 1129 bus_dmamap_sync(adv->buffer_dmat, cinfo->dmamap, op); 1130 bus_dmamap_unload(adv->buffer_dmat, cinfo->dmamap); 1131 } 1132 1133 switch (done_stat) { 1134 case QD_NO_ERROR: 1135 if (host_stat == QHSTA_NO_ERROR) { 1136 ccb->ccb_h.status = CAM_REQ_CMP; 1137 break; 1138 } 1139 xpt_print_path(ccb->ccb_h.path); 1140 printf("adv_done - queue done without error, " 1141 "but host status non-zero(%x)\n", host_stat); 1142 /*FALLTHROUGH*/ 1143 case QD_WITH_ERROR: 1144 switch (host_stat) { 1145 case QHSTA_M_TARGET_STATUS_BUSY: 1146 case QHSTA_M_BAD_QUEUE_FULL_OR_BUSY: 1147 /* 1148 * Assume that if we were a tagged transaction 1149 * the target reported queue full. Otherwise, 1150 * report busy. The firmware really should just 1151 * pass the original status back up to us even 1152 * if it thinks the target was in error for 1153 * returning this status as no other transactions 1154 * from this initiator are in effect, but this 1155 * ignores multi-initiator setups and there is 1156 * evidence that the firmware gets its per-device 1157 * transaction counts screwed up occassionally. 1158 */ 1159 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1160 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0 1161 && host_stat != QHSTA_M_TARGET_STATUS_BUSY) 1162 scsi_status = SCSI_STATUS_QUEUE_FULL; 1163 else 1164 scsi_status = SCSI_STATUS_BUSY; 1165 adv_abort_ccb(adv, ccb->ccb_h.target_id, 1166 ccb->ccb_h.target_lun, 1167 /*ccb*/NULL, CAM_REQUEUE_REQ, 1168 /*queued_only*/TRUE); 1169 /*FALLTHROUGH*/ 1170 case QHSTA_M_NO_AUTO_REQ_SENSE: 1171 case QHSTA_NO_ERROR: 1172 ccb->csio.scsi_status = scsi_status; 1173 switch (scsi_status) { 1174 case SCSI_STATUS_CHECK_COND: 1175 case SCSI_STATUS_CMD_TERMINATED: 1176 ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 1177 /* Structure copy */ 1178 ccb->csio.sense_data = 1179 adv->sense_buffers[q_no - 1]; 1180 /* FALLTHROUGH */ 1181 case SCSI_STATUS_BUSY: 1182 case SCSI_STATUS_RESERV_CONFLICT: 1183 case SCSI_STATUS_QUEUE_FULL: 1184 case SCSI_STATUS_COND_MET: 1185 case SCSI_STATUS_INTERMED: 1186 case SCSI_STATUS_INTERMED_COND_MET: 1187 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1188 break; 1189 case SCSI_STATUS_OK: 1190 ccb->ccb_h.status |= CAM_REQ_CMP; 1191 break; 1192 } 1193 break; 1194 case QHSTA_M_SEL_TIMEOUT: 1195 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 1196 break; 1197 case QHSTA_M_DATA_OVER_RUN: 1198 ccb->ccb_h.status = CAM_DATA_RUN_ERR; 1199 break; 1200 case QHSTA_M_UNEXPECTED_BUS_FREE: 1201 ccb->ccb_h.status = CAM_UNEXP_BUSFREE; 1202 break; 1203 case QHSTA_M_BAD_BUS_PHASE_SEQ: 1204 ccb->ccb_h.status = CAM_SEQUENCE_FAIL; 1205 break; 1206 case QHSTA_M_BAD_CMPL_STATUS_IN: 1207 /* No command complete after a status message */ 1208 ccb->ccb_h.status = CAM_SEQUENCE_FAIL; 1209 break; 1210 case QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT: 1211 case QHSTA_M_WTM_TIMEOUT: 1212 case QHSTA_M_HUNG_REQ_SCSI_BUS_RESET: 1213 /* The SCSI bus hung in a phase */ 1214 ccb->ccb_h.status = CAM_SEQUENCE_FAIL; 1215 adv_reset_bus(adv, /*initiate_reset*/TRUE); 1216 break; 1217 case QHSTA_M_AUTO_REQ_SENSE_FAIL: 1218 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL; 1219 break; 1220 case QHSTA_D_QDONE_SG_LIST_CORRUPTED: 1221 case QHSTA_D_ASC_DVC_ERROR_CODE_SET: 1222 case QHSTA_D_HOST_ABORT_FAILED: 1223 case QHSTA_D_EXE_SCSI_Q_FAILED: 1224 case QHSTA_D_ASPI_NO_BUF_POOL: 1225 case QHSTA_M_BAD_TAG_CODE: 1226 case QHSTA_D_LRAM_CMP_ERROR: 1227 case QHSTA_M_MICRO_CODE_ERROR_HALT: 1228 default: 1229 panic("%s: Unhandled Host status error %x", 1230 adv_name(adv), host_stat); 1231 /* NOTREACHED */ 1232 } 1233 break; 1234 1235 case QD_ABORTED_BY_HOST: 1236 /* Don't clobber any, more explicit, error codes we've set */ 1237 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) 1238 ccb->ccb_h.status = CAM_REQ_ABORTED; 1239 break; 1240 1241 default: 1242 xpt_print_path(ccb->ccb_h.path); 1243 printf("adv_done - queue done with unknown status %x:%x\n", 1244 done_stat, host_stat); 1245 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 1246 break; 1247 } 1248 adv_clear_state(adv, ccb); 1249 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP 1250 && (ccb->ccb_h.status & CAM_DEV_QFRZN) == 0) { 1251 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1); 1252 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1253 } 1254 adv_free_ccb_info(adv, cinfo); 1255 /* 1256 * Null this out so that we catch driver bugs that cause a 1257 * ccb to be completed twice. 1258 */ 1259 ccb->ccb_h.ccb_cinfo_ptr = NULL; 1260 ccb->ccb_h.status &= ~CAM_SIM_QUEUED; 1261 xpt_done(ccb); 1262 } 1263 1264 /* 1265 * Function to poll for command completion when 1266 * interrupts are disabled (crash dumps) 1267 */ 1268 static void 1269 adv_poll(struct cam_sim *sim) 1270 { 1271 adv_intr(cam_sim_softc(sim)); 1272 } 1273 1274 /* 1275 * Attach all the sub-devices we can find 1276 */ 1277 int 1278 adv_attach(adv) 1279 struct adv_softc *adv; 1280 { 1281 struct ccb_setasync csa; 1282 int max_sg; 1283 1284 /* 1285 * Allocate an array of ccb mapping structures. We put the 1286 * index of the ccb_info structure into the queue representing 1287 * a transaction and use it for mapping the queue to the 1288 * upper level SCSI transaction it represents. 1289 */ 1290 adv->ccb_infos = malloc(sizeof(*adv->ccb_infos) * adv->max_openings, 1291 M_DEVBUF, M_WAITOK); 1292 adv->init_level++; 1293 1294 /* 1295 * Create our DMA tags. These tags define the kinds of device 1296 * accessible memory allocations and memory mappings we will 1297 * need to perform during normal operation. 1298 * 1299 * Unless we need to further restrict the allocation, we rely 1300 * on the restrictions of the parent dmat, hence the common 1301 * use of MAXADDR and MAXSIZE. 1302 * 1303 * The ASC boards use chains of "queues" (the transactional 1304 * resources on the board) to represent long S/G lists. 1305 * The first queue represents the command and holds a 1306 * single address and data pair. The queues that follow 1307 * can each hold ADV_SG_LIST_PER_Q entries. Given the 1308 * total number of queues, we can express the largest 1309 * transaction we can map. We reserve a few queues for 1310 * error recovery. Take those into account as well. 1311 * 1312 * There is a way to take an interrupt to download the 1313 * next batch of S/G entries if there are more than 255 1314 * of them (the counter in the queue structure is a u_int8_t). 1315 * We don't use this feature, so limit the S/G list size 1316 * accordingly. 1317 */ 1318 max_sg = (adv->max_openings - ADV_MIN_FREE_Q - 1) * ADV_SG_LIST_PER_Q; 1319 if (max_sg > 255) 1320 max_sg = 255; 1321 1322 /* DMA tag for mapping buffers into device visible space. */ 1323 if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0, 1324 /*lowaddr*/BUS_SPACE_MAXADDR, 1325 /*highaddr*/BUS_SPACE_MAXADDR, 1326 /*filter*/NULL, /*filterarg*/NULL, 1327 /*maxsize*/MAXPHYS, 1328 /*nsegments*/max_sg, 1329 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 1330 /*flags*/BUS_DMA_ALLOCNOW, 1331 &adv->buffer_dmat) != 0) { 1332 return (ENXIO); 1333 } 1334 adv->init_level++; 1335 1336 /* DMA tag for our sense buffers */ 1337 if (bus_dma_tag_create(adv->parent_dmat, /*alignment*/1, /*boundary*/0, 1338 /*lowaddr*/BUS_SPACE_MAXADDR, 1339 /*highaddr*/BUS_SPACE_MAXADDR, 1340 /*filter*/NULL, /*filterarg*/NULL, 1341 sizeof(struct scsi_sense_data)*adv->max_openings, 1342 /*nsegments*/1, 1343 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 1344 /*flags*/0, &adv->sense_dmat) != 0) { 1345 return (ENXIO); 1346 } 1347 1348 adv->init_level++; 1349 1350 /* Allocation for our sense buffers */ 1351 if (bus_dmamem_alloc(adv->sense_dmat, (void **)&adv->sense_buffers, 1352 BUS_DMA_NOWAIT, &adv->sense_dmamap) != 0) { 1353 return (ENOMEM); 1354 } 1355 1356 adv->init_level++; 1357 1358 /* And permanently map them */ 1359 bus_dmamap_load(adv->sense_dmat, adv->sense_dmamap, 1360 adv->sense_buffers, 1361 sizeof(struct scsi_sense_data)*adv->max_openings, 1362 adv_map, &adv->sense_physbase, /*flags*/0); 1363 1364 adv->init_level++; 1365 1366 /* 1367 * Fire up the chip 1368 */ 1369 if (adv_start_chip(adv) != 1) { 1370 printf("adv%d: Unable to start on board processor. Aborting.\n", 1371 adv->unit); 1372 return (ENXIO); 1373 } 1374 1375 /* 1376 * Construct our SIM entry. 1377 */ 1378 adv->sim = cam_sim_alloc(adv_action, adv_poll, "adv", adv, adv->unit, 1379 1, adv->max_openings, NULL); 1380 if (adv->sim == NULL) 1381 return (ENOMEM); 1382 1383 /* 1384 * Register the bus. 1385 * 1386 * XXX Twin Channel EISA Cards??? 1387 */ 1388 if (xpt_bus_register(adv->sim, 0) != CAM_SUCCESS) { 1389 cam_sim_free(adv->sim); 1390 return (ENXIO); 1391 } 1392 1393 if (xpt_create_path(&adv->path, /*periph*/NULL, cam_sim_path(adv->sim), 1394 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) 1395 != CAM_REQ_CMP) { 1396 xpt_bus_deregister(cam_sim_path(adv->sim)); 1397 cam_sim_free(adv->sim); 1398 return (ENXIO); 1399 } 1400 1401 xpt_setup_ccb(&csa.ccb_h, adv->path, /*priority*/5); 1402 csa.ccb_h.func_code = XPT_SASYNC_CB; 1403 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 1404 csa.callback = advasync; 1405 csa.callback_arg = adv; 1406 xpt_action((union ccb *)&csa); 1407 return (0); 1408 } 1409