1 /* 2 * Definitions for low level routines and data structures 3 * for the Advanced Systems Inc. SCSI controllers chips. 4 * 5 * Copyright (c) 1996-1997, 1999-2000 Justin T. Gibbs. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification, immediately at the beginning of the file. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/advansys/advlib.h,v 1.8.2.1 2000/04/14 13:32:50 nyan Exp $ 33 * $DragonFly: src/sys/dev/disk/advansys/advlib.h,v 1.2 2003/06/17 04:28:21 dillon Exp $ 34 */ 35 /* 36 * Ported from: 37 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 38 * 39 * Copyright (c) 1995-1996 Advanced System Products, Inc. 40 * All Rights Reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that redistributions of source 44 * code retain the above copyright notice and this comment without 45 * modification. 46 */ 47 48 #ifndef _ADVLIB_H_ 49 #define _ADVLIB_H_ 50 51 #include <sys/queue.h> 52 53 struct cam_path; 54 union ccb; 55 56 typedef u_int8_t target_bit_vector; 57 #define TARGET_BIT_VECTOR_SET -1 58 #define ADV_SCSI_ID_BITS 3 59 #define ADV_MAX_TID 7 60 #define ADV_MAX_LUN 7 61 62 /* Enumeration of board types */ 63 typedef enum { 64 ADV_NONE = 0x000, 65 ADV_ISA = 0x001, 66 ADV_ISAPNP = 0x003, 67 ADV_VL = 0x004, 68 ADV_EISA = 0x008, 69 ADV_PCI = 0x010, 70 ADV_MCA = 0x020, 71 ADV_PCMCIA = 0x040, 72 ADV_ULTRA = 0x100, 73 ADV_WIDE = 0x200, 74 ADV_WIDE32 = 0x400 75 } adv_btype; 76 77 typedef enum { 78 ADV_STATE_NONE = 0x00, 79 ADV_RESOURCE_SHORTAGE = 0x01, 80 ADV_IN_TIMEOUT = 0x02, 81 ADV_BUSDMA_BLOCK = 0x04, 82 ADV_BUSDMA_BLOCK_CLEARED = 0x08 83 84 } adv_state; 85 86 typedef enum { 87 ACCB_FREE = 0x00, 88 ACCB_ACTIVE = 0x01, 89 ACCB_ABORT_QUEUED = 0x02, 90 ACCB_RECOVERY_CCB = 0x04 91 } adv_ccb_state; 92 93 struct adv_ccb_info { 94 adv_ccb_state state; 95 bus_dmamap_t dmamap; 96 union ccb* ccb; 97 SLIST_ENTRY(adv_ccb_info) links; 98 }; 99 100 #define ccb_cinfo_ptr spriv_ptr0 101 102 #define ADV_SYN_XFER_NO 8 103 #define ADV_SYN_MAX_OFFSET 0x0F 104 #define ADV_DEF_SDTR_OFFSET 0x0F 105 #define ADV_DEF_SDTR_INDEX 0x00 106 #define ADV_OVERRUN_BSIZE 0x00000040 107 #define ADV_MAX_CDB_LEN 12 108 #define ADV_MAX_SENSE_LEN 32 109 #define ADV_MIN_SENSE_LEN 14 110 111 #define ADV_TIDLUN_TO_IX(tid, lun) ((tid) | ((lun) << ADV_SCSI_ID_BITS) ) 112 #define ADV_TID_TO_TARGET_MASK(tid) (0x01 << (tid)) 113 #define ADV_TIX_TO_TARGET_MASK(tix) (0x01 << ((tix) & ADV_MAX_TID)) 114 #define ADV_TIX_TO_TID(tix) ((tix) & ADV_MAX_TID) 115 #define ADV_TID_TO_TIX(tid) ((tid) & ADV_MAX_TID) 116 #define ADV_TIX_TO_LUN(tix) (((tix) >> ADV_SCSI_ID_BITS) & ADV_MAX_LUN ) 117 118 119 /* 120 * XXX 121 * PnP port addresses 122 * I believe that these are standard PnP address and should be replaced 123 * by the values in a central ISA PnP header file when we get one. 124 */ 125 #define ADV_ISA_PNP_PORT_ADDR (0x279) 126 #define ADV_ISA_PNP_PORT_WRITE (ADV_ISA_PNP_PORT_ADDR+0x800) 127 128 /* 129 * Board Signatures 130 */ 131 #define ADV_SIGNATURE_WORD 0x0000 132 #define ADV_1000_ID0W 0x04C1 133 #define ADV_1000_ID0W_FIX 0x00C1 134 135 #define ADV_SIGNATURE_BYTE 0x0001 136 #define ADV_1000_ID1B 0x25 137 138 #define ADV_REG_IH 0x0002 139 #define ADV_INS_HALTINT 0x6281 140 #define ADV_INS_HALT 0x6280 141 #define ADV_INS_SINT 0x6200 142 #define ADV_INS_RFLAG_WTM 0x7380 143 144 #define ADV_CONFIG_LSW 0x0002 145 #define ADV_CFG_LSW_ISA_DMA_CHANNEL 0x0003 146 #define ADV_CFG_LSW_HOST_INT_ON 0x0020 147 #define ADV_CFG_LSW_BIOS_ON 0x0040 148 #define ADV_CFG_LSW_VERA_BURST_ON 0x0080 149 #define ADV_CFG_LSW_SCSI_PARITY_ON 0x0800 150 #define ADV_CFG_LSW_SCSIID 0x0700 151 #define ADV_CFG_LSW_SCSIID_SHIFT 8 152 #define ADV_CONFIG_SCSIID(cfg) ((cfg >> ADV_CFG_LSW_SCSIID_SHIFT) & ADV_MAX_TID) 153 154 /* 155 * Chip Revision Number 156 */ 157 #define ADV_NONEISA_CHIP_REVISION 0x0003 158 #define ADV_CHIP_MIN_VER_VL 0x01 159 #define ADV_CHIP_MAX_VER_VL 0x07 160 #define ADV_CHIP_MIN_VER_PCI 0x09 161 #define ADV_CHIP_MAX_VER_PCI 0x0F 162 #define ADV_CHIP_VER_PCI_BIT 0x08 163 #define ADV_CHIP_VER_PCI_ULTRA_3150 (ADV_CHIP_VER_PCI_BIT | 0x02) 164 #define ADV_CHIP_VER_PCI_ULTRA_3050 (ADV_CHIP_VER_PCI_BIT | 0x03) 165 #define ADV_CHIP_MIN_VER_ISA 0x11 166 #define ADV_CHIP_MIN_VER_ISA_PNP 0x21 167 #define ADV_CHIP_MAX_VER_ISA 0x27 168 #define ADV_CHIP_VER_ISA_BIT 0x30 169 #define ADV_CHIP_VER_ISAPNP_BIT 0x20 170 #define ADV_CHIP_VER_ASYN_BUG 0x21 171 #define ADV_CHIP_MIN_VER_EISA 0x41 172 #define ADV_CHIP_MAX_VER_EISA 0x47 173 #define ADV_CHIP_VER_EISA_BIT 0x40 174 175 #define ADV_CONFIG_MSW 0x0004 176 #define ADV_CFG_MSW_SCSI_TARGET_ON 0x0080 177 #define ADV_CFG_MSW_LRAM_8BITS_ON 0x0800 178 #define ADV_CFG_MSW_CLR_MASK 0x30C0 179 180 #define ADV_EEPROM_DATA 0x0006 181 182 #define ADV_EEPROM_CMD 0x0007 183 #define ADV_EEPROM_CMD_READ 0x80 184 #define ADV_EEPROM_CMD_WRITE 0x40 185 #define ADV_EEPROM_CMD_WRITE_ENABLE 0x30 186 #define ADV_EEPROM_CMD_WRITE_DISABLE 0x00 187 188 #define ADV_DMA_SPEED 0x0007 189 #define ADV_DEF_ISA_DMA_SPEED 4 190 #define ADV_REG_FLAG 0x0007 191 192 #define ADV_LRAM_DATA 0x0008 193 194 #define ADV_LRAM_ADDR 0x000A 195 196 #define ADV_SYN_OFFSET 0x000B 197 198 #define ADV_REG_PROG_COUNTER 0x000C 199 #define ADV_MCODE_START_ADDR 0x0080 200 201 #define ADV_REG_IFC 0x000D 202 #define ADV_IFC_REG_LOCK 0x00 203 #define ADV_IFC_REG_UNLOCK 0x09 204 #define ADV_IFC_WR_EN_FILTER 0x10 205 #define ADV_IFC_RD_NO_EEPROM 0x10 206 #define ADV_IFC_SLEW_RATE 0x20 207 #define ADV_IFC_ACT_NEG 0x40 208 #define ADV_IFC_INP_FILTER 0x80 209 #define ADV_IFC_INIT_DEFAULT (ADV_IFC_ACT_NEG | ADV_IFC_REG_UNLOCK) 210 211 #define ADV_CHIP_STATUS 0x000E 212 #define ADV_CSW_TEST1 0x8000 213 #define ADV_CSW_AUTO_CONFIG 0x4000 214 #define ADV_CSW_RESERVED1 0x2000 215 #define ADV_CSW_IRQ_WRITTEN 0x1000 216 #define ADV_CSW_33MHZ_SELECTED 0x0800 217 #define ADV_CSW_TEST2 0x0400 218 #define ADV_CSW_TEST3 0x0200 219 #define ADV_CSW_RESERVED2 0x0100 220 #define ADV_CSW_DMA_DONE 0x0080 221 #define ADV_CSW_FIFO_RDY 0x0040 222 #define ADV_CSW_EEP_READ_DONE 0x0020 223 #define ADV_CSW_HALTED 0x0010 224 #define ADV_CSW_SCSI_RESET_ACTIVE 0x0008 225 #define ADV_CSW_PARITY_ERR 0x0004 226 #define ADV_CSW_SCSI_RESET_LATCH 0x0002 227 #define ADV_CSW_INT_PENDING 0x0001 228 /* 229 * XXX I don't understand the relevence of the naming 230 * convention change here. What does CIW stand for? 231 * Perhaps this is to differentiate read and write 232 * values? 233 */ 234 #define ADV_CIW_INT_ACK 0x0100 235 #define ADV_CIW_TEST1 0x0200 236 #define ADV_CIW_TEST2 0x0400 237 #define ADV_CIW_SEL_33MHZ 0x0800 238 #define ADV_CIW_IRQ_ACT 0x1000 239 #define ADV_CIW_CLR_SCSI_RESET_INT 0x1000 240 241 #define ADV_CHIP_CTRL 0x000F 242 #define ADV_CC_CHIP_RESET 0x80 243 #define ADV_CC_SCSI_RESET 0x40 244 #define ADV_CC_HALT 0x20 245 #define ADV_CC_SINGLE_STEP 0x10 246 #define ADV_CC_DMA_ENABLE 0x08 247 #define ADV_CC_TEST 0x04 248 #define ADV_CC_BANK_ONE 0x02 249 #define ADV_CC_DIAG 0x01 250 251 #define ADV_HALTCODE_W 0x0040 252 #define ADV_STOP_CODE_B 0x0034 253 #define ADV_STOP_REQ_RISC_STOP 0x01 254 #define ADV_STOP_ACK_RISC_STOP 0x03 255 #define ADV_STOP_CLEAN_UP_BUSY_Q 0x10 256 #define ADV_STOP_CLEAN_UP_DISC_Q 0x20 257 #define ADV_STOP_HOST_REQ_RISC_HALT 0x40 258 259 /* 260 * EEPROM routine constants 261 * XXX What about wide controllers? 262 * Surely they have space for 8 more targets. 263 */ 264 #define ADV_EEPROM_CFG_BEG_VL 2 265 #define ADV_EEPROM_MAX_ADDR_VL 15 266 #define ADV_EEPROM_CFG_BEG 32 267 #define ADV_EEPROM_MAX_ADDR 45 268 #define ADV_EEPROM_MAX_RETRY 20 269 270 struct adv_eeprom_config { 271 u_int16_t cfg_lsw; 272 273 u_int16_t cfg_msw; 274 275 u_int8_t init_sdtr; 276 u_int8_t disc_enable; 277 278 u_int8_t use_cmd_qng; 279 u_int8_t start_motor; 280 281 u_int8_t max_total_qng; 282 u_int8_t max_tag_qng; 283 284 u_int8_t bios_scan; 285 u_int8_t power_up_wait; 286 287 u_int8_t no_scam; 288 u_int8_t scsi_id_dma_speed; 289 #define EEPROM_SCSI_ID_MASK 0x0F 290 #define EEPROM_DMA_SPEED_MASK 0xF0 291 #define EEPROM_DMA_SPEED(ep) \ 292 (((ep).scsi_id_dma_speed & EEPROM_DMA_SPEED_MASK) >> 4) 293 #define EEPROM_SET_DMA_SPEED(ep, speed) \ 294 (ep).scsi_id_dma_speed &= ~EEPROM_DMA_SPEED_MASK; \ 295 (ep).scsi_id_dma_speed |= \ 296 (((speed) << 4) & EEPROM_DMA_SPEED_MASK) 297 #define EEPROM_SCSIID(ep) ((ep).scsi_id_dma_speed & EEPROM_SCSI_ID_MASK) 298 #define EEPROM_SET_SCSIID(ep, id) \ 299 (ep).scsi_id_dma_speed &= ~EEPROM_SCSI_ID_MASK; \ 300 (ep).scsi_id_dma_speed |= ((id) & EEPROM_SCSI_ID_MASK) 301 u_int8_t sdtr_data[8]; 302 u_int8_t adapter_info[6]; 303 304 u_int16_t cntl; 305 306 u_int16_t chksum; 307 }; 308 309 /* Bank 1 */ 310 #define ADV_SEQ_ACCUM 0x0000 311 #define ADV_QUEUE_ELEMENT_INDEX 0x0001 312 #define ADV_SEQ_INSTRUCTION_HOLD 0x0002 313 #define ADV_QUEUE_ELEMENT_POINTER 0x0003 314 #define ADV_HOST_DATA_FIFO_L 0x0004 315 #define ADV_HOST_SCSIID 0x0005 316 #define ADV_HOST_DATA_FIFO_H 0x0006 317 #define ADV_SCSI_CONTROL 0x0009 318 #define SC_SEL 0x80 319 #define SC_BSY 0x40 320 #define SC_ACK 0x20 321 #define SC_REQ 0x10 322 #define SC_ATN 0x08 323 #define SC_IO 0x04 324 #define SC_CD 0x02 325 #define SC_MSG 0x01 326 #define ADV_SCSIDATL 0x000B 327 #define ADV_DMA_TRANSFER_CNT 0x000C 328 #define ADV_DMA_TRANSFER_CNT1 0x000E 329 330 /* 331 * Instruction data and code segment addresses, 332 * and transaction address translation (queues). 333 * All addresses refer to on board LRAM. 334 */ 335 #define ADV_DATA_SEC_BEG 0x0080 336 #define ADV_DATA_SEC_END 0x0080 337 #define ADV_CODE_SEC_BEG 0x0080 338 #define ADV_CODE_SEC_END 0x0080 339 #define ADV_QADR_BEG 0x4000 340 #define ADV_QADR_END 0x7FFF 341 #define ADV_QLAST_ADR 0x7FC0 342 #define ADV_QBLK_SIZE 0x40 343 #define ADV_BIOS_DATA_QBEG 0xF8 344 #define ADV_MAX_QNO 0xF8 345 #define ADV_QADR_USED (ADV_MAX_QNO * 64) 346 #define ADV_QNO_TO_QADDR(q_no) ((ADV_QADR_BEG) + ((u_int16_t)(q_no) << 6)) 347 348 #define ADV_MIN_ACTIVE_QNO 0x01 349 #define ADV_QLINK_END 0xFF 350 351 #define ADV_MAX_SG_QUEUE 5 352 #define ADV_SG_LIST_PER_Q 7 353 #define ADV_MAX_SG_LIST (1 + ((ADV_SG_LIST_PER_Q) * (ADV_MAX_SG_QUEUE))) 354 355 #define ADV_MIN_REMAIN_Q 0x02 356 #define ADV_DEF_MAX_TOTAL_QNG 0xF0 357 #define ADV_MIN_TAG_Q_PER_DVC 0x04 358 #define ADV_DEF_TAG_Q_PER_DVC 0x04 359 #define ADV_MIN_FREE_Q ADV_MIN_REMAIN_Q 360 #define ADV_MIN_TOTAL_QNG ((ADV_MAX_SG_QUEUE)+(ADV_MIN_FREE_Q)) 361 #define ADV_MAX_TOTAL_QNG 240 362 #define ADV_MAX_INRAM_TAG_QNG 16 363 #define ADV_MAX_PCI_INRAM_TOTAL_QNG 20 364 #define ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16 365 #define ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG 8 366 367 #define ADV_DEF_IRQ_NO 10 368 #define ADV_MAX_IRQ_NO 15 369 #define ADV_MIN_IRQ_NO 10 370 371 #define ADV_SCSIQ_CPY_BEG 4 372 #define ADV_SCSIQ_SGHD_CPY_BEG 2 373 374 /* SCSIQ Microcode representation offsets */ 375 #define ADV_SCSIQ_B_FWD 0 376 #define ADV_SCSIQ_B_BWD 1 377 #define ADV_SCSIQ_B_STATUS 2 378 #define ADV_SCSIQ_B_QNO 3 379 #define ADV_SCSIQ_B_CNTL 4 380 #define ADV_SCSIQ_B_SG_QUEUE_CNT 5 381 #define ADV_SCSIQ_B_LIST_CNT 6 382 #define ADV_SCSIQ_B_CUR_LIST_CNT 7 383 #define ADV_SCSIQ_D_DATA_ADDR 8 384 #define ADV_SCSIQ_D_DATA_CNT 12 385 #define ADV_SCSIQ_B_SENSE_LEN 20 386 #define ADV_SCSIQ_DONE_INFO_BEG 22 387 #define ADV_SCSIQ_D_CINFO_IDX 22 388 #define ADV_SCSIQ_B_TARGET_IX 26 389 #define ADV_SCSIQ_B_CDB_LEN 28 390 #define ADV_SCSIQ_B_TAG_CODE 29 391 #define ADV_SCSIQ_W_VM_ID 30 392 #define ADV_SCSIQ_DONE_STATUS 32 393 #define ADV_SCSIQ_HOST_STATUS 33 394 #define ADV_SCSIQ_SCSI_STATUS 34 395 #define ADV_SCSIQ_CDB_BEG 36 396 #define ADV_SCSIQ_B_FIRST_SG_QK_QP 48 397 #define ADV_SCSIQ_B_SG_WK_QP 49 398 #define ADV_SCSIQ_B_SG_WK_IX 50 399 #define ADV_SCSIQ_W_ALT_DC1 52 400 #define ADV_SCSIQ_DW_REMAIN_XFER_ADDR 56 401 #define ADV_SCSIQ_DW_REMAIN_XFER_CNT 60 402 403 /* LRAM Offsets */ 404 #define ADVV_MSGOUT_BEG 0x0000 405 #define ADVV_MSGOUT_SDTR_PERIOD (ADVV_MSGOUT_BEG+3) 406 #define ADVV_MSGOUT_SDTR_OFFSET (ADVV_MSGOUT_BEG+4) 407 408 #define ADVV_BREAK_SAVED_CODE 0x0006 409 410 #define ADVV_MSGIN_BEG (ADVV_MSGOUT_BEG+8) 411 #define ADVV_MSGIN_SDTR_PERIOD (ADVV_MSGIN_BEG+3) 412 #define ADVV_MSGIN_SDTR_OFFSET (ADVV_MSGIN_BEG+4) 413 414 #define ADVV_SDTR_DATA_BEG (ADVV_MSGIN_BEG+8) 415 #define ADVV_SDTR_DONE_BEG (ADVV_SDTR_DATA_BEG+8) 416 #define ADVV_MAX_DVC_QNG_BEG 0x0020 417 418 #define ADVV_BREAK_ADDR 0x0028 419 #define ADVV_BREAK_NOTIFY_COUNT 0x002A 420 #define ADVV_BREAK_CONTROL 0x002C 421 #define ADVV_BREAK_HIT_COUNT 0x002E 422 423 #define ADVV_ASCDVC_ERR_CODE_W 0x0030 424 #define ADVV_MCODE_CHKSUM_W 0x0032 425 #define ADVV_MCODE_SIZE_W 0x0034 426 #define ADVV_STOP_CODE_B 0x0036 427 #define ADVV_DVC_ERR_CODE_B 0x0037 428 429 #define ADVV_OVERRUN_PADDR_D 0x0038 430 #define ADVV_OVERRUN_BSIZE_D 0x003C 431 432 #define ADVV_HALTCODE_W 0x0040 433 #define ADV_HALT_EXTMSG_IN 0x8000 434 #define ADV_HALT_CHK_CONDITION 0x8100 435 #define ADV_HALT_SS_QUEUE_FULL 0x8200 436 #define ADV_HALT_DISABLE_ASYN_USE_SYN_FIX 0x8300 437 #define ADV_HALT_ENABLE_ASYN_USE_SYN_FIX 0x8400 438 #define ADV_HALT_SDTR_REJECTED 0x4000 439 #define ADV_HALT_HOST_COPY_SG_LIST_TO_RISC 0x2000 440 441 #define ADVV_CHKSUM_W 0x0042 442 #define ADVV_MC_DATE_W 0x0044 443 #define ADVV_MC_VER_W 0x0046 444 #define ADVV_NEXTRDY_B 0x0048 445 #define ADVV_DONENEXT_B 0x0049 446 #define ADVV_USE_TAGGED_QNG_B 0x004A 447 #define ADVV_SCSIBUSY_B 0x004B 448 #define ADVV_Q_DONE_IN_PROGRESS_B 0x004C 449 #define ADVV_CURCDB_B 0x004D 450 #define ADVV_RCLUN_B 0x004E 451 #define ADVV_BUSY_QHEAD_B 0x004F 452 #define ADVV_DISC1_QHEAD_B 0x0050 453 454 #define ADVV_DISC_ENABLE_B 0x0052 455 #define ADVV_CAN_TAGGED_QNG_B 0x0053 456 #define ADVV_HOSTSCSI_ID_B 0x0055 457 #define ADVV_MCODE_CNTL_B 0x0056 458 #define ADVV_NULL_TARGET_B 0x0057 459 460 #define ADVV_FREE_Q_HEAD_W 0x0058 461 #define ADVV_DONE_Q_TAIL_W 0x005A 462 #define ADVV_FREE_Q_HEAD_B (ADVV_FREE_Q_HEAD_W+1) 463 #define ADVV_DONE_Q_TAIL_B (ADVV_DONE_Q_TAIL_W+1) 464 465 #define ADVV_HOST_FLAG_B 0x005D 466 #define ADV_HOST_FLAG_IN_ISR 0x01 467 #define ADV_HOST_FLAG_ACK_INT 0x02 468 469 470 #define ADVV_TOTAL_READY_Q_B 0x0064 471 #define ADVV_VER_SERIAL_B 0x0065 472 #define ADVV_HALTCODE_SAVED_W 0x0066 473 #define ADVV_WTM_FLAG_B 0x0068 474 #define ADVV_RISC_FLAG_B 0x006A 475 #define ADV_RISC_FLAG_GEN_INT 0x01 476 #define ADV_RISC_FLAG_REQ_SG_LIST 0x02 477 478 #define ADVV_REQ_SG_LIST_QP 0x006B 479 480 #define ADV_TRANS_CUR 0x01 /* Modify current neogtiation status */ 481 #define ADV_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 482 #define ADV_TRANS_GOAL 0x04 /* Modify negotiation goal */ 483 #define ADV_TRANS_USER 0x08 /* Modify user negotiation settings */ 484 485 struct adv_transinfo { 486 u_int8_t period; 487 u_int8_t offset; 488 }; 489 490 struct adv_target_transinfo { 491 struct adv_transinfo current; 492 struct adv_transinfo goal; 493 struct adv_transinfo user; 494 }; 495 496 struct adv_softc { 497 device_t dev; 498 bus_space_tag_t tag; 499 bus_space_handle_t bsh; 500 struct cam_sim *sim; 501 LIST_HEAD(, ccb_hdr) pending_ccbs; 502 struct adv_ccb_info *ccb_infos; 503 SLIST_HEAD(, adv_ccb_info) free_ccb_infos; 504 bus_dma_tag_t parent_dmat; 505 bus_dma_tag_t buffer_dmat; 506 bus_dma_tag_t sense_dmat; 507 bus_dmamap_t sense_dmamap; 508 struct scsi_sense_data *sense_buffers; 509 bus_addr_t sense_physbase; 510 bus_addr_t overrun_physbase; 511 adv_btype type; 512 struct adv_target_transinfo tinfo[8]; 513 target_bit_vector fix_asyn_xfer; 514 target_bit_vector fix_asyn_xfer_always; 515 target_bit_vector disc_enable; 516 target_bit_vector user_disc_enable; 517 target_bit_vector cmd_qng_enabled; 518 target_bit_vector user_cmd_qng_enabled; 519 u_int16_t control; 520 #define ADV_CNTL_INITIATOR 0x0001 521 #define ADV_CNTL_BIOS_GT_1GB 0x0002 522 #define ADV_CNTL_BIOS_GT_2_DISK 0x0004 523 #define ADV_CNTL_BIOS_REMOVABLE 0x0008 524 #define ADV_CNTL_NO_SCAM 0x0010 525 #define ADV_CNTL_INT_MULTI_Q 0x0080 526 #define ADV_CNTL_NO_LUN_SUPPORT 0x0040 527 #define ADV_CNTL_NO_VERIFY_COPY 0x0100 528 #define ADV_CNTL_RESET_SCSI 0x0200 529 #define ADV_CNTL_INIT_INQUIRY 0x0400 530 #define ADV_CNTL_INIT_VERBOSE 0x0800 531 #define ADV_CNTL_SCSI_PARITY 0x1000 532 #define ADV_CNTL_BURST_MODE 0x2000 533 #define ADV_CNTL_SDTR_ENABLE_ULTRA 0x4000 534 535 u_int16_t bug_fix_control; 536 #define ADV_BUG_FIX_IF_NOT_DWB 0x0001 537 #define ADV_BUG_FIX_ASYN_USE_SYN 0x0002 538 539 adv_state state; 540 struct cam_path *path; 541 int unit; 542 int init_level; 543 u_int32_t max_dma_addr; 544 u_int32_t max_dma_count; 545 u_int8_t isa_dma_speed; 546 u_int8_t isa_dma_channel; 547 u_int8_t scsi_id; 548 u_int8_t chip_version; 549 u_int8_t max_tags_per_target; 550 u_int8_t max_openings; 551 u_int8_t cur_active; 552 u_int8_t openings_needed; 553 u_int8_t ccb_infos_allocated; 554 u_int8_t *sdtr_period_tbl; 555 u_int8_t sdtr_period_tbl_size; 556 }; 557 558 /* 559 * Structures for talking to the RISC engine. 560 */ 561 struct adv_scsiq_1 { 562 u_int8_t status; 563 #define QS_FREE 0x00 564 #define QS_READY 0x01 565 #define QS_DISC1 0x02 566 #define QS_DISC2 0x04 567 #define QS_BUSY 0x08 568 #define QS_ABORTED 0x40 569 #define QS_DONE 0x80 570 571 u_int8_t q_no; /* 572 * Queue ID of the first queue 573 * used in this transaction. 574 */ 575 u_int8_t cntl; 576 #define QC_NO_CALLBACK 0x01 577 #define QC_SG_SWAP_QUEUE 0x02 578 #define QC_SG_HEAD 0x04 579 #define QC_DATA_IN 0x08 580 #define QC_DATA_OUT 0x10 581 #define QC_URGENT 0x20 582 #define QC_MSG_OUT 0x40 583 #define QC_REQ_SENSE 0x80 584 585 u_int8_t sg_queue_cnt; /* Number of SG entries */ 586 587 u_int8_t target_id; /* target id as a bit vector */ 588 u_int8_t target_lun; /* LUN - taken from our xs */ 589 590 u_int32_t data_addr; /* 591 * physical addres of first 592 * (possibly only) segment 593 * to transfer. 594 */ 595 u_int32_t data_cnt; /* 596 * byte count of the first 597 * (possibly only) segment 598 * to transfer. 599 */ 600 u_int32_t sense_addr; /* 601 * physical address of the sense 602 * buffer. 603 */ 604 u_int8_t sense_len; /* length of sense buffer */ 605 u_int8_t extra_bytes; 606 }; 607 608 struct adv_scsiq_2 { 609 u_int32_t ccb_index; /* Index to our CCB Info */ 610 u_int8_t target_ix; /* Combined TID and LUN */ 611 612 u_int8_t flag; 613 u_int8_t cdb_len; /* 614 * Number of bytes in the SCSI 615 * command to execute. 616 */ 617 u_int8_t tag_code; /* 618 * Tag type for this transaction 619 * (SIMPLE, ORDERED, HEAD ) 620 */ 621 #define ADV_TAG_FLAG_EXTRA_BYTES 0x10 622 #define ADV_TAG_FLAG_DISABLE_DISCONNECT 0x04 623 #define ADV_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08 624 #define ADV_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40 625 626 u_int16_t vm_id; 627 }; 628 629 struct adv_scsiq_3 { 630 u_int8_t done_stat; 631 #define QD_IN_PROGRESS 0x00 632 #define QD_NO_ERROR 0x01 633 #define QD_ABORTED_BY_HOST 0x02 634 #define QD_WITH_ERROR 0x04 635 #define QD_INVALID_REQUEST 0x80 636 #define QD_INVALID_HOST_NUM 0x81 637 #define QD_INVALID_DEVICE 0x82 638 #define QD_ERR_INTERNAL 0xFF 639 640 u_int8_t host_stat; 641 #define QHSTA_NO_ERROR 0x00 642 #define QHSTA_M_SEL_TIMEOUT 0x11 643 #define QHSTA_M_DATA_OVER_RUN 0x12 644 #define QHSTA_M_DATA_UNDER_RUN 0x12 645 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 646 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14 647 648 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21 649 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22 650 #define QHSTA_D_HOST_ABORT_FAILED 0x23 651 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24 652 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25 653 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26 654 655 #define QHSTA_M_WTM_TIMEOUT 0x41 656 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 657 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 658 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 659 #define QHSTA_M_TARGET_STATUS_BUSY 0x45 660 #define QHSTA_M_BAD_TAG_CODE 0x46 661 662 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47 663 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48 664 665 #define QHSTA_D_LRAM_CMP_ERROR 0x81 666 667 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1 668 669 u_int8_t scsi_stat; 670 u_int8_t scsi_msg; 671 }; 672 673 struct adv_scsiq_4 { 674 u_int8_t cdb[ADV_MAX_CDB_LEN]; 675 u_int8_t y_first_sg_list_qp; 676 u_int8_t y_working_sg_qp; 677 u_int8_t y_working_sg_ix; 678 u_int8_t y_res; 679 u_int16_t x_req_count; 680 u_int16_t x_reconnect_rtn; 681 u_int32_t x_saved_data_addr; 682 u_int32_t x_saved_data_cnt; 683 }; 684 685 struct adv_q_done_info { 686 struct adv_scsiq_2 d2; 687 struct adv_scsiq_3 d3; 688 u_int8_t q_status; 689 u_int8_t q_no; 690 u_int8_t cntl; 691 u_int8_t sense_len; 692 u_int8_t extra_bytes; 693 u_int8_t res; 694 u_int32_t remain_bytes; 695 }; 696 697 struct adv_sg_entry { 698 u_int32_t addr; 699 u_int32_t bytes; 700 }; 701 702 struct adv_sg_head { 703 u_int16_t entry_cnt; /* 704 * Number of SG entries 705 * in this list 706 */ 707 708 u_int16_t queue_cnt; /* 709 * Number of queues required 710 * to store entry_cnt 711 * SG entries. 712 */ 713 714 u_int16_t entry_to_copy; /* 715 * Number of SG entries to 716 * copy to the board. 717 */ 718 u_int16_t res; 719 struct adv_sg_entry *sg_list; 720 }; 721 722 #define QCX_SORT (0x0001) 723 #define QCX_COALEASE (0x0002) 724 725 struct adv_scsi_q { 726 struct adv_scsiq_1 q1; 727 struct adv_scsiq_2 q2; 728 u_int8_t *cdbptr; /* 729 * Pointer to the SCSI command 730 * to execute. 731 */ 732 733 struct adv_sg_head *sg_head; /* 734 * Pointer to possible SG list 735 */ 736 }; 737 738 struct adv_scsi_req_q { 739 struct adv_scsiq_1 r1; 740 struct adv_scsiq_2 r2; 741 u_int8_t *cdbptr; 742 struct adv_sg_head *sg_head; 743 u_int8_t *sense_ptr; 744 struct adv_scsiq_3 r3; 745 u_int8_t cdb[ADV_MAX_CDB_LEN]; 746 u_int8_t sense[ADV_MIN_SENSE_LEN]; 747 }; 748 749 struct adv_risc_q { 750 u_int8_t fwd; 751 u_int8_t bwd; 752 struct adv_scsiq_1 i1; 753 struct adv_scsiq_2 i2; 754 struct adv_scsiq_3 i3; 755 struct adv_scsiq_4 i4; 756 }; 757 758 struct adv_sg_list_q { 759 u_int8_t seq_no; 760 u_int8_t q_no; 761 u_int8_t cntl; 762 #define QCSG_SG_XFER_LIST 0x02 763 #define QCSG_SG_XFER_MORE 0x04 764 #define QCSG_SG_XFER_END 0x08 765 766 u_int8_t sg_head_qp; 767 u_int8_t sg_list_cnt; 768 u_int8_t sg_cur_list_cnt; 769 }; 770 #define ADV_SGQ_B_SG_CNTL 4 771 #define ADV_SGQ_B_SG_HEAD_QP 5 772 #define ADV_SGQ_B_SG_LIST_CNT 6 773 #define ADV_SGQ_B_SG_CUR_LIST_CNT 7 774 #define ADV_SGQ_LIST_BEG 8 775 776 struct asc_risc_sg_list_q { 777 u_int8_t fwd; 778 u_int8_t bwd; 779 struct adv_sg_list_q sg; 780 struct adv_sg_entry sg_list[ADV_SG_LIST_PER_Q]; 781 }; 782 783 /* Chip Register functions */ 784 void adv_set_bank(struct adv_softc *adv, u_int8_t bank); 785 786 /* LRAM routines */ 787 u_int8_t adv_read_lram_8(struct adv_softc *adv, u_int16_t addr); 788 void adv_write_lram_8(struct adv_softc *adv, u_int16_t addr, 789 u_int8_t value); 790 u_int16_t adv_read_lram_16(struct adv_softc *adv, u_int16_t addr); 791 void adv_write_lram_16(struct adv_softc *adv, u_int16_t addr, 792 u_int16_t value); 793 794 /* Intialization */ 795 int adv_find_signature(bus_space_tag_t tag, bus_space_handle_t bsh); 796 void adv_lib_init(struct adv_softc *adv); 797 798 u_int16_t adv_get_eeprom_config(struct adv_softc *adv, 799 struct adv_eeprom_config *eeprom_config); 800 int adv_set_eeprom_config(struct adv_softc *adv, 801 struct adv_eeprom_config *eeprom_config); 802 int adv_reset_chip(struct adv_softc *adv, int reset_bus); 803 int adv_test_external_lram(struct adv_softc* adv); 804 int adv_init_lram_and_mcode(struct adv_softc *adv); 805 u_int8_t adv_get_chip_irq(struct adv_softc *adv); 806 u_int8_t adv_set_chip_irq(struct adv_softc *adv, u_int8_t irq_no); 807 void adv_set_chip_scsiid(struct adv_softc *adv, int new_id); 808 809 /* Queue handling and execution */ 810 int adv_execute_scsi_queue(struct adv_softc *adv, 811 struct adv_scsi_q *scsiq, 812 u_int32_t datalen); 813 u_int8_t adv_copy_lram_doneq(struct adv_softc *adv, u_int16_t q_addr, 814 struct adv_q_done_info *scsiq, u_int32_t max_dma_count); 815 816 /* Chip Control */ 817 int adv_start_chip(struct adv_softc *adv); 818 void adv_start_execution(struct adv_softc *adv); 819 int adv_stop_execution(struct adv_softc *adv); 820 int adv_stop_chip(struct adv_softc *adv); 821 int adv_is_chip_halted(struct adv_softc *adv); 822 823 /* Interrupt processing */ 824 void adv_ack_interrupt(struct adv_softc *adv); 825 void adv_isr_chip_halted(struct adv_softc *adv); 826 827 /* SDTR Conversion */ 828 void adv_set_syncrate(struct adv_softc *adv, struct cam_path *path, 829 u_int target_id, u_int period, u_int offset, 830 u_int type); 831 void adv_sdtr_to_period_offset(struct adv_softc *adv, 832 u_int8_t sync_data, u_int8_t *period, 833 u_int8_t *offset, int tid); 834 u_int8_t adv_period_offset_to_sdtr(struct adv_softc *adv, u_int *period, 835 u_int *offset, int tid); 836 837 /* Error recovery */ 838 union ccb; 839 int adv_abort_ccb(struct adv_softc *adv, int target, int lun, 840 union ccb *ccb, u_int32_t status, int queued_only); 841 int adv_reset_bus(struct adv_softc *adv, int initiate_reset); 842 843 /* Async event callback */ 844 void advasync(void *callback_arg, u_int32_t code, 845 struct cam_path *path, void *arg); 846 847 #define ADV_INB(adv, offset) \ 848 bus_space_read_1((adv)->tag, (adv)->bsh, offset) 849 #define ADV_INW(adv, offset) \ 850 bus_space_read_2((adv)->tag, (adv)->bsh, offset) 851 #define ADV_INSB(adv, offset, valp, count) \ 852 bus_space_read_multi_1((adv)->tag, (adv)->bsh, offset, valp, count) 853 854 /* These controllers seem to have problems with PIO on some fast processors */ 855 static __inline void ADV_INSW(struct adv_softc *, u_int, u_int16_t *, u_int); 856 static __inline void 857 ADV_INSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count) 858 { 859 while (count--) 860 *valp++ = bus_space_read_2(adv->tag, adv->bsh, offset); 861 } 862 863 #define ADV_OUTB(adv, offset, val) \ 864 bus_space_write_1((adv)->tag, (adv)->bsh, offset, val) 865 #define ADV_OUTW(adv, offset, val) \ 866 bus_space_write_2((adv)->tag, (adv)->bsh, offset, val) 867 868 /* These controllers seem to have problems with PIO on some fast processors */ 869 static __inline void ADV_OUTSW(struct adv_softc *, u_int, u_int16_t *, u_int); 870 static __inline void 871 ADV_OUTSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count) 872 { 873 while (count--) 874 bus_space_write_2(adv->tag, adv->bsh, offset, *valp++); 875 } 876 877 #endif /* _ADVLIB_H_ */ 878