1 /* 2 * Device probe and attach routines for the following 3 * Advanced Systems Inc. SCSI controllers: 4 * 5 * ABP[3]940UW - Bus-Master PCI Ultra-Wide (253 CDB) 6 * ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB/Channel) 7 * ABP970UW - Bus-Master PCI Ultra-Wide (253 CDB) 8 * ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB) 9 * ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB) 10 * 11 * Copyright (c) 1998, 1999, 2000 Justin Gibbs. 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions, and the following disclaimer, 19 * without modification. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: src/sys/dev/advansys/adw_pci.c,v 1.12.2.1 2000/08/02 22:22:40 peter Exp $ 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <sys/rman.h> 44 45 #include <bus/pci/pcireg.h> 46 #include <bus/pci/pcivar.h> 47 48 #include <bus/cam/cam.h> 49 #include <bus/cam/scsi/scsi_all.h> 50 51 #include "adwvar.h" 52 #include "adwlib.h" 53 #include "adwmcode.h" 54 55 #define ADW_PCI_IOBASE PCIR_MAPS /* I/O Address */ 56 #define ADW_PCI_MEMBASE PCIR_MAPS + 4 /* Mem I/O Address */ 57 58 #define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull 59 #define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull 60 #define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull 61 #define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 62 #define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 63 64 struct adw_pci_identity; 65 typedef int (adw_device_setup_t)(device_t, struct adw_pci_identity *, 66 struct adw_softc *adw); 67 68 struct adw_pci_identity { 69 u_int64_t full_id; 70 u_int64_t id_mask; 71 char *name; 72 adw_device_setup_t *setup; 73 const struct adw_mcode *mcode_data; 74 const struct adw_eeprom *default_eeprom; 75 }; 76 77 static adw_device_setup_t adw_asc3550_setup; 78 static adw_device_setup_t adw_asc38C0800_setup; 79 #ifdef NOTYET 80 static adw_device_setup_t adw_asc38C1600_setup; 81 #endif 82 83 struct adw_pci_identity adw_pci_ident_table[] = 84 { 85 /* asc3550 based controllers */ 86 { 87 PCI_ID_ADVANSYS_3550, 88 PCI_ID_DEV_VENDOR_MASK, 89 "AdvanSys 3550 Ultra SCSI Adapter", 90 adw_asc3550_setup, 91 &adw_asc3550_mcode_data, 92 &adw_asc3550_default_eeprom 93 }, 94 /* asc38C0800 based controllers */ 95 { 96 PCI_ID_ADVANSYS_38C0800_REV1, 97 PCI_ID_DEV_VENDOR_MASK, 98 "AdvanSys 38C0800 Ultra2 SCSI Adapter", 99 adw_asc38C0800_setup, 100 &adw_asc38C0800_mcode_data, 101 &adw_asc38C0800_default_eeprom 102 }, 103 #if 0 /* NOTYET */ 104 /* XXX Disabled until I have hardware to test with */ 105 /* asc38C1600 based controllers */ 106 { 107 PCI_ID_ADVANSYS_38C1600_REV1, 108 PCI_ID_DEV_VENDOR_MASK, 109 "AdvanSys 38C1600 Ultra160 SCSI Adapter", 110 adw_asc38C1600_setup, 111 NULL, /* None provided by vendor thus far */ 112 NULL /* None provided by vendor thus far */ 113 } 114 #endif 115 }; 116 117 static const int adw_num_pci_devs = 118 sizeof(adw_pci_ident_table) / sizeof(*adw_pci_ident_table); 119 120 #define ADW_PCI_MAX_DMA_ADDR (0xFFFFFFFFUL) 121 #define ADW_PCI_MAX_DMA_COUNT (0xFFFFFFFFUL) 122 123 static int adw_pci_probe(device_t dev); 124 static int adw_pci_attach(device_t dev); 125 126 static device_method_t adw_pci_methods[] = { 127 /* Device interface */ 128 DEVMETHOD(device_probe, adw_pci_probe), 129 DEVMETHOD(device_attach, adw_pci_attach), 130 { 0, 0 } 131 }; 132 133 static driver_t adw_pci_driver = { 134 "adw", 135 adw_pci_methods, 136 sizeof(struct adw_softc) 137 }; 138 139 static devclass_t adw_devclass; 140 141 DRIVER_MODULE(adw, pci, adw_pci_driver, adw_devclass, 0, 0); 142 143 static __inline u_int64_t 144 adw_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 145 { 146 u_int64_t id; 147 148 id = subvendor 149 | (subdevice << 16) 150 | ((u_int64_t)vendor << 32) 151 | ((u_int64_t)device << 48); 152 153 return (id); 154 } 155 156 static struct adw_pci_identity * 157 adw_find_pci_device(device_t dev) 158 { 159 u_int64_t full_id; 160 struct adw_pci_identity *entry; 161 u_int i; 162 163 full_id = adw_compose_id(pci_get_device(dev), 164 pci_get_vendor(dev), 165 pci_get_subdevice(dev), 166 pci_get_subvendor(dev)); 167 168 for (i = 0; i < adw_num_pci_devs; i++) { 169 entry = &adw_pci_ident_table[i]; 170 if (entry->full_id == (full_id & entry->id_mask)) 171 return (entry); 172 } 173 return (NULL); 174 } 175 176 static int 177 adw_pci_probe(device_t dev) 178 { 179 struct adw_pci_identity *entry; 180 181 entry = adw_find_pci_device(dev); 182 if (entry != NULL) { 183 device_set_desc(dev, entry->name); 184 return (0); 185 } 186 return (ENXIO); 187 } 188 189 static int 190 adw_pci_attach(device_t dev) 191 { 192 struct adw_softc *adw; 193 struct adw_pci_identity *entry; 194 u_int32_t command; 195 struct resource *regs; 196 int regs_type; 197 int regs_id; 198 int error; 199 int zero; 200 201 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 202 entry = adw_find_pci_device(dev); 203 if (entry == NULL) 204 return (ENXIO); 205 regs = NULL; 206 regs_type = 0; 207 regs_id = 0; 208 #ifdef ADW_ALLOW_MEMIO 209 if ((command & PCIM_CMD_MEMEN) != 0) { 210 regs_type = SYS_RES_MEMORY; 211 regs_id = ADW_PCI_MEMBASE; 212 regs = bus_alloc_resource(dev, regs_type, 213 ®s_id, 0, ~0, 1, RF_ACTIVE); 214 } 215 #endif 216 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) { 217 regs_type = SYS_RES_IOPORT; 218 regs_id = ADW_PCI_IOBASE; 219 regs = bus_alloc_resource(dev, regs_type, 220 ®s_id, 0, ~0, 1, RF_ACTIVE); 221 } 222 223 if (regs == NULL) { 224 device_printf(dev, "can't allocate register resources\n"); 225 return (ENOMEM); 226 } 227 228 adw = adw_alloc(dev, regs, regs_type, regs_id); 229 if (adw == NULL) 230 return(ENOMEM); 231 232 /* 233 * Now that we have access to our registers, just verify that 234 * this really is an AdvanSys device. 235 */ 236 if (adw_find_signature(adw) == 0) { 237 adw_free(adw); 238 return (ENXIO); 239 } 240 241 adw_reset_chip(adw); 242 243 error = entry->setup(dev, entry, adw); 244 245 if (error != 0) 246 return (error); 247 248 /* Ensure busmastering is enabled */ 249 command |= PCIM_CMD_BUSMASTEREN; 250 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 251 252 /* Allocate a dmatag for our transfer DMA maps */ 253 /* XXX Should be a child of the PCI bus dma tag */ 254 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, 255 /*boundary*/0, 256 /*lowaddr*/ADW_PCI_MAX_DMA_ADDR, 257 /*highaddr*/BUS_SPACE_MAXADDR, 258 /*filter*/NULL, /*filterarg*/NULL, 259 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 260 /*nsegments*/BUS_SPACE_UNRESTRICTED, 261 /*maxsegsz*/ADW_PCI_MAX_DMA_COUNT, 262 /*flags*/0, 263 &adw->parent_dmat); 264 265 adw->init_level++; 266 267 if (error != 0) { 268 kprintf("%s: Could not allocate DMA tag - error %d\n", 269 adw_name(adw), error); 270 adw_free(adw); 271 return (error); 272 } 273 274 adw->init_level++; 275 276 error = adw_init(adw); 277 if (error != 0) { 278 adw_free(adw); 279 return (error); 280 } 281 282 /* 283 * If the PCI Configuration Command Register "Parity Error Response 284 * Control" Bit was clear (0), then set the microcode variable 285 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 286 * to ignore DMA parity errors. 287 */ 288 if ((command & PCIM_CMD_PERRESPEN) == 0) 289 adw_lram_write_16(adw, ADW_MC_CONTROL_FLAG, 290 adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG) 291 | ADW_MC_CONTROL_IGN_PERR); 292 293 zero = 0; 294 adw->irq_res_type = SYS_RES_IRQ; 295 adw->irq = bus_alloc_resource(dev, adw->irq_res_type, &zero, 296 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 297 if (adw->irq == NULL) { 298 adw_free(adw); 299 return (ENOMEM); 300 } 301 302 error = adw_attach(adw); 303 if (error != 0) 304 adw_free(adw); 305 return (error); 306 } 307 308 static int 309 adw_generic_setup(device_t dev, struct adw_pci_identity *entry, 310 struct adw_softc *adw) 311 { 312 adw->channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 313 adw->chip = ADW_CHIP_NONE; 314 adw->features = ADW_FENONE; 315 adw->flags = ADW_FNONE; 316 adw->mcode_data = entry->mcode_data; 317 adw->default_eeprom = entry->default_eeprom; 318 return (0); 319 } 320 321 static int 322 adw_asc3550_setup(device_t dev, struct adw_pci_identity *entry, 323 struct adw_softc *adw) 324 { 325 int error; 326 327 error = adw_generic_setup(dev, entry, adw); 328 if (error != 0) 329 return (error); 330 adw->chip = ADW_CHIP_ASC3550; 331 adw->features = ADW_ASC3550_FE; 332 adw->memsize = ADW_3550_MEMSIZE; 333 /* 334 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits 335 * sets a FIFO threshold of 128 bytes. This register is 336 * only accessible to the host. 337 */ 338 adw_outb(adw, ADW_DMA_CFG0, 339 ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM); 340 adw_outb(adw, ADW_MEM_CFG, 341 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB); 342 return (0); 343 } 344 345 static int 346 adw_asc38C0800_setup(device_t dev, struct adw_pci_identity *entry, 347 struct adw_softc *adw) 348 { 349 int error; 350 351 error = adw_generic_setup(dev, entry, adw); 352 if (error != 0) 353 return (error); 354 /* 355 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 356 * START_CTL_TH [3:2] bits for the default FIFO threshold. 357 * 358 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes. 359 * 360 * For DMA Errata #4 set the BC_THRESH_ENB bit. 361 */ 362 adw_outb(adw, ADW_DMA_CFG0, 363 ADW_DMA_CFG0_BC_THRESH_ENB|ADW_DMA_CFG0_FIFO_THRESH_80B 364 |ADW_DMA_CFG0_START_CTL_TH|ADW_DMA_CFG0_READ_CMD_MRM); 365 adw_outb(adw, ADW_MEM_CFG, 366 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_16KB); 367 adw->chip = ADW_CHIP_ASC38C0800; 368 adw->features = ADW_ASC38C0800_FE; 369 adw->memsize = ADW_38C0800_MEMSIZE; 370 return (error); 371 } 372 373 #ifdef NOTYET 374 static int 375 adw_asc38C1600_setup(device_t dev, struct adw_pci_identity *entry, 376 struct adw_softc *adw) 377 { 378 int error; 379 380 error = adw_generic_setup(dev, entry, adw); 381 if (error != 0) 382 return (error); 383 adw->chip = ADW_CHIP_ASC38C1600; 384 adw->features = ADW_ASC38C1600_FE; 385 adw->memsize = ADW_38C1600_MEMSIZE; 386 return (error); 387 } 388 #endif 389