1 /* 2 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * 17 * Copyright (c) 2009 The DragonFly Project. All rights reserved. 18 * 19 * This code is derived from software contributed to The DragonFly Project 20 * by Matthew Dillon <dillon@backplane.com> 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 26 * 1. Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * 2. Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in 30 * the documentation and/or other materials provided with the 31 * distribution. 32 * 3. Neither the name of The DragonFly Project nor the names of its 33 * contributors may be used to endorse or promote products derived 34 * from this software without specific, prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 37 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 39 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 40 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 42 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 43 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 44 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 45 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 46 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 47 * SUCH DAMAGE. 48 * 49 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $ 50 */ 51 52 #include "ahci.h" 53 54 void ahci_port_interrupt_enable(struct ahci_port *ap); 55 56 int ahci_load_prdt(struct ahci_ccb *); 57 void ahci_unload_prdt(struct ahci_ccb *); 58 static void ahci_load_prdt_callback(void *info, bus_dma_segment_t *segs, 59 int nsegs, int error); 60 void ahci_start(struct ahci_ccb *); 61 int ahci_port_softreset(struct ahci_port *ap); 62 int ahci_port_hardreset(struct ahci_port *ap, int hard); 63 void ahci_port_hardstop(struct ahci_port *ap); 64 65 static void ahci_ata_cmd_timeout_unserialized(void *); 66 void ahci_check_active_timeouts(struct ahci_port *ap); 67 68 void ahci_beg_exclusive_access(struct ahci_port *ap, struct ata_port *at); 69 void ahci_end_exclusive_access(struct ahci_port *ap, struct ata_port *at); 70 void ahci_issue_pending_commands(struct ahci_port *ap, struct ahci_ccb *ccb); 71 void ahci_issue_saved_commands(struct ahci_port *ap, u_int32_t mask); 72 73 int ahci_port_read_ncq_error(struct ahci_port *, int); 74 75 struct ahci_dmamem *ahci_dmamem_alloc(struct ahci_softc *, bus_dma_tag_t tag); 76 void ahci_dmamem_free(struct ahci_softc *, struct ahci_dmamem *); 77 static void ahci_dmamem_saveseg(void *info, bus_dma_segment_t *segs, int nsegs, int error); 78 79 static void ahci_dummy_done(struct ata_xfer *xa); 80 static void ahci_empty_done(struct ahci_ccb *ccb); 81 static void ahci_ata_cmd_done(struct ahci_ccb *ccb); 82 83 /* 84 * Initialize the global AHCI hardware. This code does not set up any of 85 * its ports. 86 */ 87 int 88 ahci_init(struct ahci_softc *sc) 89 { 90 u_int32_t cap, pi, pleft; 91 int i; 92 struct ahci_port *ap; 93 94 DPRINTF(AHCI_D_VERBOSE, " GHC 0x%b", 95 ahci_read(sc, AHCI_REG_GHC), AHCI_FMT_GHC); 96 97 /* 98 * save BIOS initialised parameters, enable staggered spin up 99 */ 100 cap = ahci_read(sc, AHCI_REG_CAP); 101 cap &= AHCI_REG_CAP_SMPS; 102 cap |= AHCI_REG_CAP_SSS; 103 pi = ahci_read(sc, AHCI_REG_PI); 104 105 /* 106 * Unconditionally reset the controller, do not conditionalize on 107 * trying to figure it if it was previously active or not. 108 * 109 * NOTE: On AE before HR. The AHCI-1.1 spec has a note in section 110 * 5.2.2.1 regarding this. HR should be set to 1 only after 111 * AE is set to 1. The reset sequence will clear HR when 112 * it completes, and will also clear AE if SAM is 0. AE must 113 * then be set again. When SAM is 1 the AE bit typically reads 114 * as 1 (and is read-only). 115 * 116 * NOTE: Avoid PCI[e] transaction burst by issuing dummy reads, 117 * otherwise the writes will only be separated by a few 118 * nanoseconds. 119 * 120 * NOTE BRICKS (1) 121 * 122 * If you have a port multiplier and it does not have a device 123 * in target 0, and it probes normally, but a later operation 124 * mis-probes a target behind that PM, it is possible for the 125 * port to brick such that only (a) a power cycle of the host 126 * or (b) placing a device in target 0 will fix the problem. 127 * Power cycling the PM has no effect (it works fine on another 128 * host port). This issue is unrelated to CLO. 129 */ 130 /* 131 * Wait for any prior reset sequence to complete 132 */ 133 if (ahci_wait_ne(sc, AHCI_REG_GHC, 134 AHCI_REG_GHC_HR, AHCI_REG_GHC_HR) != 0) { 135 device_printf(sc->sc_dev, "Controller is stuck in reset\n"); 136 return (1); 137 } 138 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE); 139 ahci_os_sleep(500); 140 ahci_read(sc, AHCI_REG_GHC); /* flush */ 141 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_HR); 142 ahci_os_sleep(500); 143 ahci_read(sc, AHCI_REG_GHC); /* flush */ 144 if (ahci_wait_ne(sc, AHCI_REG_GHC, 145 AHCI_REG_GHC_HR, AHCI_REG_GHC_HR) != 0) { 146 device_printf(sc->sc_dev, "unable to reset controller\n"); 147 return (1); 148 } 149 if (ahci_read(sc, AHCI_REG_GHC) & AHCI_REG_GHC_AE) { 150 device_printf(sc->sc_dev, "AE did not auto-clear!\n"); 151 ahci_write(sc, AHCI_REG_GHC, 0); 152 ahci_os_sleep(500); 153 } 154 155 /* 156 * Enable ahci (global interrupts disabled) 157 * 158 * Restore saved parameters. Avoid pci transaction burst write 159 * by issuing dummy reads. 160 */ 161 ahci_os_sleep(500); 162 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE); 163 ahci_os_sleep(500); 164 165 ahci_read(sc, AHCI_REG_GHC); /* flush */ 166 ahci_write(sc, AHCI_REG_CAP, cap); 167 ahci_write(sc, AHCI_REG_PI, pi); 168 ahci_read(sc, AHCI_REG_GHC); /* flush */ 169 170 /* 171 * Intel hocus pocus in case the BIOS has not set the chip up 172 * properly for AHCI operation. 173 */ 174 if (pci_get_vendor(sc->sc_dev) == PCI_VENDOR_INTEL) { 175 if ((pci_read_config(sc->sc_dev, 0x92, 2) & 0x0F) != 0x0F) 176 device_printf(sc->sc_dev, "Intel hocus pocus\n"); 177 pci_write_config(sc->sc_dev, 0x92, 178 pci_read_config(sc->sc_dev, 0x92, 2) | 0x0F, 2); 179 } 180 181 /* 182 * This is a hack that currently does not appear to have 183 * a significant effect, but I noticed the port registers 184 * do not appear to be completely cleared after the host 185 * controller is reset. 186 * 187 * Use a temporary ap structure so we can call ahci_pwrite(). 188 * 189 * We must be sure to stop the port 190 */ 191 ap = kmalloc(sizeof(*ap), M_DEVBUF, M_WAITOK | M_ZERO); 192 ap->ap_sc = sc; 193 pleft = pi; 194 for (i = 0; i < AHCI_MAX_PORTS; ++i) { 195 if (pleft == 0) 196 break; 197 if ((pi & (1 << i)) == 0) 198 continue; 199 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 200 AHCI_PORT_REGION(i), AHCI_PORT_SIZE, &ap->ap_ioh) != 0) { 201 device_printf(sc->sc_dev, "can't map port\n"); 202 return (1); 203 } 204 /* 205 * NOTE! Setting AHCI_PREG_SCTL_DET_DISABLE on AHCI1.0 or 206 * AHCI1.1 can brick the chipset. Not only brick it, 207 * but also crash the PC. The bit seems unreliable 208 * on AHCI1.2 as well. 209 */ 210 ahci_port_stop(ap, 1); 211 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED); 212 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 213 ahci_pwrite(ap, AHCI_PREG_IE, 0); 214 ahci_write(ap->ap_sc, AHCI_REG_IS, 1 << i); 215 ahci_pwrite(ap, AHCI_PREG_CMD, 0); 216 ahci_pwrite(ap, AHCI_PREG_IS, -1); 217 sc->sc_portmask |= (1 << i); 218 pleft &= ~(1 << i); 219 } 220 sc->sc_numports = i; 221 kfree(ap, M_DEVBUF); 222 223 return (0); 224 } 225 226 /* 227 * Allocate and initialize an AHCI port. 228 */ 229 int 230 ahci_port_alloc(struct ahci_softc *sc, u_int port) 231 { 232 struct ahci_port *ap; 233 struct ata_port *at; 234 struct ahci_ccb *ccb; 235 u_int64_t dva; 236 u_int32_t cmd; 237 u_int32_t data; 238 struct ahci_cmd_hdr *hdr; 239 struct ahci_cmd_table *table; 240 int rc = ENOMEM; 241 int error; 242 int i; 243 244 ap = kmalloc(sizeof(*ap), M_DEVBUF, M_WAITOK | M_ZERO); 245 ap->ap_err_scratch = kmalloc(512, M_DEVBUF, M_WAITOK | M_ZERO); 246 247 ksnprintf(ap->ap_name, sizeof(ap->ap_name), "%s%d.%d", 248 device_get_name(sc->sc_dev), 249 device_get_unit(sc->sc_dev), 250 port); 251 sc->sc_ports[port] = ap; 252 253 /* 254 * Allocate enough so we never have to reallocate, it makes 255 * it easier. 256 * 257 * ap_pmcount will be reduced by the scan if we encounter the 258 * port multiplier port prior to target 15. 259 * 260 * kmalloc power-of-2 allocations are guaranteed not to cross 261 * a page boundary. Make sure the identify sub-structure in the 262 * at structure does not cross a page boundary, just in case the 263 * part is AHCI-1.1 and can't handle multiple DRQ blocks. 264 */ 265 if (ap->ap_ata[0] == NULL) { 266 int pw2; 267 268 for (pw2 = 1; pw2 < sizeof(*at); pw2 <<= 1) 269 ; 270 for (i = 0; i < AHCI_MAX_PMPORTS; ++i) { 271 at = kmalloc(pw2, M_DEVBUF, M_INTWAIT | M_ZERO); 272 ap->ap_ata[i] = at; 273 at->at_ahci_port = ap; 274 at->at_target = i; 275 at->at_probe = ATA_PROBE_NEED_INIT; 276 at->at_features |= ATA_PORT_F_RESCAN; 277 ksnprintf(at->at_name, sizeof(at->at_name), 278 "%s.%d", ap->ap_name, i); 279 } 280 } 281 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 282 AHCI_PORT_REGION(port), AHCI_PORT_SIZE, &ap->ap_ioh) != 0) { 283 device_printf(sc->sc_dev, 284 "unable to create register window for port %d\n", 285 port); 286 goto freeport; 287 } 288 289 ap->ap_sc = sc; 290 ap->ap_num = port; 291 ap->ap_probe = ATA_PROBE_NEED_INIT; 292 ap->link_pwr_mgmt = AHCI_LINK_PWR_MGMT_NONE; 293 ap->sysctl_tree = NULL; 294 TAILQ_INIT(&ap->ap_ccb_free); 295 TAILQ_INIT(&ap->ap_ccb_pending); 296 lockinit(&ap->ap_ccb_lock, "ahcipo", 0, 0); 297 298 /* Disable port interrupts */ 299 ahci_pwrite(ap, AHCI_PREG_IE, 0); 300 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 301 302 /* 303 * Sec 10.1.2 - deinitialise port if it is already running 304 */ 305 cmd = ahci_pread(ap, AHCI_PREG_CMD); 306 kprintf("%s: Caps %b\n", PORTNAME(ap), cmd, AHCI_PFMT_CMD); 307 308 if ((cmd & (AHCI_PREG_CMD_ST | AHCI_PREG_CMD_CR | 309 AHCI_PREG_CMD_FRE | AHCI_PREG_CMD_FR)) || 310 (ahci_pread(ap, AHCI_PREG_SCTL) & AHCI_PREG_SCTL_DET)) { 311 int r; 312 313 r = ahci_port_stop(ap, 1); 314 if (r) { 315 device_printf(sc->sc_dev, 316 "unable to disable %s, ignoring port %d\n", 317 ((r == 2) ? "CR" : "FR"), port); 318 rc = ENXIO; 319 goto freeport; 320 } 321 322 /* Write DET to zero */ 323 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED); 324 } 325 326 /* Allocate RFIS */ 327 ap->ap_dmamem_rfis = ahci_dmamem_alloc(sc, sc->sc_tag_rfis); 328 if (ap->ap_dmamem_rfis == NULL) { 329 kprintf("%s: NORFIS\n", PORTNAME(ap)); 330 goto nomem; 331 } 332 333 /* Setup RFIS base address */ 334 ap->ap_rfis = (struct ahci_rfis *) AHCI_DMA_KVA(ap->ap_dmamem_rfis); 335 dva = AHCI_DMA_DVA(ap->ap_dmamem_rfis); 336 ahci_pwrite(ap, AHCI_PREG_FBU, (u_int32_t)(dva >> 32)); 337 ahci_pwrite(ap, AHCI_PREG_FB, (u_int32_t)dva); 338 339 /* Clear SERR before starting FIS reception or ST or anything */ 340 ahci_flush_tfd(ap); 341 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 342 343 /* Enable FIS reception and activate port. */ 344 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC; 345 cmd &= ~(AHCI_PREG_CMD_CLO | AHCI_PREG_CMD_PMA); 346 cmd |= AHCI_PREG_CMD_FRE | AHCI_PREG_CMD_POD | AHCI_PREG_CMD_SUD; 347 ahci_pwrite(ap, AHCI_PREG_CMD, cmd | AHCI_PREG_CMD_ICC_ACTIVE); 348 349 /* Check whether port activated. Skip it if not. */ 350 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC; 351 if ((cmd & AHCI_PREG_CMD_FRE) == 0) { 352 kprintf("%s: NOT-ACTIVATED\n", PORTNAME(ap)); 353 rc = ENXIO; 354 goto freeport; 355 } 356 357 /* Allocate a CCB for each command slot */ 358 ap->ap_ccbs = kmalloc(sizeof(struct ahci_ccb) * sc->sc_ncmds, M_DEVBUF, 359 M_WAITOK | M_ZERO); 360 if (ap->ap_ccbs == NULL) { 361 device_printf(sc->sc_dev, 362 "unable to allocate command list for port %d\n", 363 port); 364 goto freeport; 365 } 366 367 /* Command List Structures and Command Tables */ 368 ap->ap_dmamem_cmd_list = ahci_dmamem_alloc(sc, sc->sc_tag_cmdh); 369 ap->ap_dmamem_cmd_table = ahci_dmamem_alloc(sc, sc->sc_tag_cmdt); 370 if (ap->ap_dmamem_cmd_table == NULL || 371 ap->ap_dmamem_cmd_list == NULL) { 372 nomem: 373 device_printf(sc->sc_dev, 374 "unable to allocate DMA memory for port %d\n", 375 port); 376 goto freeport; 377 } 378 379 /* Setup command list base address */ 380 dva = AHCI_DMA_DVA(ap->ap_dmamem_cmd_list); 381 ahci_pwrite(ap, AHCI_PREG_CLBU, (u_int32_t)(dva >> 32)); 382 ahci_pwrite(ap, AHCI_PREG_CLB, (u_int32_t)dva); 383 384 /* Split CCB allocation into CCBs and assign to command header/table */ 385 hdr = AHCI_DMA_KVA(ap->ap_dmamem_cmd_list); 386 table = AHCI_DMA_KVA(ap->ap_dmamem_cmd_table); 387 for (i = 0; i < sc->sc_ncmds; i++) { 388 ccb = &ap->ap_ccbs[i]; 389 390 error = bus_dmamap_create(sc->sc_tag_data, BUS_DMA_ALLOCNOW, 391 &ccb->ccb_dmamap); 392 if (error) { 393 device_printf(sc->sc_dev, 394 "unable to create dmamap for port %d " 395 "ccb %d\n", port, i); 396 goto freeport; 397 } 398 399 callout_init(&ccb->ccb_timeout); 400 ccb->ccb_slot = i; 401 ccb->ccb_port = ap; 402 ccb->ccb_cmd_hdr = &hdr[i]; 403 ccb->ccb_cmd_table = &table[i]; 404 dva = AHCI_DMA_DVA(ap->ap_dmamem_cmd_table) + 405 ccb->ccb_slot * sizeof(struct ahci_cmd_table); 406 ccb->ccb_cmd_hdr->ctba_hi = htole32((u_int32_t)(dva >> 32)); 407 ccb->ccb_cmd_hdr->ctba_lo = htole32((u_int32_t)dva); 408 409 ccb->ccb_xa.fis = 410 (struct ata_fis_h2d *)ccb->ccb_cmd_table->cfis; 411 ccb->ccb_xa.packetcmd = ccb->ccb_cmd_table->acmd; 412 ccb->ccb_xa.tag = i; 413 414 ccb->ccb_xa.state = ATA_S_COMPLETE; 415 416 /* 417 * CCB[1] is the error CCB and is not get or put. It is 418 * also used for probing. Numerous HBAs only load the 419 * signature from CCB[1] so it MUST be used for the second 420 * FIS. 421 */ 422 if (i == 1) 423 ap->ap_err_ccb = ccb; 424 else 425 ahci_put_ccb(ccb); 426 } 427 428 /* 429 * Wait for ICC change to complete 430 */ 431 ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_ICC); 432 433 /* 434 * Calculate the interrupt mask 435 */ 436 data = AHCI_PREG_IE_TFEE | AHCI_PREG_IE_HBFE | 437 AHCI_PREG_IE_IFE | AHCI_PREG_IE_OFE | 438 AHCI_PREG_IE_DPE | AHCI_PREG_IE_UFE | 439 AHCI_PREG_IE_PCE | AHCI_PREG_IE_PRCE | 440 AHCI_PREG_IE_DHRE | AHCI_PREG_IE_SDBE; 441 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSNTF) 442 data |= AHCI_PREG_IE_IPME; 443 #ifdef AHCI_COALESCE 444 if (sc->sc_ccc_ports & (1 << port) 445 data &= ~(AHCI_PREG_IE_SDBE | AHCI_PREG_IE_DHRE); 446 #endif 447 ap->ap_intmask = data; 448 449 /* 450 * Start the port helper thread. The helper thread will call 451 * ahci_port_init() so the ports can all be started in parallel. 452 * A failure by ahci_port_init() does not deallocate the port 453 * since we still want hot-plug events. 454 */ 455 ahci_os_start_port(ap); 456 return(0); 457 freeport: 458 ahci_port_free(sc, port); 459 return (rc); 460 } 461 462 /* 463 * [re]initialize an idle port. No CCBs should be active. 464 * 465 * This function is called during the initial port allocation sequence 466 * and is also called on hot-plug insertion. We take no chances and 467 * use a portreset instead of a softreset. 468 * 469 * This function is the only way to move a failed port back to active 470 * status. 471 * 472 * Returns 0 if a device is successfully detected. 473 */ 474 int 475 ahci_port_init(struct ahci_port *ap) 476 { 477 /* 478 * Register [re]initialization 479 */ 480 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSNTF) 481 ahci_pwrite(ap, AHCI_PREG_SNTF, -1); 482 ap->ap_probe = ATA_PROBE_NEED_HARD_RESET; 483 ap->ap_pmcount = 0; 484 485 /* 486 * Flush the TFD and SERR and make sure the port is stopped before 487 * enabling its interrupt. We no longer cycle the port start as 488 * the port should not be started unless a device is present. 489 * 490 * XXX should we enable FIS reception? (FRE)? 491 */ 492 ahci_flush_tfd(ap); 493 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 494 ahci_port_stop(ap, 0); 495 ahci_port_interrupt_enable(ap); 496 return (0); 497 } 498 499 /* 500 * Enable or re-enable interrupts on a port. 501 * 502 * This routine is called from the port initialization code or from the 503 * helper thread as the real interrupt may be forced to turn off certain 504 * interrupt sources. 505 */ 506 void 507 ahci_port_interrupt_enable(struct ahci_port *ap) 508 { 509 ahci_pwrite(ap, AHCI_PREG_IE, ap->ap_intmask); 510 } 511 512 /* 513 * Manage the agressive link power management capability. 514 */ 515 void 516 ahci_port_link_pwr_mgmt(struct ahci_port *ap, int link_pwr_mgmt) 517 { 518 u_int32_t cmd, sctl; 519 520 if (link_pwr_mgmt == ap->link_pwr_mgmt) 521 return; 522 523 if ((ap->ap_sc->sc_cap & AHCI_REG_CAP_SALP) == 0) { 524 kprintf("%s: link power management not supported.\n", 525 PORTNAME(ap)); 526 return; 527 } 528 529 ahci_os_lock_port(ap); 530 531 if (link_pwr_mgmt == AHCI_LINK_PWR_MGMT_AGGR && 532 (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSC)) { 533 kprintf("%s: enabling aggressive link power management.\n", 534 PORTNAME(ap)); 535 536 ap->link_pwr_mgmt = link_pwr_mgmt; 537 538 ap->ap_intmask &= ~AHCI_PREG_IE_PRCE; 539 ahci_port_interrupt_enable(ap); 540 541 sctl = ahci_pread(ap, AHCI_PREG_SCTL); 542 sctl &= ~(AHCI_PREG_SCTL_IPM_DISABLED); 543 ahci_pwrite(ap, AHCI_PREG_SCTL, sctl); 544 545 /* 546 * Enable device initiated link power management for 547 * directly attached devices that support it. 548 */ 549 if (ap->ap_type != ATA_PORT_T_PM && 550 ap->ap_ata[0]->at_identify.satafsup & (1 << 3)) { 551 if (ahci_set_feature(ap, NULL, ATA_SATAFT_DEVIPS, 1)) 552 kprintf("%s: Could not enable device initiated " 553 "link power management.\n", 554 PORTNAME(ap)); 555 } 556 557 cmd = ahci_pread(ap, AHCI_PREG_CMD); 558 cmd |= AHCI_PREG_CMD_ASP; 559 cmd |= AHCI_PREG_CMD_ALPE; 560 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 561 562 } else if (link_pwr_mgmt == AHCI_LINK_PWR_MGMT_MEDIUM && 563 (ap->ap_sc->sc_cap & AHCI_REG_CAP_PSC)) { 564 kprintf("%s: enabling medium link power management.\n", 565 PORTNAME(ap)); 566 567 ap->link_pwr_mgmt = link_pwr_mgmt; 568 569 ap->ap_intmask &= ~AHCI_PREG_IE_PRCE; 570 ahci_port_interrupt_enable(ap); 571 572 sctl = ahci_pread(ap, AHCI_PREG_SCTL); 573 sctl |= AHCI_PREG_SCTL_IPM_DISABLED; 574 sctl &= ~AHCI_PREG_SCTL_IPM_NOPARTIAL; 575 ahci_pwrite(ap, AHCI_PREG_SCTL, sctl); 576 577 cmd = ahci_pread(ap, AHCI_PREG_CMD); 578 cmd &= ~AHCI_PREG_CMD_ASP; 579 cmd |= AHCI_PREG_CMD_ALPE; 580 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 581 582 } else if (link_pwr_mgmt == AHCI_LINK_PWR_MGMT_NONE) { 583 kprintf("%s: disabling link power management.\n", 584 PORTNAME(ap)); 585 586 /* Disable device initiated link power management */ 587 if (ap->ap_type != ATA_PORT_T_PM && 588 ap->ap_ata[0]->at_identify.satafsup & (1 << 3)) 589 ahci_set_feature(ap, NULL, ATA_SATAFT_DEVIPS, 0); 590 591 cmd = ahci_pread(ap, AHCI_PREG_CMD); 592 cmd &= ~(AHCI_PREG_CMD_ALPE | AHCI_PREG_CMD_ASP); 593 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 594 595 sctl = ahci_pread(ap, AHCI_PREG_SCTL); 596 sctl |= AHCI_PREG_SCTL_IPM_DISABLED; 597 ahci_pwrite(ap, AHCI_PREG_SCTL, sctl); 598 599 /* let the drive come back to avoid PRCS interrupts later */ 600 ahci_os_unlock_port(ap); 601 ahci_os_sleep(1000); 602 ahci_os_lock_port(ap); 603 604 ahci_pwrite(ap, AHCI_PREG_SERR, 605 AHCI_PREG_SERR_DIAG_N | AHCI_PREG_SERR_DIAG_W); 606 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_PRCS); 607 608 ap->ap_intmask |= AHCI_PREG_IE_PRCE; 609 ahci_port_interrupt_enable(ap); 610 611 ap->link_pwr_mgmt = link_pwr_mgmt; 612 } else { 613 kprintf("%s: unsupported link power management state %d.\n", 614 PORTNAME(ap), link_pwr_mgmt); 615 } 616 617 ahci_os_unlock_port(ap); 618 } 619 620 /* 621 * Return current link power state. 622 */ 623 int 624 ahci_port_link_pwr_state(struct ahci_port *ap) 625 { 626 uint32_t r; 627 628 r = ahci_pread(ap, AHCI_PREG_SSTS); 629 switch (r & SATA_PM_SSTS_IPM) { 630 case SATA_PM_SSTS_IPM_ACTIVE: 631 return 1; 632 case SATA_PM_SSTS_IPM_PARTIAL: 633 return 2; 634 case SATA_PM_SSTS_IPM_SLUMBER: 635 return 3; 636 default: 637 return 0; 638 } 639 } 640 641 /* 642 * Run the port / target state machine from a main context. 643 * 644 * The state machine for the port is always run. 645 * 646 * If atx is non-NULL run the state machine for a particular target. 647 * If atx is NULL run the state machine for all targets. 648 */ 649 void 650 ahci_port_state_machine(struct ahci_port *ap, int initial) 651 { 652 struct ata_port *at; 653 u_int32_t data; 654 int target; 655 int didsleep; 656 int loop; 657 658 /* 659 * State machine for port. Note that CAM is not yet associated 660 * during the initial parallel probe and the port's probe state 661 * will not get past ATA_PROBE_NEED_IDENT. 662 */ 663 { 664 if (initial == 0 && ap->ap_probe <= ATA_PROBE_NEED_HARD_RESET) { 665 kprintf("%s: Waiting 10 seconds on insertion\n", 666 PORTNAME(ap)); 667 ahci_os_sleep(10000); 668 initial = 1; 669 } 670 if (ap->ap_probe == ATA_PROBE_NEED_INIT) 671 ahci_port_init(ap); 672 if (ap->ap_probe == ATA_PROBE_NEED_HARD_RESET) 673 ahci_port_reset(ap, NULL, 1); 674 if (ap->ap_probe == ATA_PROBE_NEED_SOFT_RESET) 675 ahci_port_reset(ap, NULL, 0); 676 if (ap->ap_probe == ATA_PROBE_NEED_IDENT) 677 ahci_cam_probe(ap, NULL); 678 } 679 if (ap->ap_type != ATA_PORT_T_PM) { 680 if (ap->ap_probe == ATA_PROBE_FAILED) { 681 ahci_cam_changed(ap, NULL, 0); 682 } else if (ap->ap_probe >= ATA_PROBE_NEED_IDENT) { 683 ahci_cam_changed(ap, NULL, 1); 684 } 685 return; 686 } 687 688 /* 689 * Port Multiplier state machine. 690 * 691 * Get a mask of changed targets and combine with any runnable 692 * states already present. 693 */ 694 for (loop = 0; ;++loop) { 695 if (ahci_pm_read(ap, 15, SATA_PMREG_EINFO, &data)) { 696 kprintf("%s: PM unable to read hot-plug bitmap\n", 697 PORTNAME(ap)); 698 break; 699 } 700 701 /* 702 * Do at least one loop, then stop if no more state changes 703 * have occured. The PM might not generate a new 704 * notification until we clear the entire bitmap. 705 */ 706 if (loop && data == 0) 707 break; 708 709 /* 710 * New devices showing up in the bitmap require some spin-up 711 * time before we start probing them. Reset didsleep. The 712 * first new device we detect will sleep before probing. 713 * 714 * This only applies to devices whos change bit is set in 715 * the data, and does not apply to the initial boot-time 716 * probe. 717 */ 718 didsleep = 0; 719 720 for (target = 0; target < ap->ap_pmcount; ++target) { 721 at = ap->ap_ata[target]; 722 723 /* 724 * Check the target state for targets behind the PM 725 * which have changed state. This will adjust 726 * at_probe and set ATA_PORT_F_RESCAN 727 * 728 * We want to wait at least 10 seconds before probing 729 * a newly inserted device. If the check status 730 * indicates a device is present and in need of a 731 * hard reset, we make sure we have slept before 732 * continuing. 733 * 734 * We also need to wait at least 1 second for the 735 * PHY state to change after insertion, if we 736 * haven't already waited the 10 seconds. 737 * 738 * NOTE: When pm_check_good finds a good port it 739 * typically starts us in probe state 740 * NEED_HARD_RESET rather than INIT. 741 */ 742 if (data & (1 << target)) { 743 if (initial == 0 && didsleep == 0) 744 ahci_os_sleep(1000); 745 ahci_pm_check_good(ap, target); 746 if (initial == 0 && didsleep == 0 && 747 at->at_probe <= ATA_PROBE_NEED_HARD_RESET 748 ) { 749 didsleep = 1; 750 kprintf("%s: Waiting 10 seconds on insertion\n", PORTNAME(ap)); 751 ahci_os_sleep(10000); 752 } 753 } 754 755 /* 756 * Report hot-plug events before the probe state 757 * really gets hot. Only actual events are reported 758 * here to reduce spew. 759 */ 760 if (data & (1 << target)) { 761 kprintf("%s: HOTPLUG (PM) - ", ATANAME(ap, at)); 762 switch(at->at_probe) { 763 case ATA_PROBE_NEED_INIT: 764 case ATA_PROBE_NEED_HARD_RESET: 765 kprintf("Device inserted\n"); 766 break; 767 case ATA_PROBE_FAILED: 768 kprintf("Device removed\n"); 769 break; 770 default: 771 kprintf("Device probe in progress\n"); 772 break; 773 } 774 } 775 776 /* 777 * Run through the state machine as necessary if 778 * the port is not marked failed. 779 * 780 * The state machine may stop at NEED_IDENT if 781 * CAM is not yet attached. 782 * 783 * Acquire exclusive access to the port while we 784 * are doing this. This prevents command-completion 785 * from queueing commands for non-polled targets 786 * inbetween our probe steps. We need to do this 787 * because the reset probes can generate severe PHY 788 * and protocol errors and soft-brick the port. 789 */ 790 if (at->at_probe != ATA_PROBE_FAILED && 791 at->at_probe != ATA_PROBE_GOOD) { 792 ahci_beg_exclusive_access(ap, at); 793 if (at->at_probe == ATA_PROBE_NEED_INIT) 794 ahci_pm_port_init(ap, at); 795 if (at->at_probe == ATA_PROBE_NEED_HARD_RESET) 796 ahci_port_reset(ap, at, 1); 797 if (at->at_probe == ATA_PROBE_NEED_SOFT_RESET) 798 ahci_port_reset(ap, at, 0); 799 if (at->at_probe == ATA_PROBE_NEED_IDENT) 800 ahci_cam_probe(ap, at); 801 ahci_end_exclusive_access(ap, at); 802 } 803 804 /* 805 * Add or remove from CAM 806 */ 807 if (at->at_features & ATA_PORT_F_RESCAN) { 808 at->at_features &= ~ATA_PORT_F_RESCAN; 809 if (at->at_probe == ATA_PROBE_FAILED) { 810 ahci_cam_changed(ap, at, 0); 811 } else if (at->at_probe >= ATA_PROBE_NEED_IDENT) { 812 ahci_cam_changed(ap, at, 1); 813 } 814 } 815 data &= ~(1 << target); 816 } 817 if (data) { 818 kprintf("%s: WARNING (PM): extra bits set in " 819 "EINFO: %08x\n", PORTNAME(ap), data); 820 while (target < AHCI_MAX_PMPORTS) { 821 ahci_pm_check_good(ap, target); 822 ++target; 823 } 824 } 825 } 826 } 827 828 829 /* 830 * De-initialize and detach a port. 831 */ 832 void 833 ahci_port_free(struct ahci_softc *sc, u_int port) 834 { 835 struct ahci_port *ap = sc->sc_ports[port]; 836 struct ahci_ccb *ccb; 837 int i; 838 839 /* 840 * Ensure port is disabled and its interrupts are all flushed. 841 */ 842 if (ap->ap_sc) { 843 ahci_port_stop(ap, 1); 844 ahci_os_stop_port(ap); 845 ahci_pwrite(ap, AHCI_PREG_CMD, 0); 846 ahci_pwrite(ap, AHCI_PREG_IE, 0); 847 ahci_pwrite(ap, AHCI_PREG_IS, ahci_pread(ap, AHCI_PREG_IS)); 848 ahci_write(sc, AHCI_REG_IS, 1 << port); 849 } 850 851 if (ap->ap_ccbs) { 852 while ((ccb = ahci_get_ccb(ap)) != NULL) { 853 if (ccb->ccb_dmamap) { 854 bus_dmamap_destroy(sc->sc_tag_data, 855 ccb->ccb_dmamap); 856 ccb->ccb_dmamap = NULL; 857 } 858 } 859 if ((ccb = ap->ap_err_ccb) != NULL) { 860 if (ccb->ccb_dmamap) { 861 bus_dmamap_destroy(sc->sc_tag_data, 862 ccb->ccb_dmamap); 863 ccb->ccb_dmamap = NULL; 864 } 865 ap->ap_err_ccb = NULL; 866 } 867 kfree(ap->ap_ccbs, M_DEVBUF); 868 ap->ap_ccbs = NULL; 869 } 870 871 if (ap->ap_dmamem_cmd_list) { 872 ahci_dmamem_free(sc, ap->ap_dmamem_cmd_list); 873 ap->ap_dmamem_cmd_list = NULL; 874 } 875 if (ap->ap_dmamem_rfis) { 876 ahci_dmamem_free(sc, ap->ap_dmamem_rfis); 877 ap->ap_dmamem_rfis = NULL; 878 } 879 if (ap->ap_dmamem_cmd_table) { 880 ahci_dmamem_free(sc, ap->ap_dmamem_cmd_table); 881 ap->ap_dmamem_cmd_table = NULL; 882 } 883 if (ap->ap_ata) { 884 for (i = 0; i < AHCI_MAX_PMPORTS; ++i) { 885 if (ap->ap_ata[i]) { 886 kfree(ap->ap_ata[i], M_DEVBUF); 887 ap->ap_ata[i] = NULL; 888 } 889 } 890 } 891 if (ap->ap_err_scratch) { 892 kfree(ap->ap_err_scratch, M_DEVBUF); 893 ap->ap_err_scratch = NULL; 894 } 895 896 /* bus_space(9) says we dont free the subregions handle */ 897 898 kfree(ap, M_DEVBUF); 899 sc->sc_ports[port] = NULL; 900 } 901 902 /* 903 * Start high-level command processing on the port 904 */ 905 int 906 ahci_port_start(struct ahci_port *ap) 907 { 908 u_int32_t r, s, is, tfd; 909 910 /* 911 * FRE must be turned on before ST. Wait for FR to go active 912 * before turning on ST. The spec doesn't seem to think this 913 * is necessary but waiting here avoids an on-off race in the 914 * ahci_port_stop() code. 915 */ 916 r = ahci_pread(ap, AHCI_PREG_CMD); 917 if ((r & AHCI_PREG_CMD_FRE) == 0) { 918 r |= AHCI_PREG_CMD_FRE; 919 ahci_pwrite(ap, AHCI_PREG_CMD, r); 920 } 921 if ((ap->ap_sc->sc_flags & AHCI_F_IGN_FR) == 0) { 922 if (ahci_pwait_set(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR)) { 923 kprintf("%s: Cannot start FIS reception\n", 924 PORTNAME(ap)); 925 return (2); 926 } 927 } else { 928 ahci_os_sleep(10); 929 } 930 931 /* 932 * Turn on ST, wait for CR to come up. 933 */ 934 r |= AHCI_PREG_CMD_ST; 935 ahci_pwrite(ap, AHCI_PREG_CMD, r); 936 if (ahci_pwait_set_to(ap, 2000, AHCI_PREG_CMD, AHCI_PREG_CMD_CR)) { 937 s = ahci_pread(ap, AHCI_PREG_SERR); 938 is = ahci_pread(ap, AHCI_PREG_IS); 939 tfd = ahci_pread(ap, AHCI_PREG_TFD); 940 kprintf("%s: Cannot start command DMA\n" 941 "NCMP=%b NSERR=%b\n" 942 "NEWIS=%b\n" 943 "NEWTFD=%b\n", 944 PORTNAME(ap), 945 r, AHCI_PFMT_CMD, s, AHCI_PFMT_SERR, 946 is, AHCI_PFMT_IS, 947 tfd, AHCI_PFMT_TFD_STS); 948 return (1); 949 } 950 951 #ifdef AHCI_COALESCE 952 /* 953 * (Re-)enable coalescing on the port. 954 */ 955 if (ap->ap_sc->sc_ccc_ports & (1 << ap->ap_num)) { 956 ap->ap_sc->sc_ccc_ports_cur |= (1 << ap->ap_num); 957 ahci_write(ap->ap_sc, AHCI_REG_CCC_PORTS, 958 ap->ap_sc->sc_ccc_ports_cur); 959 } 960 #endif 961 962 return (0); 963 } 964 965 /* 966 * Stop high-level command processing on a port 967 * 968 * WARNING! If the port is stopped while CR is still active our saved 969 * CI/SACT will race any commands completed by the command 970 * processor prior to being able to stop. Thus we never call 971 * this function unless we intend to dispose of any remaining 972 * active commands. In particular, this complicates the timeout 973 * code. 974 */ 975 int 976 ahci_port_stop(struct ahci_port *ap, int stop_fis_rx) 977 { 978 u_int32_t r; 979 980 #ifdef AHCI_COALESCE 981 /* 982 * Disable coalescing on the port while it is stopped. 983 */ 984 if (ap->ap_sc->sc_ccc_ports & (1 << ap->ap_num)) { 985 ap->ap_sc->sc_ccc_ports_cur &= ~(1 << ap->ap_num); 986 ahci_write(ap->ap_sc, AHCI_REG_CCC_PORTS, 987 ap->ap_sc->sc_ccc_ports_cur); 988 } 989 #endif 990 991 /* 992 * Turn off ST, then wait for CR to go off. 993 */ 994 r = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC; 995 r &= ~AHCI_PREG_CMD_ST; 996 ahci_pwrite(ap, AHCI_PREG_CMD, r); 997 998 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_CR)) { 999 kprintf("%s: Port bricked, unable to stop (ST)\n", 1000 PORTNAME(ap)); 1001 return (1); 1002 } 1003 1004 #if 0 1005 /* 1006 * Turn off FRE, then wait for FR to go off. FRE cannot 1007 * be turned off until CR transitions to 0. 1008 */ 1009 if ((r & AHCI_PREG_CMD_FR) == 0) { 1010 kprintf("%s: FR stopped, clear FRE for next start\n", 1011 PORTNAME(ap)); 1012 stop_fis_rx = 2; 1013 } 1014 #endif 1015 if (stop_fis_rx) { 1016 r &= ~AHCI_PREG_CMD_FRE; 1017 ahci_pwrite(ap, AHCI_PREG_CMD, r); 1018 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR)) { 1019 kprintf("%s: Port bricked, unable to stop (FRE)\n", 1020 PORTNAME(ap)); 1021 return (2); 1022 } 1023 } 1024 1025 return (0); 1026 } 1027 1028 /* 1029 * AHCI command list override -> forcibly clear TFD.STS.{BSY,DRQ} 1030 */ 1031 int 1032 ahci_port_clo(struct ahci_port *ap) 1033 { 1034 struct ahci_softc *sc = ap->ap_sc; 1035 u_int32_t cmd; 1036 1037 /* Only attempt CLO if supported by controller */ 1038 if ((ahci_read(sc, AHCI_REG_CAP) & AHCI_REG_CAP_SCLO) == 0) 1039 return (1); 1040 1041 /* Issue CLO */ 1042 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC; 1043 ahci_pwrite(ap, AHCI_PREG_CMD, cmd | AHCI_PREG_CMD_CLO); 1044 1045 /* Wait for completion */ 1046 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_CLO)) { 1047 kprintf("%s: CLO did not complete\n", PORTNAME(ap)); 1048 return (1); 1049 } 1050 1051 return (0); 1052 } 1053 1054 /* 1055 * Reset a port. 1056 * 1057 * If hard is 0 perform a softreset of the port. 1058 * If hard is 1 perform a hard reset of the port. 1059 * 1060 * If at is non-NULL an indirect port via a port-multiplier is being 1061 * reset, otherwise a direct port is being reset. 1062 * 1063 * NOTE: Indirect ports can only be soft-reset. 1064 */ 1065 int 1066 ahci_port_reset(struct ahci_port *ap, struct ata_port *at, int hard) 1067 { 1068 int rc; 1069 1070 if (hard) { 1071 if (at) 1072 rc = ahci_pm_hardreset(ap, at->at_target, hard); 1073 else 1074 rc = ahci_port_hardreset(ap, hard); 1075 } else { 1076 if (at) 1077 rc = ahci_pm_softreset(ap, at->at_target); 1078 else 1079 rc = ahci_port_softreset(ap); 1080 } 1081 return(rc); 1082 } 1083 1084 /* 1085 * AHCI soft reset, Section 10.4.1 1086 * 1087 * (at) will be NULL when soft-resetting a directly-attached device, and 1088 * non-NULL when soft-resetting a device through a port multiplier. 1089 * 1090 * This function keeps port communications intact and attempts to generate 1091 * a reset to the connected device using device commands. 1092 */ 1093 int 1094 ahci_port_softreset(struct ahci_port *ap) 1095 { 1096 struct ahci_ccb *ccb = NULL; 1097 struct ahci_cmd_hdr *cmd_slot; 1098 u_int8_t *fis; 1099 int error; 1100 1101 error = EIO; 1102 1103 if (bootverbose) { 1104 kprintf("%s: START SOFTRESET %b\n", PORTNAME(ap), 1105 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD); 1106 } 1107 1108 DPRINTF(AHCI_D_VERBOSE, "%s: soft reset\n", PORTNAME(ap)); 1109 1110 crit_enter(); 1111 ap->ap_flags |= AP_F_IN_RESET; 1112 ap->ap_state = AP_S_NORMAL; 1113 1114 /* 1115 * Remember port state in cmd (main to restore start/stop) 1116 * 1117 * Idle port. 1118 */ 1119 if (ahci_port_stop(ap, 0)) { 1120 kprintf("%s: failed to stop port, cannot softreset\n", 1121 PORTNAME(ap)); 1122 goto err; 1123 } 1124 1125 /* 1126 * Request CLO if device appears hung. 1127 */ 1128 if (ahci_pread(ap, AHCI_PREG_TFD) & 1129 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 1130 ahci_port_clo(ap); 1131 } 1132 1133 /* 1134 * This is an attempt to clear errors so a new signature will 1135 * be latched. It isn't working properly. XXX 1136 */ 1137 ahci_flush_tfd(ap); 1138 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 1139 1140 /* Restart port */ 1141 if (ahci_port_start(ap)) { 1142 kprintf("%s: failed to start port, cannot softreset\n", 1143 PORTNAME(ap)); 1144 goto err; 1145 } 1146 1147 /* Check whether CLO worked */ 1148 if (ahci_pwait_clr(ap, AHCI_PREG_TFD, 1149 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 1150 kprintf("%s: CLO %s, need port reset\n", 1151 PORTNAME(ap), 1152 (ahci_read(ap->ap_sc, AHCI_REG_CAP) & AHCI_REG_CAP_SCLO) 1153 ? "failed" : "unsupported"); 1154 error = EBUSY; 1155 goto err; 1156 } 1157 1158 /* 1159 * Prep first D2H command with SRST feature & clear busy/reset flags 1160 * 1161 * It is unclear which other fields in the FIS are used. Just zero 1162 * everything. 1163 * 1164 * NOTE! This CCB is used for both the first and second commands. 1165 * The second command must use CCB slot 1 to properly load 1166 * the signature. 1167 */ 1168 ccb = ahci_get_err_ccb(ap); 1169 ccb->ccb_xa.complete = ahci_dummy_done; 1170 ccb->ccb_xa.flags = ATA_F_POLL | ATA_F_EXCLUSIVE; 1171 KKASSERT(ccb->ccb_slot == 1); 1172 ccb->ccb_xa.at = NULL; 1173 cmd_slot = ccb->ccb_cmd_hdr; 1174 1175 fis = ccb->ccb_cmd_table->cfis; 1176 bzero(fis, sizeof(ccb->ccb_cmd_table->cfis)); 1177 fis[0] = ATA_FIS_TYPE_H2D; 1178 fis[15] = ATA_FIS_CONTROL_SRST|ATA_FIS_CONTROL_4BIT; 1179 1180 cmd_slot->prdtl = 0; 1181 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */ 1182 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_C); /* Clear busy on OK */ 1183 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_R); /* Reset */ 1184 1185 ccb->ccb_xa.state = ATA_S_PENDING; 1186 1187 if (ahci_poll(ccb, 1000, ahci_quick_timeout) != ATA_S_COMPLETE) { 1188 kprintf("%s: First FIS failed\n", PORTNAME(ap)); 1189 goto err; 1190 } 1191 1192 /* 1193 * WARNING! TIME SENSITIVE SPACE! WARNING! 1194 * 1195 * The two FISes are supposed to be back to back. Don't issue other 1196 * commands or even delay if we can help it. 1197 */ 1198 1199 /* 1200 * Prep second D2H command to read status and complete reset sequence 1201 * AHCI 10.4.1 and "Serial ATA Revision 2.6". I can't find the ATA 1202 * Rev 2.6 and it is unclear how the second FIS should be set up 1203 * from the AHCI document. 1204 * 1205 * Give the device 3ms before sending the second FIS. 1206 * 1207 * It is unclear which other fields in the FIS are used. Just zero 1208 * everything. 1209 */ 1210 ccb->ccb_xa.flags = ATA_F_POLL | ATA_F_AUTOSENSE | ATA_F_EXCLUSIVE; 1211 1212 bzero(fis, sizeof(ccb->ccb_cmd_table->cfis)); 1213 fis[0] = ATA_FIS_TYPE_H2D; 1214 fis[15] = ATA_FIS_CONTROL_4BIT; 1215 1216 cmd_slot->prdtl = 0; 1217 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */ 1218 1219 ccb->ccb_xa.state = ATA_S_PENDING; 1220 if (ahci_poll(ccb, 1000, ahci_quick_timeout) != ATA_S_COMPLETE) { 1221 kprintf("%s: Second FIS failed\n", PORTNAME(ap)); 1222 goto err; 1223 } 1224 1225 if (ahci_pwait_clr(ap, AHCI_PREG_TFD, 1226 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 1227 kprintf("%s: device didn't come ready after reset, TFD: 0x%b\n", 1228 PORTNAME(ap), 1229 ahci_pread(ap, AHCI_PREG_TFD), AHCI_PFMT_TFD_STS); 1230 error = EBUSY; 1231 goto err; 1232 } 1233 ahci_os_sleep(10); 1234 1235 /* 1236 * If the softreset is trying to clear a BSY condition after a 1237 * normal portreset we assign the port type. 1238 * 1239 * If the softreset is being run first as part of the ccb error 1240 * processing code then report if the device signature changed 1241 * unexpectedly. 1242 */ 1243 if (ap->ap_type == ATA_PORT_T_NONE) { 1244 ap->ap_type = ahci_port_signature_detect(ap, NULL); 1245 } else { 1246 if (ahci_port_signature_detect(ap, NULL) != ap->ap_type) { 1247 kprintf("%s: device signature unexpectedly " 1248 "changed\n", PORTNAME(ap)); 1249 error = EBUSY; /* XXX */ 1250 } 1251 } 1252 error = 0; 1253 1254 ahci_os_sleep(3); 1255 err: 1256 if (ccb != NULL) { 1257 ahci_put_err_ccb(ccb); 1258 1259 /* 1260 * If the target is busy use CLO to clear the busy 1261 * condition. The BSY should be cleared on the next 1262 * start. 1263 */ 1264 if (ahci_pread(ap, AHCI_PREG_TFD) & 1265 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 1266 ahci_port_clo(ap); 1267 } 1268 } 1269 1270 /* 1271 * If we failed to softreset make the port quiescent, otherwise 1272 * make sure the port's start/stop state matches what it was on 1273 * entry. 1274 * 1275 * Don't kill the port if the softreset is on a port multiplier 1276 * target, that would kill all the targets! 1277 */ 1278 if (error) { 1279 ahci_port_hardstop(ap); 1280 /* ap_probe set to failed */ 1281 } else { 1282 ap->ap_probe = ATA_PROBE_NEED_IDENT; 1283 ap->ap_pmcount = 1; 1284 ahci_port_start(ap); 1285 } 1286 ap->ap_flags &= ~AP_F_IN_RESET; 1287 crit_exit(); 1288 1289 if (bootverbose) 1290 kprintf("%s: END SOFTRESET\n", PORTNAME(ap)); 1291 1292 return (error); 1293 } 1294 1295 /* 1296 * AHCI port reset, Section 10.4.2 1297 * 1298 * This function does a hard reset of the port. Note that the device 1299 * connected to the port could still end-up hung. 1300 */ 1301 int 1302 ahci_port_hardreset(struct ahci_port *ap, int hard) 1303 { 1304 u_int32_t cmd, r; 1305 u_int32_t data; 1306 int error; 1307 int loop; 1308 1309 if (bootverbose) 1310 kprintf("%s: START HARDRESET\n", PORTNAME(ap)); 1311 ap->ap_flags |= AP_F_IN_RESET; 1312 1313 /* 1314 * Idle the port, 1315 */ 1316 ahci_port_stop(ap, 0); 1317 ap->ap_state = AP_S_NORMAL; 1318 1319 /* 1320 * The port may have been quiescent with its SUD bit cleared, so 1321 * set the SUD (spin up device). 1322 */ 1323 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC; 1324 cmd |= AHCI_PREG_CMD_SUD; 1325 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 1326 1327 /* 1328 * Perform device detection. 1329 * 1330 * NOTE! AHCi_PREG_SCTL_DET_DISABLE seems to be highly unreliable 1331 * on multiple chipsets and can brick the chipset or even 1332 * the whole PC. Never use it. 1333 */ 1334 ap->ap_type = ATA_PORT_T_NONE; 1335 1336 r = AHCI_PREG_SCTL_IPM_DISABLED; 1337 ahci_pwrite(ap, AHCI_PREG_SCTL, r); 1338 ahci_os_sleep(10); 1339 1340 /* 1341 * Start transmitting COMRESET. COMRESET must be sent for at 1342 * least 1ms. 1343 */ 1344 r = AHCI_PREG_SCTL_IPM_DISABLED | AHCI_PREG_SCTL_DET_INIT; 1345 if (AhciForceGen1 & (1 << ap->ap_num)) 1346 r |= AHCI_PREG_SCTL_SPD_GEN1; 1347 else 1348 r |= AHCI_PREG_SCTL_SPD_ANY; 1349 ahci_pwrite(ap, AHCI_PREG_SCTL, r); 1350 1351 /* 1352 * Through trial and error it seems to take around 100ms 1353 * for the detect logic to settle down. If this is too 1354 * short the softreset code will fail. 1355 */ 1356 ahci_os_sleep(100); 1357 1358 /* 1359 * Only SERR_DIAG_X needs to be cleared for TFD updates, but 1360 * since we are hard-resetting the port we might as well clear 1361 * the whole enchillada 1362 */ 1363 ahci_flush_tfd(ap); 1364 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 1365 r &= ~AHCI_PREG_SCTL_DET_INIT; 1366 r |= AHCI_PREG_SCTL_DET_NONE; 1367 ahci_pwrite(ap, AHCI_PREG_SCTL, r); 1368 1369 /* 1370 * Try to determine if there is a device on the port. 1371 * 1372 * Give the device 3/10 second to at least be detected. 1373 * If we fail clear PRCS (phy detect) since we may cycled 1374 * the phy and probably caused another PRCS interrupt. 1375 */ 1376 loop = 300; 1377 while (loop > 0) { 1378 r = ahci_pread(ap, AHCI_PREG_SSTS); 1379 if (r & AHCI_PREG_SSTS_DET) 1380 break; 1381 loop -= ahci_os_softsleep(); 1382 } 1383 if (loop == 0) { 1384 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_PRCS); 1385 if (bootverbose) { 1386 kprintf("%s: Port appears to be unplugged\n", 1387 PORTNAME(ap)); 1388 } 1389 error = ENODEV; 1390 goto done; 1391 } 1392 1393 /* 1394 * There is something on the port. Give the device 3 seconds 1395 * to fully negotiate. 1396 */ 1397 if (ahci_pwait_eq(ap, 3000, AHCI_PREG_SSTS, 1398 AHCI_PREG_SSTS_DET, AHCI_PREG_SSTS_DET_DEV)) { 1399 if (bootverbose) { 1400 kprintf("%s: Device may be powered down\n", 1401 PORTNAME(ap)); 1402 } 1403 error = ENODEV; 1404 goto pmdetect; 1405 } 1406 1407 /* 1408 * We got something that definitely looks like a device. Give 1409 * the device time to send us its first D2H FIS. Waiting for 1410 * BSY to clear accomplishes this. 1411 * 1412 * NOTE that a port multiplier may or may not clear BSY here, 1413 * depending on what is sitting in target 0 behind it. 1414 */ 1415 ahci_flush_tfd(ap); 1416 1417 if (ahci_pwait_clr_to(ap, 3000, AHCI_PREG_TFD, 1418 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 1419 error = EBUSY; 1420 } else { 1421 error = 0; 1422 } 1423 1424 pmdetect: 1425 /* 1426 * Do the PM port probe regardless of how things turned out on 1427 * the BSY check. 1428 */ 1429 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SPM) 1430 error = ahci_pm_port_probe(ap, error); 1431 1432 done: 1433 /* 1434 * Finish up. 1435 */ 1436 switch(error) { 1437 case 0: 1438 /* 1439 * All good, make sure the port is running and set the 1440 * probe state. Ignore the signature junk (it's unreliable) 1441 * until we get to the softreset code. 1442 */ 1443 if (ahci_port_start(ap)) { 1444 kprintf("%s: failed to start command DMA on port, " 1445 "disabling\n", PORTNAME(ap)); 1446 error = EBUSY; 1447 goto done; 1448 } 1449 if (ap->ap_type == ATA_PORT_T_PM) 1450 ap->ap_probe = ATA_PROBE_GOOD; 1451 else 1452 ap->ap_probe = ATA_PROBE_NEED_SOFT_RESET; 1453 break; 1454 case ENODEV: 1455 /* 1456 * Normal device probe failure 1457 */ 1458 data = ahci_pread(ap, AHCI_PREG_SSTS); 1459 1460 switch(data & AHCI_PREG_SSTS_DET) { 1461 case AHCI_PREG_SSTS_DET_DEV_NE: 1462 kprintf("%s: Device not communicating\n", 1463 PORTNAME(ap)); 1464 break; 1465 case AHCI_PREG_SSTS_DET_PHYOFFLINE: 1466 kprintf("%s: PHY offline\n", 1467 PORTNAME(ap)); 1468 break; 1469 default: 1470 kprintf("%s: No device detected\n", 1471 PORTNAME(ap)); 1472 break; 1473 } 1474 ahci_port_hardstop(ap); 1475 break; 1476 default: 1477 /* 1478 * Abnormal probe (EBUSY) 1479 */ 1480 kprintf("%s: Device on port is bricked\n", 1481 PORTNAME(ap)); 1482 ahci_port_hardstop(ap); 1483 #if 0 1484 rc = ahci_port_reset(ap, atx, 0); 1485 if (rc) { 1486 kprintf("%s: Unable unbrick device\n", 1487 PORTNAME(ap)); 1488 } else { 1489 kprintf("%s: Successfully unbricked\n", 1490 PORTNAME(ap)); 1491 } 1492 #endif 1493 break; 1494 } 1495 1496 /* 1497 * Clean up 1498 */ 1499 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 1500 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS); 1501 1502 ap->ap_flags &= ~AP_F_IN_RESET; 1503 1504 if (bootverbose) 1505 kprintf("%s: END HARDRESET %d\n", PORTNAME(ap), error); 1506 return (error); 1507 } 1508 1509 /* 1510 * Hard-stop on hot-swap device removal. See 10.10.1 1511 * 1512 * Place the port in a mode that will allow it to detect hot-swap insertions. 1513 * This is a bit imprecise because just setting-up SCTL to DET_INIT doesn't 1514 * seem to do the job. 1515 * 1516 * FIS reception is left enabled but command processing is disabled. 1517 * Cycling FIS reception (FRE) can brick ports. 1518 */ 1519 void 1520 ahci_port_hardstop(struct ahci_port *ap) 1521 { 1522 struct ahci_ccb *ccb; 1523 struct ata_port *at; 1524 u_int32_t r; 1525 u_int32_t cmd; 1526 int slot; 1527 int i; 1528 1529 /* 1530 * Stop the port. We can't modify things like SUD if the port 1531 * is running. 1532 */ 1533 ap->ap_state = AP_S_FATAL_ERROR; 1534 ap->ap_probe = ATA_PROBE_FAILED; 1535 ap->ap_type = ATA_PORT_T_NONE; 1536 ahci_port_stop(ap, 0); 1537 cmd = ahci_pread(ap, AHCI_PREG_CMD); 1538 1539 /* 1540 * Clean up AT sub-ports on SATA port. 1541 */ 1542 for (i = 0; ap->ap_ata && i < AHCI_MAX_PMPORTS; ++i) { 1543 at = ap->ap_ata[i]; 1544 at->at_type = ATA_PORT_T_NONE; 1545 at->at_probe = ATA_PROBE_FAILED; 1546 } 1547 1548 /* 1549 * Turn off port-multiplier control bit 1550 */ 1551 if (cmd & AHCI_PREG_CMD_PMA) { 1552 cmd &= ~AHCI_PREG_CMD_PMA; 1553 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 1554 } 1555 1556 /* 1557 * Make sure FRE is active. There isn't anything we can do if it 1558 * fails so just ignore errors. 1559 */ 1560 if ((cmd & AHCI_PREG_CMD_FRE) == 0) { 1561 cmd |= AHCI_PREG_CMD_FRE; 1562 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 1563 if ((ap->ap_sc->sc_flags & AHCI_F_IGN_FR) == 0) 1564 ahci_pwait_set(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR); 1565 } 1566 1567 /* 1568 * 10.10.3 DET must be set to 0 before setting SUD to 0. 1569 * 10.10.1 place us in the Listen state. 1570 * 1571 * Deactivating SUD only applies if the controller supports SUD. 1572 */ 1573 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED); 1574 ahci_os_sleep(1); 1575 if (cmd & AHCI_PREG_CMD_SUD) { 1576 cmd &= ~AHCI_PREG_CMD_SUD; 1577 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 1578 } 1579 ahci_os_sleep(1); 1580 1581 /* 1582 * Transition su to the spin-up state. HVA shall send COMRESET and 1583 * begin initialization sequence (whatever that means). 1584 * 1585 * This only applies if the controller supports SUD. 1586 * NEVER use AHCI_PREG_DET_DISABLE. 1587 */ 1588 cmd |= AHCI_PREG_CMD_SUD; 1589 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 1590 ahci_os_sleep(1); 1591 1592 /* 1593 * Transition us to the Reset state. Theoretically we send a 1594 * continuous stream of COMRESETs in this state. 1595 */ 1596 r = AHCI_PREG_SCTL_IPM_DISABLED | AHCI_PREG_SCTL_DET_INIT; 1597 if (AhciForceGen1 & (1 << ap->ap_num)) { 1598 kprintf("%s: Force 1.5Gbits\n", PORTNAME(ap)); 1599 r |= AHCI_PREG_SCTL_SPD_GEN1; 1600 } else { 1601 r |= AHCI_PREG_SCTL_SPD_ANY; 1602 } 1603 ahci_pwrite(ap, AHCI_PREG_SCTL, r); 1604 ahci_os_sleep(1); 1605 1606 /* 1607 * Flush SERR_DIAG_X so the TFD can update. 1608 */ 1609 ahci_flush_tfd(ap); 1610 1611 /* 1612 * Clean out pending ccbs 1613 */ 1614 while (ap->ap_active) { 1615 slot = ffs(ap->ap_active) - 1; 1616 ap->ap_active &= ~(1 << slot); 1617 ap->ap_expired &= ~(1 << slot); 1618 --ap->ap_active_cnt; 1619 ccb = &ap->ap_ccbs[slot]; 1620 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_RUNNING) { 1621 callout_stop(&ccb->ccb_timeout); 1622 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_RUNNING; 1623 } 1624 ccb->ccb_xa.flags &= ~(ATA_F_TIMEOUT_DESIRED | 1625 ATA_F_TIMEOUT_EXPIRED); 1626 ccb->ccb_xa.state = ATA_S_TIMEOUT; 1627 ccb->ccb_done(ccb); 1628 ccb->ccb_xa.complete(&ccb->ccb_xa); 1629 } 1630 while (ap->ap_sactive) { 1631 slot = ffs(ap->ap_sactive) - 1; 1632 ap->ap_sactive &= ~(1 << slot); 1633 ap->ap_expired &= ~(1 << slot); 1634 ccb = &ap->ap_ccbs[slot]; 1635 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_RUNNING) { 1636 callout_stop(&ccb->ccb_timeout); 1637 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_RUNNING; 1638 } 1639 ccb->ccb_xa.flags &= ~(ATA_F_TIMEOUT_DESIRED | 1640 ATA_F_TIMEOUT_EXPIRED); 1641 ccb->ccb_xa.state = ATA_S_TIMEOUT; 1642 ccb->ccb_done(ccb); 1643 ccb->ccb_xa.complete(&ccb->ccb_xa); 1644 } 1645 KKASSERT(ap->ap_active_cnt == 0); 1646 1647 while ((ccb = TAILQ_FIRST(&ap->ap_ccb_pending)) != NULL) { 1648 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry); 1649 ccb->ccb_xa.state = ATA_S_TIMEOUT; 1650 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_DESIRED; 1651 ccb->ccb_done(ccb); 1652 ccb->ccb_xa.complete(&ccb->ccb_xa); 1653 } 1654 1655 /* 1656 * Leave us in COMRESET (both SUD and INIT active), the HBA should 1657 * hopefully send us a DIAG_X-related interrupt if it receives 1658 * a COMINIT, and if not that then at least a Phy transition 1659 * interrupt. 1660 * 1661 * If we transition INIT from 1->0 to begin the initalization 1662 * sequence it is unclear if that sequence will remain active 1663 * until the next device insertion. 1664 * 1665 * If we go back to the listen state it is unclear if the 1666 * device will actually send us a COMINIT, since we aren't 1667 * sending any COMRESET's 1668 */ 1669 /* NOP */ 1670 } 1671 1672 /* 1673 * We can't loop on the X bit, a continuous COMINIT received will make 1674 * it loop forever. Just assume one event has built up and clear X 1675 * so the task file descriptor can update. 1676 */ 1677 void 1678 ahci_flush_tfd(struct ahci_port *ap) 1679 { 1680 u_int32_t r; 1681 1682 r = ahci_pread(ap, AHCI_PREG_SERR); 1683 if (r & AHCI_PREG_SERR_DIAG_X) 1684 ahci_pwrite(ap, AHCI_PREG_SERR, AHCI_PREG_SERR_DIAG_X); 1685 } 1686 1687 /* 1688 * Figure out what type of device is connected to the port, ATAPI or 1689 * DISK. 1690 */ 1691 int 1692 ahci_port_signature_detect(struct ahci_port *ap, struct ata_port *at) 1693 { 1694 u_int32_t sig; 1695 1696 sig = ahci_pread(ap, AHCI_PREG_SIG); 1697 if (bootverbose) 1698 kprintf("%s: sig %08x\n", ATANAME(ap, at), sig); 1699 if ((sig & 0xffff0000) == (SATA_SIGNATURE_ATAPI & 0xffff0000)) { 1700 return(ATA_PORT_T_ATAPI); 1701 } else if ((sig & 0xffff0000) == 1702 (SATA_SIGNATURE_PORT_MULTIPLIER & 0xffff0000)) { 1703 return(ATA_PORT_T_PM); 1704 } else { 1705 return(ATA_PORT_T_DISK); 1706 } 1707 } 1708 1709 /* 1710 * Load the DMA descriptor table for a CCB's buffer. 1711 */ 1712 int 1713 ahci_load_prdt(struct ahci_ccb *ccb) 1714 { 1715 struct ahci_port *ap = ccb->ccb_port; 1716 struct ahci_softc *sc = ap->ap_sc; 1717 struct ata_xfer *xa = &ccb->ccb_xa; 1718 struct ahci_prdt *prdt = ccb->ccb_cmd_table->prdt; 1719 bus_dmamap_t dmap = ccb->ccb_dmamap; 1720 struct ahci_cmd_hdr *cmd_slot = ccb->ccb_cmd_hdr; 1721 int error; 1722 1723 if (xa->datalen == 0) { 1724 ccb->ccb_cmd_hdr->prdtl = 0; 1725 return (0); 1726 } 1727 1728 error = bus_dmamap_load(sc->sc_tag_data, dmap, 1729 xa->data, xa->datalen, 1730 ahci_load_prdt_callback, 1731 &prdt, 1732 ((xa->flags & ATA_F_NOWAIT) ? 1733 BUS_DMA_NOWAIT : BUS_DMA_WAITOK)); 1734 if (error != 0) { 1735 kprintf("%s: error %d loading dmamap\n", PORTNAME(ap), error); 1736 return (1); 1737 } 1738 #if 0 1739 if (xa->flags & ATA_F_PIO) 1740 prdt->flags |= htole32(AHCI_PRDT_FLAG_INTR); 1741 #endif 1742 1743 cmd_slot->prdtl = htole16(prdt - ccb->ccb_cmd_table->prdt + 1); 1744 1745 if (xa->flags & ATA_F_READ) 1746 bus_dmamap_sync(sc->sc_tag_data, dmap, BUS_DMASYNC_PREREAD); 1747 if (xa->flags & ATA_F_WRITE) 1748 bus_dmamap_sync(sc->sc_tag_data, dmap, BUS_DMASYNC_PREWRITE); 1749 1750 return (0); 1751 } 1752 1753 /* 1754 * Callback from BUSDMA system to load the segment list. The passed segment 1755 * list is a temporary structure. 1756 */ 1757 static 1758 void 1759 ahci_load_prdt_callback(void *info, bus_dma_segment_t *segs, int nsegs, 1760 int error) 1761 { 1762 struct ahci_prdt *prd = *(void **)info; 1763 u_int64_t addr; 1764 1765 KKASSERT(nsegs <= AHCI_MAX_PRDT); 1766 1767 while (nsegs) { 1768 addr = segs->ds_addr; 1769 prd->dba_hi = htole32((u_int32_t)(addr >> 32)); 1770 prd->dba_lo = htole32((u_int32_t)addr); 1771 prd->flags = htole32(segs->ds_len - 1); 1772 --nsegs; 1773 if (nsegs) 1774 ++prd; 1775 ++segs; 1776 } 1777 *(void **)info = prd; /* return last valid segment */ 1778 } 1779 1780 void 1781 ahci_unload_prdt(struct ahci_ccb *ccb) 1782 { 1783 struct ahci_port *ap = ccb->ccb_port; 1784 struct ahci_softc *sc = ap->ap_sc; 1785 struct ata_xfer *xa = &ccb->ccb_xa; 1786 bus_dmamap_t dmap = ccb->ccb_dmamap; 1787 1788 if (xa->datalen != 0) { 1789 if (xa->flags & ATA_F_READ) { 1790 bus_dmamap_sync(sc->sc_tag_data, dmap, 1791 BUS_DMASYNC_POSTREAD); 1792 } 1793 if (xa->flags & ATA_F_WRITE) { 1794 bus_dmamap_sync(sc->sc_tag_data, dmap, 1795 BUS_DMASYNC_POSTWRITE); 1796 } 1797 bus_dmamap_unload(sc->sc_tag_data, dmap); 1798 1799 /* 1800 * prdbc is only updated by hardware for non-NCQ commands. 1801 */ 1802 if (ccb->ccb_xa.flags & ATA_F_NCQ) { 1803 xa->resid = 0; 1804 } else { 1805 if (ccb->ccb_cmd_hdr->prdbc == 0 && 1806 ccb->ccb_xa.state == ATA_S_COMPLETE) { 1807 kprintf("%s: WARNING! Unload prdbc resid " 1808 "was zero! tag=%d\n", 1809 ATANAME(ap, xa->at), ccb->ccb_slot); 1810 } 1811 xa->resid = xa->datalen - 1812 le32toh(ccb->ccb_cmd_hdr->prdbc); 1813 } 1814 } 1815 } 1816 1817 /* 1818 * Start a command and poll for completion. 1819 * 1820 * timeout is in ms and only counts once the command gets on-chip. 1821 * 1822 * Returns ATA_S_* state, compare against ATA_S_COMPLETE to determine 1823 * that no error occured. 1824 * 1825 * NOTE: If the caller specifies a NULL timeout function the caller is 1826 * responsible for clearing hardware state on failure, but we will 1827 * deal with removing the ccb from any pending queue. 1828 * 1829 * NOTE: NCQ should never be used with this function. 1830 * 1831 * NOTE: If the port is in a failed state and stopped we do not try 1832 * to activate the ccb. 1833 */ 1834 int 1835 ahci_poll(struct ahci_ccb *ccb, int timeout, 1836 void (*timeout_fn)(struct ahci_ccb *)) 1837 { 1838 struct ahci_port *ap = ccb->ccb_port; 1839 1840 if (ccb->ccb_port->ap_state == AP_S_FATAL_ERROR) { 1841 ccb->ccb_xa.state = ATA_S_ERROR; 1842 return(ccb->ccb_xa.state); 1843 } 1844 crit_enter(); 1845 #if 0 1846 kprintf("%s: Start command %02x tag=%d\n", 1847 ATANAME(ccb->ccb_port, ccb->ccb_xa.at), 1848 ccb->ccb_xa.fis->command, ccb->ccb_slot); 1849 #endif 1850 ahci_start(ccb); 1851 1852 do { 1853 ahci_port_intr(ap, 1); 1854 switch(ccb->ccb_xa.state) { 1855 case ATA_S_ONCHIP: 1856 timeout -= ahci_os_softsleep(); 1857 break; 1858 case ATA_S_PENDING: 1859 ahci_os_softsleep(); 1860 ahci_check_active_timeouts(ap); 1861 break; 1862 default: 1863 crit_exit(); 1864 return (ccb->ccb_xa.state); 1865 } 1866 } while (timeout > 0); 1867 1868 kprintf("%s: Poll timeout slot %d CMD: %b TFD: 0x%b SERR: %b\n", 1869 ATANAME(ap, ccb->ccb_xa.at), ccb->ccb_slot, 1870 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD, 1871 ahci_pread(ap, AHCI_PREG_TFD), AHCI_PFMT_TFD_STS, 1872 ahci_pread(ap, AHCI_PREG_SERR), AHCI_PFMT_SERR); 1873 1874 timeout_fn(ccb); 1875 1876 crit_exit(); 1877 1878 return(ccb->ccb_xa.state); 1879 } 1880 1881 /* 1882 * When polling we have to check if the currently active CCB(s) 1883 * have timed out as the callout will be deadlocked while we 1884 * hold the port lock. 1885 */ 1886 void 1887 ahci_check_active_timeouts(struct ahci_port *ap) 1888 { 1889 struct ahci_ccb *ccb; 1890 u_int32_t mask; 1891 int tag; 1892 1893 mask = ap->ap_active | ap->ap_sactive; 1894 while (mask) { 1895 tag = ffs(mask) - 1; 1896 mask &= ~(1 << tag); 1897 ccb = &ap->ap_ccbs[tag]; 1898 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_EXPIRED) { 1899 ahci_ata_cmd_timeout(ccb); 1900 } 1901 } 1902 } 1903 1904 static 1905 __inline 1906 void 1907 ahci_start_timeout(struct ahci_ccb *ccb) 1908 { 1909 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_DESIRED) { 1910 ccb->ccb_xa.flags |= ATA_F_TIMEOUT_RUNNING; 1911 callout_reset(&ccb->ccb_timeout, 1912 (ccb->ccb_xa.timeout * hz + 999) / 1000, 1913 ahci_ata_cmd_timeout_unserialized, ccb); 1914 } 1915 } 1916 1917 void 1918 ahci_start(struct ahci_ccb *ccb) 1919 { 1920 struct ahci_port *ap = ccb->ccb_port; 1921 struct ahci_softc *sc = ap->ap_sc; 1922 1923 KKASSERT(ccb->ccb_xa.state == ATA_S_PENDING); 1924 1925 /* Zero transferred byte count before transfer */ 1926 ccb->ccb_cmd_hdr->prdbc = 0; 1927 1928 /* Sync command list entry and corresponding command table entry */ 1929 bus_dmamap_sync(sc->sc_tag_cmdh, 1930 AHCI_DMA_MAP(ap->ap_dmamem_cmd_list), 1931 BUS_DMASYNC_PREWRITE); 1932 bus_dmamap_sync(sc->sc_tag_cmdt, 1933 AHCI_DMA_MAP(ap->ap_dmamem_cmd_table), 1934 BUS_DMASYNC_PREWRITE); 1935 1936 /* Prepare RFIS area for write by controller */ 1937 bus_dmamap_sync(sc->sc_tag_rfis, 1938 AHCI_DMA_MAP(ap->ap_dmamem_rfis), 1939 BUS_DMASYNC_PREREAD); 1940 1941 /* 1942 * There's no point trying to optimize this, it only shaves a few 1943 * nanoseconds so just queue the command and call our generic issue. 1944 */ 1945 ahci_issue_pending_commands(ap, ccb); 1946 } 1947 1948 /* 1949 * While holding the port lock acquire exclusive access to the port. 1950 * 1951 * This is used when running the state machine to initialize and identify 1952 * targets over a port multiplier. Setting exclusive access prevents 1953 * ahci_port_intr() from activating any requests sitting on the pending 1954 * queue. 1955 */ 1956 void 1957 ahci_beg_exclusive_access(struct ahci_port *ap, struct ata_port *at) 1958 { 1959 KKASSERT((ap->ap_flags & AP_F_EXCLUSIVE_ACCESS) == 0); 1960 ap->ap_flags |= AP_F_EXCLUSIVE_ACCESS; 1961 while (ap->ap_active || ap->ap_sactive) { 1962 ahci_port_intr(ap, 1); 1963 ahci_os_softsleep(); 1964 } 1965 } 1966 1967 void 1968 ahci_end_exclusive_access(struct ahci_port *ap, struct ata_port *at) 1969 { 1970 KKASSERT((ap->ap_flags & AP_F_EXCLUSIVE_ACCESS) != 0); 1971 ap->ap_flags &= ~AP_F_EXCLUSIVE_ACCESS; 1972 ahci_issue_pending_commands(ap, NULL); 1973 } 1974 1975 #if 0 1976 1977 static void 1978 fubar(struct ahci_ccb *ccb) 1979 { 1980 struct ahci_port *ap = ccb->ccb_port; 1981 struct ahci_cmd_hdr *cmd; 1982 struct ahci_cmd_table *tab; 1983 struct ahci_prdt *prdt; 1984 int i; 1985 1986 kprintf("%s: ISSUE %02x\n", 1987 ATANAME(ap, ccb->ccb_xa.at), 1988 ccb->ccb_xa.fis->command); 1989 cmd = ccb->ccb_cmd_hdr; 1990 tab = ccb->ccb_cmd_table; 1991 prdt = ccb->ccb_cmd_table->prdt; 1992 kprintf("cmd flags=%04x prdtl=%d prdbc=%d ctba=%08x%08x\n", 1993 cmd->flags, cmd->prdtl, cmd->prdbc, 1994 cmd->ctba_hi, cmd->ctba_lo); 1995 for (i = 0; i < cmd->prdtl; ++i) { 1996 kprintf("\t%d dba=%08x%08x res=%08x flags=%08x\n", 1997 i, prdt->dba_hi, prdt->dba_lo, prdt->reserved, 1998 prdt->flags); 1999 } 2000 kprintf("tab\n"); 2001 } 2002 2003 #endif 2004 2005 /* 2006 * If ccb is not NULL enqueue and/or issue it. 2007 * 2008 * If ccb is NULL issue whatever we can from the queue. However, nothing 2009 * new is issued if the exclusive access flag is set or expired ccb's are 2010 * present. 2011 * 2012 * If existing commands are still active (ap_active/ap_sactive) we can only 2013 * issue matching new commands. 2014 */ 2015 void 2016 ahci_issue_pending_commands(struct ahci_port *ap, struct ahci_ccb *ccb) 2017 { 2018 u_int32_t mask; 2019 int limit; 2020 2021 /* 2022 * Enqueue the ccb. 2023 * 2024 * If just running the queue and in exclusive access mode we 2025 * just return. Also in this case if there are any expired ccb's 2026 * we want to clear the queue so the port can be safely stopped. 2027 */ 2028 if (ccb) { 2029 TAILQ_INSERT_TAIL(&ap->ap_ccb_pending, ccb, ccb_entry); 2030 } else if ((ap->ap_flags & AP_F_EXCLUSIVE_ACCESS) || ap->ap_expired) { 2031 return; 2032 } 2033 2034 /* 2035 * Pull the next ccb off the queue and run it if possible. 2036 */ 2037 if ((ccb = TAILQ_FIRST(&ap->ap_ccb_pending)) == NULL) 2038 return; 2039 2040 /* 2041 * Handle exclusivity requirements. 2042 * 2043 * ATA_F_EXCLUSIVE is used when we want to be the only command 2044 * running. 2045 * 2046 * ATA_F_AUTOSENSE is used when we want the D2H rfis loaded 2047 * back into the ccb on a normal (non-errored) command completion. 2048 * For example, for PM requests to target 15. Because the AHCI 2049 * spec does not stop the command processor and has only one rfis 2050 * area (for non-FBSS anyway), AUTOSENSE currently implies EXCLUSIVE. 2051 * Otherwise multiple completions can destroy the rfis data before 2052 * we have a chance to copy it. 2053 */ 2054 if (ap->ap_active & ~ap->ap_expired) { 2055 /* 2056 * There may be multiple ccb's already running, 2057 * if any are running and ap_run_flags sets 2058 * one of these flags then we know only one is 2059 * running. 2060 * 2061 * XXX Current AUTOSENSE code forces exclusivity 2062 * to simplify the code. 2063 */ 2064 if (ap->ap_run_flags & 2065 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) { 2066 return; 2067 } 2068 2069 if (ccb->ccb_xa.flags & 2070 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) { 2071 return; 2072 } 2073 } 2074 2075 if (ccb->ccb_xa.flags & ATA_F_NCQ) { 2076 /* 2077 * The next command is a NCQ command and can be issued as 2078 * long as currently active commands are not standard. 2079 */ 2080 if (ap->ap_active) { 2081 KKASSERT(ap->ap_active_cnt > 0); 2082 return; 2083 } 2084 KKASSERT(ap->ap_active_cnt == 0); 2085 2086 mask = 0; 2087 do { 2088 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry); 2089 mask |= 1 << ccb->ccb_slot; 2090 ccb->ccb_xa.state = ATA_S_ONCHIP; 2091 ahci_start_timeout(ccb); 2092 ap->ap_run_flags = ccb->ccb_xa.flags; 2093 ccb = TAILQ_FIRST(&ap->ap_ccb_pending); 2094 } while (ccb && (ccb->ccb_xa.flags & ATA_F_NCQ) && 2095 (ap->ap_run_flags & 2096 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) == 0); 2097 2098 ap->ap_sactive |= mask; 2099 ahci_pwrite(ap, AHCI_PREG_SACT, mask); 2100 ahci_pwrite(ap, AHCI_PREG_CI, mask); 2101 } else { 2102 /* 2103 * The next command is a standard command and can be issued 2104 * as long as currently active commands are not NCQ. 2105 * 2106 * We limit ourself to 1 command if we have a port multiplier, 2107 * (at least without FBSS support), otherwise timeouts on 2108 * one port can race completions on other ports (see 2109 * ahci_ata_cmd_timeout() for more information). 2110 * 2111 * If not on a port multiplier generally allow up to 4 2112 * standard commands to be enqueued. Remember that the 2113 * command processor will still process them sequentially. 2114 */ 2115 if (ap->ap_sactive) 2116 return; 2117 if (ap->ap_type == ATA_PORT_T_PM) 2118 limit = 1; 2119 else if (ap->ap_sc->sc_ncmds > 4) 2120 limit = 4; 2121 else 2122 limit = 2; 2123 2124 while (ap->ap_active_cnt < limit && ccb && 2125 (ccb->ccb_xa.flags & ATA_F_NCQ) == 0) { 2126 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry); 2127 #if 0 2128 fubar(ccb); 2129 #endif 2130 ap->ap_active |= 1 << ccb->ccb_slot; 2131 ap->ap_active_cnt++; 2132 ap->ap_run_flags = ccb->ccb_xa.flags; 2133 ccb->ccb_xa.state = ATA_S_ONCHIP; 2134 ahci_pwrite(ap, AHCI_PREG_CI, 1 << ccb->ccb_slot); 2135 ahci_start_timeout(ccb); 2136 if ((ap->ap_run_flags & 2137 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) == 0) { 2138 break; 2139 } 2140 ccb = TAILQ_FIRST(&ap->ap_ccb_pending); 2141 if (ccb && (ccb->ccb_xa.flags & 2142 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE))) { 2143 break; 2144 } 2145 } 2146 } 2147 } 2148 2149 void 2150 ahci_intr(void *arg) 2151 { 2152 struct ahci_softc *sc = arg; 2153 struct ahci_port *ap; 2154 u_int32_t is; 2155 u_int32_t ack; 2156 int port; 2157 2158 /* 2159 * Check if the master enable is up, and whether any interrupts are 2160 * pending. 2161 */ 2162 if ((sc->sc_flags & AHCI_F_INT_GOOD) == 0) 2163 return; 2164 is = ahci_read(sc, AHCI_REG_IS); 2165 if (is == 0 || is == 0xffffffff) { 2166 return; 2167 } 2168 is &= sc->sc_portmask; 2169 2170 #ifdef AHCI_COALESCE 2171 /* Check coalescing interrupt first */ 2172 if (is & sc->sc_ccc_mask) { 2173 DPRINTF(AHCI_D_INTR, "%s: command coalescing interrupt\n", 2174 DEVNAME(sc)); 2175 is &= ~sc->sc_ccc_mask; 2176 is |= sc->sc_ccc_ports_cur; 2177 } 2178 #endif 2179 2180 /* 2181 * Process interrupts for each port in a non-blocking fashion. 2182 * 2183 * The global IS bit is forced on if any unmasked port interrupts 2184 * are pending, even if we clear. 2185 */ 2186 for (ack = 0; is; is &= ~(1 << port)) { 2187 port = ffs(is) - 1; 2188 ack |= 1 << port; 2189 2190 ap = sc->sc_ports[port]; 2191 if (ap == NULL) 2192 continue; 2193 2194 if (ahci_os_lock_port_nb(ap) == 0) { 2195 ahci_port_intr(ap, 0); 2196 ahci_os_unlock_port(ap); 2197 } else { 2198 ahci_pwrite(ap, AHCI_PREG_IE, 0); 2199 ahci_os_signal_port_thread(ap, AP_SIGF_PORTINT); 2200 } 2201 } 2202 ahci_write(sc, AHCI_REG_IS, ack); 2203 } 2204 2205 /* 2206 * Core called from helper thread. 2207 */ 2208 void 2209 ahci_port_thread_core(struct ahci_port *ap, int mask) 2210 { 2211 /* 2212 * Process any expired timedouts. 2213 */ 2214 ahci_os_lock_port(ap); 2215 if (mask & AP_SIGF_TIMEOUT) { 2216 ahci_check_active_timeouts(ap); 2217 } 2218 2219 /* 2220 * Process port interrupts which require a higher level of 2221 * intervention. 2222 */ 2223 if (mask & AP_SIGF_PORTINT) { 2224 ahci_port_intr(ap, 1); 2225 ahci_port_interrupt_enable(ap); 2226 ahci_os_unlock_port(ap); 2227 } else if (ap->ap_probe != ATA_PROBE_FAILED) { 2228 ahci_port_intr(ap, 1); 2229 ahci_port_interrupt_enable(ap); 2230 ahci_os_unlock_port(ap); 2231 } else { 2232 ahci_os_unlock_port(ap); 2233 } 2234 } 2235 2236 /* 2237 * Core per-port interrupt handler. 2238 * 2239 * If blockable is 0 we cannot call ahci_os_sleep() at all and we can only 2240 * deal with normal command completions which do not require blocking. 2241 */ 2242 void 2243 ahci_port_intr(struct ahci_port *ap, int blockable) 2244 { 2245 struct ahci_softc *sc = ap->ap_sc; 2246 u_int32_t is, ci_saved, ci_masked; 2247 int slot; 2248 struct ahci_ccb *ccb = NULL; 2249 struct ata_port *ccb_at = NULL; 2250 volatile u_int32_t *active; 2251 const u_int32_t blockable_mask = AHCI_PREG_IS_TFES | 2252 AHCI_PREG_IS_IFS | 2253 AHCI_PREG_IS_PCS | 2254 AHCI_PREG_IS_PRCS | 2255 AHCI_PREG_IS_HBFS | 2256 AHCI_PREG_IS_OFS | 2257 AHCI_PREG_IS_UFS; 2258 2259 enum { NEED_NOTHING, NEED_RESTART, NEED_HOTPLUG_INSERT, 2260 NEED_HOTPLUG_REMOVE } need = NEED_NOTHING; 2261 2262 /* 2263 * All basic command completions are always processed. 2264 */ 2265 is = ahci_pread(ap, AHCI_PREG_IS); 2266 if (is & AHCI_PREG_IS_DPS) 2267 ahci_pwrite(ap, AHCI_PREG_IS, is & AHCI_PREG_IS_DPS); 2268 2269 /* 2270 * If we can't block then we can't handle these here. Disable 2271 * the interrupts in question so we don't live-lock, the helper 2272 * thread will re-enable them. 2273 * 2274 * If the port is in a completely failed state we do not want 2275 * to drop through to failed-command-processing if blockable is 0, 2276 * just let the thread deal with it all. 2277 * 2278 * Otherwise we fall through and still handle DHRS and any commands 2279 * which completed normally. Even if we are errored we haven't 2280 * stopped the port yet so CI/SACT are still good. 2281 */ 2282 if (blockable == 0) { 2283 if (ap->ap_state == AP_S_FATAL_ERROR) { 2284 ahci_pwrite(ap, AHCI_PREG_IE, 0); 2285 ahci_os_signal_port_thread(ap, AP_SIGF_PORTINT); 2286 return; 2287 } 2288 if (is & blockable_mask) { 2289 ahci_pwrite(ap, AHCI_PREG_IE, 0); 2290 ahci_os_signal_port_thread(ap, AP_SIGF_PORTINT); 2291 return; 2292 } 2293 } 2294 2295 /* 2296 * Either NCQ or non-NCQ commands will be active, never both. 2297 */ 2298 if (ap->ap_sactive) { 2299 KKASSERT(ap->ap_active == 0); 2300 KKASSERT(ap->ap_active_cnt == 0); 2301 ci_saved = ahci_pread(ap, AHCI_PREG_SACT); 2302 active = &ap->ap_sactive; 2303 } else { 2304 ci_saved = ahci_pread(ap, AHCI_PREG_CI); 2305 active = &ap->ap_active; 2306 } 2307 KKASSERT(!(ap->ap_sactive && ap->ap_active)); 2308 #if 0 2309 kprintf("CHECK act=%08x/%08x sact=%08x/%08x\n", 2310 ap->ap_active, ahci_pread(ap, AHCI_PREG_CI), 2311 ap->ap_sactive, ahci_pread(ap, AHCI_PREG_SACT)); 2312 #endif 2313 2314 /* ignore AHCI_PREG_IS_PRCS when link power management is on */ 2315 if (ap->link_pwr_mgmt != AHCI_LINK_PWR_MGMT_NONE) { 2316 is &= ~AHCI_PREG_IS_PRCS; 2317 ahci_pwrite(ap, AHCI_PREG_SERR, 2318 AHCI_PREG_SERR_DIAG_N | AHCI_PREG_SERR_DIAG_W); 2319 } 2320 2321 if (is & AHCI_PREG_IS_TFES) { 2322 /* 2323 * Command failed (blockable). 2324 * 2325 * See AHCI 1.1 spec 6.2.2.1 and 6.2.2.2. 2326 * 2327 * This stops command processing. 2328 */ 2329 u_int32_t tfd, serr; 2330 int err_slot; 2331 2332 process_error: 2333 tfd = ahci_pread(ap, AHCI_PREG_TFD); 2334 serr = ahci_pread(ap, AHCI_PREG_SERR); 2335 2336 /* 2337 * Load the error slot and restart command processing. 2338 * CLO if we need to. The error slot may not be valid. 2339 * MUST BE DONE BEFORE CLEARING ST! 2340 * 2341 * Cycle ST. 2342 * 2343 * It is unclear but we may have to clear SERR to reenable 2344 * error processing. 2345 */ 2346 err_slot = AHCI_PREG_CMD_CCS(ahci_pread(ap, AHCI_PREG_CMD)); 2347 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_TFES | 2348 AHCI_PREG_IS_PSS | 2349 AHCI_PREG_IS_DHRS | 2350 AHCI_PREG_IS_SDBS); 2351 is &= ~(AHCI_PREG_IS_TFES | AHCI_PREG_IS_PSS | 2352 AHCI_PREG_IS_DHRS | AHCI_PREG_IS_SDBS); 2353 ahci_pwrite(ap, AHCI_PREG_SERR, serr); 2354 ahci_port_stop(ap, 0); 2355 ahci_os_hardsleep(10); 2356 if (tfd & (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 2357 kprintf("%s: Issuing CLO\n", PORTNAME(ap)); 2358 ahci_port_clo(ap); 2359 } 2360 ahci_port_start(ap); 2361 need = NEED_RESTART; 2362 2363 /* 2364 * ATAPI errors are fairly common from probing, just 2365 * report disk errors or if bootverbose is on. 2366 */ 2367 if (bootverbose || ap->ap_type != ATA_PORT_T_ATAPI) { 2368 kprintf("%s: TFES slot %d ci_saved = %08x\n", 2369 PORTNAME(ap), err_slot, ci_saved); 2370 } 2371 2372 /* 2373 * If we got an error on an error CCB just complete it 2374 * with an error. ci_saved has the mask to restart 2375 * (the err_ccb will be removed from it by finish_error). 2376 */ 2377 if (ap->ap_flags & AP_F_ERR_CCB_RESERVED) { 2378 err_slot = ap->ap_err_ccb->ccb_slot; 2379 goto finish_error; 2380 } 2381 2382 /* 2383 * If NCQ commands were active get the error slot from 2384 * the log page. NCQ is not supported for PM's so this 2385 * is a direct-attached target. 2386 * 2387 * Otherwise if no commands were active we have a problem. 2388 * 2389 * Otherwise if the error slot is bad we have a problem. 2390 * 2391 * Otherwise process the error for the slot. 2392 */ 2393 if (ap->ap_sactive) { 2394 err_slot = ahci_port_read_ncq_error(ap, 0); 2395 } else if (ap->ap_active == 0) { 2396 kprintf("%s: TFES with no commands pending\n", 2397 PORTNAME(ap)); 2398 err_slot = -1; 2399 } else if (err_slot < 0 || err_slot >= ap->ap_sc->sc_ncmds) { 2400 kprintf("%s: bad error slot %d\n", 2401 PORTNAME(ap), err_slot); 2402 err_slot = -1; 2403 } else { 2404 ccb = &ap->ap_ccbs[err_slot]; 2405 2406 /* 2407 * Validate the errored ccb. Note that ccb_at can 2408 * be NULL for direct-attached ccb's. 2409 * 2410 * Copy received taskfile data from the RFIS. 2411 */ 2412 if (ccb->ccb_xa.state == ATA_S_ONCHIP) { 2413 ccb_at = ccb->ccb_xa.at; 2414 memcpy(&ccb->ccb_xa.rfis, ap->ap_rfis->rfis, 2415 sizeof(struct ata_fis_d2h)); 2416 if (bootverbose) { 2417 kprintf("%s: Copying rfis slot %d\n", 2418 ATANAME(ap, ccb_at), err_slot); 2419 } 2420 } else { 2421 kprintf("%s: Cannot copy rfis, CCB slot " 2422 "%d is not on-chip (state=%d)\n", 2423 ATANAME(ap, ccb->ccb_xa.at), 2424 err_slot, ccb->ccb_xa.state); 2425 err_slot = -1; 2426 } 2427 } 2428 2429 /* 2430 * If we could not determine the errored slot then 2431 * reset the port. 2432 */ 2433 if (err_slot < 0) { 2434 kprintf("%s: TFES: Unable to determine errored slot\n", 2435 PORTNAME(ap)); 2436 if (ap->ap_flags & AP_F_IN_RESET) 2437 goto fatal; 2438 goto failall; 2439 } 2440 2441 /* 2442 * Finish error on slot. We will restart ci_saved 2443 * commands except the errored slot which we generate 2444 * a failure for. 2445 */ 2446 finish_error: 2447 ccb = &ap->ap_ccbs[err_slot]; 2448 ci_saved &= ~(1 << err_slot); 2449 KKASSERT(ccb->ccb_xa.state == ATA_S_ONCHIP); 2450 ccb->ccb_xa.state = ATA_S_ERROR; 2451 } else if (is & AHCI_PREG_IS_DHRS) { 2452 /* 2453 * Command posted D2H register FIS to the rfis (non-blocking). 2454 * 2455 * A normal completion with an error may set DHRS instead 2456 * of TFES. The CCS bits are only valid if ERR was set. 2457 * If ERR is set command processing was probably stopped. 2458 * 2459 * If ERR was not set we can only copy-back data for 2460 * exclusive-mode commands because otherwise we won't know 2461 * which tag the rfis belonged to. 2462 * 2463 * err_slot must be read from the CCS before any other port 2464 * action, such as stopping the port. 2465 * 2466 * WARNING! This is not well documented in the AHCI spec. 2467 * It can be found in the state machine tables 2468 * but not in the explanations. 2469 */ 2470 u_int32_t tfd; 2471 u_int32_t cmd; 2472 int err_slot; 2473 2474 tfd = ahci_pread(ap, AHCI_PREG_TFD); 2475 cmd = ahci_pread(ap, AHCI_PREG_CMD); 2476 2477 if ((tfd & AHCI_PREG_TFD_STS_ERR) && 2478 (cmd & AHCI_PREG_CMD_CR) == 0) { 2479 err_slot = AHCI_PREG_CMD_CCS( 2480 ahci_pread(ap, AHCI_PREG_CMD)); 2481 ccb = &ap->ap_ccbs[err_slot]; 2482 kprintf("%s: DHRS tfd=%b err_slot=%d cmd=%02x\n", 2483 PORTNAME(ap), 2484 tfd, AHCI_PFMT_TFD_STS, 2485 err_slot, ccb->ccb_xa.fis->command); 2486 goto process_error; 2487 } 2488 /* 2489 * NO ELSE... copy back is in the normal command completion 2490 * code and only if no error occured and ATA_F_AUTOSENSE 2491 * was set. 2492 */ 2493 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_DHRS); 2494 } 2495 2496 /* 2497 * Device notification to us (non-blocking) 2498 * 2499 * NOTE! On some parts notification bits can cause an IPMS 2500 * interrupt instead of a SDBS interrupt. 2501 * 2502 * NOTE! On some parts (e.g. VBOX, probably intel ICHx), 2503 * SDBS notifies us of the completion of a NCQ command 2504 * and DBS does not. 2505 */ 2506 if (is & (AHCI_PREG_IS_SDBS | AHCI_PREG_IS_IPMS)) { 2507 u_int32_t data; 2508 2509 ahci_pwrite(ap, AHCI_PREG_IS, 2510 AHCI_PREG_IS_SDBS | AHCI_PREG_IS_IPMS); 2511 if (sc->sc_cap & AHCI_REG_CAP_SSNTF) { 2512 data = ahci_pread(ap, AHCI_PREG_SNTF); 2513 if (data) { 2514 ahci_pwrite(ap, AHCI_PREG_IS, 2515 AHCI_PREG_IS_SDBS); 2516 kprintf("%s: NOTIFY %08x\n", 2517 PORTNAME(ap), data); 2518 ahci_pwrite(ap, AHCI_PREG_SERR, 2519 AHCI_PREG_SERR_DIAG_N); 2520 ahci_pwrite(ap, AHCI_PREG_SNTF, data); 2521 ahci_cam_changed(ap, NULL, -1); 2522 } 2523 } 2524 is &= ~(AHCI_PREG_IS_SDBS | AHCI_PREG_IS_IPMS); 2525 } 2526 2527 /* 2528 * Spurious IFS errors (blockable). 2529 * 2530 * Spurious IFS errors can occur while we are doing a reset 2531 * sequence through a PM. Try to recover if we are being asked 2532 * to ignore IFS errors during these periods. 2533 */ 2534 if ((is & AHCI_PREG_IS_IFS) && (ap->ap_flags & AP_F_IGNORE_IFS)) { 2535 u_int32_t serr = ahci_pread(ap, AHCI_PREG_SERR); 2536 if ((ap->ap_flags & AP_F_IFS_IGNORED) == 0) { 2537 kprintf("%s: Ignoring IFS (XXX) (IS: %b, SERR: %b)\n", 2538 PORTNAME(ap), 2539 is, AHCI_PFMT_IS, 2540 serr, AHCI_PFMT_SERR); 2541 ap->ap_flags |= AP_F_IFS_IGNORED; 2542 } 2543 ap->ap_flags |= AP_F_IFS_OCCURED; 2544 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 2545 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_IFS); 2546 is &= ~AHCI_PREG_IS_IFS; 2547 ahci_port_stop(ap, 0); 2548 ahci_port_start(ap); 2549 kprintf("%s: Spurious IFS error\n", PORTNAME(ap)); 2550 goto failall; 2551 /* need = NEED_RESTART; */ 2552 } 2553 2554 /* 2555 * Port change (hot-plug) (blockable). 2556 * 2557 * A PCS interrupt will occur on hot-plug once communication is 2558 * established. 2559 * 2560 * A PRCS interrupt will occur on hot-unplug (and possibly also 2561 * on hot-plug). 2562 * 2563 * XXX We can then check the CPS (Cold Presence State) bit, if 2564 * supported, to determine if a device is plugged in or not and do 2565 * the right thing. 2566 * 2567 * WARNING: A PCS interrupt is cleared by clearing DIAG_X, and 2568 * can also occur if an unsolicited COMINIT is received. 2569 * If this occurs command processing is automatically 2570 * stopped (CR goes inactive) and the port must be stopped 2571 * and restarted. 2572 */ 2573 2574 if (is & (AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS)) { 2575 kprintf("%s: Transient Errors: %b\n", 2576 PORTNAME(ap), is, AHCI_PFMT_IS); 2577 ahci_pwrite(ap, AHCI_PREG_SERR, 2578 (AHCI_PREG_SERR_DIAG_N | AHCI_PREG_SERR_DIAG_X)); 2579 ahci_pwrite(ap, AHCI_PREG_IS, 2580 is & (AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS)); 2581 is &= ~(AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS); 2582 ahci_port_stop(ap, 0); 2583 2584 switch (ahci_pread(ap, AHCI_PREG_SSTS) & AHCI_PREG_SSTS_DET) { 2585 case AHCI_PREG_SSTS_DET_DEV: 2586 if (ap->ap_probe == ATA_PROBE_FAILED) { 2587 need = NEED_HOTPLUG_INSERT; 2588 goto fatal; 2589 } 2590 need = NEED_RESTART; 2591 break; 2592 default: 2593 if (ap->ap_probe != ATA_PROBE_FAILED) { 2594 need = NEED_HOTPLUG_REMOVE; 2595 goto fatal; 2596 } 2597 need = NEED_RESTART; 2598 break; 2599 } 2600 } 2601 2602 /* 2603 * Check for remaining errors - they are fatal. (blockable) 2604 */ 2605 if (is & (AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS | AHCI_PREG_IS_IFS | 2606 AHCI_PREG_IS_OFS | AHCI_PREG_IS_UFS)) { 2607 u_int32_t serr; 2608 2609 ahci_pwrite(ap, AHCI_PREG_IS, 2610 is & (AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS | 2611 AHCI_PREG_IS_IFS | AHCI_PREG_IS_OFS | 2612 AHCI_PREG_IS_UFS)); 2613 serr = ahci_pread(ap, AHCI_PREG_SERR); 2614 kprintf("%s: Unrecoverable errors (IS: %b, SERR: %b), " 2615 "disabling port.\n", 2616 PORTNAME(ap), 2617 is, AHCI_PFMT_IS, 2618 serr, AHCI_PFMT_SERR 2619 ); 2620 is &= ~(AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS | 2621 AHCI_PREG_IS_IFS | AHCI_PREG_IS_OFS | 2622 AHCI_PREG_IS_UFS); 2623 /* XXX try recovery first */ 2624 goto fatal; 2625 } 2626 2627 /* 2628 * Fail all outstanding commands if we know the port won't recover. 2629 * 2630 * We may have a ccb_at if the failed command is known and was 2631 * being sent to a device over a port multiplier (PM). In this 2632 * case if the port itself has not completely failed we fail just 2633 * the commands related to that target. 2634 * 2635 * ci_saved contains the mask of active commands as of when the 2636 * error occured, prior to any port stops. 2637 */ 2638 if (ap->ap_state == AP_S_FATAL_ERROR) { 2639 fatal: 2640 ap->ap_state = AP_S_FATAL_ERROR; 2641 ahci_port_stop(ap, 0); 2642 failall: 2643 kprintf("%s: Failing all commands\n", PORTNAME(ap)); 2644 2645 /* 2646 * Error all the active slots not already errored. If 2647 * running across a PM try to error out just the slots 2648 * related to the target. 2649 */ 2650 ci_masked = ci_saved & *active & ~ap->ap_expired; 2651 while (ci_masked) { 2652 slot = ffs(ci_masked) - 1; 2653 ccb = &ap->ap_ccbs[slot]; 2654 if (ccb_at == ccb->ccb_xa.at || 2655 ap->ap_state == AP_S_FATAL_ERROR) { 2656 ccb->ccb_xa.state = ATA_S_TIMEOUT; 2657 ap->ap_expired |= 1 << slot; 2658 ci_saved &= ~(1 << slot); 2659 } 2660 ci_masked &= ~(1 << slot); 2661 } 2662 2663 /* 2664 * Clear bits in ci_saved (cause completions to be run) 2665 * for all slots which are not active. 2666 */ 2667 ci_saved &= ~*active; 2668 2669 /* 2670 * Don't restart the port if our problems were deemed fatal. 2671 * 2672 * Also acknowlege all fatal interrupt sources to prevent 2673 * a livelock. 2674 */ 2675 if (ap->ap_state == AP_S_FATAL_ERROR) { 2676 if (need == NEED_RESTART) 2677 need = NEED_NOTHING; 2678 ahci_pwrite(ap, AHCI_PREG_IS, 2679 AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS | 2680 AHCI_PREG_IS_IFS | AHCI_PREG_IS_OFS | 2681 AHCI_PREG_IS_UFS); 2682 } 2683 } 2684 2685 /* 2686 * CCB completion (non blocking). 2687 * 2688 * CCB completion is detected by noticing its slot's bit in CI has 2689 * changed to zero some time after we activated it. 2690 * If we are polling, we may only be interested in particular slot(s). 2691 * 2692 * Any active bits not saved are completed within the restrictions 2693 * imposed by the caller. 2694 */ 2695 ci_masked = ~ci_saved & *active; 2696 while (ci_masked) { 2697 slot = ffs(ci_masked) - 1; 2698 ccb = &ap->ap_ccbs[slot]; 2699 ci_masked &= ~(1 << slot); 2700 2701 DPRINTF(AHCI_D_INTR, "%s: slot %d is complete%s\n", 2702 PORTNAME(ap), slot, ccb->ccb_xa.state == ATA_S_ERROR ? 2703 " (error)" : ""); 2704 2705 bus_dmamap_sync(sc->sc_tag_cmdh, 2706 AHCI_DMA_MAP(ap->ap_dmamem_cmd_list), 2707 BUS_DMASYNC_POSTWRITE); 2708 2709 bus_dmamap_sync(sc->sc_tag_cmdt, 2710 AHCI_DMA_MAP(ap->ap_dmamem_cmd_table), 2711 BUS_DMASYNC_POSTWRITE); 2712 2713 bus_dmamap_sync(sc->sc_tag_rfis, 2714 AHCI_DMA_MAP(ap->ap_dmamem_rfis), 2715 BUS_DMASYNC_POSTREAD); 2716 2717 *active &= ~(1 << ccb->ccb_slot); 2718 if (active == &ap->ap_active) { 2719 KKASSERT(ap->ap_active_cnt > 0); 2720 --ap->ap_active_cnt; 2721 } 2722 2723 /* 2724 * Complete the ccb. If the ccb was marked expired it 2725 * was probably already removed from the command processor, 2726 * so don't take the clear ci_saved bit as meaning the 2727 * command actually succeeded, it didn't. 2728 */ 2729 if (ap->ap_expired & (1 << ccb->ccb_slot)) { 2730 ap->ap_expired &= ~(1 << ccb->ccb_slot); 2731 ccb->ccb_xa.state = ATA_S_TIMEOUT; 2732 ccb->ccb_done(ccb); 2733 ccb->ccb_xa.complete(&ccb->ccb_xa); 2734 } else { 2735 if (ccb->ccb_xa.state == ATA_S_ONCHIP) { 2736 ccb->ccb_xa.state = ATA_S_COMPLETE; 2737 if (ccb->ccb_xa.flags & ATA_F_AUTOSENSE) { 2738 memcpy(&ccb->ccb_xa.rfis, 2739 ap->ap_rfis->rfis, 2740 sizeof(struct ata_fis_d2h)); 2741 if (ccb->ccb_xa.state == ATA_S_TIMEOUT) 2742 ccb->ccb_xa.state = ATA_S_ERROR; 2743 } 2744 } 2745 ccb->ccb_done(ccb); 2746 } 2747 } 2748 ahci_issue_pending_commands(ap, NULL); 2749 2750 /* 2751 * Cleanup. Will not be set if non-blocking. 2752 */ 2753 switch(need) { 2754 case NEED_RESTART: 2755 /* 2756 * A recoverable error occured and we can restart outstanding 2757 * commands on the port. 2758 */ 2759 ci_saved &= ~ap->ap_expired; 2760 if (ci_saved) { 2761 kprintf("%s: Restart %08x\n", PORTNAME(ap), ci_saved); 2762 ahci_issue_saved_commands(ap, ci_saved); 2763 } 2764 break; 2765 case NEED_HOTPLUG_INSERT: 2766 /* 2767 * A hot-plug insertion event has occured and all 2768 * outstanding commands have already been revoked. 2769 * 2770 * Don't recurse if this occurs while we are 2771 * resetting the port. 2772 */ 2773 if ((ap->ap_flags & AP_F_IN_RESET) == 0) { 2774 kprintf("%s: HOTPLUG - Device inserted\n", 2775 PORTNAME(ap)); 2776 ap->ap_probe = ATA_PROBE_NEED_INIT; 2777 ahci_cam_changed(ap, NULL, -1); 2778 } 2779 break; 2780 case NEED_HOTPLUG_REMOVE: 2781 /* 2782 * A hot-plug removal event has occured and all 2783 * outstanding commands have already been revoked. 2784 * 2785 * Don't recurse if this occurs while we are 2786 * resetting the port. 2787 */ 2788 if ((ap->ap_flags & AP_F_IN_RESET) == 0) { 2789 kprintf("%s: HOTPLUG - Device removed\n", 2790 PORTNAME(ap)); 2791 ahci_port_hardstop(ap); 2792 /* ap_probe set to failed */ 2793 ahci_cam_changed(ap, NULL, -1); 2794 } 2795 break; 2796 default: 2797 break; 2798 } 2799 } 2800 2801 struct ahci_ccb * 2802 ahci_get_ccb(struct ahci_port *ap) 2803 { 2804 struct ahci_ccb *ccb; 2805 2806 lockmgr(&ap->ap_ccb_lock, LK_EXCLUSIVE); 2807 ccb = TAILQ_FIRST(&ap->ap_ccb_free); 2808 if (ccb != NULL) { 2809 KKASSERT(ccb->ccb_xa.state == ATA_S_PUT); 2810 TAILQ_REMOVE(&ap->ap_ccb_free, ccb, ccb_entry); 2811 ccb->ccb_xa.state = ATA_S_SETUP; 2812 ccb->ccb_xa.at = NULL; 2813 } 2814 lockmgr(&ap->ap_ccb_lock, LK_RELEASE); 2815 2816 return (ccb); 2817 } 2818 2819 void 2820 ahci_put_ccb(struct ahci_ccb *ccb) 2821 { 2822 struct ahci_port *ap = ccb->ccb_port; 2823 2824 ccb->ccb_xa.state = ATA_S_PUT; 2825 lockmgr(&ap->ap_ccb_lock, LK_EXCLUSIVE); 2826 TAILQ_INSERT_TAIL(&ap->ap_ccb_free, ccb, ccb_entry); 2827 lockmgr(&ap->ap_ccb_lock, LK_RELEASE); 2828 } 2829 2830 struct ahci_ccb * 2831 ahci_get_err_ccb(struct ahci_port *ap) 2832 { 2833 struct ahci_ccb *err_ccb; 2834 u_int32_t sact; 2835 u_int32_t ci; 2836 2837 /* No commands may be active on the chip. */ 2838 2839 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SNCQ) { 2840 sact = ahci_pread(ap, AHCI_PREG_SACT); 2841 if (sact != 0) { 2842 kprintf("%s: ahci_get_err_ccb but SACT %08x != 0?\n", 2843 PORTNAME(ap), sact); 2844 } 2845 } 2846 ci = ahci_pread(ap, AHCI_PREG_CI); 2847 if (ci) { 2848 kprintf("%s: ahci_get_err_ccb: ci not 0 (%08x)\n", 2849 ap->ap_name, ci); 2850 } 2851 KKASSERT(ci == 0); 2852 KKASSERT((ap->ap_flags & AP_F_ERR_CCB_RESERVED) == 0); 2853 ap->ap_flags |= AP_F_ERR_CCB_RESERVED; 2854 2855 /* Save outstanding command state. */ 2856 ap->ap_err_saved_active = ap->ap_active; 2857 ap->ap_err_saved_active_cnt = ap->ap_active_cnt; 2858 ap->ap_err_saved_sactive = ap->ap_sactive; 2859 2860 /* 2861 * Pretend we have no commands outstanding, so that completions won't 2862 * run prematurely. 2863 */ 2864 ap->ap_active = ap->ap_active_cnt = ap->ap_sactive = 0; 2865 2866 /* 2867 * Grab a CCB to use for error recovery. This should never fail, as 2868 * we ask atascsi to reserve one for us at init time. 2869 */ 2870 err_ccb = ap->ap_err_ccb; 2871 KKASSERT(err_ccb != NULL); 2872 err_ccb->ccb_xa.flags = 0; 2873 err_ccb->ccb_done = ahci_empty_done; 2874 2875 return err_ccb; 2876 } 2877 2878 void 2879 ahci_put_err_ccb(struct ahci_ccb *ccb) 2880 { 2881 struct ahci_port *ap = ccb->ccb_port; 2882 u_int32_t sact; 2883 u_int32_t ci; 2884 2885 KKASSERT((ap->ap_flags & AP_F_ERR_CCB_RESERVED) != 0); 2886 2887 /* 2888 * No commands may be active on the chip 2889 */ 2890 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SNCQ) { 2891 sact = ahci_pread(ap, AHCI_PREG_SACT); 2892 if (sact) { 2893 panic("ahci_port_err_ccb(%d) but SACT %08x != 0\n", 2894 ccb->ccb_slot, sact); 2895 } 2896 } 2897 ci = ahci_pread(ap, AHCI_PREG_CI); 2898 if (ci) { 2899 panic("ahci_put_err_ccb(%d) but CI %08x != 0 " 2900 "(act=%08x sact=%08x)\n", 2901 ccb->ccb_slot, ci, 2902 ap->ap_active, ap->ap_sactive); 2903 } 2904 2905 KKASSERT(ccb == ap->ap_err_ccb); 2906 2907 /* Restore outstanding command state */ 2908 ap->ap_sactive = ap->ap_err_saved_sactive; 2909 ap->ap_active_cnt = ap->ap_err_saved_active_cnt; 2910 ap->ap_active = ap->ap_err_saved_active; 2911 2912 ap->ap_flags &= ~AP_F_ERR_CCB_RESERVED; 2913 } 2914 2915 /* 2916 * Read log page to get NCQ error. 2917 * 2918 * NOTE: NCQ not currently supported on port multipliers. XXX 2919 */ 2920 int 2921 ahci_port_read_ncq_error(struct ahci_port *ap, int target) 2922 { 2923 struct ata_log_page_10h *log; 2924 struct ahci_ccb *ccb; 2925 struct ahci_cmd_hdr *cmd_slot; 2926 struct ata_fis_h2d *fis; 2927 int err_slot; 2928 2929 if (bootverbose) { 2930 kprintf("%s: READ LOG PAGE target %d\n", PORTNAME(ap), 2931 target); 2932 } 2933 2934 /* 2935 * Prep error CCB for READ LOG EXT, page 10h, 1 sector. 2936 * 2937 * Getting err_ccb clears active/sactive/active_cnt, putting 2938 * it back restores the fields. 2939 */ 2940 ccb = ahci_get_err_ccb(ap); 2941 ccb->ccb_xa.flags = ATA_F_READ | ATA_F_POLL; 2942 ccb->ccb_xa.data = ap->ap_err_scratch; 2943 ccb->ccb_xa.datalen = 512; 2944 ccb->ccb_xa.complete = ahci_dummy_done; 2945 ccb->ccb_xa.at = ap->ap_ata[target]; 2946 2947 fis = (struct ata_fis_h2d *)ccb->ccb_cmd_table->cfis; 2948 bzero(fis, sizeof(*fis)); 2949 fis->type = ATA_FIS_TYPE_H2D; 2950 fis->flags = ATA_H2D_FLAGS_CMD | target; 2951 fis->command = ATA_C_READ_LOG_EXT; 2952 fis->lba_low = 0x10; /* queued error log page (10h) */ 2953 fis->sector_count = 1; /* number of sectors (1) */ 2954 fis->sector_count_exp = 0; 2955 fis->lba_mid = 0; /* starting offset */ 2956 fis->lba_mid_exp = 0; 2957 fis->device = 0; 2958 2959 cmd_slot = ccb->ccb_cmd_hdr; 2960 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */ 2961 2962 if (ahci_load_prdt(ccb) != 0) { 2963 err_slot = -1; 2964 goto err; 2965 } 2966 2967 ccb->ccb_xa.state = ATA_S_PENDING; 2968 if (ahci_poll(ccb, 1000, ahci_quick_timeout) != ATA_S_COMPLETE) { 2969 err_slot = -1; 2970 ahci_unload_prdt(ccb); 2971 goto err; 2972 } 2973 ahci_unload_prdt(ccb); 2974 2975 /* 2976 * Success, extract failed register set and tags from the scratch 2977 * space. 2978 */ 2979 log = (struct ata_log_page_10h *)ap->ap_err_scratch; 2980 if (log->err_regs.type & ATA_LOG_10H_TYPE_NOTQUEUED) { 2981 /* Not queued bit was set - wasn't an NCQ error? */ 2982 kprintf("%s: read NCQ error page, but not an NCQ error?\n", 2983 PORTNAME(ap)); 2984 err_slot = -1; 2985 } else { 2986 /* Copy back the log record as a D2H register FIS. */ 2987 err_slot = log->err_regs.type & ATA_LOG_10H_TYPE_TAG_MASK; 2988 2989 ccb = &ap->ap_ccbs[err_slot]; 2990 if (ccb->ccb_xa.state == ATA_S_ONCHIP) { 2991 kprintf("%s: read NCQ error page slot=%d\n", 2992 ATANAME(ap, ccb->ccb_xa.at), 2993 err_slot); 2994 memcpy(&ccb->ccb_xa.rfis, &log->err_regs, 2995 sizeof(struct ata_fis_d2h)); 2996 ccb->ccb_xa.rfis.type = ATA_FIS_TYPE_D2H; 2997 ccb->ccb_xa.rfis.flags = 0; 2998 } else { 2999 kprintf("%s: read NCQ error page slot=%d, " 3000 "slot does not match any cmds\n", 3001 ATANAME(ccb->ccb_port, ccb->ccb_xa.at), 3002 err_slot); 3003 err_slot = -1; 3004 } 3005 } 3006 err: 3007 ahci_put_err_ccb(ccb); 3008 kprintf("%s: DONE log page target %d err_slot=%d\n", 3009 PORTNAME(ap), target, err_slot); 3010 return (err_slot); 3011 } 3012 3013 /* 3014 * Allocate memory for various structures DMAd by hardware. The maximum 3015 * number of segments for these tags is 1 so the DMA memory will have a 3016 * single physical base address. 3017 */ 3018 struct ahci_dmamem * 3019 ahci_dmamem_alloc(struct ahci_softc *sc, bus_dma_tag_t tag) 3020 { 3021 struct ahci_dmamem *adm; 3022 int error; 3023 3024 adm = kmalloc(sizeof(*adm), M_DEVBUF, M_INTWAIT | M_ZERO); 3025 3026 error = bus_dmamem_alloc(tag, (void **)&adm->adm_kva, 3027 BUS_DMA_ZERO, &adm->adm_map); 3028 if (error == 0) { 3029 adm->adm_tag = tag; 3030 error = bus_dmamap_load(tag, adm->adm_map, 3031 adm->adm_kva, 3032 bus_dma_tag_getmaxsize(tag), 3033 ahci_dmamem_saveseg, &adm->adm_busaddr, 3034 0); 3035 } 3036 if (error) { 3037 if (adm->adm_map) { 3038 bus_dmamap_destroy(tag, adm->adm_map); 3039 adm->adm_map = NULL; 3040 adm->adm_tag = NULL; 3041 adm->adm_kva = NULL; 3042 } 3043 kfree(adm, M_DEVBUF); 3044 adm = NULL; 3045 } 3046 return (adm); 3047 } 3048 3049 static 3050 void 3051 ahci_dmamem_saveseg(void *info, bus_dma_segment_t *segs, int nsegs, int error) 3052 { 3053 KKASSERT(error == 0); 3054 KKASSERT(nsegs == 1); 3055 *(bus_addr_t *)info = segs->ds_addr; 3056 } 3057 3058 3059 void 3060 ahci_dmamem_free(struct ahci_softc *sc, struct ahci_dmamem *adm) 3061 { 3062 if (adm->adm_map) { 3063 bus_dmamap_unload(adm->adm_tag, adm->adm_map); 3064 bus_dmamap_destroy(adm->adm_tag, adm->adm_map); 3065 adm->adm_map = NULL; 3066 adm->adm_tag = NULL; 3067 adm->adm_kva = NULL; 3068 } 3069 kfree(adm, M_DEVBUF); 3070 } 3071 3072 u_int32_t 3073 ahci_read(struct ahci_softc *sc, bus_size_t r) 3074 { 3075 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 3076 BUS_SPACE_BARRIER_READ); 3077 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, r)); 3078 } 3079 3080 void 3081 ahci_write(struct ahci_softc *sc, bus_size_t r, u_int32_t v) 3082 { 3083 bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v); 3084 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 3085 BUS_SPACE_BARRIER_WRITE); 3086 } 3087 3088 u_int32_t 3089 ahci_pread(struct ahci_port *ap, bus_size_t r) 3090 { 3091 bus_space_barrier(ap->ap_sc->sc_iot, ap->ap_ioh, r, 4, 3092 BUS_SPACE_BARRIER_READ); 3093 return (bus_space_read_4(ap->ap_sc->sc_iot, ap->ap_ioh, r)); 3094 } 3095 3096 void 3097 ahci_pwrite(struct ahci_port *ap, bus_size_t r, u_int32_t v) 3098 { 3099 bus_space_write_4(ap->ap_sc->sc_iot, ap->ap_ioh, r, v); 3100 bus_space_barrier(ap->ap_sc->sc_iot, ap->ap_ioh, r, 4, 3101 BUS_SPACE_BARRIER_WRITE); 3102 } 3103 3104 /* 3105 * Wait up to (timeout) milliseconds for the masked port register to 3106 * match the target. 3107 * 3108 * Timeout is in milliseconds. 3109 */ 3110 int 3111 ahci_pwait_eq(struct ahci_port *ap, int timeout, 3112 bus_size_t r, u_int32_t mask, u_int32_t target) 3113 { 3114 int t; 3115 3116 /* 3117 * Loop hard up to 100uS 3118 */ 3119 for (t = 0; t < 100; ++t) { 3120 if ((ahci_pread(ap, r) & mask) == target) 3121 return (0); 3122 ahci_os_hardsleep(1); /* us */ 3123 } 3124 3125 do { 3126 timeout -= ahci_os_softsleep(); 3127 if ((ahci_pread(ap, r) & mask) == target) 3128 return (0); 3129 } while (timeout > 0); 3130 return (1); 3131 } 3132 3133 int 3134 ahci_wait_ne(struct ahci_softc *sc, bus_size_t r, u_int32_t mask, 3135 u_int32_t target) 3136 { 3137 int t; 3138 3139 /* 3140 * Loop hard up to 100uS 3141 */ 3142 for (t = 0; t < 100; ++t) { 3143 if ((ahci_read(sc, r) & mask) != target) 3144 return (0); 3145 ahci_os_hardsleep(1); /* us */ 3146 } 3147 3148 /* 3149 * And one millisecond the slow way 3150 */ 3151 t = 1000; 3152 do { 3153 t -= ahci_os_softsleep(); 3154 if ((ahci_read(sc, r) & mask) != target) 3155 return (0); 3156 } while (t > 0); 3157 3158 return (1); 3159 } 3160 3161 3162 /* 3163 * Acquire an ata transfer. 3164 * 3165 * Pass a NULL at for direct-attached transfers, and a non-NULL at for 3166 * targets that go through the port multiplier. 3167 */ 3168 struct ata_xfer * 3169 ahci_ata_get_xfer(struct ahci_port *ap, struct ata_port *at) 3170 { 3171 struct ahci_ccb *ccb; 3172 3173 ccb = ahci_get_ccb(ap); 3174 if (ccb == NULL) { 3175 DPRINTF(AHCI_D_XFER, "%s: ahci_ata_get_xfer: NULL ccb\n", 3176 PORTNAME(ap)); 3177 return (NULL); 3178 } 3179 3180 DPRINTF(AHCI_D_XFER, "%s: ahci_ata_get_xfer got slot %d\n", 3181 PORTNAME(ap), ccb->ccb_slot); 3182 3183 bzero(ccb->ccb_xa.fis, sizeof(*ccb->ccb_xa.fis)); 3184 ccb->ccb_xa.at = at; 3185 ccb->ccb_xa.fis->type = ATA_FIS_TYPE_H2D; 3186 3187 return (&ccb->ccb_xa); 3188 } 3189 3190 void 3191 ahci_ata_put_xfer(struct ata_xfer *xa) 3192 { 3193 struct ahci_ccb *ccb = (struct ahci_ccb *)xa; 3194 3195 DPRINTF(AHCI_D_XFER, "ahci_ata_put_xfer slot %d\n", ccb->ccb_slot); 3196 3197 ahci_put_ccb(ccb); 3198 } 3199 3200 int 3201 ahci_ata_cmd(struct ata_xfer *xa) 3202 { 3203 struct ahci_ccb *ccb = (struct ahci_ccb *)xa; 3204 struct ahci_cmd_hdr *cmd_slot; 3205 3206 KKASSERT(xa->state == ATA_S_SETUP); 3207 3208 if (ccb->ccb_port->ap_state == AP_S_FATAL_ERROR) 3209 goto failcmd; 3210 ccb->ccb_done = ahci_ata_cmd_done; 3211 3212 cmd_slot = ccb->ccb_cmd_hdr; 3213 cmd_slot->flags = htole16(5); /* FIS length (in DWORDs) */ 3214 if (ccb->ccb_xa.at) { 3215 cmd_slot->flags |= htole16(ccb->ccb_xa.at->at_target << 3216 AHCI_CMD_LIST_FLAG_PMP_SHIFT); 3217 } 3218 3219 if (xa->flags & ATA_F_WRITE) 3220 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_W); 3221 3222 if (xa->flags & ATA_F_PACKET) 3223 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_A); 3224 3225 if (ahci_load_prdt(ccb) != 0) 3226 goto failcmd; 3227 3228 xa->state = ATA_S_PENDING; 3229 3230 if (xa->flags & ATA_F_POLL) 3231 return (ahci_poll(ccb, xa->timeout, ahci_ata_cmd_timeout)); 3232 3233 crit_enter(); 3234 KKASSERT((xa->flags & ATA_F_TIMEOUT_EXPIRED) == 0); 3235 xa->flags |= ATA_F_TIMEOUT_DESIRED; 3236 ahci_start(ccb); 3237 crit_exit(); 3238 return (xa->state); 3239 3240 failcmd: 3241 crit_enter(); 3242 xa->state = ATA_S_ERROR; 3243 xa->complete(xa); 3244 crit_exit(); 3245 return (ATA_S_ERROR); 3246 } 3247 3248 void 3249 ahci_ata_cmd_done(struct ahci_ccb *ccb) 3250 { 3251 struct ata_xfer *xa = &ccb->ccb_xa; 3252 3253 /* 3254 * NOTE: callout does not lock port and may race us modifying 3255 * the flags, so make sure its stopped. 3256 */ 3257 if (xa->flags & ATA_F_TIMEOUT_RUNNING) { 3258 callout_stop(&ccb->ccb_timeout); 3259 xa->flags &= ~ATA_F_TIMEOUT_RUNNING; 3260 } 3261 xa->flags &= ~(ATA_F_TIMEOUT_DESIRED | ATA_F_TIMEOUT_EXPIRED); 3262 3263 KKASSERT(xa->state != ATA_S_ONCHIP); 3264 ahci_unload_prdt(ccb); 3265 3266 if (xa->state != ATA_S_TIMEOUT) 3267 xa->complete(xa); 3268 } 3269 3270 /* 3271 * Timeout from callout, MPSAFE - nothing can mess with the CCB's flags 3272 * while the callout is runing. 3273 * 3274 * We can't safely get the port lock here or delay, we could block 3275 * the callout thread. 3276 */ 3277 static void 3278 ahci_ata_cmd_timeout_unserialized(void *arg) 3279 { 3280 struct ahci_ccb *ccb = arg; 3281 struct ahci_port *ap = ccb->ccb_port; 3282 3283 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_RUNNING; 3284 ccb->ccb_xa.flags |= ATA_F_TIMEOUT_EXPIRED; 3285 ahci_os_signal_port_thread(ap, AP_SIGF_TIMEOUT); 3286 } 3287 3288 /* 3289 * Timeout code, typically called when the port command processor is running. 3290 * 3291 * We have to be very very careful here. We cannot stop the port unless 3292 * CR is already clear or the only active commands remaining are timed-out 3293 * ones. Otherwise stopping the port will race the command processor and 3294 * we can lose events. While we can theoretically just restart everything 3295 * that could result in a double-issue which will not work for ATAPI commands. 3296 */ 3297 void 3298 ahci_ata_cmd_timeout(struct ahci_ccb *ccb) 3299 { 3300 struct ata_xfer *xa = &ccb->ccb_xa; 3301 struct ahci_port *ap = ccb->ccb_port; 3302 struct ata_port *at; 3303 int ci_saved; 3304 int slot; 3305 3306 at = ccb->ccb_xa.at; 3307 3308 kprintf("%s: CMD TIMEOUT state=%d slot=%d\n" 3309 "\tcmd-reg 0x%b\n" 3310 "\tsactive=%08x active=%08x expired=%08x\n" 3311 "\t sact=%08x ci=%08x\n" 3312 "\t STS=%b\n", 3313 ATANAME(ap, at), 3314 ccb->ccb_xa.state, ccb->ccb_slot, 3315 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD, 3316 ap->ap_sactive, ap->ap_active, ap->ap_expired, 3317 ahci_pread(ap, AHCI_PREG_SACT), 3318 ahci_pread(ap, AHCI_PREG_CI), 3319 ahci_pread(ap, AHCI_PREG_TFD), AHCI_PFMT_TFD_STS 3320 ); 3321 3322 3323 /* 3324 * NOTE: Timeout will not be running if the command was polled. 3325 * If we got here at least one of these flags should be set. 3326 */ 3327 KKASSERT(xa->flags & (ATA_F_POLL | ATA_F_TIMEOUT_DESIRED | 3328 ATA_F_TIMEOUT_RUNNING)); 3329 xa->flags &= ~(ATA_F_TIMEOUT_RUNNING | ATA_F_TIMEOUT_EXPIRED); 3330 3331 if (ccb->ccb_xa.state == ATA_S_PENDING) { 3332 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry); 3333 ccb->ccb_xa.state = ATA_S_TIMEOUT; 3334 ccb->ccb_done(ccb); 3335 xa->complete(xa); 3336 ahci_issue_pending_commands(ap, NULL); 3337 return; 3338 } 3339 if (ccb->ccb_xa.state != ATA_S_ONCHIP) { 3340 kprintf("%s: Unexpected state during timeout: %d\n", 3341 ATANAME(ap, at), ccb->ccb_xa.state); 3342 return; 3343 } 3344 3345 /* 3346 * Ok, we can only get this command off the chip if CR is inactive 3347 * or if the only commands running on the chip are all expired. 3348 * Otherwise we have to wait until the port is in a safe state. 3349 * 3350 * Do not set state here, it will cause polls to return when the 3351 * ccb is not yet off the chip. 3352 */ 3353 ap->ap_expired |= 1 << ccb->ccb_slot; 3354 3355 if ((ahci_pread(ap, AHCI_PREG_CMD) & AHCI_PREG_CMD_CR) && 3356 (ap->ap_active | ap->ap_sactive) != ap->ap_expired) { 3357 /* 3358 * If using FBSS or NCQ we can't safely stop the port 3359 * right now. 3360 */ 3361 kprintf("%s: Deferred timeout until its safe, slot %d\n", 3362 ATANAME(ap, at), ccb->ccb_slot); 3363 return; 3364 } 3365 3366 /* 3367 * We can safely stop the port and process all expired ccb's, 3368 * which will include our current ccb. 3369 */ 3370 ci_saved = (ap->ap_sactive) ? ahci_pread(ap, AHCI_PREG_SACT) : 3371 ahci_pread(ap, AHCI_PREG_CI); 3372 ahci_port_stop(ap, 0); 3373 3374 while (ap->ap_expired) { 3375 slot = ffs(ap->ap_expired) - 1; 3376 ap->ap_expired &= ~(1 << slot); 3377 ci_saved &= ~(1 << slot); 3378 ccb = &ap->ap_ccbs[slot]; 3379 ccb->ccb_xa.state = ATA_S_TIMEOUT; 3380 if (ccb->ccb_xa.flags & ATA_F_NCQ) { 3381 KKASSERT(ap->ap_sactive & (1 << slot)); 3382 ap->ap_sactive &= ~(1 << slot); 3383 } else { 3384 KKASSERT(ap->ap_active & (1 << slot)); 3385 ap->ap_active &= ~(1 << slot); 3386 --ap->ap_active_cnt; 3387 } 3388 ccb->ccb_done(ccb); 3389 ccb->ccb_xa.complete(&ccb->ccb_xa); 3390 } 3391 /* ccb invalid now */ 3392 3393 /* 3394 * We can safely CLO the port to clear any BSY/DRQ, a case which 3395 * can occur with port multipliers. This will unbrick the port 3396 * and allow commands to other targets behind the PM continue. 3397 * (FBSS). 3398 * 3399 * Finally, once the port has been restarted we can issue any 3400 * previously saved pending commands, and run the port interrupt 3401 * code to handle any completions which may have occured when 3402 * we saved CI. 3403 */ 3404 if (ahci_pread(ap, AHCI_PREG_TFD) & 3405 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 3406 kprintf("%s: Warning, issuing CLO after timeout\n", 3407 ATANAME(ap, at)); 3408 ahci_port_clo(ap); 3409 } 3410 ahci_port_start(ap); 3411 ahci_issue_saved_commands(ap, ci_saved & ~ap->ap_expired); 3412 ahci_issue_pending_commands(ap, NULL); 3413 ahci_port_intr(ap, 0); 3414 } 3415 3416 /* 3417 * Issue a previously saved set of commands 3418 */ 3419 void 3420 ahci_issue_saved_commands(struct ahci_port *ap, u_int32_t ci_saved) 3421 { 3422 if (ci_saved) { 3423 KKASSERT(!((ap->ap_active & ci_saved) && 3424 (ap->ap_sactive & ci_saved))); 3425 KKASSERT((ci_saved & ap->ap_expired) == 0); 3426 if (ap->ap_sactive & ci_saved) 3427 ahci_pwrite(ap, AHCI_PREG_SACT, ci_saved); 3428 ahci_pwrite(ap, AHCI_PREG_CI, ci_saved); 3429 } 3430 } 3431 3432 /* 3433 * Used by the softreset, pmprobe, and read_ncq_error only, in very 3434 * specialized, controlled circumstances. 3435 * 3436 * Only one command may be pending. 3437 */ 3438 void 3439 ahci_quick_timeout(struct ahci_ccb *ccb) 3440 { 3441 struct ahci_port *ap = ccb->ccb_port; 3442 3443 switch (ccb->ccb_xa.state) { 3444 case ATA_S_PENDING: 3445 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry); 3446 ccb->ccb_xa.state = ATA_S_TIMEOUT; 3447 break; 3448 case ATA_S_ONCHIP: 3449 KKASSERT(ap->ap_active == (1 << ccb->ccb_slot) && 3450 ap->ap_sactive == 0); 3451 ahci_port_stop(ap, 0); 3452 ahci_port_start(ap); 3453 3454 ccb->ccb_xa.state = ATA_S_TIMEOUT; 3455 ap->ap_active &= ~(1 << ccb->ccb_slot); 3456 KKASSERT(ap->ap_active_cnt > 0); 3457 --ap->ap_active_cnt; 3458 break; 3459 default: 3460 panic("%s: ahci_quick_timeout: ccb in bad state %d", 3461 ATANAME(ap, ccb->ccb_xa.at), ccb->ccb_xa.state); 3462 } 3463 } 3464 3465 static void 3466 ahci_dummy_done(struct ata_xfer *xa) 3467 { 3468 } 3469 3470 static void 3471 ahci_empty_done(struct ahci_ccb *ccb) 3472 { 3473 } 3474 3475 int 3476 ahci_set_feature(struct ahci_port *ap, struct ata_port *atx, int feature, int enable) 3477 { 3478 struct ata_port *at; 3479 struct ata_xfer *xa; 3480 int error; 3481 3482 at = atx ? atx : ap->ap_ata[0]; 3483 3484 xa = ahci_ata_get_xfer(ap, atx); 3485 3486 xa->fis->type = ATA_FIS_TYPE_H2D; 3487 xa->fis->flags = ATA_H2D_FLAGS_CMD | at->at_target; 3488 xa->fis->command = ATA_C_SET_FEATURES; 3489 xa->fis->features = enable ? ATA_C_SATA_FEATURE_ENA : 3490 ATA_C_SATA_FEATURE_DIS; 3491 xa->fis->sector_count = feature; 3492 xa->fis->control = ATA_FIS_CONTROL_4BIT; 3493 3494 xa->complete = ahci_dummy_done; 3495 xa->datalen = 0; 3496 xa->flags = ATA_F_POLL; 3497 xa->timeout = 1000; 3498 3499 if (ahci_ata_cmd(xa) == ATA_S_COMPLETE) 3500 error = 0; 3501 else 3502 error = EIO; 3503 ahci_ata_put_xfer(xa); 3504 return(error); 3505 } 3506