1 /* 2 * (MPSAFE) 3 * 4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * 19 * Copyright (c) 2009 The DragonFly Project. All rights reserved. 20 * 21 * This code is derived from software contributed to The DragonFly Project 22 * by Matthew Dillon <dillon@backplane.com> 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in 32 * the documentation and/or other materials provided with the 33 * distribution. 34 * 3. Neither the name of The DragonFly Project nor the names of its 35 * contributors may be used to endorse or promote products derived 36 * from this software without specific, prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 41 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 42 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 43 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 48 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 49 * SUCH DAMAGE. 50 * 51 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $ 52 */ 53 54 #include "ahci.h" 55 56 void ahci_port_interrupt_enable(struct ahci_port *ap); 57 58 int ahci_load_prdt(struct ahci_ccb *); 59 void ahci_unload_prdt(struct ahci_ccb *); 60 static void ahci_load_prdt_callback(void *info, bus_dma_segment_t *segs, 61 int nsegs, int error); 62 void ahci_start(struct ahci_ccb *); 63 int ahci_port_softreset(struct ahci_port *ap); 64 int ahci_port_hardreset(struct ahci_port *ap, int hard); 65 void ahci_port_hardstop(struct ahci_port *ap); 66 67 static void ahci_ata_cmd_timeout_unserialized(void *); 68 void ahci_check_active_timeouts(struct ahci_port *ap); 69 70 void ahci_beg_exclusive_access(struct ahci_port *ap, struct ata_port *at); 71 void ahci_end_exclusive_access(struct ahci_port *ap, struct ata_port *at); 72 void ahci_issue_pending_commands(struct ahci_port *ap, struct ahci_ccb *ccb); 73 void ahci_issue_saved_commands(struct ahci_port *ap, u_int32_t mask); 74 75 int ahci_port_read_ncq_error(struct ahci_port *, int); 76 77 struct ahci_dmamem *ahci_dmamem_alloc(struct ahci_softc *, bus_dma_tag_t tag); 78 void ahci_dmamem_free(struct ahci_softc *, struct ahci_dmamem *); 79 static void ahci_dmamem_saveseg(void *info, bus_dma_segment_t *segs, int nsegs, int error); 80 81 static void ahci_dummy_done(struct ata_xfer *xa); 82 static void ahci_empty_done(struct ahci_ccb *ccb); 83 static void ahci_ata_cmd_done(struct ahci_ccb *ccb); 84 static u_int32_t ahci_pactive(struct ahci_port *ap); 85 86 /* 87 * Initialize the global AHCI hardware. This code does not set up any of 88 * its ports. 89 */ 90 int 91 ahci_init(struct ahci_softc *sc) 92 { 93 u_int32_t cap, pi, pleft; 94 int i; 95 struct ahci_port *ap; 96 97 DPRINTF(AHCI_D_VERBOSE, " GHC 0x%b", 98 ahci_read(sc, AHCI_REG_GHC), AHCI_FMT_GHC); 99 100 /* 101 * save BIOS initialised parameters, enable staggered spin up 102 */ 103 cap = ahci_read(sc, AHCI_REG_CAP); 104 cap &= AHCI_REG_CAP_SMPS; 105 cap |= AHCI_REG_CAP_SSS; 106 pi = ahci_read(sc, AHCI_REG_PI); 107 108 /* 109 * Unconditionally reset the controller, do not conditionalize on 110 * trying to figure it if it was previously active or not. 111 * 112 * NOTE: On AE before HR. The AHCI-1.1 spec has a note in section 113 * 5.2.2.1 regarding this. HR should be set to 1 only after 114 * AE is set to 1. The reset sequence will clear HR when 115 * it completes, and will also clear AE if SAM is 0. AE must 116 * then be set again. When SAM is 1 the AE bit typically reads 117 * as 1 (and is read-only). 118 * 119 * NOTE: Avoid PCI[e] transaction burst by issuing dummy reads, 120 * otherwise the writes will only be separated by a few 121 * nanoseconds. 122 * 123 * NOTE BRICKS (1) 124 * 125 * If you have a port multiplier and it does not have a device 126 * in target 0, and it probes normally, but a later operation 127 * mis-probes a target behind that PM, it is possible for the 128 * port to brick such that only (a) a power cycle of the host 129 * or (b) placing a device in target 0 will fix the problem. 130 * Power cycling the PM has no effect (it works fine on another 131 * host port). This issue is unrelated to CLO. 132 */ 133 /* 134 * Wait for any prior reset sequence to complete 135 */ 136 if (ahci_wait_ne(sc, AHCI_REG_GHC, 137 AHCI_REG_GHC_HR, AHCI_REG_GHC_HR) != 0) { 138 device_printf(sc->sc_dev, "Controller is stuck in reset\n"); 139 return (1); 140 } 141 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE); 142 ahci_os_sleep(500); 143 ahci_read(sc, AHCI_REG_GHC); /* flush */ 144 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_HR); 145 ahci_os_sleep(500); 146 ahci_read(sc, AHCI_REG_GHC); /* flush */ 147 if (ahci_wait_ne(sc, AHCI_REG_GHC, 148 AHCI_REG_GHC_HR, AHCI_REG_GHC_HR) != 0) { 149 device_printf(sc->sc_dev, "unable to reset controller\n"); 150 return (1); 151 } 152 if (ahci_read(sc, AHCI_REG_GHC) & AHCI_REG_GHC_AE) { 153 device_printf(sc->sc_dev, "AE did not auto-clear!\n"); 154 ahci_write(sc, AHCI_REG_GHC, 0); 155 ahci_os_sleep(500); 156 } 157 158 /* 159 * Enable ahci (global interrupts disabled) 160 * 161 * Restore saved parameters. Avoid pci transaction burst write 162 * by issuing dummy reads. 163 */ 164 ahci_os_sleep(500); 165 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE); 166 ahci_os_sleep(500); 167 168 ahci_read(sc, AHCI_REG_GHC); /* flush */ 169 ahci_write(sc, AHCI_REG_CAP, cap); 170 ahci_write(sc, AHCI_REG_PI, pi); 171 ahci_read(sc, AHCI_REG_GHC); /* flush */ 172 173 /* 174 * Intel hocus pocus in case the BIOS has not set the chip up 175 * properly for AHCI operation. 176 */ 177 if (pci_get_vendor(sc->sc_dev) == PCI_VENDOR_INTEL) { 178 if ((pci_read_config(sc->sc_dev, 0x92, 2) & 0x0F) != 0x0F) 179 device_printf(sc->sc_dev, "Intel hocus pocus\n"); 180 pci_write_config(sc->sc_dev, 0x92, 181 pci_read_config(sc->sc_dev, 0x92, 2) | 0x0F, 2); 182 } 183 184 /* 185 * This is a hack that currently does not appear to have 186 * a significant effect, but I noticed the port registers 187 * do not appear to be completely cleared after the host 188 * controller is reset. 189 * 190 * Use a temporary ap structure so we can call ahci_pwrite(). 191 * 192 * We must be sure to stop the port 193 */ 194 ap = kmalloc(sizeof(*ap), M_DEVBUF, M_WAITOK | M_ZERO); 195 ap->ap_sc = sc; 196 pleft = pi; 197 for (i = 0; i < AHCI_MAX_PORTS; ++i) { 198 if (pleft == 0) 199 break; 200 if ((pi & (1 << i)) == 0) 201 continue; 202 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 203 AHCI_PORT_REGION(i), AHCI_PORT_SIZE, &ap->ap_ioh) != 0) { 204 device_printf(sc->sc_dev, "can't map port\n"); 205 return (1); 206 } 207 /* 208 * NOTE! Setting AHCI_PREG_SCTL_DET_DISABLE on AHCI1.0 or 209 * AHCI1.1 can brick the chipset. Not only brick it, 210 * but also crash the PC. The bit seems unreliable 211 * on AHCI1.2 as well. 212 */ 213 ahci_port_stop(ap, 1); 214 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED); 215 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 216 ahci_pwrite(ap, AHCI_PREG_IE, 0); 217 ahci_write(ap->ap_sc, AHCI_REG_IS, 1 << i); 218 ahci_pwrite(ap, AHCI_PREG_CMD, 0); 219 ahci_pwrite(ap, AHCI_PREG_IS, -1); 220 sc->sc_portmask |= (1 << i); 221 pleft &= ~(1 << i); 222 } 223 sc->sc_numports = i; 224 kfree(ap, M_DEVBUF); 225 226 return (0); 227 } 228 229 /* 230 * Allocate and initialize an AHCI port. 231 */ 232 int 233 ahci_port_alloc(struct ahci_softc *sc, u_int port) 234 { 235 struct ahci_port *ap; 236 struct ata_port *at; 237 struct ahci_ccb *ccb; 238 u_int64_t dva; 239 u_int32_t cmd; 240 u_int32_t data; 241 struct ahci_cmd_hdr *hdr; 242 struct ahci_cmd_table *table; 243 int rc = ENOMEM; 244 int error; 245 int i; 246 247 ap = kmalloc(sizeof(*ap), M_DEVBUF, M_WAITOK | M_ZERO); 248 ap->ap_err_scratch = kmalloc(512, M_DEVBUF, M_WAITOK | M_ZERO); 249 250 ksnprintf(ap->ap_name, sizeof(ap->ap_name), "%s%d.%d", 251 device_get_name(sc->sc_dev), 252 device_get_unit(sc->sc_dev), 253 port); 254 sc->sc_ports[port] = ap; 255 256 /* 257 * Allocate enough so we never have to reallocate, it makes 258 * it easier. 259 * 260 * ap_pmcount will be reduced by the scan if we encounter the 261 * port multiplier port prior to target 15. 262 * 263 * kmalloc power-of-2 allocations are guaranteed not to cross 264 * a page boundary. Make sure the identify sub-structure in the 265 * at structure does not cross a page boundary, just in case the 266 * part is AHCI-1.1 and can't handle multiple DRQ blocks. 267 */ 268 if (ap->ap_ata[0] == NULL) { 269 int pw2; 270 271 for (pw2 = 1; pw2 < sizeof(*at); pw2 <<= 1) 272 ; 273 for (i = 0; i < AHCI_MAX_PMPORTS; ++i) { 274 at = kmalloc(pw2, M_DEVBUF, M_INTWAIT | M_ZERO); 275 ap->ap_ata[i] = at; 276 at->at_ahci_port = ap; 277 at->at_target = i; 278 at->at_probe = ATA_PROBE_NEED_INIT; 279 at->at_features |= ATA_PORT_F_RESCAN; 280 ksnprintf(at->at_name, sizeof(at->at_name), 281 "%s.%d", ap->ap_name, i); 282 } 283 } 284 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 285 AHCI_PORT_REGION(port), AHCI_PORT_SIZE, &ap->ap_ioh) != 0) { 286 device_printf(sc->sc_dev, 287 "unable to create register window for port %d\n", 288 port); 289 goto freeport; 290 } 291 292 ap->ap_sc = sc; 293 ap->ap_num = port; 294 ap->ap_probe = ATA_PROBE_NEED_INIT; 295 ap->link_pwr_mgmt = AHCI_LINK_PWR_MGMT_NONE; 296 ap->sysctl_tree = NULL; 297 TAILQ_INIT(&ap->ap_ccb_free); 298 TAILQ_INIT(&ap->ap_ccb_pending); 299 lockinit(&ap->ap_ccb_lock, "ahcipo", 0, 0); 300 301 /* Disable port interrupts */ 302 ahci_pwrite(ap, AHCI_PREG_IE, 0); 303 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 304 305 /* 306 * Sec 10.1.2 - deinitialise port if it is already running 307 */ 308 cmd = ahci_pread(ap, AHCI_PREG_CMD); 309 kprintf("%s: Caps %b\n", PORTNAME(ap), cmd, AHCI_PFMT_CMD); 310 311 if ((cmd & (AHCI_PREG_CMD_ST | AHCI_PREG_CMD_CR | 312 AHCI_PREG_CMD_FRE | AHCI_PREG_CMD_FR)) || 313 (ahci_pread(ap, AHCI_PREG_SCTL) & AHCI_PREG_SCTL_DET)) { 314 int r; 315 316 r = ahci_port_stop(ap, 1); 317 if (r) { 318 device_printf(sc->sc_dev, 319 "unable to disable %s, ignoring port %d\n", 320 ((r == 2) ? "CR" : "FR"), port); 321 rc = ENXIO; 322 goto freeport; 323 } 324 325 /* Write DET to zero */ 326 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED); 327 } 328 329 /* Allocate RFIS */ 330 ap->ap_dmamem_rfis = ahci_dmamem_alloc(sc, sc->sc_tag_rfis); 331 if (ap->ap_dmamem_rfis == NULL) { 332 kprintf("%s: NORFIS\n", PORTNAME(ap)); 333 goto nomem; 334 } 335 336 /* Setup RFIS base address */ 337 ap->ap_rfis = (struct ahci_rfis *) AHCI_DMA_KVA(ap->ap_dmamem_rfis); 338 dva = AHCI_DMA_DVA(ap->ap_dmamem_rfis); 339 ahci_pwrite(ap, AHCI_PREG_FBU, (u_int32_t)(dva >> 32)); 340 ahci_pwrite(ap, AHCI_PREG_FB, (u_int32_t)dva); 341 342 /* Clear SERR before starting FIS reception or ST or anything */ 343 ahci_flush_tfd(ap); 344 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 345 346 /* Enable FIS reception and activate port. */ 347 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC; 348 cmd &= ~(AHCI_PREG_CMD_CLO | AHCI_PREG_CMD_PMA); 349 cmd |= AHCI_PREG_CMD_FRE | AHCI_PREG_CMD_POD | AHCI_PREG_CMD_SUD; 350 ahci_pwrite(ap, AHCI_PREG_CMD, cmd | AHCI_PREG_CMD_ICC_ACTIVE); 351 352 /* Check whether port activated. Skip it if not. */ 353 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC; 354 if ((cmd & AHCI_PREG_CMD_FRE) == 0) { 355 kprintf("%s: NOT-ACTIVATED\n", PORTNAME(ap)); 356 rc = ENXIO; 357 goto freeport; 358 } 359 360 /* Allocate a CCB for each command slot */ 361 ap->ap_ccbs = kmalloc(sizeof(struct ahci_ccb) * sc->sc_ncmds, M_DEVBUF, 362 M_WAITOK | M_ZERO); 363 if (ap->ap_ccbs == NULL) { 364 device_printf(sc->sc_dev, 365 "unable to allocate command list for port %d\n", 366 port); 367 goto freeport; 368 } 369 370 /* Command List Structures and Command Tables */ 371 ap->ap_dmamem_cmd_list = ahci_dmamem_alloc(sc, sc->sc_tag_cmdh); 372 ap->ap_dmamem_cmd_table = ahci_dmamem_alloc(sc, sc->sc_tag_cmdt); 373 if (ap->ap_dmamem_cmd_table == NULL || 374 ap->ap_dmamem_cmd_list == NULL) { 375 nomem: 376 device_printf(sc->sc_dev, 377 "unable to allocate DMA memory for port %d\n", 378 port); 379 goto freeport; 380 } 381 382 /* Setup command list base address */ 383 dva = AHCI_DMA_DVA(ap->ap_dmamem_cmd_list); 384 ahci_pwrite(ap, AHCI_PREG_CLBU, (u_int32_t)(dva >> 32)); 385 ahci_pwrite(ap, AHCI_PREG_CLB, (u_int32_t)dva); 386 387 /* Split CCB allocation into CCBs and assign to command header/table */ 388 hdr = AHCI_DMA_KVA(ap->ap_dmamem_cmd_list); 389 table = AHCI_DMA_KVA(ap->ap_dmamem_cmd_table); 390 for (i = 0; i < sc->sc_ncmds; i++) { 391 ccb = &ap->ap_ccbs[i]; 392 393 error = bus_dmamap_create(sc->sc_tag_data, BUS_DMA_ALLOCNOW, 394 &ccb->ccb_dmamap); 395 if (error) { 396 device_printf(sc->sc_dev, 397 "unable to create dmamap for port %d " 398 "ccb %d\n", port, i); 399 goto freeport; 400 } 401 402 callout_init(&ccb->ccb_timeout); 403 ccb->ccb_slot = i; 404 ccb->ccb_port = ap; 405 ccb->ccb_cmd_hdr = &hdr[i]; 406 ccb->ccb_cmd_table = &table[i]; 407 dva = AHCI_DMA_DVA(ap->ap_dmamem_cmd_table) + 408 ccb->ccb_slot * sizeof(struct ahci_cmd_table); 409 ccb->ccb_cmd_hdr->ctba_hi = htole32((u_int32_t)(dva >> 32)); 410 ccb->ccb_cmd_hdr->ctba_lo = htole32((u_int32_t)dva); 411 412 ccb->ccb_xa.fis = 413 (struct ata_fis_h2d *)ccb->ccb_cmd_table->cfis; 414 ccb->ccb_xa.packetcmd = ccb->ccb_cmd_table->acmd; 415 ccb->ccb_xa.tag = i; 416 417 ccb->ccb_xa.state = ATA_S_COMPLETE; 418 419 /* 420 * CCB[1] is the error CCB and is not get or put. It is 421 * also used for probing. Numerous HBAs only load the 422 * signature from CCB[1] so it MUST be used for the second 423 * FIS. 424 */ 425 if (i == 1) 426 ap->ap_err_ccb = ccb; 427 else 428 ahci_put_ccb(ccb); 429 } 430 431 /* 432 * Wait for ICC change to complete 433 */ 434 ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_ICC); 435 436 /* 437 * Calculate the interrupt mask 438 */ 439 data = AHCI_PREG_IE_TFEE | AHCI_PREG_IE_HBFE | 440 AHCI_PREG_IE_IFE | AHCI_PREG_IE_OFE | 441 AHCI_PREG_IE_DPE | AHCI_PREG_IE_UFE | 442 AHCI_PREG_IE_PCE | AHCI_PREG_IE_PRCE | 443 AHCI_PREG_IE_DHRE | AHCI_PREG_IE_SDBE; 444 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSNTF) 445 data |= AHCI_PREG_IE_IPME; 446 #ifdef AHCI_COALESCE 447 if (sc->sc_ccc_ports & (1 << port) 448 data &= ~(AHCI_PREG_IE_SDBE | AHCI_PREG_IE_DHRE); 449 #endif 450 ap->ap_intmask = data; 451 452 /* 453 * Start the port helper thread. The helper thread will call 454 * ahci_port_init() so the ports can all be started in parallel. 455 * A failure by ahci_port_init() does not deallocate the port 456 * since we still want hot-plug events. 457 */ 458 ahci_os_start_port(ap); 459 return(0); 460 freeport: 461 ahci_port_free(sc, port); 462 return (rc); 463 } 464 465 /* 466 * [re]initialize an idle port. No CCBs should be active. (from port thread) 467 * 468 * This function is called during the initial port allocation sequence 469 * and is also called on hot-plug insertion. We take no chances and 470 * use a portreset instead of a softreset. 471 * 472 * This function is the only way to move a failed port back to active 473 * status. 474 * 475 * Returns 0 if a device is successfully detected. 476 */ 477 int 478 ahci_port_init(struct ahci_port *ap) 479 { 480 u_int32_t cmd; 481 482 /* 483 * Register [re]initialization 484 * 485 * Flush the TFD and SERR and make sure the port is stopped before 486 * enabling its interrupt. We no longer cycle the port start as 487 * the port should not be started unless a device is present. 488 * 489 * XXX should we enable FIS reception? (FRE)? 490 */ 491 ahci_pwrite(ap, AHCI_PREG_IE, 0); 492 ahci_port_stop(ap, 0); 493 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSNTF) 494 ahci_pwrite(ap, AHCI_PREG_SNTF, -1); 495 ahci_flush_tfd(ap); 496 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 497 498 /* 499 * If we are being harsh try to kill the port completely. Normally 500 * we would want to hold on to some of the state the BIOS may have 501 * set, such as SUD (spin up device). 502 * 503 * AP_F_HARSH_REINIT is cleared in the hard reset state 504 */ 505 if (ap->ap_flags & AP_F_HARSH_REINIT) { 506 ahci_pwrite(ap, AHCI_PREG_SCTL, AHCI_PREG_SCTL_IPM_DISABLED); 507 ahci_pwrite(ap, AHCI_PREG_CMD, 0); 508 509 ahci_os_sleep(1000); 510 511 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC; 512 cmd &= ~(AHCI_PREG_CMD_CLO | AHCI_PREG_CMD_PMA); 513 cmd |= AHCI_PREG_CMD_FRE | AHCI_PREG_CMD_POD | 514 AHCI_PREG_CMD_SUD; 515 ahci_pwrite(ap, AHCI_PREG_CMD, cmd | AHCI_PREG_CMD_ICC_ACTIVE); 516 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC; 517 if ((cmd & AHCI_PREG_CMD_FRE) == 0) { 518 kprintf("%s: Warning: FRE did not come up during " 519 "harsh reinitialization\n", 520 PORTNAME(ap)); 521 } 522 ahci_os_sleep(1000); 523 } 524 525 /* 526 * Clear any pending garbage and re-enable the interrupt before 527 * going to the next stage. 528 */ 529 ap->ap_probe = ATA_PROBE_NEED_HARD_RESET; 530 ap->ap_pmcount = 0; 531 532 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSNTF) 533 ahci_pwrite(ap, AHCI_PREG_SNTF, -1); 534 ahci_flush_tfd(ap); 535 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 536 ahci_pwrite(ap, AHCI_PREG_IS, -1); 537 538 ahci_port_interrupt_enable(ap); 539 540 return (0); 541 } 542 543 /* 544 * Enable or re-enable interrupts on a port. 545 * 546 * This routine is called from the port initialization code or from the 547 * helper thread as the real interrupt may be forced to turn off certain 548 * interrupt sources. 549 */ 550 void 551 ahci_port_interrupt_enable(struct ahci_port *ap) 552 { 553 ahci_pwrite(ap, AHCI_PREG_IE, ap->ap_intmask); 554 } 555 556 /* 557 * Manage the agressive link power management capability. 558 */ 559 void 560 ahci_port_link_pwr_mgmt(struct ahci_port *ap, int link_pwr_mgmt) 561 { 562 u_int32_t cmd, sctl; 563 564 if (link_pwr_mgmt == ap->link_pwr_mgmt) 565 return; 566 567 if ((ap->ap_sc->sc_cap & AHCI_REG_CAP_SALP) == 0) { 568 kprintf("%s: link power management not supported.\n", 569 PORTNAME(ap)); 570 return; 571 } 572 573 ahci_os_lock_port(ap); 574 575 if (link_pwr_mgmt == AHCI_LINK_PWR_MGMT_AGGR && 576 (ap->ap_sc->sc_cap & AHCI_REG_CAP_SSC)) { 577 kprintf("%s: enabling aggressive link power management.\n", 578 PORTNAME(ap)); 579 580 ap->link_pwr_mgmt = link_pwr_mgmt; 581 582 ap->ap_intmask &= ~AHCI_PREG_IE_PRCE; 583 ahci_port_interrupt_enable(ap); 584 585 sctl = ahci_pread(ap, AHCI_PREG_SCTL); 586 sctl &= ~(AHCI_PREG_SCTL_IPM_DISABLED); 587 ahci_pwrite(ap, AHCI_PREG_SCTL, sctl); 588 589 /* 590 * Enable device initiated link power management for 591 * directly attached devices that support it. 592 */ 593 if (ap->ap_type != ATA_PORT_T_PM && 594 ap->ap_ata[0]->at_identify.satafsup & (1 << 3)) { 595 if (ahci_set_feature(ap, NULL, ATA_SATAFT_DEVIPS, 1)) 596 kprintf("%s: Could not enable device initiated " 597 "link power management.\n", 598 PORTNAME(ap)); 599 } 600 601 cmd = ahci_pread(ap, AHCI_PREG_CMD); 602 cmd |= AHCI_PREG_CMD_ASP; 603 cmd |= AHCI_PREG_CMD_ALPE; 604 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 605 606 } else if (link_pwr_mgmt == AHCI_LINK_PWR_MGMT_MEDIUM && 607 (ap->ap_sc->sc_cap & AHCI_REG_CAP_PSC)) { 608 kprintf("%s: enabling medium link power management.\n", 609 PORTNAME(ap)); 610 611 ap->link_pwr_mgmt = link_pwr_mgmt; 612 613 ap->ap_intmask &= ~AHCI_PREG_IE_PRCE; 614 ahci_port_interrupt_enable(ap); 615 616 sctl = ahci_pread(ap, AHCI_PREG_SCTL); 617 sctl |= AHCI_PREG_SCTL_IPM_DISABLED; 618 sctl &= ~AHCI_PREG_SCTL_IPM_NOPARTIAL; 619 ahci_pwrite(ap, AHCI_PREG_SCTL, sctl); 620 621 cmd = ahci_pread(ap, AHCI_PREG_CMD); 622 cmd &= ~AHCI_PREG_CMD_ASP; 623 cmd |= AHCI_PREG_CMD_ALPE; 624 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 625 626 } else if (link_pwr_mgmt == AHCI_LINK_PWR_MGMT_NONE) { 627 kprintf("%s: disabling link power management.\n", 628 PORTNAME(ap)); 629 630 /* Disable device initiated link power management */ 631 if (ap->ap_type != ATA_PORT_T_PM && 632 ap->ap_ata[0]->at_identify.satafsup & (1 << 3)) 633 ahci_set_feature(ap, NULL, ATA_SATAFT_DEVIPS, 0); 634 635 cmd = ahci_pread(ap, AHCI_PREG_CMD); 636 cmd &= ~(AHCI_PREG_CMD_ALPE | AHCI_PREG_CMD_ASP); 637 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 638 639 sctl = ahci_pread(ap, AHCI_PREG_SCTL); 640 sctl |= AHCI_PREG_SCTL_IPM_DISABLED; 641 ahci_pwrite(ap, AHCI_PREG_SCTL, sctl); 642 643 /* let the drive come back to avoid PRCS interrupts later */ 644 ahci_os_unlock_port(ap); 645 ahci_os_sleep(1000); 646 ahci_os_lock_port(ap); 647 648 ahci_pwrite(ap, AHCI_PREG_SERR, 649 AHCI_PREG_SERR_DIAG_N | AHCI_PREG_SERR_DIAG_W); 650 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_PRCS); 651 652 ap->ap_intmask |= AHCI_PREG_IE_PRCE; 653 ahci_port_interrupt_enable(ap); 654 655 ap->link_pwr_mgmt = link_pwr_mgmt; 656 } else { 657 kprintf("%s: unsupported link power management state %d.\n", 658 PORTNAME(ap), link_pwr_mgmt); 659 } 660 661 ahci_os_unlock_port(ap); 662 } 663 664 /* 665 * Return current link power state. 666 */ 667 int 668 ahci_port_link_pwr_state(struct ahci_port *ap) 669 { 670 uint32_t r; 671 672 r = ahci_pread(ap, AHCI_PREG_SSTS); 673 switch (r & SATA_PM_SSTS_IPM) { 674 case SATA_PM_SSTS_IPM_ACTIVE: 675 return 1; 676 case SATA_PM_SSTS_IPM_PARTIAL: 677 return 2; 678 case SATA_PM_SSTS_IPM_SLUMBER: 679 return 3; 680 default: 681 return 0; 682 } 683 } 684 685 /* 686 * Run the port / target state machine from a main context. 687 * 688 * The state machine for the port is always run. 689 * 690 * If atx is non-NULL run the state machine for a particular target. 691 * If atx is NULL run the state machine for all targets. 692 */ 693 void 694 ahci_port_state_machine(struct ahci_port *ap, int initial) 695 { 696 struct ata_port *at; 697 u_int32_t data; 698 int target; 699 int didsleep; 700 int loop; 701 702 /* 703 * State machine for port. Note that CAM is not yet associated 704 * during the initial parallel probe and the port's probe state 705 * will not get past ATA_PROBE_NEED_IDENT. 706 */ 707 { 708 if (initial == 0 && ap->ap_probe <= ATA_PROBE_NEED_HARD_RESET) { 709 kprintf("%s: Waiting 10 seconds on insertion\n", 710 PORTNAME(ap)); 711 ahci_os_sleep(10000); 712 initial = 1; 713 } 714 if (ap->ap_probe == ATA_PROBE_NEED_INIT) 715 ahci_port_init(ap); 716 if (ap->ap_probe == ATA_PROBE_NEED_HARD_RESET) 717 ahci_port_reset(ap, NULL, 1); 718 if (ap->ap_probe == ATA_PROBE_NEED_SOFT_RESET) 719 ahci_port_reset(ap, NULL, 0); 720 if (ap->ap_probe == ATA_PROBE_NEED_IDENT) 721 ahci_cam_probe(ap, NULL); 722 } 723 if (ap->ap_type != ATA_PORT_T_PM) { 724 if (ap->ap_probe == ATA_PROBE_FAILED) { 725 ahci_cam_changed(ap, NULL, 0); 726 } else if (ap->ap_probe >= ATA_PROBE_NEED_IDENT) { 727 ahci_cam_changed(ap, NULL, 1); 728 } 729 return; 730 } 731 732 /* 733 * Port Multiplier state machine. 734 * 735 * Get a mask of changed targets and combine with any runnable 736 * states already present. 737 */ 738 for (loop = 0; ;++loop) { 739 if (ahci_pm_read(ap, 15, SATA_PMREG_EINFO, &data)) { 740 kprintf("%s: PM unable to read hot-plug bitmap\n", 741 PORTNAME(ap)); 742 break; 743 } 744 745 /* 746 * Do at least one loop, then stop if no more state changes 747 * have occured. The PM might not generate a new 748 * notification until we clear the entire bitmap. 749 */ 750 if (loop && data == 0) 751 break; 752 753 /* 754 * New devices showing up in the bitmap require some spin-up 755 * time before we start probing them. Reset didsleep. The 756 * first new device we detect will sleep before probing. 757 * 758 * This only applies to devices whos change bit is set in 759 * the data, and does not apply to the initial boot-time 760 * probe. 761 */ 762 didsleep = 0; 763 764 for (target = 0; target < ap->ap_pmcount; ++target) { 765 at = ap->ap_ata[target]; 766 767 /* 768 * Check the target state for targets behind the PM 769 * which have changed state. This will adjust 770 * at_probe and set ATA_PORT_F_RESCAN 771 * 772 * We want to wait at least 10 seconds before probing 773 * a newly inserted device. If the check status 774 * indicates a device is present and in need of a 775 * hard reset, we make sure we have slept before 776 * continuing. 777 * 778 * We also need to wait at least 1 second for the 779 * PHY state to change after insertion, if we 780 * haven't already waited the 10 seconds. 781 * 782 * NOTE: When pm_check_good finds a good port it 783 * typically starts us in probe state 784 * NEED_HARD_RESET rather than INIT. 785 */ 786 if (data & (1 << target)) { 787 if (initial == 0 && didsleep == 0) 788 ahci_os_sleep(1000); 789 ahci_pm_check_good(ap, target); 790 if (initial == 0 && didsleep == 0 && 791 at->at_probe <= ATA_PROBE_NEED_HARD_RESET 792 ) { 793 didsleep = 1; 794 kprintf("%s: Waiting 10 seconds on insertion\n", PORTNAME(ap)); 795 ahci_os_sleep(10000); 796 } 797 } 798 799 /* 800 * Report hot-plug events before the probe state 801 * really gets hot. Only actual events are reported 802 * here to reduce spew. 803 */ 804 if (data & (1 << target)) { 805 kprintf("%s: HOTPLUG (PM) - ", ATANAME(ap, at)); 806 switch(at->at_probe) { 807 case ATA_PROBE_NEED_INIT: 808 case ATA_PROBE_NEED_HARD_RESET: 809 kprintf("Device inserted\n"); 810 break; 811 case ATA_PROBE_FAILED: 812 kprintf("Device removed\n"); 813 break; 814 default: 815 kprintf("Device probe in progress\n"); 816 break; 817 } 818 } 819 820 /* 821 * Run through the state machine as necessary if 822 * the port is not marked failed. 823 * 824 * The state machine may stop at NEED_IDENT if 825 * CAM is not yet attached. 826 * 827 * Acquire exclusive access to the port while we 828 * are doing this. This prevents command-completion 829 * from queueing commands for non-polled targets 830 * inbetween our probe steps. We need to do this 831 * because the reset probes can generate severe PHY 832 * and protocol errors and soft-brick the port. 833 */ 834 if (at->at_probe != ATA_PROBE_FAILED && 835 at->at_probe != ATA_PROBE_GOOD) { 836 ahci_beg_exclusive_access(ap, at); 837 if (at->at_probe == ATA_PROBE_NEED_INIT) 838 ahci_pm_port_init(ap, at); 839 if (at->at_probe == ATA_PROBE_NEED_HARD_RESET) 840 ahci_port_reset(ap, at, 1); 841 if (at->at_probe == ATA_PROBE_NEED_SOFT_RESET) 842 ahci_port_reset(ap, at, 0); 843 if (at->at_probe == ATA_PROBE_NEED_IDENT) 844 ahci_cam_probe(ap, at); 845 ahci_end_exclusive_access(ap, at); 846 } 847 848 /* 849 * Add or remove from CAM 850 */ 851 if (at->at_features & ATA_PORT_F_RESCAN) { 852 at->at_features &= ~ATA_PORT_F_RESCAN; 853 if (at->at_probe == ATA_PROBE_FAILED) { 854 ahci_cam_changed(ap, at, 0); 855 } else if (at->at_probe >= ATA_PROBE_NEED_IDENT) { 856 ahci_cam_changed(ap, at, 1); 857 } 858 } 859 data &= ~(1 << target); 860 } 861 if (data) { 862 kprintf("%s: WARNING (PM): extra bits set in " 863 "EINFO: %08x\n", PORTNAME(ap), data); 864 while (target < AHCI_MAX_PMPORTS) { 865 ahci_pm_check_good(ap, target); 866 ++target; 867 } 868 } 869 } 870 } 871 872 873 /* 874 * De-initialize and detach a port. 875 */ 876 void 877 ahci_port_free(struct ahci_softc *sc, u_int port) 878 { 879 struct ahci_port *ap = sc->sc_ports[port]; 880 struct ahci_ccb *ccb; 881 int i; 882 883 /* 884 * Ensure port is disabled and its interrupts are all flushed. 885 */ 886 if (ap->ap_sc) { 887 ahci_port_stop(ap, 1); 888 ahci_os_stop_port(ap); 889 ahci_pwrite(ap, AHCI_PREG_CMD, 0); 890 ahci_pwrite(ap, AHCI_PREG_IE, 0); 891 ahci_pwrite(ap, AHCI_PREG_IS, ahci_pread(ap, AHCI_PREG_IS)); 892 ahci_write(sc, AHCI_REG_IS, 1 << port); 893 } 894 895 if (ap->ap_ccbs) { 896 while ((ccb = ahci_get_ccb(ap)) != NULL) { 897 if (ccb->ccb_dmamap) { 898 bus_dmamap_destroy(sc->sc_tag_data, 899 ccb->ccb_dmamap); 900 ccb->ccb_dmamap = NULL; 901 } 902 } 903 if ((ccb = ap->ap_err_ccb) != NULL) { 904 if (ccb->ccb_dmamap) { 905 bus_dmamap_destroy(sc->sc_tag_data, 906 ccb->ccb_dmamap); 907 ccb->ccb_dmamap = NULL; 908 } 909 ap->ap_err_ccb = NULL; 910 } 911 kfree(ap->ap_ccbs, M_DEVBUF); 912 ap->ap_ccbs = NULL; 913 } 914 915 if (ap->ap_dmamem_cmd_list) { 916 ahci_dmamem_free(sc, ap->ap_dmamem_cmd_list); 917 ap->ap_dmamem_cmd_list = NULL; 918 } 919 if (ap->ap_dmamem_rfis) { 920 ahci_dmamem_free(sc, ap->ap_dmamem_rfis); 921 ap->ap_dmamem_rfis = NULL; 922 } 923 if (ap->ap_dmamem_cmd_table) { 924 ahci_dmamem_free(sc, ap->ap_dmamem_cmd_table); 925 ap->ap_dmamem_cmd_table = NULL; 926 } 927 if (ap->ap_ata) { 928 for (i = 0; i < AHCI_MAX_PMPORTS; ++i) { 929 if (ap->ap_ata[i]) { 930 kfree(ap->ap_ata[i], M_DEVBUF); 931 ap->ap_ata[i] = NULL; 932 } 933 } 934 } 935 if (ap->ap_err_scratch) { 936 kfree(ap->ap_err_scratch, M_DEVBUF); 937 ap->ap_err_scratch = NULL; 938 } 939 940 /* bus_space(9) says we dont free the subregions handle */ 941 942 kfree(ap, M_DEVBUF); 943 sc->sc_ports[port] = NULL; 944 } 945 946 static 947 u_int32_t 948 ahci_pactive(struct ahci_port *ap) 949 { 950 u_int32_t mask; 951 952 mask = ahci_pread(ap, AHCI_PREG_CI); 953 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SNCQ) 954 mask |= ahci_pread(ap, AHCI_PREG_SACT); 955 return(mask); 956 } 957 958 /* 959 * Start high-level command processing on the port 960 */ 961 int 962 ahci_port_start(struct ahci_port *ap) 963 { 964 u_int32_t r, s, is, tfd; 965 966 /* 967 * FRE must be turned on before ST. Wait for FR to go active 968 * before turning on ST. The spec doesn't seem to think this 969 * is necessary but waiting here avoids an on-off race in the 970 * ahci_port_stop() code. 971 */ 972 r = ahci_pread(ap, AHCI_PREG_CMD); 973 if ((r & AHCI_PREG_CMD_FRE) == 0) { 974 r |= AHCI_PREG_CMD_FRE; 975 ahci_pwrite(ap, AHCI_PREG_CMD, r); 976 } 977 if ((ap->ap_sc->sc_flags & AHCI_F_IGN_FR) == 0) { 978 if (ahci_pwait_set(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR)) { 979 kprintf("%s: Cannot start FIS reception\n", 980 PORTNAME(ap)); 981 return (2); 982 } 983 } else { 984 ahci_os_sleep(10); 985 } 986 987 /* 988 * Turn on ST, wait for CR to come up. 989 */ 990 r |= AHCI_PREG_CMD_ST; 991 ahci_pwrite(ap, AHCI_PREG_CMD, r); 992 if (ahci_pwait_set_to(ap, 2000, AHCI_PREG_CMD, AHCI_PREG_CMD_CR)) { 993 s = ahci_pread(ap, AHCI_PREG_SERR); 994 is = ahci_pread(ap, AHCI_PREG_IS); 995 tfd = ahci_pread(ap, AHCI_PREG_TFD); 996 kprintf("%s: Cannot start command DMA\n" 997 "NCMP=%b NSERR=%b\n" 998 "NEWIS=%b\n" 999 "NEWTFD=%b\n", 1000 PORTNAME(ap), 1001 r, AHCI_PFMT_CMD, s, AHCI_PFMT_SERR, 1002 is, AHCI_PFMT_IS, 1003 tfd, AHCI_PFMT_TFD_STS); 1004 return (1); 1005 } 1006 1007 #ifdef AHCI_COALESCE 1008 /* 1009 * (Re-)enable coalescing on the port. 1010 */ 1011 if (ap->ap_sc->sc_ccc_ports & (1 << ap->ap_num)) { 1012 ap->ap_sc->sc_ccc_ports_cur |= (1 << ap->ap_num); 1013 ahci_write(ap->ap_sc, AHCI_REG_CCC_PORTS, 1014 ap->ap_sc->sc_ccc_ports_cur); 1015 } 1016 #endif 1017 1018 return (0); 1019 } 1020 1021 /* 1022 * Stop high-level command processing on a port 1023 * 1024 * WARNING! If the port is stopped while CR is still active our saved 1025 * CI/SACT will race any commands completed by the command 1026 * processor prior to being able to stop. Thus we never call 1027 * this function unless we intend to dispose of any remaining 1028 * active commands. In particular, this complicates the timeout 1029 * code. 1030 */ 1031 int 1032 ahci_port_stop(struct ahci_port *ap, int stop_fis_rx) 1033 { 1034 u_int32_t r; 1035 1036 #ifdef AHCI_COALESCE 1037 /* 1038 * Disable coalescing on the port while it is stopped. 1039 */ 1040 if (ap->ap_sc->sc_ccc_ports & (1 << ap->ap_num)) { 1041 ap->ap_sc->sc_ccc_ports_cur &= ~(1 << ap->ap_num); 1042 ahci_write(ap->ap_sc, AHCI_REG_CCC_PORTS, 1043 ap->ap_sc->sc_ccc_ports_cur); 1044 } 1045 #endif 1046 1047 /* 1048 * Turn off ST, then wait for CR to go off. 1049 */ 1050 r = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC; 1051 r &= ~AHCI_PREG_CMD_ST; 1052 ahci_pwrite(ap, AHCI_PREG_CMD, r); 1053 1054 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_CR)) { 1055 kprintf("%s: Port bricked, unable to stop (ST)\n", 1056 PORTNAME(ap)); 1057 return (1); 1058 } 1059 1060 #if 0 1061 /* 1062 * Turn off FRE, then wait for FR to go off. FRE cannot 1063 * be turned off until CR transitions to 0. 1064 */ 1065 if ((r & AHCI_PREG_CMD_FR) == 0) { 1066 kprintf("%s: FR stopped, clear FRE for next start\n", 1067 PORTNAME(ap)); 1068 stop_fis_rx = 2; 1069 } 1070 #endif 1071 if (stop_fis_rx) { 1072 r &= ~AHCI_PREG_CMD_FRE; 1073 ahci_pwrite(ap, AHCI_PREG_CMD, r); 1074 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR)) { 1075 kprintf("%s: Port bricked, unable to stop (FRE)\n", 1076 PORTNAME(ap)); 1077 return (2); 1078 } 1079 } 1080 1081 return (0); 1082 } 1083 1084 /* 1085 * AHCI command list override -> forcibly clear TFD.STS.{BSY,DRQ} 1086 */ 1087 int 1088 ahci_port_clo(struct ahci_port *ap) 1089 { 1090 struct ahci_softc *sc = ap->ap_sc; 1091 u_int32_t cmd; 1092 1093 /* Only attempt CLO if supported by controller */ 1094 if ((ahci_read(sc, AHCI_REG_CAP) & AHCI_REG_CAP_SCLO) == 0) 1095 return (1); 1096 1097 /* Issue CLO */ 1098 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC; 1099 ahci_pwrite(ap, AHCI_PREG_CMD, cmd | AHCI_PREG_CMD_CLO); 1100 1101 /* Wait for completion */ 1102 if (ahci_pwait_clr(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_CLO)) { 1103 kprintf("%s: CLO did not complete\n", PORTNAME(ap)); 1104 return (1); 1105 } 1106 1107 return (0); 1108 } 1109 1110 /* 1111 * Reset a port. 1112 * 1113 * If hard is 0 perform a softreset of the port. 1114 * If hard is 1 perform a hard reset of the port. 1115 * 1116 * If at is non-NULL an indirect port via a port-multiplier is being 1117 * reset, otherwise a direct port is being reset. 1118 * 1119 * NOTE: Indirect ports can only be soft-reset. 1120 */ 1121 int 1122 ahci_port_reset(struct ahci_port *ap, struct ata_port *at, int hard) 1123 { 1124 int rc; 1125 1126 if (hard) { 1127 if (at) 1128 rc = ahci_pm_hardreset(ap, at->at_target, hard); 1129 else 1130 rc = ahci_port_hardreset(ap, hard); 1131 } else { 1132 if (at) 1133 rc = ahci_pm_softreset(ap, at->at_target); 1134 else 1135 rc = ahci_port_softreset(ap); 1136 } 1137 return(rc); 1138 } 1139 1140 /* 1141 * AHCI soft reset, Section 10.4.1 1142 * 1143 * (at) will be NULL when soft-resetting a directly-attached device, and 1144 * non-NULL when soft-resetting a device through a port multiplier. 1145 * 1146 * This function keeps port communications intact and attempts to generate 1147 * a reset to the connected device using device commands. 1148 */ 1149 int 1150 ahci_port_softreset(struct ahci_port *ap) 1151 { 1152 struct ahci_ccb *ccb = NULL; 1153 struct ahci_cmd_hdr *cmd_slot; 1154 u_int8_t *fis; 1155 int error; 1156 1157 error = EIO; 1158 1159 if (bootverbose) { 1160 kprintf("%s: START SOFTRESET %b\n", PORTNAME(ap), 1161 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD); 1162 } 1163 1164 DPRINTF(AHCI_D_VERBOSE, "%s: soft reset\n", PORTNAME(ap)); 1165 1166 crit_enter(); 1167 ap->ap_flags |= AP_F_IN_RESET; 1168 ap->ap_state = AP_S_NORMAL; 1169 1170 /* 1171 * Remember port state in cmd (main to restore start/stop) 1172 * 1173 * Idle port. 1174 */ 1175 if (ahci_port_stop(ap, 0)) { 1176 kprintf("%s: failed to stop port, cannot softreset\n", 1177 PORTNAME(ap)); 1178 goto err; 1179 } 1180 1181 /* 1182 * Request CLO if device appears hung. 1183 */ 1184 if (ahci_pread(ap, AHCI_PREG_TFD) & 1185 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 1186 ahci_port_clo(ap); 1187 } 1188 1189 /* 1190 * This is an attempt to clear errors so a new signature will 1191 * be latched. It isn't working properly. XXX 1192 */ 1193 ahci_flush_tfd(ap); 1194 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 1195 1196 /* Restart port */ 1197 if (ahci_port_start(ap)) { 1198 kprintf("%s: failed to start port, cannot softreset\n", 1199 PORTNAME(ap)); 1200 goto err; 1201 } 1202 1203 /* Check whether CLO worked */ 1204 if (ahci_pwait_clr(ap, AHCI_PREG_TFD, 1205 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 1206 kprintf("%s: CLO %s, need port reset\n", 1207 PORTNAME(ap), 1208 (ahci_read(ap->ap_sc, AHCI_REG_CAP) & AHCI_REG_CAP_SCLO) 1209 ? "failed" : "unsupported"); 1210 error = EBUSY; 1211 goto err; 1212 } 1213 1214 /* 1215 * Prep first D2H command with SRST feature & clear busy/reset flags 1216 * 1217 * It is unclear which other fields in the FIS are used. Just zero 1218 * everything. 1219 * 1220 * NOTE! This CCB is used for both the first and second commands. 1221 * The second command must use CCB slot 1 to properly load 1222 * the signature. 1223 */ 1224 ccb = ahci_get_err_ccb(ap); 1225 ccb->ccb_xa.complete = ahci_dummy_done; 1226 ccb->ccb_xa.flags = ATA_F_POLL | ATA_F_EXCLUSIVE; 1227 KKASSERT(ccb->ccb_slot == 1); 1228 ccb->ccb_xa.at = NULL; 1229 cmd_slot = ccb->ccb_cmd_hdr; 1230 1231 fis = ccb->ccb_cmd_table->cfis; 1232 bzero(fis, sizeof(ccb->ccb_cmd_table->cfis)); 1233 fis[0] = ATA_FIS_TYPE_H2D; 1234 fis[15] = ATA_FIS_CONTROL_SRST|ATA_FIS_CONTROL_4BIT; 1235 1236 cmd_slot->prdtl = 0; 1237 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */ 1238 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_C); /* Clear busy on OK */ 1239 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_R); /* Reset */ 1240 1241 ccb->ccb_xa.state = ATA_S_PENDING; 1242 1243 if (ahci_poll(ccb, 1000, ahci_quick_timeout) != ATA_S_COMPLETE) { 1244 kprintf("%s: First FIS failed\n", PORTNAME(ap)); 1245 goto err; 1246 } 1247 1248 /* 1249 * WARNING! TIME SENSITIVE SPACE! WARNING! 1250 * 1251 * The two FISes are supposed to be back to back. Don't issue other 1252 * commands or even delay if we can help it. 1253 */ 1254 1255 /* 1256 * Prep second D2H command to read status and complete reset sequence 1257 * AHCI 10.4.1 and "Serial ATA Revision 2.6". I can't find the ATA 1258 * Rev 2.6 and it is unclear how the second FIS should be set up 1259 * from the AHCI document. 1260 * 1261 * It is unclear which other fields in the FIS are used. Just zero 1262 * everything. 1263 */ 1264 ccb->ccb_xa.flags = ATA_F_POLL | ATA_F_AUTOSENSE | ATA_F_EXCLUSIVE; 1265 1266 bzero(fis, sizeof(ccb->ccb_cmd_table->cfis)); 1267 fis[0] = ATA_FIS_TYPE_H2D; 1268 fis[15] = ATA_FIS_CONTROL_4BIT; 1269 1270 cmd_slot->prdtl = 0; 1271 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */ 1272 1273 ccb->ccb_xa.state = ATA_S_PENDING; 1274 if (ahci_poll(ccb, 1000, ahci_quick_timeout) != ATA_S_COMPLETE) { 1275 kprintf("%s: Second FIS failed\n", PORTNAME(ap)); 1276 goto err; 1277 } 1278 1279 if (ahci_pwait_clr(ap, AHCI_PREG_TFD, 1280 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 1281 kprintf("%s: device didn't come ready after reset, TFD: 0x%b\n", 1282 PORTNAME(ap), 1283 ahci_pread(ap, AHCI_PREG_TFD), AHCI_PFMT_TFD_STS); 1284 error = EBUSY; 1285 goto err; 1286 } 1287 1288 /* 1289 * If the softreset is trying to clear a BSY condition after a 1290 * normal portreset we assign the port type. 1291 * 1292 * If the softreset is being run first as part of the ccb error 1293 * processing code then report if the device signature changed 1294 * unexpectedly. 1295 */ 1296 ahci_os_sleep(100); 1297 if (ap->ap_type == ATA_PORT_T_NONE) { 1298 ap->ap_type = ahci_port_signature_detect(ap, NULL); 1299 } else { 1300 if (ahci_port_signature_detect(ap, NULL) != ap->ap_type) { 1301 kprintf("%s: device signature unexpectedly " 1302 "changed\n", PORTNAME(ap)); 1303 error = EBUSY; /* XXX */ 1304 } 1305 } 1306 error = 0; 1307 1308 ahci_os_sleep(3); 1309 err: 1310 if (ccb != NULL) { 1311 ahci_put_err_ccb(ccb); 1312 1313 /* 1314 * If the target is busy use CLO to clear the busy 1315 * condition. The BSY should be cleared on the next 1316 * start. 1317 */ 1318 if (ahci_pread(ap, AHCI_PREG_TFD) & 1319 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 1320 ahci_port_clo(ap); 1321 } 1322 } 1323 1324 /* 1325 * If we failed to softreset make the port quiescent, otherwise 1326 * make sure the port's start/stop state matches what it was on 1327 * entry. 1328 * 1329 * Don't kill the port if the softreset is on a port multiplier 1330 * target, that would kill all the targets! 1331 */ 1332 if (error) { 1333 ahci_port_hardstop(ap); 1334 /* ap_probe set to failed */ 1335 } else { 1336 ap->ap_probe = ATA_PROBE_NEED_IDENT; 1337 ap->ap_pmcount = 1; 1338 ahci_port_start(ap); 1339 } 1340 ap->ap_flags &= ~AP_F_IN_RESET; 1341 crit_exit(); 1342 1343 if (bootverbose) 1344 kprintf("%s: END SOFTRESET\n", PORTNAME(ap)); 1345 1346 return (error); 1347 } 1348 1349 /* 1350 * Issue just do the core COMRESET and basic device detection on a port. 1351 * 1352 * NOTE: Only called by ahci_port_hardreset(). 1353 */ 1354 static int 1355 ahci_comreset(struct ahci_port *ap, int *pmdetectp) 1356 { 1357 u_int32_t cmd; 1358 u_int32_t r; 1359 int error; 1360 int loop; 1361 1362 /* 1363 * Idle the port, 1364 */ 1365 *pmdetectp = 0; 1366 ahci_port_stop(ap, 0); 1367 ap->ap_state = AP_S_NORMAL; 1368 ahci_os_sleep(10); 1369 1370 /* 1371 * The port may have been quiescent with its SUD bit cleared, so 1372 * set the SUD (spin up device). 1373 * 1374 * NOTE: I do not know if SUD is a hardware pin/low-level signal 1375 * or if it is messaged. 1376 */ 1377 cmd = ahci_pread(ap, AHCI_PREG_CMD) & ~AHCI_PREG_CMD_ICC; 1378 1379 cmd |= AHCI_PREG_CMD_SUD | AHCI_PREG_CMD_POD; 1380 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 1381 ahci_os_sleep(10); 1382 1383 /* 1384 * Make sure that all power management is disabled. 1385 * 1386 * NOTE! AHCI_PREG_SCTL_DET_DISABLE seems to be highly unreliable 1387 * on multiple chipsets and can brick the chipset or even 1388 * the whole PC. Never use it. 1389 */ 1390 ap->ap_type = ATA_PORT_T_NONE; 1391 1392 r = AHCI_PREG_SCTL_IPM_DISABLED | 1393 AHCI_PREG_SCTL_SPM_DISABLED; 1394 ahci_pwrite(ap, AHCI_PREG_SCTL, r); 1395 ahci_os_sleep(10); 1396 1397 /* 1398 * Start transmitting COMRESET. The spec says that COMRESET must 1399 * be sent for at least 1ms but in actual fact numerous devices 1400 * appear to take much longer. Delay a whole second here. 1401 * 1402 * In addition, SATA-3 ports can take longer to train, so even 1403 * SATA-2 devices which would normally detect very quickly may 1404 * take longer when plugged into a SATA-3 port. 1405 */ 1406 r |= AHCI_PREG_SCTL_DET_INIT; 1407 switch(AhciForceGen) { 1408 case 0: 1409 r |= AHCI_PREG_SCTL_SPD_ANY; 1410 break; 1411 case 1: 1412 r |= AHCI_PREG_SCTL_SPD_GEN1; 1413 break; 1414 case 2: 1415 r |= AHCI_PREG_SCTL_SPD_GEN2; 1416 break; 1417 case 3: 1418 r |= AHCI_PREG_SCTL_SPD_GEN3; 1419 break; 1420 default: 1421 r |= AHCI_PREG_SCTL_SPD_GEN3; 1422 break; 1423 } 1424 ahci_pwrite(ap, AHCI_PREG_SCTL, r); 1425 ahci_os_sleep(1000); 1426 r &= ~AHCI_PREG_SCTL_SPD; 1427 1428 ap->ap_flags &= ~AP_F_HARSH_REINIT; 1429 1430 /* 1431 * Only SERR_DIAG_X needs to be cleared for TFD updates, but 1432 * since we are hard-resetting the port we might as well clear 1433 * the whole enchillada. 1434 * 1435 * Wait 1 whole second after clearing INIT before checking 1436 * the device detection bits in an attempt to work around chipsets 1437 * which do not properly mask PCS/PRCS during low level init. 1438 */ 1439 ahci_flush_tfd(ap); 1440 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 1441 ahci_os_sleep(10); 1442 1443 r &= ~AHCI_PREG_SCTL_DET_INIT; 1444 r |= AHCI_PREG_SCTL_DET_NONE; 1445 ahci_pwrite(ap, AHCI_PREG_SCTL, r); 1446 ahci_os_sleep(1000); 1447 1448 /* 1449 * Try to determine if there is a device on the port. 1450 * 1451 * Give the device 3/10 second to at least be detected. 1452 * If we fail clear PRCS (phy detect) since we may cycled 1453 * the phy and probably caused another PRCS interrupt. 1454 */ 1455 loop = 300; 1456 while (loop > 0) { 1457 r = ahci_pread(ap, AHCI_PREG_SSTS); 1458 if (r & AHCI_PREG_SSTS_DET) 1459 break; 1460 loop -= ahci_os_softsleep(); 1461 } 1462 if (loop == 0) { 1463 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_PRCS); 1464 if (bootverbose) { 1465 kprintf("%s: Port appears to be unplugged\n", 1466 PORTNAME(ap)); 1467 } 1468 error = ENODEV; 1469 goto done; 1470 } 1471 1472 /* 1473 * There is something on the port. Regardless of what happens 1474 * after this tell the caller to try to detect a port multiplier. 1475 * 1476 * Give the device 3 seconds to fully negotiate. 1477 */ 1478 *pmdetectp = 1; 1479 1480 if (ahci_pwait_eq(ap, 3000, AHCI_PREG_SSTS, 1481 AHCI_PREG_SSTS_DET, AHCI_PREG_SSTS_DET_DEV)) { 1482 if (bootverbose) { 1483 kprintf("%s: Device may be powered down\n", 1484 PORTNAME(ap)); 1485 } 1486 error = ENODEV; 1487 goto done; 1488 } 1489 1490 /* 1491 * We got something that definitely looks like a device. Give 1492 * the device time to send us its first D2H FIS. Waiting for 1493 * BSY to clear accomplishes this. 1494 * 1495 * NOTE: A port multiplier may or may not clear BSY here, 1496 * depending on what is sitting in target 0 behind it. 1497 */ 1498 ahci_flush_tfd(ap); 1499 if (ahci_pwait_clr_to(ap, 3000, AHCI_PREG_TFD, 1500 AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 1501 error = EBUSY; 1502 } else { 1503 error = 0; 1504 } 1505 1506 done: 1507 ahci_flush_tfd(ap); 1508 return error; 1509 } 1510 1511 1512 /* 1513 * AHCI port reset, Section 10.4.2 1514 * 1515 * This function does a hard reset of the port. Note that the device 1516 * connected to the port could still end-up hung. 1517 */ 1518 int 1519 ahci_port_hardreset(struct ahci_port *ap, int hard) 1520 { 1521 u_int32_t data; 1522 int error; 1523 int pmdetect; 1524 1525 if (bootverbose) 1526 kprintf("%s: START HARDRESET\n", PORTNAME(ap)); 1527 ap->ap_flags |= AP_F_IN_RESET; 1528 1529 error = ahci_comreset(ap, &pmdetect); 1530 1531 /* 1532 * We may be asked to perform a port multiplier check even if the 1533 * comreset failed. This typically occurs when the PM has nothing 1534 * in slot 0, which can cause BSY to remain set. 1535 * 1536 * If the PM detection is successful it will override (error), 1537 * otherwise (error) is retained. If an error does occur it 1538 * is possible that a normal device has blown up on us DUE to 1539 * the PM detection code, so re-run the comreset and assume 1540 * a normal device. 1541 */ 1542 if (pmdetect) { 1543 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SPM) { 1544 error = ahci_pm_port_probe(ap, error); 1545 if (error) { 1546 error = ahci_comreset(ap, &pmdetect); 1547 } 1548 } 1549 } 1550 1551 /* 1552 * Finish up. 1553 */ 1554 ahci_os_sleep(500); 1555 1556 switch(error) { 1557 case 0: 1558 /* 1559 * All good, make sure the port is running and set the 1560 * probe state. Ignore the signature junk (it's unreliable) 1561 * until we get to the softreset code. 1562 */ 1563 if (ahci_port_start(ap)) { 1564 kprintf("%s: failed to start command DMA on port, " 1565 "disabling\n", PORTNAME(ap)); 1566 error = EBUSY; 1567 break; 1568 } 1569 if (ap->ap_type == ATA_PORT_T_PM) 1570 ap->ap_probe = ATA_PROBE_GOOD; 1571 else 1572 ap->ap_probe = ATA_PROBE_NEED_SOFT_RESET; 1573 break; 1574 case ENODEV: 1575 /* 1576 * Normal device probe failure 1577 */ 1578 data = ahci_pread(ap, AHCI_PREG_SSTS); 1579 1580 switch(data & AHCI_PREG_SSTS_DET) { 1581 case AHCI_PREG_SSTS_DET_DEV_NE: 1582 kprintf("%s: Device not communicating\n", 1583 PORTNAME(ap)); 1584 break; 1585 case AHCI_PREG_SSTS_DET_PHYOFFLINE: 1586 kprintf("%s: PHY offline\n", 1587 PORTNAME(ap)); 1588 break; 1589 default: 1590 kprintf("%s: No device detected\n", 1591 PORTNAME(ap)); 1592 break; 1593 } 1594 ahci_port_hardstop(ap); 1595 break; 1596 default: 1597 /* 1598 * Abnormal probe (EBUSY) 1599 */ 1600 kprintf("%s: Device on port is bricked\n", 1601 PORTNAME(ap)); 1602 ahci_port_hardstop(ap); 1603 #if 0 1604 rc = ahci_port_reset(ap, atx, 0); 1605 if (rc) { 1606 kprintf("%s: Unable unbrick device\n", 1607 PORTNAME(ap)); 1608 } else { 1609 kprintf("%s: Successfully unbricked\n", 1610 PORTNAME(ap)); 1611 } 1612 #endif 1613 break; 1614 } 1615 1616 /* 1617 * Clean up 1618 */ 1619 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 1620 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS); 1621 1622 ap->ap_flags &= ~AP_F_IN_RESET; 1623 1624 if (bootverbose) 1625 kprintf("%s: END HARDRESET %d\n", PORTNAME(ap), error); 1626 return (error); 1627 } 1628 1629 /* 1630 * Hard-stop on hot-swap device removal. See 10.10.1 1631 * 1632 * Place the port in a mode that will allow it to detect hot-swap insertions. 1633 * This is a bit imprecise because just setting-up SCTL to DET_INIT doesn't 1634 * seem to do the job. 1635 * 1636 * FIS reception is left enabled but command processing is disabled. 1637 * Cycling FIS reception (FRE) can brick ports. 1638 */ 1639 void 1640 ahci_port_hardstop(struct ahci_port *ap) 1641 { 1642 struct ahci_ccb *ccb; 1643 struct ata_port *at; 1644 u_int32_t r; 1645 u_int32_t cmd; 1646 int slot; 1647 int i; 1648 1649 /* 1650 * Stop the port. We can't modify things like SUD if the port 1651 * is running. 1652 */ 1653 ap->ap_state = AP_S_FATAL_ERROR; 1654 ap->ap_probe = ATA_PROBE_FAILED; 1655 ap->ap_type = ATA_PORT_T_NONE; 1656 ahci_port_stop(ap, 0); 1657 cmd = ahci_pread(ap, AHCI_PREG_CMD); 1658 cmd &= ~(AHCI_PREG_CMD_CLO | AHCI_PREG_CMD_PMA | AHCI_PREG_CMD_ICC); 1659 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 1660 1661 /* 1662 * Clean up AT sub-ports on SATA port. 1663 */ 1664 for (i = 0; ap->ap_ata && i < AHCI_MAX_PMPORTS; ++i) { 1665 at = ap->ap_ata[i]; 1666 at->at_type = ATA_PORT_T_NONE; 1667 at->at_probe = ATA_PROBE_FAILED; 1668 } 1669 1670 /* 1671 * Make sure FRE is active. There isn't anything we can do if it 1672 * fails so just ignore errors. 1673 */ 1674 if ((cmd & AHCI_PREG_CMD_FRE) == 0) { 1675 cmd |= AHCI_PREG_CMD_FRE; 1676 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 1677 if ((ap->ap_sc->sc_flags & AHCI_F_IGN_FR) == 0) 1678 ahci_pwait_set(ap, AHCI_PREG_CMD, AHCI_PREG_CMD_FR); 1679 } 1680 1681 /* 1682 * 10.10.1 place us in the Listen state. 1683 * 1684 * 10.10.3 DET must be set to 0 and found to be 0 before 1685 * setting SUD to 0. 1686 * 1687 * Deactivating SUD only applies if the controller supports SUD, it 1688 * is a bit unclear what happens w/regards to detecting hotplug 1689 * if it doesn't. 1690 */ 1691 r = AHCI_PREG_SCTL_IPM_DISABLED | 1692 AHCI_PREG_SCTL_SPM_DISABLED; 1693 ahci_pwrite(ap, AHCI_PREG_SCTL, r); 1694 ahci_os_sleep(10); 1695 cmd &= ~AHCI_PREG_CMD_SUD; 1696 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 1697 ahci_os_sleep(10); 1698 1699 /* 1700 * 10.10.1 1701 * 1702 * Transition su to the spin-up state. HBA shall send COMRESET and 1703 * begin initialization sequence (whatever that means). Presumably 1704 * this is edge-triggered. Following the spin-up state the HBA 1705 * will automatically transition to the Normal state. 1706 * 1707 * This only applies if the controller supports SUD. 1708 * NEVER use AHCI_PREG_DET_DISABLE. 1709 */ 1710 cmd |= AHCI_PREG_CMD_POD | 1711 AHCI_PREG_CMD_SUD | 1712 AHCI_PREG_CMD_ICC_ACTIVE; 1713 ahci_pwrite(ap, AHCI_PREG_CMD, cmd); 1714 ahci_os_sleep(10); 1715 1716 /* 1717 * Flush SERR_DIAG_X so the TFD can update. 1718 */ 1719 ahci_flush_tfd(ap); 1720 1721 /* 1722 * Clean out pending ccbs 1723 */ 1724 while (ap->ap_active) { 1725 slot = ffs(ap->ap_active) - 1; 1726 ap->ap_active &= ~(1 << slot); 1727 ap->ap_expired &= ~(1 << slot); 1728 --ap->ap_active_cnt; 1729 ccb = &ap->ap_ccbs[slot]; 1730 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_RUNNING) { 1731 callout_stop(&ccb->ccb_timeout); 1732 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_RUNNING; 1733 } 1734 ccb->ccb_xa.flags &= ~(ATA_F_TIMEOUT_DESIRED | 1735 ATA_F_TIMEOUT_EXPIRED); 1736 ccb->ccb_xa.state = ATA_S_TIMEOUT; 1737 ccb->ccb_done(ccb); 1738 ccb->ccb_xa.complete(&ccb->ccb_xa); 1739 } 1740 while (ap->ap_sactive) { 1741 slot = ffs(ap->ap_sactive) - 1; 1742 ap->ap_sactive &= ~(1 << slot); 1743 ap->ap_expired &= ~(1 << slot); 1744 ccb = &ap->ap_ccbs[slot]; 1745 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_RUNNING) { 1746 callout_stop(&ccb->ccb_timeout); 1747 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_RUNNING; 1748 } 1749 ccb->ccb_xa.flags &= ~(ATA_F_TIMEOUT_DESIRED | 1750 ATA_F_TIMEOUT_EXPIRED); 1751 ccb->ccb_xa.state = ATA_S_TIMEOUT; 1752 ccb->ccb_done(ccb); 1753 ccb->ccb_xa.complete(&ccb->ccb_xa); 1754 } 1755 KKASSERT(ap->ap_active_cnt == 0); 1756 1757 while ((ccb = TAILQ_FIRST(&ap->ap_ccb_pending)) != NULL) { 1758 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry); 1759 ccb->ccb_xa.state = ATA_S_TIMEOUT; 1760 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_DESIRED; 1761 ccb->ccb_done(ccb); 1762 ccb->ccb_xa.complete(&ccb->ccb_xa); 1763 } 1764 1765 /* 1766 * Hot-plug device detection should work at this point. e.g. on 1767 * AMD chipsets Spin-Up/Normal state is sufficient for hot-plug 1768 * detection and entering RESET (continuous COMRESET by setting INIT) 1769 * will actually prevent hot-plug detection from working properly. 1770 * 1771 * There may be cases where this will fail to work, I have some 1772 * additional code to place the HBA in RESET (send continuous 1773 * COMRESET) and hopefully get DIAG.X or other events when something 1774 * is plugged in. Unfortunately this isn't universal and can 1775 * also prevent events from generating interrupts. 1776 */ 1777 1778 #if 0 1779 /* 1780 * Transition us to the Reset state. Theoretically we send a 1781 * continuous stream of COMRESETs in this state. 1782 */ 1783 r |= AHCI_PREG_SCTL_DET_INIT; 1784 if (AhciForceGen1 & (1 << ap->ap_num)) { 1785 kprintf("%s: Force 1.5Gbits\n", PORTNAME(ap)); 1786 r |= AHCI_PREG_SCTL_SPD_GEN1; 1787 } else { 1788 r |= AHCI_PREG_SCTL_SPD_ANY; 1789 } 1790 ahci_pwrite(ap, AHCI_PREG_SCTL, r); 1791 ahci_os_sleep(10); 1792 1793 /* 1794 * Flush SERR_DIAG_X so the TFD can update. 1795 */ 1796 ahci_flush_tfd(ap); 1797 #endif 1798 /* NOP */ 1799 } 1800 1801 /* 1802 * We can't loop on the X bit, a continuous COMINIT received will make 1803 * it loop forever. Just assume one event has built up and clear X 1804 * so the task file descriptor can update. 1805 */ 1806 void 1807 ahci_flush_tfd(struct ahci_port *ap) 1808 { 1809 u_int32_t r; 1810 1811 r = ahci_pread(ap, AHCI_PREG_SERR); 1812 if (r & AHCI_PREG_SERR_DIAG_X) 1813 ahci_pwrite(ap, AHCI_PREG_SERR, AHCI_PREG_SERR_DIAG_X); 1814 } 1815 1816 /* 1817 * Figure out what type of device is connected to the port, ATAPI or 1818 * DISK. 1819 */ 1820 int 1821 ahci_port_signature_detect(struct ahci_port *ap, struct ata_port *at) 1822 { 1823 u_int32_t sig; 1824 1825 sig = ahci_pread(ap, AHCI_PREG_SIG); 1826 if (bootverbose) 1827 kprintf("%s: sig %08x\n", ATANAME(ap, at), sig); 1828 if ((sig & 0xffff0000) == (SATA_SIGNATURE_ATAPI & 0xffff0000)) { 1829 return(ATA_PORT_T_ATAPI); 1830 } else if ((sig & 0xffff0000) == 1831 (SATA_SIGNATURE_PORT_MULTIPLIER & 0xffff0000)) { 1832 return(ATA_PORT_T_PM); 1833 } else { 1834 return(ATA_PORT_T_DISK); 1835 } 1836 } 1837 1838 /* 1839 * Load the DMA descriptor table for a CCB's buffer. 1840 */ 1841 int 1842 ahci_load_prdt(struct ahci_ccb *ccb) 1843 { 1844 struct ahci_port *ap = ccb->ccb_port; 1845 struct ahci_softc *sc = ap->ap_sc; 1846 struct ata_xfer *xa = &ccb->ccb_xa; 1847 struct ahci_prdt *prdt = ccb->ccb_cmd_table->prdt; 1848 bus_dmamap_t dmap = ccb->ccb_dmamap; 1849 struct ahci_cmd_hdr *cmd_slot = ccb->ccb_cmd_hdr; 1850 int error; 1851 1852 if (xa->datalen == 0) { 1853 ccb->ccb_cmd_hdr->prdtl = 0; 1854 return (0); 1855 } 1856 1857 error = bus_dmamap_load(sc->sc_tag_data, dmap, 1858 xa->data, xa->datalen, 1859 ahci_load_prdt_callback, 1860 &prdt, 1861 ((xa->flags & ATA_F_NOWAIT) ? 1862 BUS_DMA_NOWAIT : BUS_DMA_WAITOK)); 1863 if (error != 0) { 1864 kprintf("%s: error %d loading dmamap\n", PORTNAME(ap), error); 1865 return (1); 1866 } 1867 #if 0 1868 if (xa->flags & ATA_F_PIO) 1869 prdt->flags |= htole32(AHCI_PRDT_FLAG_INTR); 1870 #endif 1871 1872 cmd_slot->prdtl = htole16(prdt - ccb->ccb_cmd_table->prdt + 1); 1873 1874 if (xa->flags & ATA_F_READ) 1875 bus_dmamap_sync(sc->sc_tag_data, dmap, BUS_DMASYNC_PREREAD); 1876 if (xa->flags & ATA_F_WRITE) 1877 bus_dmamap_sync(sc->sc_tag_data, dmap, BUS_DMASYNC_PREWRITE); 1878 1879 return (0); 1880 } 1881 1882 /* 1883 * Callback from BUSDMA system to load the segment list. The passed segment 1884 * list is a temporary structure. 1885 */ 1886 static 1887 void 1888 ahci_load_prdt_callback(void *info, bus_dma_segment_t *segs, int nsegs, 1889 int error) 1890 { 1891 struct ahci_prdt *prd = *(void **)info; 1892 u_int64_t addr; 1893 1894 KKASSERT(nsegs <= AHCI_MAX_PRDT); 1895 1896 while (nsegs) { 1897 addr = segs->ds_addr; 1898 prd->dba_hi = htole32((u_int32_t)(addr >> 32)); 1899 prd->dba_lo = htole32((u_int32_t)addr); 1900 prd->flags = htole32(segs->ds_len - 1); 1901 --nsegs; 1902 if (nsegs) 1903 ++prd; 1904 ++segs; 1905 } 1906 *(void **)info = prd; /* return last valid segment */ 1907 } 1908 1909 void 1910 ahci_unload_prdt(struct ahci_ccb *ccb) 1911 { 1912 struct ahci_port *ap = ccb->ccb_port; 1913 struct ahci_softc *sc = ap->ap_sc; 1914 struct ata_xfer *xa = &ccb->ccb_xa; 1915 bus_dmamap_t dmap = ccb->ccb_dmamap; 1916 1917 if (xa->datalen != 0) { 1918 if (xa->flags & ATA_F_READ) { 1919 bus_dmamap_sync(sc->sc_tag_data, dmap, 1920 BUS_DMASYNC_POSTREAD); 1921 } 1922 if (xa->flags & ATA_F_WRITE) { 1923 bus_dmamap_sync(sc->sc_tag_data, dmap, 1924 BUS_DMASYNC_POSTWRITE); 1925 } 1926 bus_dmamap_unload(sc->sc_tag_data, dmap); 1927 1928 /* 1929 * prdbc is only updated by hardware for non-NCQ commands. 1930 */ 1931 if (ccb->ccb_xa.flags & ATA_F_NCQ) { 1932 xa->resid = 0; 1933 } else { 1934 if (ccb->ccb_cmd_hdr->prdbc == 0 && 1935 ccb->ccb_xa.state == ATA_S_COMPLETE) { 1936 kprintf("%s: WARNING! Unload prdbc resid " 1937 "was zero! tag=%d\n", 1938 ATANAME(ap, xa->at), ccb->ccb_slot); 1939 } 1940 xa->resid = xa->datalen - 1941 le32toh(ccb->ccb_cmd_hdr->prdbc); 1942 } 1943 } 1944 } 1945 1946 /* 1947 * Start a command and poll for completion. 1948 * 1949 * timeout is in ms and only counts once the command gets on-chip. 1950 * 1951 * Returns ATA_S_* state, compare against ATA_S_COMPLETE to determine 1952 * that no error occured. 1953 * 1954 * NOTE: If the caller specifies a NULL timeout function the caller is 1955 * responsible for clearing hardware state on failure, but we will 1956 * deal with removing the ccb from any pending queue. 1957 * 1958 * NOTE: NCQ should never be used with this function. 1959 * 1960 * NOTE: If the port is in a failed state and stopped we do not try 1961 * to activate the ccb. 1962 */ 1963 int 1964 ahci_poll(struct ahci_ccb *ccb, int timeout, 1965 void (*timeout_fn)(struct ahci_ccb *)) 1966 { 1967 struct ahci_port *ap = ccb->ccb_port; 1968 1969 if (ccb->ccb_port->ap_state == AP_S_FATAL_ERROR) { 1970 ccb->ccb_xa.state = ATA_S_ERROR; 1971 return(ccb->ccb_xa.state); 1972 } 1973 crit_enter(); 1974 #if 0 1975 kprintf("%s: Start command %02x tag=%d\n", 1976 ATANAME(ccb->ccb_port, ccb->ccb_xa.at), 1977 ccb->ccb_xa.fis->command, ccb->ccb_slot); 1978 #endif 1979 ahci_start(ccb); 1980 1981 do { 1982 ahci_port_intr(ap, 1); 1983 switch(ccb->ccb_xa.state) { 1984 case ATA_S_ONCHIP: 1985 timeout -= ahci_os_softsleep(); 1986 break; 1987 case ATA_S_PENDING: 1988 ahci_os_softsleep(); 1989 ahci_check_active_timeouts(ap); 1990 break; 1991 default: 1992 crit_exit(); 1993 return (ccb->ccb_xa.state); 1994 } 1995 } while (timeout > 0); 1996 1997 if ((ccb->ccb_xa.flags & ATA_F_SILENT) == 0) { 1998 kprintf("%s: Poll timeout slot %d CMD: %b TFD: 0x%b SERR: %b\n", 1999 ATANAME(ap, ccb->ccb_xa.at), ccb->ccb_slot, 2000 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD, 2001 ahci_pread(ap, AHCI_PREG_TFD), AHCI_PFMT_TFD_STS, 2002 ahci_pread(ap, AHCI_PREG_SERR), AHCI_PFMT_SERR); 2003 } 2004 2005 timeout_fn(ccb); 2006 2007 crit_exit(); 2008 2009 return(ccb->ccb_xa.state); 2010 } 2011 2012 /* 2013 * When polling we have to check if the currently active CCB(s) 2014 * have timed out as the callout will be deadlocked while we 2015 * hold the port lock. 2016 */ 2017 void 2018 ahci_check_active_timeouts(struct ahci_port *ap) 2019 { 2020 struct ahci_ccb *ccb; 2021 u_int32_t mask; 2022 int tag; 2023 2024 mask = ap->ap_active | ap->ap_sactive; 2025 while (mask) { 2026 tag = ffs(mask) - 1; 2027 mask &= ~(1 << tag); 2028 ccb = &ap->ap_ccbs[tag]; 2029 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_EXPIRED) { 2030 ahci_ata_cmd_timeout(ccb); 2031 } 2032 } 2033 } 2034 2035 static 2036 __inline 2037 void 2038 ahci_start_timeout(struct ahci_ccb *ccb) 2039 { 2040 if (ccb->ccb_xa.flags & ATA_F_TIMEOUT_DESIRED) { 2041 ccb->ccb_xa.flags |= ATA_F_TIMEOUT_RUNNING; 2042 callout_reset(&ccb->ccb_timeout, 2043 (ccb->ccb_xa.timeout * hz + 999) / 1000, 2044 ahci_ata_cmd_timeout_unserialized, ccb); 2045 } 2046 } 2047 2048 void 2049 ahci_start(struct ahci_ccb *ccb) 2050 { 2051 struct ahci_port *ap = ccb->ccb_port; 2052 struct ahci_softc *sc = ap->ap_sc; 2053 2054 KKASSERT(ccb->ccb_xa.state == ATA_S_PENDING); 2055 2056 /* Zero transferred byte count before transfer */ 2057 ccb->ccb_cmd_hdr->prdbc = 0; 2058 2059 /* Sync command list entry and corresponding command table entry */ 2060 bus_dmamap_sync(sc->sc_tag_cmdh, 2061 AHCI_DMA_MAP(ap->ap_dmamem_cmd_list), 2062 BUS_DMASYNC_PREWRITE); 2063 bus_dmamap_sync(sc->sc_tag_cmdt, 2064 AHCI_DMA_MAP(ap->ap_dmamem_cmd_table), 2065 BUS_DMASYNC_PREWRITE); 2066 2067 /* Prepare RFIS area for write by controller */ 2068 bus_dmamap_sync(sc->sc_tag_rfis, 2069 AHCI_DMA_MAP(ap->ap_dmamem_rfis), 2070 BUS_DMASYNC_PREREAD); 2071 2072 /* 2073 * There's no point trying to optimize this, it only shaves a few 2074 * nanoseconds so just queue the command and call our generic issue. 2075 */ 2076 ahci_issue_pending_commands(ap, ccb); 2077 } 2078 2079 /* 2080 * While holding the port lock acquire exclusive access to the port. 2081 * 2082 * This is used when running the state machine to initialize and identify 2083 * targets over a port multiplier. Setting exclusive access prevents 2084 * ahci_port_intr() from activating any requests sitting on the pending 2085 * queue. 2086 */ 2087 void 2088 ahci_beg_exclusive_access(struct ahci_port *ap, struct ata_port *at) 2089 { 2090 KKASSERT((ap->ap_flags & AP_F_EXCLUSIVE_ACCESS) == 0); 2091 ap->ap_flags |= AP_F_EXCLUSIVE_ACCESS; 2092 while (ap->ap_active || ap->ap_sactive) { 2093 ahci_port_intr(ap, 1); 2094 ahci_os_softsleep(); 2095 } 2096 } 2097 2098 void 2099 ahci_end_exclusive_access(struct ahci_port *ap, struct ata_port *at) 2100 { 2101 KKASSERT((ap->ap_flags & AP_F_EXCLUSIVE_ACCESS) != 0); 2102 ap->ap_flags &= ~AP_F_EXCLUSIVE_ACCESS; 2103 ahci_issue_pending_commands(ap, NULL); 2104 } 2105 2106 #if 0 2107 2108 static void 2109 fubar(struct ahci_ccb *ccb) 2110 { 2111 struct ahci_port *ap = ccb->ccb_port; 2112 struct ahci_cmd_hdr *cmd; 2113 struct ahci_cmd_table *tab; 2114 struct ahci_prdt *prdt; 2115 int i; 2116 2117 kprintf("%s: ISSUE %02x\n", 2118 ATANAME(ap, ccb->ccb_xa.at), 2119 ccb->ccb_xa.fis->command); 2120 cmd = ccb->ccb_cmd_hdr; 2121 tab = ccb->ccb_cmd_table; 2122 prdt = ccb->ccb_cmd_table->prdt; 2123 kprintf("cmd flags=%04x prdtl=%d prdbc=%d ctba=%08x%08x\n", 2124 cmd->flags, cmd->prdtl, cmd->prdbc, 2125 cmd->ctba_hi, cmd->ctba_lo); 2126 for (i = 0; i < cmd->prdtl; ++i) { 2127 kprintf("\t%d dba=%08x%08x res=%08x flags=%08x\n", 2128 i, prdt->dba_hi, prdt->dba_lo, prdt->reserved, 2129 prdt->flags); 2130 } 2131 kprintf("tab\n"); 2132 } 2133 2134 #endif 2135 2136 /* 2137 * If ccb is not NULL enqueue and/or issue it. 2138 * 2139 * If ccb is NULL issue whatever we can from the queue. However, nothing 2140 * new is issued if the exclusive access flag is set or expired ccb's are 2141 * present. 2142 * 2143 * If existing commands are still active (ap_active/ap_sactive) we can only 2144 * issue matching new commands. 2145 */ 2146 void 2147 ahci_issue_pending_commands(struct ahci_port *ap, struct ahci_ccb *ccb) 2148 { 2149 u_int32_t mask; 2150 int limit; 2151 2152 /* 2153 * Enqueue the ccb. 2154 * 2155 * If just running the queue and in exclusive access mode we 2156 * just return. Also in this case if there are any expired ccb's 2157 * we want to clear the queue so the port can be safely stopped. 2158 */ 2159 if (ccb) { 2160 TAILQ_INSERT_TAIL(&ap->ap_ccb_pending, ccb, ccb_entry); 2161 } else if ((ap->ap_flags & AP_F_EXCLUSIVE_ACCESS) || ap->ap_expired) { 2162 return; 2163 } 2164 2165 /* 2166 * Pull the next ccb off the queue and run it if possible. 2167 */ 2168 if ((ccb = TAILQ_FIRST(&ap->ap_ccb_pending)) == NULL) 2169 return; 2170 2171 /* 2172 * Handle exclusivity requirements. 2173 * 2174 * ATA_F_EXCLUSIVE is used when we want to be the only command 2175 * running. 2176 * 2177 * ATA_F_AUTOSENSE is used when we want the D2H rfis loaded 2178 * back into the ccb on a normal (non-errored) command completion. 2179 * For example, for PM requests to target 15. Because the AHCI 2180 * spec does not stop the command processor and has only one rfis 2181 * area (for non-FBSS anyway), AUTOSENSE currently implies EXCLUSIVE. 2182 * Otherwise multiple completions can destroy the rfis data before 2183 * we have a chance to copy it. 2184 */ 2185 if (ap->ap_active & ~ap->ap_expired) { 2186 /* 2187 * There may be multiple ccb's already running, 2188 * if any are running and ap_run_flags sets 2189 * one of these flags then we know only one is 2190 * running. 2191 * 2192 * XXX Current AUTOSENSE code forces exclusivity 2193 * to simplify the code. 2194 */ 2195 if (ap->ap_run_flags & 2196 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) { 2197 return; 2198 } 2199 2200 if (ccb->ccb_xa.flags & 2201 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) { 2202 return; 2203 } 2204 } 2205 2206 if (ccb->ccb_xa.flags & ATA_F_NCQ) { 2207 /* 2208 * The next command is a NCQ command and can be issued as 2209 * long as currently active commands are not standard. 2210 */ 2211 if (ap->ap_active) { 2212 KKASSERT(ap->ap_active_cnt > 0); 2213 return; 2214 } 2215 KKASSERT(ap->ap_active_cnt == 0); 2216 2217 mask = 0; 2218 do { 2219 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry); 2220 mask |= 1 << ccb->ccb_slot; 2221 ccb->ccb_xa.state = ATA_S_ONCHIP; 2222 ahci_start_timeout(ccb); 2223 ap->ap_run_flags = ccb->ccb_xa.flags; 2224 ccb = TAILQ_FIRST(&ap->ap_ccb_pending); 2225 } while (ccb && (ccb->ccb_xa.flags & ATA_F_NCQ) && 2226 (ap->ap_run_flags & 2227 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) == 0); 2228 2229 ap->ap_sactive |= mask; 2230 ahci_pwrite(ap, AHCI_PREG_SACT, mask); 2231 ahci_pwrite(ap, AHCI_PREG_CI, mask); 2232 } else { 2233 /* 2234 * The next command is a standard command and can be issued 2235 * as long as currently active commands are not NCQ. 2236 * 2237 * We limit ourself to 1 command if we have a port multiplier, 2238 * (at least without FBSS support), otherwise timeouts on 2239 * one port can race completions on other ports (see 2240 * ahci_ata_cmd_timeout() for more information). 2241 * 2242 * If not on a port multiplier generally allow up to 4 2243 * standard commands to be enqueued. Remember that the 2244 * command processor will still process them sequentially. 2245 */ 2246 if (ap->ap_sactive) 2247 return; 2248 if (ap->ap_type == ATA_PORT_T_PM) 2249 limit = 1; 2250 else if (ap->ap_sc->sc_ncmds > 4) 2251 limit = 4; 2252 else 2253 limit = 2; 2254 2255 while (ap->ap_active_cnt < limit && ccb && 2256 (ccb->ccb_xa.flags & ATA_F_NCQ) == 0) { 2257 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry); 2258 #if 0 2259 fubar(ccb); 2260 #endif 2261 ap->ap_active |= 1 << ccb->ccb_slot; 2262 ap->ap_active_cnt++; 2263 ap->ap_run_flags = ccb->ccb_xa.flags; 2264 ccb->ccb_xa.state = ATA_S_ONCHIP; 2265 ahci_pwrite(ap, AHCI_PREG_CI, 1 << ccb->ccb_slot); 2266 ahci_start_timeout(ccb); 2267 if ((ap->ap_run_flags & 2268 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE)) == 0) { 2269 break; 2270 } 2271 ccb = TAILQ_FIRST(&ap->ap_ccb_pending); 2272 if (ccb && (ccb->ccb_xa.flags & 2273 (ATA_F_EXCLUSIVE | ATA_F_AUTOSENSE))) { 2274 break; 2275 } 2276 } 2277 } 2278 } 2279 2280 void 2281 ahci_intr(void *arg) 2282 { 2283 struct ahci_softc *sc = arg; 2284 struct ahci_port *ap; 2285 u_int32_t is; 2286 u_int32_t ack; 2287 int port; 2288 2289 /* 2290 * Check if the master enable is up, and whether any interrupts are 2291 * pending. 2292 */ 2293 if ((sc->sc_flags & AHCI_F_INT_GOOD) == 0) 2294 return; 2295 is = ahci_read(sc, AHCI_REG_IS); 2296 if (is == 0 || is == 0xffffffff) { 2297 return; 2298 } 2299 is &= sc->sc_portmask; 2300 2301 #ifdef AHCI_COALESCE 2302 /* Check coalescing interrupt first */ 2303 if (is & sc->sc_ccc_mask) { 2304 DPRINTF(AHCI_D_INTR, "%s: command coalescing interrupt\n", 2305 DEVNAME(sc)); 2306 is &= ~sc->sc_ccc_mask; 2307 is |= sc->sc_ccc_ports_cur; 2308 } 2309 #endif 2310 2311 /* 2312 * Process interrupts for each port in a non-blocking fashion. 2313 * 2314 * The global IS bit is forced on if any unmasked port interrupts 2315 * are pending, even if we clear. 2316 */ 2317 for (ack = 0; is; is &= ~(1 << port)) { 2318 port = ffs(is) - 1; 2319 ack |= 1 << port; 2320 2321 ap = sc->sc_ports[port]; 2322 if (ap == NULL) 2323 continue; 2324 2325 if (ahci_os_lock_port_nb(ap) == 0) { 2326 ahci_port_intr(ap, 0); 2327 ahci_os_unlock_port(ap); 2328 } else { 2329 ahci_pwrite(ap, AHCI_PREG_IE, 0); 2330 ahci_os_signal_port_thread(ap, AP_SIGF_PORTINT); 2331 } 2332 } 2333 ahci_write(sc, AHCI_REG_IS, ack); 2334 } 2335 2336 /* 2337 * Core called from helper thread. 2338 */ 2339 void 2340 ahci_port_thread_core(struct ahci_port *ap, int mask) 2341 { 2342 /* 2343 * Process any expired timedouts. 2344 */ 2345 ahci_os_lock_port(ap); 2346 if (mask & AP_SIGF_TIMEOUT) { 2347 ahci_check_active_timeouts(ap); 2348 } 2349 2350 /* 2351 * Process port interrupts which require a higher level of 2352 * intervention. 2353 */ 2354 if (mask & AP_SIGF_PORTINT) { 2355 ahci_port_intr(ap, 1); 2356 ahci_port_interrupt_enable(ap); 2357 ahci_os_unlock_port(ap); 2358 } else if (ap->ap_probe != ATA_PROBE_FAILED) { 2359 ahci_port_intr(ap, 1); 2360 ahci_port_interrupt_enable(ap); 2361 ahci_os_unlock_port(ap); 2362 } else { 2363 ahci_os_unlock_port(ap); 2364 } 2365 } 2366 2367 /* 2368 * Core per-port interrupt handler. 2369 * 2370 * If blockable is 0 we cannot call ahci_os_sleep() at all and we can only 2371 * deal with normal command completions which do not require blocking. 2372 */ 2373 void 2374 ahci_port_intr(struct ahci_port *ap, int blockable) 2375 { 2376 struct ahci_softc *sc = ap->ap_sc; 2377 u_int32_t is, ci_saved, ci_masked; 2378 int slot; 2379 int stopped = 0; 2380 struct ahci_ccb *ccb = NULL; 2381 struct ata_port *ccb_at = NULL; 2382 volatile u_int32_t *active; 2383 const u_int32_t blockable_mask = AHCI_PREG_IS_TFES | 2384 AHCI_PREG_IS_IFS | 2385 AHCI_PREG_IS_PCS | 2386 AHCI_PREG_IS_PRCS | 2387 AHCI_PREG_IS_HBFS | 2388 AHCI_PREG_IS_OFS | 2389 AHCI_PREG_IS_UFS; 2390 2391 enum { NEED_NOTHING, NEED_REINIT, NEED_RESTART, 2392 NEED_HOTPLUG_INSERT, NEED_HOTPLUG_REMOVE } need = NEED_NOTHING; 2393 2394 /* 2395 * All basic command completions are always processed. 2396 */ 2397 is = ahci_pread(ap, AHCI_PREG_IS); 2398 if (is & AHCI_PREG_IS_DPS) 2399 ahci_pwrite(ap, AHCI_PREG_IS, is & AHCI_PREG_IS_DPS); 2400 2401 /* 2402 * If we can't block then we can't handle these here. Disable 2403 * the interrupts in question so we don't live-lock, the helper 2404 * thread will re-enable them. 2405 * 2406 * If the port is in a completely failed state we do not want 2407 * to drop through to failed-command-processing if blockable is 0, 2408 * just let the thread deal with it all. 2409 * 2410 * Otherwise we fall through and still handle DHRS and any commands 2411 * which completed normally. Even if we are errored we haven't 2412 * stopped the port yet so CI/SACT are still good. 2413 */ 2414 if (blockable == 0) { 2415 if (ap->ap_state == AP_S_FATAL_ERROR) { 2416 ahci_pwrite(ap, AHCI_PREG_IE, 0); 2417 ahci_os_signal_port_thread(ap, AP_SIGF_PORTINT); 2418 return; 2419 } 2420 if (is & blockable_mask) { 2421 ahci_pwrite(ap, AHCI_PREG_IE, 0); 2422 ahci_os_signal_port_thread(ap, AP_SIGF_PORTINT); 2423 return; 2424 } 2425 } 2426 2427 /* 2428 * Either NCQ or non-NCQ commands will be active, never both. 2429 */ 2430 if (ap->ap_sactive) { 2431 KKASSERT(ap->ap_active == 0); 2432 KKASSERT(ap->ap_active_cnt == 0); 2433 ci_saved = ahci_pread(ap, AHCI_PREG_SACT); 2434 active = &ap->ap_sactive; 2435 } else { 2436 ci_saved = ahci_pread(ap, AHCI_PREG_CI); 2437 active = &ap->ap_active; 2438 } 2439 KKASSERT(!(ap->ap_sactive && ap->ap_active)); 2440 #if 0 2441 kprintf("CHECK act=%08x/%08x sact=%08x/%08x\n", 2442 ap->ap_active, ahci_pread(ap, AHCI_PREG_CI), 2443 ap->ap_sactive, ahci_pread(ap, AHCI_PREG_SACT)); 2444 #endif 2445 2446 /* 2447 * Ignore AHCI_PREG_IS_PRCS when link power management is on 2448 */ 2449 if (ap->link_pwr_mgmt != AHCI_LINK_PWR_MGMT_NONE) { 2450 is &= ~AHCI_PREG_IS_PRCS; 2451 ahci_pwrite(ap, AHCI_PREG_SERR, 2452 AHCI_PREG_SERR_DIAG_N | AHCI_PREG_SERR_DIAG_W); 2453 } 2454 2455 /* 2456 * Command failed (blockable). 2457 * 2458 * See AHCI 1.1 spec 6.2.2.1 and 6.2.2.2. 2459 * 2460 * This stops command processing. 2461 */ 2462 if (is & AHCI_PREG_IS_TFES) { 2463 u_int32_t tfd, serr; 2464 int err_slot; 2465 2466 process_error: 2467 tfd = ahci_pread(ap, AHCI_PREG_TFD); 2468 serr = ahci_pread(ap, AHCI_PREG_SERR); 2469 2470 /* 2471 * Load the error slot and restart command processing. 2472 * CLO if we need to. The error slot may not be valid. 2473 * MUST BE DONE BEFORE CLEARING ST! 2474 * 2475 * Cycle ST. 2476 * 2477 * It is unclear but we may have to clear SERR to reenable 2478 * error processing. 2479 */ 2480 err_slot = AHCI_PREG_CMD_CCS(ahci_pread(ap, AHCI_PREG_CMD)); 2481 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_TFES | 2482 AHCI_PREG_IS_PSS | 2483 AHCI_PREG_IS_DHRS | 2484 AHCI_PREG_IS_SDBS); 2485 is &= ~(AHCI_PREG_IS_TFES | AHCI_PREG_IS_PSS | 2486 AHCI_PREG_IS_DHRS | AHCI_PREG_IS_SDBS); 2487 ahci_pwrite(ap, AHCI_PREG_SERR, serr); 2488 ahci_port_stop(ap, 0); 2489 ahci_os_hardsleep(10); 2490 if (tfd & (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 2491 kprintf("%s: Issuing CLO\n", PORTNAME(ap)); 2492 ahci_port_clo(ap); 2493 } 2494 2495 /* 2496 * We are now stopped and need a restart. If we have to 2497 * process a NCQ error we will temporarily start and then 2498 * stop the port again, so this condition holds. 2499 */ 2500 stopped = 1; 2501 need = NEED_RESTART; 2502 2503 /* 2504 * ATAPI errors are fairly common from probing, just 2505 * report disk errors or if bootverbose is on. 2506 */ 2507 if (bootverbose || ap->ap_type != ATA_PORT_T_ATAPI) { 2508 kprintf("%s: TFES slot %d ci_saved = %08x\n", 2509 PORTNAME(ap), err_slot, ci_saved); 2510 } 2511 2512 /* 2513 * If we got an error on an error CCB just complete it 2514 * with an error. ci_saved has the mask to restart 2515 * (the err_ccb will be removed from it by finish_error). 2516 */ 2517 if (ap->ap_flags & AP_F_ERR_CCB_RESERVED) { 2518 err_slot = ap->ap_err_ccb->ccb_slot; 2519 goto finish_error; 2520 } 2521 2522 /* 2523 * If NCQ commands were active get the error slot from 2524 * the log page. NCQ is not supported for PM's so this 2525 * is a direct-attached target. 2526 * 2527 * Otherwise if no commands were active we have a problem. 2528 * 2529 * Otherwise if the error slot is bad we have a problem. 2530 * 2531 * Otherwise process the error for the slot. 2532 */ 2533 if (ap->ap_sactive) { 2534 ahci_port_start(ap); 2535 err_slot = ahci_port_read_ncq_error(ap, 0); 2536 ahci_port_stop(ap, 0); 2537 } else if (ap->ap_active == 0) { 2538 kprintf("%s: TFES with no commands pending\n", 2539 PORTNAME(ap)); 2540 err_slot = -1; 2541 } else if (err_slot < 0 || err_slot >= ap->ap_sc->sc_ncmds) { 2542 kprintf("%s: bad error slot %d\n", 2543 PORTNAME(ap), err_slot); 2544 err_slot = -1; 2545 } else { 2546 ccb = &ap->ap_ccbs[err_slot]; 2547 2548 /* 2549 * Validate the errored ccb. Note that ccb_at can 2550 * be NULL for direct-attached ccb's. 2551 * 2552 * Copy received taskfile data from the RFIS. 2553 */ 2554 if (ccb->ccb_xa.state == ATA_S_ONCHIP) { 2555 ccb_at = ccb->ccb_xa.at; 2556 memcpy(&ccb->ccb_xa.rfis, ap->ap_rfis->rfis, 2557 sizeof(struct ata_fis_d2h)); 2558 if (bootverbose) { 2559 kprintf("%s: Copying rfis slot %d\n", 2560 ATANAME(ap, ccb_at), err_slot); 2561 } 2562 } else { 2563 kprintf("%s: Cannot copy rfis, CCB slot " 2564 "%d is not on-chip (state=%d)\n", 2565 ATANAME(ap, ccb->ccb_xa.at), 2566 err_slot, ccb->ccb_xa.state); 2567 err_slot = -1; 2568 } 2569 } 2570 2571 /* 2572 * If we could not determine the errored slot then 2573 * reset the port. 2574 */ 2575 if (err_slot < 0) { 2576 kprintf("%s: TFES: Unable to determine errored slot\n", 2577 PORTNAME(ap)); 2578 if (ap->ap_flags & AP_F_IN_RESET) 2579 goto fatal; 2580 goto failall; 2581 } 2582 2583 /* 2584 * Finish error on slot. We will restart ci_saved 2585 * commands except the errored slot which we generate 2586 * a failure for. 2587 */ 2588 finish_error: 2589 ccb = &ap->ap_ccbs[err_slot]; 2590 ci_saved &= ~(1 << err_slot); 2591 KKASSERT(ccb->ccb_xa.state == ATA_S_ONCHIP); 2592 ccb->ccb_xa.state = ATA_S_ERROR; 2593 } else if (is & AHCI_PREG_IS_DHRS) { 2594 /* 2595 * Command posted D2H register FIS to the rfis (non-blocking). 2596 * 2597 * A normal completion with an error may set DHRS instead 2598 * of TFES. The CCS bits are only valid if ERR was set. 2599 * If ERR is set command processing was probably stopped. 2600 * 2601 * If ERR was not set we can only copy-back data for 2602 * exclusive-mode commands because otherwise we won't know 2603 * which tag the rfis belonged to. 2604 * 2605 * err_slot must be read from the CCS before any other port 2606 * action, such as stopping the port. 2607 * 2608 * WARNING! This is not well documented in the AHCI spec. 2609 * It can be found in the state machine tables 2610 * but not in the explanations. 2611 */ 2612 u_int32_t tfd; 2613 u_int32_t cmd; 2614 int err_slot; 2615 2616 tfd = ahci_pread(ap, AHCI_PREG_TFD); 2617 cmd = ahci_pread(ap, AHCI_PREG_CMD); 2618 2619 if ((tfd & AHCI_PREG_TFD_STS_ERR) && 2620 (cmd & AHCI_PREG_CMD_CR) == 0) { 2621 err_slot = AHCI_PREG_CMD_CCS( 2622 ahci_pread(ap, AHCI_PREG_CMD)); 2623 ccb = &ap->ap_ccbs[err_slot]; 2624 kprintf("%s: DHRS tfd=%b err_slot=%d cmd=%02x\n", 2625 PORTNAME(ap), 2626 tfd, AHCI_PFMT_TFD_STS, 2627 err_slot, ccb->ccb_xa.fis->command); 2628 goto process_error; 2629 } 2630 /* 2631 * NO ELSE... copy back is in the normal command completion 2632 * code and only if no error occured and ATA_F_AUTOSENSE 2633 * was set. 2634 */ 2635 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_DHRS); 2636 } 2637 2638 /* 2639 * Device notification to us (non-blocking) 2640 * 2641 * NOTE! On some parts notification bits can cause an IPMS 2642 * interrupt instead of a SDBS interrupt. 2643 * 2644 * NOTE! On some parts (e.g. VBOX, probably intel ICHx), 2645 * SDBS notifies us of the completion of a NCQ command 2646 * and DBS does not. 2647 */ 2648 if (is & (AHCI_PREG_IS_SDBS | AHCI_PREG_IS_IPMS)) { 2649 u_int32_t data; 2650 2651 ahci_pwrite(ap, AHCI_PREG_IS, 2652 AHCI_PREG_IS_SDBS | AHCI_PREG_IS_IPMS); 2653 if (sc->sc_cap & AHCI_REG_CAP_SSNTF) { 2654 data = ahci_pread(ap, AHCI_PREG_SNTF); 2655 if (data) { 2656 ahci_pwrite(ap, AHCI_PREG_IS, 2657 AHCI_PREG_IS_SDBS); 2658 kprintf("%s: NOTIFY %08x\n", 2659 PORTNAME(ap), data); 2660 ahci_pwrite(ap, AHCI_PREG_SERR, 2661 AHCI_PREG_SERR_DIAG_N); 2662 ahci_pwrite(ap, AHCI_PREG_SNTF, data); 2663 ahci_cam_changed(ap, NULL, -1); 2664 } 2665 } 2666 is &= ~(AHCI_PREG_IS_SDBS | AHCI_PREG_IS_IPMS); 2667 } 2668 2669 /* 2670 * Spurious IFS errors (blockable) - when AP_F_IGNORE_IFS is set. 2671 * 2672 * Spurious IFS errors can occur while we are doing a reset 2673 * sequence through a PM, probably due to an unexpected FIS 2674 * being received during the PM target reset sequence. Chipsets 2675 * are supposed to mask these events but some do not. 2676 * 2677 * Try to recover from the condition. 2678 */ 2679 if ((is & AHCI_PREG_IS_IFS) && (ap->ap_flags & AP_F_IGNORE_IFS)) { 2680 u_int32_t serr = ahci_pread(ap, AHCI_PREG_SERR); 2681 if ((ap->ap_flags & AP_F_IFS_IGNORED) == 0) { 2682 kprintf("%s: IFS during PM probe (ignored) " 2683 "IS=%b, SERR=%b\n", 2684 PORTNAME(ap), 2685 is, AHCI_PFMT_IS, 2686 serr, AHCI_PFMT_SERR); 2687 ap->ap_flags |= AP_F_IFS_IGNORED; 2688 } 2689 2690 /* 2691 * Try to clear the error condition. The IFS error killed 2692 * the port so stop it so we can restart it. 2693 */ 2694 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 2695 ahci_pwrite(ap, AHCI_PREG_IS, AHCI_PREG_IS_IFS); 2696 is &= ~AHCI_PREG_IS_IFS; 2697 need = NEED_RESTART; 2698 goto failall; 2699 } 2700 2701 /* 2702 * Port change (hot-plug) (blockable). 2703 * 2704 * A PRCS interrupt can occur: 2705 * (1) On hot-unplug / normal-unplug (phy lost) 2706 * (2) Sometimes on hot-plug too. 2707 * 2708 * A PCS interrupt can occur in a number of situations: 2709 * (1) On hot-plug once communication is established 2710 * (2) On hot-unplug sometimes. 2711 * (3) For chipsets with badly written firmware it can occur 2712 * during INIT/RESET sequences due to the device reset. 2713 * (4) For chipsets with badly written firmware it can occur 2714 * when it thinks an unsolicited COMRESET is received 2715 * during a INIT/RESET sequence, even though we actually 2716 * did request it. 2717 * 2718 * XXX We can then check the CPS (Cold Presence State) bit, if 2719 * supported, to determine if a device is plugged in or not and do 2720 * the right thing. 2721 * 2722 * PCS interrupts are cleared by clearing DIAG_X. If this occurs 2723 * command processing is automatically stopped (CR goes inactive) 2724 * and the port must be stopped and restarted. 2725 * 2726 * WARNING: AMD parts (e.g. 880G chipset, probably others) can 2727 * generate PCS on initialization even when device is 2728 * already connected up. It is unclear why this happens. 2729 * Depending on the state of the device detect this can 2730 * cause us to go into harsh reinit or hot-plug insertion 2731 * mode. 2732 * 2733 * WARNING: PCS errors can be repetitive (e.g. unsolicited COMRESET 2734 * continues to flow in from the device), we must clear the 2735 * interrupt in all cases and enforce a delay to prevent 2736 * a livelock and give the port time to settle down. 2737 * Only print something if we aren't in INIT/HARD-RESET. 2738 */ 2739 if (is & (AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS)) { 2740 /* 2741 * Try to clear the error. Because of the repetitiveness 2742 * of this interrupt avoid any harsh action if the port is 2743 * already in the init or hard-reset probe state. 2744 */ 2745 ahci_pwrite(ap, AHCI_PREG_SERR, -1); 2746 /* (AHCI_PREG_SERR_DIAG_N | AHCI_PREG_SERR_DIAG_X) */ 2747 ahci_pwrite(ap, AHCI_PREG_IS, 2748 is & (AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS)); 2749 2750 /* 2751 * Ignore PCS/PRCS errors during probes (but still clear the 2752 * interrupt to avoid a livelock). The AMD 880/890/SB850 2753 * chipsets do not mask PCS/PRCS internally during reset 2754 * sequences. 2755 */ 2756 if (ap->ap_flags & AP_F_IN_RESET) 2757 goto skip_pcs; 2758 2759 if (ap->ap_probe == ATA_PROBE_NEED_INIT || 2760 ap->ap_probe == ATA_PROBE_NEED_HARD_RESET) { 2761 is &= ~(AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS); 2762 need = NEED_NOTHING; 2763 ahci_os_sleep(1000); 2764 goto failall; 2765 } 2766 kprintf("%s: Transient Errors: %b (%d)\n", 2767 PORTNAME(ap), is, AHCI_PFMT_IS, ap->ap_probe); 2768 is &= ~(AHCI_PREG_IS_PCS | AHCI_PREG_IS_PRCS); 2769 ahci_os_sleep(200); 2770 2771 /* 2772 * Stop the port and figure out what to do next. 2773 */ 2774 ahci_port_stop(ap, 0); 2775 stopped = 1; 2776 2777 switch (ahci_pread(ap, AHCI_PREG_SSTS) & AHCI_PREG_SSTS_DET) { 2778 case AHCI_PREG_SSTS_DET_DEV: 2779 /* 2780 * Device detect 2781 */ 2782 if (ap->ap_probe == ATA_PROBE_FAILED) { 2783 need = NEED_HOTPLUG_INSERT; 2784 goto fatal; 2785 } 2786 need = NEED_RESTART; 2787 break; 2788 case AHCI_PREG_SSTS_DET_DEV_NE: 2789 /* 2790 * Device not communicating. AMD parts seem to 2791 * like to throw this error on initialization 2792 * for no reason that I can fathom. 2793 */ 2794 kprintf("%s: Device present but not communicating, " 2795 "attempting port restart\n", 2796 PORTNAME(ap)); 2797 need = NEED_REINIT; 2798 goto fatal; 2799 default: 2800 if (ap->ap_probe != ATA_PROBE_FAILED) { 2801 need = NEED_HOTPLUG_REMOVE; 2802 goto fatal; 2803 } 2804 need = NEED_RESTART; 2805 break; 2806 } 2807 skip_pcs: 2808 ; 2809 } 2810 2811 /* 2812 * Check for remaining errors - they are fatal. (blockable) 2813 */ 2814 if (is & (AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS | AHCI_PREG_IS_IFS | 2815 AHCI_PREG_IS_OFS | AHCI_PREG_IS_UFS)) { 2816 u_int32_t serr; 2817 2818 ahci_pwrite(ap, AHCI_PREG_IS, 2819 is & (AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS | 2820 AHCI_PREG_IS_IFS | AHCI_PREG_IS_OFS | 2821 AHCI_PREG_IS_UFS)); 2822 serr = ahci_pread(ap, AHCI_PREG_SERR); 2823 kprintf("%s: Unrecoverable errors (IS: %b, SERR: %b), " 2824 "disabling port.\n", 2825 PORTNAME(ap), 2826 is, AHCI_PFMT_IS, 2827 serr, AHCI_PFMT_SERR 2828 ); 2829 is &= ~(AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS | 2830 AHCI_PREG_IS_IFS | AHCI_PREG_IS_OFS | 2831 AHCI_PREG_IS_UFS); 2832 2833 /* 2834 * Fail all commands but then what? For now try to 2835 * reinitialize the port. 2836 */ 2837 need = NEED_REINIT; 2838 goto fatal; 2839 } 2840 2841 /* 2842 * Fail all outstanding commands if we know the port won't recover. 2843 * 2844 * We may have a ccb_at if the failed command is known and was 2845 * being sent to a device over a port multiplier (PM). In this 2846 * case if the port itself has not completely failed we fail just 2847 * the commands related to that target. 2848 * 2849 * ci_saved contains the mask of active commands as of when the 2850 * error occured, prior to any port stops. 2851 */ 2852 if (ap->ap_state == AP_S_FATAL_ERROR) { 2853 fatal: 2854 ap->ap_state = AP_S_FATAL_ERROR; 2855 failall: 2856 ahci_port_stop(ap, 0); 2857 stopped = 1; 2858 2859 /* 2860 * Error all the active slots not already errored. 2861 */ 2862 ci_masked = ci_saved & *active & ~ap->ap_expired; 2863 if (ci_masked) { 2864 kprintf("%s: Failing all commands: %08x\n", 2865 PORTNAME(ap), ci_masked); 2866 } 2867 2868 while (ci_masked) { 2869 slot = ffs(ci_masked) - 1; 2870 ccb = &ap->ap_ccbs[slot]; 2871 ccb->ccb_xa.state = ATA_S_TIMEOUT; 2872 ap->ap_expired |= 1 << slot; 2873 ci_saved &= ~(1 << slot); 2874 ci_masked &= ~(1 << slot); 2875 } 2876 2877 /* 2878 * Clear bits in ci_saved (cause completions to be run) 2879 * for all slots which are not active. 2880 */ 2881 ci_saved &= ~*active; 2882 2883 /* 2884 * Don't restart the port if our problems were deemed fatal. 2885 * 2886 * Also acknowlege all fatal interrupt sources to prevent 2887 * a livelock. 2888 */ 2889 if (ap->ap_state == AP_S_FATAL_ERROR) { 2890 if (need == NEED_RESTART) 2891 need = NEED_NOTHING; 2892 ahci_pwrite(ap, AHCI_PREG_IS, 2893 AHCI_PREG_IS_TFES | AHCI_PREG_IS_HBFS | 2894 AHCI_PREG_IS_IFS | AHCI_PREG_IS_OFS | 2895 AHCI_PREG_IS_UFS); 2896 } 2897 } 2898 2899 /* 2900 * If we are stopped the AHCI chipset is supposed to have cleared 2901 * CI and SACT. Did it? If it didn't we try very hard to clear 2902 * the fields otherwise we may end up completing CCBs which are 2903 * actually still active. 2904 * 2905 * IFS errors on (at least) AMD chipsets create this confusion. 2906 */ 2907 if (stopped) { 2908 u_int32_t mask; 2909 if ((mask = ahci_pactive(ap)) != 0) { 2910 kprintf("%s: chipset failed to clear " 2911 "active cmds %08x\n", 2912 PORTNAME(ap), mask); 2913 ahci_port_start(ap); 2914 ahci_port_stop(ap, 0); 2915 if ((mask = ahci_pactive(ap)) != 0) { 2916 kprintf("%s: unable to prod the chip into " 2917 "clearing active cmds %08x\n", 2918 PORTNAME(ap), mask); 2919 /* what do we do now? */ 2920 } 2921 } 2922 } 2923 2924 /* 2925 * CCB completion (non blocking). 2926 * 2927 * CCB completion is detected by noticing its slot's bit in CI has 2928 * changed to zero some time after we activated it. 2929 * If we are polling, we may only be interested in particular slot(s). 2930 * 2931 * Any active bits not saved are completed within the restrictions 2932 * imposed by the caller. 2933 */ 2934 ci_masked = ~ci_saved & *active; 2935 while (ci_masked) { 2936 slot = ffs(ci_masked) - 1; 2937 ccb = &ap->ap_ccbs[slot]; 2938 ci_masked &= ~(1 << slot); 2939 2940 DPRINTF(AHCI_D_INTR, "%s: slot %d is complete%s\n", 2941 PORTNAME(ap), slot, ccb->ccb_xa.state == ATA_S_ERROR ? 2942 " (error)" : ""); 2943 2944 bus_dmamap_sync(sc->sc_tag_cmdh, 2945 AHCI_DMA_MAP(ap->ap_dmamem_cmd_list), 2946 BUS_DMASYNC_POSTWRITE); 2947 2948 bus_dmamap_sync(sc->sc_tag_cmdt, 2949 AHCI_DMA_MAP(ap->ap_dmamem_cmd_table), 2950 BUS_DMASYNC_POSTWRITE); 2951 2952 bus_dmamap_sync(sc->sc_tag_rfis, 2953 AHCI_DMA_MAP(ap->ap_dmamem_rfis), 2954 BUS_DMASYNC_POSTREAD); 2955 2956 *active &= ~(1 << ccb->ccb_slot); 2957 if (active == &ap->ap_active) { 2958 KKASSERT(ap->ap_active_cnt > 0); 2959 --ap->ap_active_cnt; 2960 } 2961 2962 /* 2963 * Complete the ccb. If the ccb was marked expired it 2964 * was probably already removed from the command processor, 2965 * so don't take the clear ci_saved bit as meaning the 2966 * command actually succeeded, it didn't. 2967 */ 2968 if (ap->ap_expired & (1 << ccb->ccb_slot)) { 2969 ap->ap_expired &= ~(1 << ccb->ccb_slot); 2970 ccb->ccb_xa.state = ATA_S_TIMEOUT; 2971 ccb->ccb_done(ccb); 2972 ccb->ccb_xa.complete(&ccb->ccb_xa); 2973 } else { 2974 if (ccb->ccb_xa.state == ATA_S_ONCHIP) { 2975 ccb->ccb_xa.state = ATA_S_COMPLETE; 2976 if (ccb->ccb_xa.flags & ATA_F_AUTOSENSE) { 2977 memcpy(&ccb->ccb_xa.rfis, 2978 ap->ap_rfis->rfis, 2979 sizeof(struct ata_fis_d2h)); 2980 if (ccb->ccb_xa.state == ATA_S_TIMEOUT) 2981 ccb->ccb_xa.state = ATA_S_ERROR; 2982 } 2983 } 2984 ccb->ccb_done(ccb); 2985 } 2986 } 2987 2988 /* 2989 * Cleanup. Will not be set if non-blocking. 2990 */ 2991 switch(need) { 2992 case NEED_NOTHING: 2993 /* 2994 * If operating normally and not stopped the interrupt was 2995 * probably just a normal completion and we may be able to 2996 * issue more commands. 2997 */ 2998 if (stopped == 0 && ap->ap_state != AP_S_FATAL_ERROR) 2999 ahci_issue_pending_commands(ap, NULL); 3000 break; 3001 case NEED_RESTART: 3002 /* 3003 * A recoverable error occured and we can restart outstanding 3004 * commands on the port. 3005 */ 3006 ci_saved &= ~ap->ap_expired; 3007 if (ci_saved) { 3008 kprintf("%s: Restart %08x\n", PORTNAME(ap), ci_saved); 3009 ahci_issue_saved_commands(ap, ci_saved); 3010 } 3011 3012 /* 3013 * Potentially issue new commands if not in a failed 3014 * state. 3015 */ 3016 if (ap->ap_state != AP_S_FATAL_ERROR) { 3017 ahci_port_start(ap); 3018 ahci_issue_pending_commands(ap, NULL); 3019 } 3020 break; 3021 case NEED_REINIT: 3022 /* 3023 * Something horrible happened to the port and we 3024 * need to reinitialize it. 3025 */ 3026 kprintf("%s: REINIT - Attempting to reinitialize the port " 3027 "after it had a horrible accident\n", 3028 PORTNAME(ap)); 3029 ap->ap_flags |= AP_F_IN_RESET; 3030 ap->ap_flags |= AP_F_HARSH_REINIT; 3031 ap->ap_probe = ATA_PROBE_NEED_INIT; 3032 ahci_cam_changed(ap, NULL, -1); 3033 break; 3034 case NEED_HOTPLUG_INSERT: 3035 /* 3036 * A hot-plug insertion event has occured and all 3037 * outstanding commands have already been revoked. 3038 * 3039 * Don't recurse if this occurs while we are 3040 * resetting the port. 3041 */ 3042 if ((ap->ap_flags & AP_F_IN_RESET) == 0) { 3043 kprintf("%s: HOTPLUG - Device inserted\n", 3044 PORTNAME(ap)); 3045 ap->ap_probe = ATA_PROBE_NEED_INIT; 3046 ahci_cam_changed(ap, NULL, -1); 3047 } 3048 break; 3049 case NEED_HOTPLUG_REMOVE: 3050 /* 3051 * A hot-plug removal event has occured and all 3052 * outstanding commands have already been revoked. 3053 * 3054 * Don't recurse if this occurs while we are 3055 * resetting the port. 3056 */ 3057 if ((ap->ap_flags & AP_F_IN_RESET) == 0) { 3058 kprintf("%s: HOTPLUG - Device removed\n", 3059 PORTNAME(ap)); 3060 ahci_port_hardstop(ap); 3061 /* ap_probe set to failed */ 3062 ahci_cam_changed(ap, NULL, -1); 3063 } 3064 break; 3065 default: 3066 break; 3067 } 3068 } 3069 3070 struct ahci_ccb * 3071 ahci_get_ccb(struct ahci_port *ap) 3072 { 3073 struct ahci_ccb *ccb; 3074 3075 lockmgr(&ap->ap_ccb_lock, LK_EXCLUSIVE); 3076 ccb = TAILQ_FIRST(&ap->ap_ccb_free); 3077 if (ccb != NULL) { 3078 KKASSERT(ccb->ccb_xa.state == ATA_S_PUT); 3079 TAILQ_REMOVE(&ap->ap_ccb_free, ccb, ccb_entry); 3080 ccb->ccb_xa.state = ATA_S_SETUP; 3081 ccb->ccb_xa.flags = 0; 3082 ccb->ccb_xa.at = NULL; 3083 } 3084 lockmgr(&ap->ap_ccb_lock, LK_RELEASE); 3085 3086 return (ccb); 3087 } 3088 3089 void 3090 ahci_put_ccb(struct ahci_ccb *ccb) 3091 { 3092 struct ahci_port *ap = ccb->ccb_port; 3093 3094 lockmgr(&ap->ap_ccb_lock, LK_EXCLUSIVE); 3095 ccb->ccb_xa.state = ATA_S_PUT; 3096 TAILQ_INSERT_TAIL(&ap->ap_ccb_free, ccb, ccb_entry); 3097 lockmgr(&ap->ap_ccb_lock, LK_RELEASE); 3098 } 3099 3100 struct ahci_ccb * 3101 ahci_get_err_ccb(struct ahci_port *ap) 3102 { 3103 struct ahci_ccb *err_ccb; 3104 u_int32_t sact; 3105 u_int32_t ci; 3106 3107 /* No commands may be active on the chip. */ 3108 3109 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SNCQ) { 3110 sact = ahci_pread(ap, AHCI_PREG_SACT); 3111 if (sact != 0) { 3112 kprintf("%s: ahci_get_err_ccb but SACT %08x != 0?\n", 3113 PORTNAME(ap), sact); 3114 } 3115 } 3116 ci = ahci_pread(ap, AHCI_PREG_CI); 3117 if (ci) { 3118 kprintf("%s: ahci_get_err_ccb: ci not 0 (%08x)\n", 3119 ap->ap_name, ci); 3120 } 3121 KKASSERT(ci == 0); 3122 KKASSERT((ap->ap_flags & AP_F_ERR_CCB_RESERVED) == 0); 3123 ap->ap_flags |= AP_F_ERR_CCB_RESERVED; 3124 3125 /* Save outstanding command state. */ 3126 ap->ap_err_saved_active = ap->ap_active; 3127 ap->ap_err_saved_active_cnt = ap->ap_active_cnt; 3128 ap->ap_err_saved_sactive = ap->ap_sactive; 3129 3130 /* 3131 * Pretend we have no commands outstanding, so that completions won't 3132 * run prematurely. 3133 */ 3134 ap->ap_active = ap->ap_active_cnt = ap->ap_sactive = 0; 3135 3136 /* 3137 * Grab a CCB to use for error recovery. This should never fail, as 3138 * we ask atascsi to reserve one for us at init time. 3139 */ 3140 err_ccb = ap->ap_err_ccb; 3141 KKASSERT(err_ccb != NULL); 3142 err_ccb->ccb_xa.flags = 0; 3143 err_ccb->ccb_done = ahci_empty_done; 3144 3145 return err_ccb; 3146 } 3147 3148 void 3149 ahci_put_err_ccb(struct ahci_ccb *ccb) 3150 { 3151 struct ahci_port *ap = ccb->ccb_port; 3152 u_int32_t sact; 3153 u_int32_t ci; 3154 3155 KKASSERT((ap->ap_flags & AP_F_ERR_CCB_RESERVED) != 0); 3156 3157 /* 3158 * No commands may be active on the chip 3159 */ 3160 if (ap->ap_sc->sc_cap & AHCI_REG_CAP_SNCQ) { 3161 sact = ahci_pread(ap, AHCI_PREG_SACT); 3162 if (sact) { 3163 panic("ahci_port_err_ccb(%d) but SACT %08x != 0\n", 3164 ccb->ccb_slot, sact); 3165 } 3166 } 3167 ci = ahci_pread(ap, AHCI_PREG_CI); 3168 if (ci) { 3169 panic("ahci_put_err_ccb(%d) but CI %08x != 0 " 3170 "(act=%08x sact=%08x)\n", 3171 ccb->ccb_slot, ci, 3172 ap->ap_active, ap->ap_sactive); 3173 } 3174 3175 KKASSERT(ccb == ap->ap_err_ccb); 3176 3177 /* Restore outstanding command state */ 3178 ap->ap_sactive = ap->ap_err_saved_sactive; 3179 ap->ap_active_cnt = ap->ap_err_saved_active_cnt; 3180 ap->ap_active = ap->ap_err_saved_active; 3181 3182 ap->ap_flags &= ~AP_F_ERR_CCB_RESERVED; 3183 } 3184 3185 /* 3186 * Read log page to get NCQ error. 3187 * 3188 * NOTE: NCQ not currently supported on port multipliers. XXX 3189 */ 3190 int 3191 ahci_port_read_ncq_error(struct ahci_port *ap, int target) 3192 { 3193 struct ata_log_page_10h *log; 3194 struct ahci_ccb *ccb; 3195 struct ahci_ccb *ccb2; 3196 struct ahci_cmd_hdr *cmd_slot; 3197 struct ata_fis_h2d *fis; 3198 int err_slot; 3199 3200 if (bootverbose) { 3201 kprintf("%s: READ LOG PAGE target %d\n", PORTNAME(ap), 3202 target); 3203 } 3204 3205 /* 3206 * Prep error CCB for READ LOG EXT, page 10h, 1 sector. 3207 * 3208 * Getting err_ccb clears active/sactive/active_cnt, putting 3209 * it back restores the fields. 3210 */ 3211 ccb = ahci_get_err_ccb(ap); 3212 ccb->ccb_xa.flags = ATA_F_READ | ATA_F_POLL; 3213 ccb->ccb_xa.data = ap->ap_err_scratch; 3214 ccb->ccb_xa.datalen = 512; 3215 ccb->ccb_xa.complete = ahci_dummy_done; 3216 ccb->ccb_xa.at = ap->ap_ata[target]; 3217 3218 fis = (struct ata_fis_h2d *)ccb->ccb_cmd_table->cfis; 3219 bzero(fis, sizeof(*fis)); 3220 fis->type = ATA_FIS_TYPE_H2D; 3221 fis->flags = ATA_H2D_FLAGS_CMD | target; 3222 fis->command = ATA_C_READ_LOG_EXT; 3223 fis->lba_low = 0x10; /* queued error log page (10h) */ 3224 fis->sector_count = 1; /* number of sectors (1) */ 3225 fis->sector_count_exp = 0; 3226 fis->lba_mid = 0; /* starting offset */ 3227 fis->lba_mid_exp = 0; 3228 fis->device = 0; 3229 3230 cmd_slot = ccb->ccb_cmd_hdr; 3231 cmd_slot->flags = htole16(5); /* FIS length: 5 DWORDS */ 3232 3233 if (ahci_load_prdt(ccb) != 0) { 3234 err_slot = -1; 3235 goto err; 3236 } 3237 3238 ccb->ccb_xa.state = ATA_S_PENDING; 3239 if (ahci_poll(ccb, 1000, ahci_quick_timeout) != ATA_S_COMPLETE) { 3240 err_slot = -1; 3241 ahci_unload_prdt(ccb); 3242 goto err; 3243 } 3244 ahci_unload_prdt(ccb); 3245 3246 /* 3247 * Success, extract failed register set and tags from the scratch 3248 * space. 3249 */ 3250 log = (struct ata_log_page_10h *)ap->ap_err_scratch; 3251 if (log->err_regs.type & ATA_LOG_10H_TYPE_NOTQUEUED) { 3252 /* Not queued bit was set - wasn't an NCQ error? */ 3253 kprintf("%s: read NCQ error page, but not an NCQ error?\n", 3254 PORTNAME(ap)); 3255 err_slot = -1; 3256 } else { 3257 /* Copy back the log record as a D2H register FIS. */ 3258 err_slot = log->err_regs.type & ATA_LOG_10H_TYPE_TAG_MASK; 3259 3260 ccb2 = &ap->ap_ccbs[err_slot]; 3261 if (ccb2->ccb_xa.state == ATA_S_ONCHIP) { 3262 kprintf("%s: read NCQ error page slot=%d\n", 3263 ATANAME(ap, ccb2->ccb_xa.at), 3264 err_slot); 3265 memcpy(&ccb2->ccb_xa.rfis, &log->err_regs, 3266 sizeof(struct ata_fis_d2h)); 3267 ccb2->ccb_xa.rfis.type = ATA_FIS_TYPE_D2H; 3268 ccb2->ccb_xa.rfis.flags = 0; 3269 } else { 3270 kprintf("%s: read NCQ error page slot=%d, " 3271 "slot does not match any cmds\n", 3272 ATANAME(ccb2->ccb_port, ccb2->ccb_xa.at), 3273 err_slot); 3274 err_slot = -1; 3275 } 3276 } 3277 err: 3278 ahci_put_err_ccb(ccb); 3279 kprintf("%s: DONE log page target %d err_slot=%d\n", 3280 PORTNAME(ap), target, err_slot); 3281 return (err_slot); 3282 } 3283 3284 /* 3285 * Allocate memory for various structures DMAd by hardware. The maximum 3286 * number of segments for these tags is 1 so the DMA memory will have a 3287 * single physical base address. 3288 */ 3289 struct ahci_dmamem * 3290 ahci_dmamem_alloc(struct ahci_softc *sc, bus_dma_tag_t tag) 3291 { 3292 struct ahci_dmamem *adm; 3293 int error; 3294 3295 adm = kmalloc(sizeof(*adm), M_DEVBUF, M_INTWAIT | M_ZERO); 3296 3297 error = bus_dmamem_alloc(tag, (void **)&adm->adm_kva, 3298 BUS_DMA_ZERO, &adm->adm_map); 3299 if (error == 0) { 3300 adm->adm_tag = tag; 3301 error = bus_dmamap_load(tag, adm->adm_map, 3302 adm->adm_kva, 3303 bus_dma_tag_getmaxsize(tag), 3304 ahci_dmamem_saveseg, &adm->adm_busaddr, 3305 0); 3306 } 3307 if (error) { 3308 if (adm->adm_map) { 3309 bus_dmamap_destroy(tag, adm->adm_map); 3310 adm->adm_map = NULL; 3311 adm->adm_tag = NULL; 3312 adm->adm_kva = NULL; 3313 } 3314 kfree(adm, M_DEVBUF); 3315 adm = NULL; 3316 } 3317 return (adm); 3318 } 3319 3320 static 3321 void 3322 ahci_dmamem_saveseg(void *info, bus_dma_segment_t *segs, int nsegs, int error) 3323 { 3324 KKASSERT(error == 0); 3325 KKASSERT(nsegs == 1); 3326 *(bus_addr_t *)info = segs->ds_addr; 3327 } 3328 3329 3330 void 3331 ahci_dmamem_free(struct ahci_softc *sc, struct ahci_dmamem *adm) 3332 { 3333 if (adm->adm_map) { 3334 bus_dmamap_unload(adm->adm_tag, adm->adm_map); 3335 bus_dmamap_destroy(adm->adm_tag, adm->adm_map); 3336 adm->adm_map = NULL; 3337 adm->adm_tag = NULL; 3338 adm->adm_kva = NULL; 3339 } 3340 kfree(adm, M_DEVBUF); 3341 } 3342 3343 u_int32_t 3344 ahci_read(struct ahci_softc *sc, bus_size_t r) 3345 { 3346 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 3347 BUS_SPACE_BARRIER_READ); 3348 return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, r)); 3349 } 3350 3351 void 3352 ahci_write(struct ahci_softc *sc, bus_size_t r, u_int32_t v) 3353 { 3354 bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v); 3355 bus_space_barrier(sc->sc_iot, sc->sc_ioh, r, 4, 3356 BUS_SPACE_BARRIER_WRITE); 3357 } 3358 3359 u_int32_t 3360 ahci_pread(struct ahci_port *ap, bus_size_t r) 3361 { 3362 bus_space_barrier(ap->ap_sc->sc_iot, ap->ap_ioh, r, 4, 3363 BUS_SPACE_BARRIER_READ); 3364 return (bus_space_read_4(ap->ap_sc->sc_iot, ap->ap_ioh, r)); 3365 } 3366 3367 void 3368 ahci_pwrite(struct ahci_port *ap, bus_size_t r, u_int32_t v) 3369 { 3370 bus_space_write_4(ap->ap_sc->sc_iot, ap->ap_ioh, r, v); 3371 bus_space_barrier(ap->ap_sc->sc_iot, ap->ap_ioh, r, 4, 3372 BUS_SPACE_BARRIER_WRITE); 3373 } 3374 3375 /* 3376 * Wait up to (timeout) milliseconds for the masked port register to 3377 * match the target. 3378 * 3379 * Timeout is in milliseconds. 3380 */ 3381 int 3382 ahci_pwait_eq(struct ahci_port *ap, int timeout, 3383 bus_size_t r, u_int32_t mask, u_int32_t target) 3384 { 3385 int t; 3386 3387 /* 3388 * Loop hard up to 100uS 3389 */ 3390 for (t = 0; t < 100; ++t) { 3391 if ((ahci_pread(ap, r) & mask) == target) 3392 return (0); 3393 ahci_os_hardsleep(1); /* us */ 3394 } 3395 3396 do { 3397 timeout -= ahci_os_softsleep(); 3398 if ((ahci_pread(ap, r) & mask) == target) 3399 return (0); 3400 } while (timeout > 0); 3401 return (1); 3402 } 3403 3404 int 3405 ahci_wait_ne(struct ahci_softc *sc, bus_size_t r, u_int32_t mask, 3406 u_int32_t target) 3407 { 3408 int t; 3409 3410 /* 3411 * Loop hard up to 100uS 3412 */ 3413 for (t = 0; t < 100; ++t) { 3414 if ((ahci_read(sc, r) & mask) != target) 3415 return (0); 3416 ahci_os_hardsleep(1); /* us */ 3417 } 3418 3419 /* 3420 * And one millisecond the slow way 3421 */ 3422 t = 1000; 3423 do { 3424 t -= ahci_os_softsleep(); 3425 if ((ahci_read(sc, r) & mask) != target) 3426 return (0); 3427 } while (t > 0); 3428 3429 return (1); 3430 } 3431 3432 3433 /* 3434 * Acquire an ata transfer. 3435 * 3436 * Pass a NULL at for direct-attached transfers, and a non-NULL at for 3437 * targets that go through the port multiplier. 3438 */ 3439 struct ata_xfer * 3440 ahci_ata_get_xfer(struct ahci_port *ap, struct ata_port *at) 3441 { 3442 struct ahci_ccb *ccb; 3443 3444 ccb = ahci_get_ccb(ap); 3445 if (ccb == NULL) { 3446 DPRINTF(AHCI_D_XFER, "%s: ahci_ata_get_xfer: NULL ccb\n", 3447 PORTNAME(ap)); 3448 return (NULL); 3449 } 3450 3451 DPRINTF(AHCI_D_XFER, "%s: ahci_ata_get_xfer got slot %d\n", 3452 PORTNAME(ap), ccb->ccb_slot); 3453 3454 bzero(ccb->ccb_xa.fis, sizeof(*ccb->ccb_xa.fis)); 3455 ccb->ccb_xa.at = at; 3456 ccb->ccb_xa.fis->type = ATA_FIS_TYPE_H2D; 3457 3458 return (&ccb->ccb_xa); 3459 } 3460 3461 void 3462 ahci_ata_put_xfer(struct ata_xfer *xa) 3463 { 3464 struct ahci_ccb *ccb = (struct ahci_ccb *)xa; 3465 3466 DPRINTF(AHCI_D_XFER, "ahci_ata_put_xfer slot %d\n", ccb->ccb_slot); 3467 3468 ahci_put_ccb(ccb); 3469 } 3470 3471 int 3472 ahci_ata_cmd(struct ata_xfer *xa) 3473 { 3474 struct ahci_ccb *ccb = (struct ahci_ccb *)xa; 3475 struct ahci_cmd_hdr *cmd_slot; 3476 3477 KKASSERT(xa->state == ATA_S_SETUP); 3478 3479 if (ccb->ccb_port->ap_state == AP_S_FATAL_ERROR) 3480 goto failcmd; 3481 ccb->ccb_done = ahci_ata_cmd_done; 3482 3483 cmd_slot = ccb->ccb_cmd_hdr; 3484 cmd_slot->flags = htole16(5); /* FIS length (in DWORDs) */ 3485 if (ccb->ccb_xa.at) { 3486 cmd_slot->flags |= htole16(ccb->ccb_xa.at->at_target << 3487 AHCI_CMD_LIST_FLAG_PMP_SHIFT); 3488 } 3489 3490 if (xa->flags & ATA_F_WRITE) 3491 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_W); 3492 3493 if (xa->flags & ATA_F_PACKET) 3494 cmd_slot->flags |= htole16(AHCI_CMD_LIST_FLAG_A); 3495 3496 if (ahci_load_prdt(ccb) != 0) 3497 goto failcmd; 3498 3499 xa->state = ATA_S_PENDING; 3500 3501 if (xa->flags & ATA_F_POLL) 3502 return (ahci_poll(ccb, xa->timeout, ahci_ata_cmd_timeout)); 3503 3504 crit_enter(); 3505 KKASSERT((xa->flags & ATA_F_TIMEOUT_EXPIRED) == 0); 3506 xa->flags |= ATA_F_TIMEOUT_DESIRED; 3507 ahci_start(ccb); 3508 crit_exit(); 3509 return (xa->state); 3510 3511 failcmd: 3512 crit_enter(); 3513 xa->state = ATA_S_ERROR; 3514 xa->complete(xa); 3515 crit_exit(); 3516 return (ATA_S_ERROR); 3517 } 3518 3519 void 3520 ahci_ata_cmd_done(struct ahci_ccb *ccb) 3521 { 3522 struct ata_xfer *xa = &ccb->ccb_xa; 3523 3524 /* 3525 * NOTE: callout does not lock port and may race us modifying 3526 * the flags, so make sure its stopped. 3527 */ 3528 if (xa->flags & ATA_F_TIMEOUT_RUNNING) { 3529 callout_stop(&ccb->ccb_timeout); 3530 xa->flags &= ~ATA_F_TIMEOUT_RUNNING; 3531 } 3532 xa->flags &= ~(ATA_F_TIMEOUT_DESIRED | ATA_F_TIMEOUT_EXPIRED); 3533 3534 KKASSERT(xa->state != ATA_S_ONCHIP); 3535 ahci_unload_prdt(ccb); 3536 3537 if (xa->state != ATA_S_TIMEOUT) 3538 xa->complete(xa); 3539 } 3540 3541 /* 3542 * Timeout from callout, MPSAFE - nothing can mess with the CCB's flags 3543 * while the callout is runing. 3544 * 3545 * We can't safely get the port lock here or delay, we could block 3546 * the callout thread. 3547 */ 3548 static void 3549 ahci_ata_cmd_timeout_unserialized(void *arg) 3550 { 3551 struct ahci_ccb *ccb = arg; 3552 struct ahci_port *ap = ccb->ccb_port; 3553 3554 ccb->ccb_xa.flags &= ~ATA_F_TIMEOUT_RUNNING; 3555 ccb->ccb_xa.flags |= ATA_F_TIMEOUT_EXPIRED; 3556 ahci_os_signal_port_thread(ap, AP_SIGF_TIMEOUT); 3557 } 3558 3559 /* 3560 * Timeout code, typically called when the port command processor is running. 3561 * 3562 * We have to be very very careful here. We cannot stop the port unless 3563 * CR is already clear or the only active commands remaining are timed-out 3564 * ones. Otherwise stopping the port will race the command processor and 3565 * we can lose events. While we can theoretically just restart everything 3566 * that could result in a double-issue which will not work for ATAPI commands. 3567 */ 3568 void 3569 ahci_ata_cmd_timeout(struct ahci_ccb *ccb) 3570 { 3571 struct ata_xfer *xa = &ccb->ccb_xa; 3572 struct ahci_port *ap = ccb->ccb_port; 3573 struct ata_port *at; 3574 u_int32_t ci_saved; 3575 u_int32_t mask; 3576 int slot; 3577 3578 at = ccb->ccb_xa.at; 3579 3580 kprintf("%s: CMD TIMEOUT state=%d slot=%d\n" 3581 "\tcmd-reg 0x%b\n" 3582 "\tsactive=%08x active=%08x expired=%08x\n" 3583 "\t sact=%08x ci=%08x\n" 3584 "\t STS=%b\n", 3585 ATANAME(ap, at), 3586 ccb->ccb_xa.state, ccb->ccb_slot, 3587 ahci_pread(ap, AHCI_PREG_CMD), AHCI_PFMT_CMD, 3588 ap->ap_sactive, ap->ap_active, ap->ap_expired, 3589 ahci_pread(ap, AHCI_PREG_SACT), 3590 ahci_pread(ap, AHCI_PREG_CI), 3591 ahci_pread(ap, AHCI_PREG_TFD), AHCI_PFMT_TFD_STS 3592 ); 3593 3594 3595 /* 3596 * NOTE: Timeout will not be running if the command was polled. 3597 * If we got here at least one of these flags should be set. 3598 */ 3599 KKASSERT(xa->flags & (ATA_F_POLL | ATA_F_TIMEOUT_DESIRED | 3600 ATA_F_TIMEOUT_RUNNING)); 3601 xa->flags &= ~(ATA_F_TIMEOUT_RUNNING | ATA_F_TIMEOUT_EXPIRED); 3602 3603 if (ccb->ccb_xa.state == ATA_S_PENDING) { 3604 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry); 3605 ccb->ccb_xa.state = ATA_S_TIMEOUT; 3606 ccb->ccb_done(ccb); 3607 xa->complete(xa); 3608 ahci_issue_pending_commands(ap, NULL); 3609 return; 3610 } 3611 if (ccb->ccb_xa.state != ATA_S_ONCHIP) { 3612 kprintf("%s: Unexpected state during timeout: %d\n", 3613 ATANAME(ap, at), ccb->ccb_xa.state); 3614 return; 3615 } 3616 3617 /* 3618 * Ok, we can only get this command off the chip if CR is inactive 3619 * or if the only commands running on the chip are all expired. 3620 * Otherwise we have to wait until the port is in a safe state. 3621 * 3622 * Do not set state here, it will cause polls to return when the 3623 * ccb is not yet off the chip. 3624 */ 3625 ap->ap_expired |= 1 << ccb->ccb_slot; 3626 3627 if ((ahci_pread(ap, AHCI_PREG_CMD) & AHCI_PREG_CMD_CR) && 3628 (ap->ap_active | ap->ap_sactive) != ap->ap_expired) { 3629 /* 3630 * If using FBSS or NCQ we can't safely stop the port 3631 * right now. 3632 */ 3633 kprintf("%s: Deferred timeout until its safe, slot %d\n", 3634 ATANAME(ap, at), ccb->ccb_slot); 3635 return; 3636 } 3637 3638 /* 3639 * We can safely stop the port and process all expired ccb's, 3640 * which will include our current ccb. 3641 */ 3642 ci_saved = (ap->ap_sactive) ? ahci_pread(ap, AHCI_PREG_SACT) : 3643 ahci_pread(ap, AHCI_PREG_CI); 3644 ahci_port_stop(ap, 0); 3645 3646 while (ap->ap_expired) { 3647 slot = ffs(ap->ap_expired) - 1; 3648 ap->ap_expired &= ~(1 << slot); 3649 ci_saved &= ~(1 << slot); 3650 ccb = &ap->ap_ccbs[slot]; 3651 ccb->ccb_xa.state = ATA_S_TIMEOUT; 3652 if (ccb->ccb_xa.flags & ATA_F_NCQ) { 3653 KKASSERT(ap->ap_sactive & (1 << slot)); 3654 ap->ap_sactive &= ~(1 << slot); 3655 } else { 3656 KKASSERT(ap->ap_active & (1 << slot)); 3657 ap->ap_active &= ~(1 << slot); 3658 --ap->ap_active_cnt; 3659 } 3660 ccb->ccb_done(ccb); 3661 ccb->ccb_xa.complete(&ccb->ccb_xa); 3662 } 3663 /* ccb invalid now */ 3664 3665 /* 3666 * We can safely CLO the port to clear any BSY/DRQ, a case which 3667 * can occur with port multipliers. This will unbrick the port 3668 * and allow commands to other targets behind the PM continue. 3669 * (FBSS). 3670 * 3671 * Finally, once the port has been restarted we can issue any 3672 * previously saved pending commands, and run the port interrupt 3673 * code to handle any completions which may have occured when 3674 * we saved CI. 3675 */ 3676 if (ahci_pread(ap, AHCI_PREG_TFD) & 3677 (AHCI_PREG_TFD_STS_BSY | AHCI_PREG_TFD_STS_DRQ)) { 3678 kprintf("%s: Warning, issuing CLO after timeout\n", 3679 ATANAME(ap, at)); 3680 ahci_port_clo(ap); 3681 } 3682 ahci_port_start(ap); 3683 3684 /* 3685 * We absolutely must make sure the chipset cleared activity on 3686 * all slots. This sometimes might not happen due to races with 3687 * a chipset interrupt which stops the port before we can manage 3688 * to. For some reason some chipsets don't clear the active 3689 * commands when we turn off CMD_ST after the chip has stopped 3690 * operations itself. 3691 */ 3692 if (ahci_pactive(ap) != 0) { 3693 ahci_port_stop(ap, 0); 3694 ahci_port_start(ap); 3695 if ((mask = ahci_pactive(ap)) != 0) { 3696 kprintf("%s: quick-timeout: chipset failed " 3697 "to clear active cmds %08x\n", 3698 PORTNAME(ap), mask); 3699 } 3700 } 3701 ahci_issue_saved_commands(ap, ci_saved & ~ap->ap_expired); 3702 ahci_issue_pending_commands(ap, NULL); 3703 ahci_port_intr(ap, 0); 3704 } 3705 3706 /* 3707 * Issue a previously saved set of commands 3708 */ 3709 void 3710 ahci_issue_saved_commands(struct ahci_port *ap, u_int32_t ci_saved) 3711 { 3712 if (ci_saved) { 3713 KKASSERT(!((ap->ap_active & ci_saved) && 3714 (ap->ap_sactive & ci_saved))); 3715 KKASSERT((ci_saved & ap->ap_expired) == 0); 3716 if (ap->ap_sactive & ci_saved) 3717 ahci_pwrite(ap, AHCI_PREG_SACT, ci_saved); 3718 ahci_pwrite(ap, AHCI_PREG_CI, ci_saved); 3719 } 3720 } 3721 3722 /* 3723 * Used by the softreset, pmprobe, and read_ncq_error only, in very 3724 * specialized, controlled circumstances. 3725 * 3726 * Only one command may be pending. 3727 */ 3728 void 3729 ahci_quick_timeout(struct ahci_ccb *ccb) 3730 { 3731 struct ahci_port *ap = ccb->ccb_port; 3732 u_int32_t mask; 3733 3734 switch (ccb->ccb_xa.state) { 3735 case ATA_S_PENDING: 3736 TAILQ_REMOVE(&ap->ap_ccb_pending, ccb, ccb_entry); 3737 ccb->ccb_xa.state = ATA_S_TIMEOUT; 3738 break; 3739 case ATA_S_ONCHIP: 3740 /* 3741 * We have to clear the command on-chip. 3742 */ 3743 KKASSERT(ap->ap_active == (1 << ccb->ccb_slot) && 3744 ap->ap_sactive == 0); 3745 ahci_port_stop(ap, 0); 3746 ahci_port_start(ap); 3747 if (ahci_pactive(ap) != 0) { 3748 ahci_port_stop(ap, 0); 3749 ahci_port_start(ap); 3750 if ((mask = ahci_pactive(ap)) != 0) { 3751 kprintf("%s: quick-timeout: chipset failed " 3752 "to clear active cmds %08x\n", 3753 PORTNAME(ap), mask); 3754 } 3755 } 3756 3757 ccb->ccb_xa.state = ATA_S_TIMEOUT; 3758 ap->ap_active &= ~(1 << ccb->ccb_slot); 3759 KKASSERT(ap->ap_active_cnt > 0); 3760 --ap->ap_active_cnt; 3761 break; 3762 default: 3763 panic("%s: ahci_quick_timeout: ccb in bad state %d", 3764 ATANAME(ap, ccb->ccb_xa.at), ccb->ccb_xa.state); 3765 } 3766 } 3767 3768 static void 3769 ahci_dummy_done(struct ata_xfer *xa) 3770 { 3771 } 3772 3773 static void 3774 ahci_empty_done(struct ahci_ccb *ccb) 3775 { 3776 } 3777 3778 int 3779 ahci_set_feature(struct ahci_port *ap, struct ata_port *atx, 3780 int feature, int enable) 3781 { 3782 struct ata_port *at; 3783 struct ata_xfer *xa; 3784 int error; 3785 3786 at = atx ? atx : ap->ap_ata[0]; 3787 3788 xa = ahci_ata_get_xfer(ap, atx); 3789 3790 xa->fis->type = ATA_FIS_TYPE_H2D; 3791 xa->fis->flags = ATA_H2D_FLAGS_CMD | at->at_target; 3792 xa->fis->command = ATA_C_SET_FEATURES; 3793 xa->fis->features = enable ? ATA_C_SATA_FEATURE_ENA : 3794 ATA_C_SATA_FEATURE_DIS; 3795 xa->fis->sector_count = feature; 3796 xa->fis->control = ATA_FIS_CONTROL_4BIT; 3797 3798 xa->complete = ahci_dummy_done; 3799 xa->datalen = 0; 3800 xa->flags = ATA_F_POLL; 3801 xa->timeout = 1000; 3802 3803 if (ahci_ata_cmd(xa) == ATA_S_COMPLETE) 3804 error = 0; 3805 else 3806 error = EIO; 3807 ahci_ata_put_xfer(xa); 3808 return(error); 3809 } 3810